1 // SPDX-License-Identifier: GPL-2.0
3 * ARM Message Handling Unit Version 2 (MHUv2) driver.
5 * Copyright (C) 2020 ARM Ltd.
6 * Copyright (C) 2020 Linaro Ltd.
8 * An MHUv2 mailbox controller can provide up to 124 channel windows (each 32
9 * bit long) and the driver allows any combination of both the transport
10 * protocol modes: data-transfer and doorbell, to be used on those channel
13 * The transport protocols should be specified in the device tree entry for the
14 * device. The transport protocols determine how the underlying hardware
15 * resources of the device are utilized when transmitting data. Refer to the
16 * device tree bindings of the ARM MHUv2 controller for more details.
18 * The number of registered mailbox channels is dependent on both the underlying
19 * hardware - mainly the number of channel windows implemented by the platform,
20 * as well as the selected transport protocols.
22 * The MHUv2 controller can work both as a sender and receiver, but the driver
23 * and the DT bindings support unidirectional transfers for better allocation of
24 * the channels. That is, this driver will be probed for two separate devices
25 * for each mailbox controller, a sender device and a receiver device.
28 #include <linux/amba/bus.h>
29 #include <linux/interrupt.h>
30 #include <linux/mailbox_controller.h>
31 #include <linux/mailbox/arm_mhuv2_message.h>
32 #include <linux/module.h>
33 #include <linux/of_address.h>
34 #include <linux/spinlock.h>
36 /* ====== MHUv2 Registers ====== */
38 /* Maximum number of channel windows */
39 #define MHUV2_CH_WN_MAX 124
40 /* Number of combined interrupt status registers */
41 #define MHUV2_CMB_INT_ST_REG_CNT 4
42 #define MHUV2_STAT_BYTES (sizeof(u32))
43 #define MHUV2_STAT_BITS (MHUV2_STAT_BYTES * __CHAR_BIT__)
45 #define LSB_MASK(n) ((1 << (n * __CHAR_BIT__)) - 1)
46 #define MHUV2_PROTOCOL_PROP "arm,mhuv2-protocols"
48 /* Register Message Handling Unit Configuration fields */
54 /* register Interrupt Status fields */
61 /* Register Interrupt Clear fields */
68 /* Register Interrupt Enable fields */
76 /* Register Implementer Identification fields */
84 /* Register Architecture Identification Register fields */
86 u32 arch_minor_rev
: 4;
87 u32 arch_major_rev
: 4;
91 /* Sender Channel Window fields */
92 struct mhu2_send_ch_wn_reg
{
102 /* Sender frame register fields */
103 struct mhu2_send_frame_reg
{
104 struct mhu2_send_ch_wn_reg ch_wn
[MHUV2_CH_WN_MAX
];
105 struct mhu_cfg_t mhu_cfg
;
109 struct int_st_t int_st
;
110 struct int_clr_t int_clr
;
111 struct int_en_t int_en
;
113 u32 chcomb_int_st
[MHUV2_CMB_INT_ST_REG_CNT
];
114 u8 pad
[0xFC8 - 0xFB0];
119 /* Receiver Channel Window fields */
120 struct mhu2_recv_ch_wn_reg
{
124 u8 reserved0
[0x10 - 0x0C];
131 /* Receiver frame register fields */
132 struct mhu2_recv_frame_reg
{
133 struct mhu2_recv_ch_wn_reg ch_wn
[MHUV2_CH_WN_MAX
];
134 struct mhu_cfg_t mhu_cfg
;
135 u8 reserved0
[0xF90 - 0xF84];
136 struct int_st_t int_st
;
137 struct int_clr_t int_clr
;
138 struct int_en_t int_en
;
140 u32 chcomb_int_st
[MHUV2_CMB_INT_ST_REG_CNT
];
141 u8 reserved2
[0xFC8 - 0xFB0];
147 /* ====== MHUv2 data structures ====== */
149 enum mhuv2_transport_protocol
{
160 * struct mhuv2 - MHUv2 mailbox controller data
162 * @mbox: Mailbox controller belonging to the MHU frame.
163 * @send: Base address of the register mapping region.
164 * @recv: Base address of the register mapping region.
165 * @frame: Frame type: RECEIVER_FRAME or SENDER_FRAME.
167 * @windows: Channel windows implemented by the platform.
168 * @minor: Minor version of the controller.
169 * @length: Length of the protocols array in bytes.
170 * @protocols: Raw protocol information, derived from device tree.
171 * @doorbell_pending_lock: spinlock required for correct operation of Tx
172 * interrupt for doorbells.
175 struct mbox_controller mbox
;
177 struct mhu2_send_frame_reg __iomem
*send
;
178 struct mhu2_recv_frame_reg __iomem
*recv
;
180 enum mhuv2_frame frame
;
182 unsigned int windows
;
187 spinlock_t doorbell_pending_lock
;
190 #define mhu_from_mbox(_mbox) container_of(_mbox, struct mhuv2, mbox)
193 * struct mhuv2_protocol_ops - MHUv2 operations
195 * Each transport protocol must provide an implementation of the operations
198 * @rx_startup: Startup callback for receiver.
199 * @rx_shutdown: Shutdown callback for receiver.
200 * @read_data: Reads and clears newly available data.
201 * @tx_startup: Startup callback for receiver.
202 * @tx_shutdown: Shutdown callback for receiver.
203 * @last_tx_done: Report back if the last tx is completed or not.
204 * @send_data: Send data to the receiver.
206 struct mhuv2_protocol_ops
{
207 int (*rx_startup
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
208 void (*rx_shutdown
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
209 void *(*read_data
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
211 void (*tx_startup
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
212 void (*tx_shutdown
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
213 int (*last_tx_done
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
);
214 int (*send_data
)(struct mhuv2
*mhu
, struct mbox_chan
*chan
, void *arg
);
218 * MHUv2 mailbox channel's private information
220 * @ops: protocol specific ops for the channel.
221 * @ch_wn_idx: Channel window index allocated to the channel.
222 * @windows: Total number of windows consumed by the channel, only relevant
223 * in DATA_TRANSFER protocol.
224 * @doorbell: Doorbell bit number within the ch_wn_idx window, only relevant
225 * in DOORBELL protocol.
226 * @pending: Flag indicating pending doorbell interrupt, only relevant in
229 struct mhuv2_mbox_chan_priv
{
230 const struct mhuv2_protocol_ops
*ops
;
241 /* Macro for reading a bitfield within a physically mapped packed struct */
242 #define readl_relaxed_bitfield(_regptr, _type, _field) \
245 _regval = readl_relaxed((_regptr)); \
246 (*(_type *)(&_regval))._field; \
249 /* Macro for writing a bitfield within a physically mapped packed struct */
250 #define writel_relaxed_bitfield(_value, _regptr, _type, _field) \
253 _regval = readl_relaxed(_regptr); \
254 (*(_type *)(&_regval))._field = _value; \
255 writel_relaxed(_regval, _regptr); \
259 /* =================== Doorbell transport protocol operations =============== */
261 static int mhuv2_doorbell_rx_startup(struct mhuv2
*mhu
, struct mbox_chan
*chan
)
263 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
265 writel_relaxed(BIT(priv
->doorbell
),
266 &mhu
->recv
->ch_wn
[priv
->ch_wn_idx
].mask_clear
);
270 static void mhuv2_doorbell_rx_shutdown(struct mhuv2
*mhu
,
271 struct mbox_chan
*chan
)
273 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
275 writel_relaxed(BIT(priv
->doorbell
),
276 &mhu
->recv
->ch_wn
[priv
->ch_wn_idx
].mask_set
);
279 static void *mhuv2_doorbell_read_data(struct mhuv2
*mhu
, struct mbox_chan
*chan
)
281 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
283 writel_relaxed(BIT(priv
->doorbell
),
284 &mhu
->recv
->ch_wn
[priv
->ch_wn_idx
].stat_clear
);
288 static int mhuv2_doorbell_last_tx_done(struct mhuv2
*mhu
,
289 struct mbox_chan
*chan
)
291 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
293 return !(readl_relaxed(&mhu
->send
->ch_wn
[priv
->ch_wn_idx
].stat
) &
294 BIT(priv
->doorbell
));
297 static int mhuv2_doorbell_send_data(struct mhuv2
*mhu
, struct mbox_chan
*chan
,
300 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
303 spin_lock_irqsave(&mhu
->doorbell_pending_lock
, flags
);
306 writel_relaxed(BIT(priv
->doorbell
),
307 &mhu
->send
->ch_wn
[priv
->ch_wn_idx
].stat_set
);
309 spin_unlock_irqrestore(&mhu
->doorbell_pending_lock
, flags
);
314 static const struct mhuv2_protocol_ops mhuv2_doorbell_ops
= {
315 .rx_startup
= mhuv2_doorbell_rx_startup
,
316 .rx_shutdown
= mhuv2_doorbell_rx_shutdown
,
317 .read_data
= mhuv2_doorbell_read_data
,
318 .last_tx_done
= mhuv2_doorbell_last_tx_done
,
319 .send_data
= mhuv2_doorbell_send_data
,
321 #define IS_PROTOCOL_DOORBELL(_priv) (_priv->ops == &mhuv2_doorbell_ops)
323 /* ============= Data transfer transport protocol operations ================ */
325 static int mhuv2_data_transfer_rx_startup(struct mhuv2
*mhu
,
326 struct mbox_chan
*chan
)
328 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
329 int i
= priv
->ch_wn_idx
+ priv
->windows
- 1;
332 * The protocol mandates that all but the last status register must be
335 writel_relaxed(0xFFFFFFFF, &mhu
->recv
->ch_wn
[i
].mask_clear
);
339 static void mhuv2_data_transfer_rx_shutdown(struct mhuv2
*mhu
,
340 struct mbox_chan
*chan
)
342 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
343 int i
= priv
->ch_wn_idx
+ priv
->windows
- 1;
345 writel_relaxed(0xFFFFFFFF, &mhu
->recv
->ch_wn
[i
].mask_set
);
348 static void *mhuv2_data_transfer_read_data(struct mhuv2
*mhu
,
349 struct mbox_chan
*chan
)
351 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
352 const int windows
= priv
->windows
;
353 struct arm_mhuv2_mbox_msg
*msg
;
357 msg
= kzalloc(sizeof(*msg
) + windows
* MHUV2_STAT_BYTES
, GFP_KERNEL
);
359 return ERR_PTR(-ENOMEM
);
361 data
= msg
->data
= msg
+ 1;
362 msg
->len
= windows
* MHUV2_STAT_BYTES
;
365 * Messages are expected in order of most significant word to least
366 * significant word. Refer mhuv2_data_transfer_send_data() for more
369 * We also need to read the stat register instead of stat_masked, as we
370 * masked all but the last window.
372 * Last channel window must be cleared as the final operation. Upon
373 * clearing the last channel window register, which is unmasked in
374 * data-transfer protocol, the interrupt is de-asserted.
376 for (i
= 0; i
< windows
; i
++) {
377 idx
= priv
->ch_wn_idx
+ i
;
378 data
[windows
- 1 - i
] = readl_relaxed(&mhu
->recv
->ch_wn
[idx
].stat
);
379 writel_relaxed(0xFFFFFFFF, &mhu
->recv
->ch_wn
[idx
].stat_clear
);
385 static void mhuv2_data_transfer_tx_startup(struct mhuv2
*mhu
,
386 struct mbox_chan
*chan
)
388 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
389 int i
= priv
->ch_wn_idx
+ priv
->windows
- 1;
391 /* Enable interrupts only for the last window */
393 writel_relaxed(0x1, &mhu
->send
->ch_wn
[i
].int_clr
);
394 writel_relaxed(0x1, &mhu
->send
->ch_wn
[i
].int_en
);
398 static void mhuv2_data_transfer_tx_shutdown(struct mhuv2
*mhu
,
399 struct mbox_chan
*chan
)
401 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
402 int i
= priv
->ch_wn_idx
+ priv
->windows
- 1;
405 writel_relaxed(0x0, &mhu
->send
->ch_wn
[i
].int_en
);
408 static int mhuv2_data_transfer_last_tx_done(struct mhuv2
*mhu
,
409 struct mbox_chan
*chan
)
411 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
412 int i
= priv
->ch_wn_idx
+ priv
->windows
- 1;
414 /* Just checking the last channel window should be enough */
415 return !readl_relaxed(&mhu
->send
->ch_wn
[i
].stat
);
419 * Message will be transmitted from most significant to least significant word.
420 * This is to allow for messages shorter than channel windows to still trigger
421 * the receiver interrupt which gets activated when the last stat register is
422 * written. As an example, a 6-word message is to be written on a 4-channel MHU
423 * connection: Registers marked with '*' are masked, and will not generate an
424 * interrupt on the receiver side once written.
426 * u32 *data = [0x00000001], [0x00000002], [0x00000003], [0x00000004],
427 * [0x00000005], [0x00000006]
430 * stat reg To write Write sequence
431 * [ stat 3 ] <- [0x00000001] 4 <- triggers interrupt on receiver
432 * [ stat 2 ] <- [0x00000002] 3
433 * [ stat 1 ] <- [0x00000003] 2
434 * [ stat 0 ] <- [0x00000004] 1
436 * data += 4 // Increment data pointer by number of stat regs
439 * stat reg To write Write sequence
440 * [ stat 3 ] <- [0x00000005] 2 <- triggers interrupt on receiver
441 * [ stat 2 ] <- [0x00000006] 1
442 * [ stat 1 ] <- [0x00000000]
443 * [ stat 0 ] <- [0x00000000]
445 static int mhuv2_data_transfer_send_data(struct mhuv2
*mhu
,
446 struct mbox_chan
*chan
, void *arg
)
448 const struct arm_mhuv2_mbox_msg
*msg
= arg
;
449 int bytes_left
= msg
->len
, bytes_to_send
, bytes_in_round
, i
;
450 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
451 int windows
= priv
->windows
;
452 u32
*data
= msg
->data
, word
;
456 dev_err(mhu
->mbox
.dev
, "Data aligned at first window can't be zero to guarantee interrupt generation at receiver");
460 while(!mhuv2_data_transfer_last_tx_done(mhu
, chan
))
463 bytes_in_round
= min(bytes_left
, (int)(windows
* MHUV2_STAT_BYTES
));
465 for (i
= windows
- 1; i
>= 0; i
--) {
466 /* Data less than windows can transfer ? */
467 if (unlikely(bytes_in_round
<= i
* MHUV2_STAT_BYTES
))
471 bytes_to_send
= bytes_in_round
& (MHUV2_STAT_BYTES
- 1);
472 if (unlikely(bytes_to_send
))
473 word
&= LSB_MASK(bytes_to_send
);
475 bytes_to_send
= MHUV2_STAT_BYTES
;
477 writel_relaxed(word
, &mhu
->send
->ch_wn
[priv
->ch_wn_idx
+ windows
- 1 - i
].stat_set
);
478 bytes_left
-= bytes_to_send
;
479 bytes_in_round
-= bytes_to_send
;
488 static const struct mhuv2_protocol_ops mhuv2_data_transfer_ops
= {
489 .rx_startup
= mhuv2_data_transfer_rx_startup
,
490 .rx_shutdown
= mhuv2_data_transfer_rx_shutdown
,
491 .read_data
= mhuv2_data_transfer_read_data
,
492 .tx_startup
= mhuv2_data_transfer_tx_startup
,
493 .tx_shutdown
= mhuv2_data_transfer_tx_shutdown
,
494 .last_tx_done
= mhuv2_data_transfer_last_tx_done
,
495 .send_data
= mhuv2_data_transfer_send_data
,
498 /* Interrupt handlers */
500 static struct mbox_chan
*get_irq_chan_comb(struct mhuv2
*mhu
, u32 __iomem
*reg
)
502 struct mbox_chan
*chans
= mhu
->mbox
.chans
;
503 int channel
= 0, i
, j
, offset
= 0, windows
, protocol
, ch_wn
;
506 for (i
= 0; i
< MHUV2_CMB_INT_ST_REG_CNT
; i
++) {
507 stat
= readl_relaxed(reg
+ i
);
511 ch_wn
= i
* MHUV2_STAT_BITS
+ __builtin_ctz(stat
);
513 for (j
= 0; j
< mhu
->length
; j
+= 2) {
514 protocol
= mhu
->protocols
[j
];
515 windows
= mhu
->protocols
[j
+ 1];
517 if (ch_wn
>= offset
+ windows
) {
518 if (protocol
== DOORBELL
)
519 channel
+= MHUV2_STAT_BITS
* windows
;
527 /* Return first chan of the window in doorbell mode */
528 if (protocol
== DOORBELL
)
529 channel
+= MHUV2_STAT_BITS
* (ch_wn
- offset
);
531 return &chans
[channel
];
535 return ERR_PTR(-EIO
);
538 static irqreturn_t
mhuv2_sender_interrupt(int irq
, void *data
)
540 struct mhuv2
*mhu
= data
;
541 struct device
*dev
= mhu
->mbox
.dev
;
542 struct mhuv2_mbox_chan_priv
*priv
;
543 struct mbox_chan
*chan
;
548 chan
= get_irq_chan_comb(mhu
, mhu
->send
->chcomb_int_st
);
550 dev_warn(dev
, "Failed to find channel for the Tx interrupt\n");
553 priv
= chan
->con_priv
;
555 if (!IS_PROTOCOL_DOORBELL(priv
)) {
556 for (i
= 0; i
< priv
->windows
; i
++)
557 writel_relaxed(1, &mhu
->send
->ch_wn
[priv
->ch_wn_idx
+ i
].int_clr
);
560 mbox_chan_txdone(chan
, 0);
564 dev_warn(dev
, "Tx interrupt Received on channel (%u) not currently attached to a mailbox client\n",
569 /* Clear the interrupt first, so we don't miss any doorbell later */
570 writel_relaxed(1, &mhu
->send
->ch_wn
[priv
->ch_wn_idx
].int_clr
);
573 * In Doorbell mode, make sure no new transitions happen while the
574 * interrupt handler is trying to find the finished doorbell tx
575 * operations, else we may think few of the transfers were complete
576 * before they actually were.
578 spin_lock_irqsave(&mhu
->doorbell_pending_lock
, flags
);
581 * In case of doorbell mode, the first channel of the window is returned
582 * by get_irq_chan_comb(). Find all the pending channels here.
584 stat
= readl_relaxed(&mhu
->send
->ch_wn
[priv
->ch_wn_idx
].stat
);
586 for (i
= 0; i
< MHUV2_STAT_BITS
; i
++) {
587 priv
= chan
[i
].con_priv
;
589 /* Find cases where pending was 1, but stat's bit is cleared */
590 if (priv
->pending
^ ((stat
>> i
) & 0x1)) {
591 BUG_ON(!priv
->pending
);
594 dev_warn(dev
, "Tx interrupt received on doorbell (%u : %u) channel not currently attached to a mailbox client\n",
599 mbox_chan_txdone(&chan
[i
], 0);
605 spin_unlock_irqrestore(&mhu
->doorbell_pending_lock
, flags
);
609 * We may have already processed the doorbell in the previous
610 * iteration if the interrupt came right after we cleared it but
611 * before we read the stat register.
613 dev_dbg(dev
, "Couldn't find the doorbell (%u) for the Tx interrupt interrupt\n",
621 static struct mbox_chan
*get_irq_chan_comb_rx(struct mhuv2
*mhu
)
623 struct mhuv2_mbox_chan_priv
*priv
;
624 struct mbox_chan
*chan
;
627 chan
= get_irq_chan_comb(mhu
, mhu
->recv
->chcomb_int_st
);
631 priv
= chan
->con_priv
;
632 if (!IS_PROTOCOL_DOORBELL(priv
))
636 * In case of doorbell mode, the first channel of the window is returned
637 * by the routine. Find the exact channel here.
639 stat
= readl_relaxed(&mhu
->recv
->ch_wn
[priv
->ch_wn_idx
].stat_masked
);
642 return chan
+ __builtin_ctz(stat
);
645 static struct mbox_chan
*get_irq_chan_stat_rx(struct mhuv2
*mhu
)
647 struct mbox_chan
*chans
= mhu
->mbox
.chans
;
648 struct mhuv2_mbox_chan_priv
*priv
;
652 while (i
< mhu
->mbox
.num_chans
) {
653 priv
= chans
[i
].con_priv
;
654 stat
= readl_relaxed(&mhu
->recv
->ch_wn
[priv
->ch_wn_idx
].stat_masked
);
657 if (IS_PROTOCOL_DOORBELL(priv
))
658 i
+= __builtin_ctz(stat
);
662 i
+= IS_PROTOCOL_DOORBELL(priv
) ? MHUV2_STAT_BITS
: 1;
665 return ERR_PTR(-EIO
);
668 static struct mbox_chan
*get_irq_chan_rx(struct mhuv2
*mhu
)
671 return get_irq_chan_stat_rx(mhu
);
673 return get_irq_chan_comb_rx(mhu
);
676 static irqreturn_t
mhuv2_receiver_interrupt(int irq
, void *arg
)
678 struct mhuv2
*mhu
= arg
;
679 struct mbox_chan
*chan
= get_irq_chan_rx(mhu
);
680 struct device
*dev
= mhu
->mbox
.dev
;
681 struct mhuv2_mbox_chan_priv
*priv
;
686 dev_warn(dev
, "Failed to find channel for the rx interrupt\n");
689 priv
= chan
->con_priv
;
691 /* Read and clear the data first */
692 data
= priv
->ops
->read_data(mhu
, chan
);
695 dev_warn(dev
, "Received data on channel (%u) not currently attached to a mailbox client\n",
697 } else if (IS_ERR(data
)) {
698 dev_err(dev
, "Failed to read data: %lu\n", PTR_ERR(data
));
700 mbox_chan_received_data(chan
, data
);
710 /* Sender and receiver ops */
711 static bool mhuv2_sender_last_tx_done(struct mbox_chan
*chan
)
713 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
714 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
716 return priv
->ops
->last_tx_done(mhu
, chan
);
719 static int mhuv2_sender_send_data(struct mbox_chan
*chan
, void *data
)
721 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
722 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
724 if (!priv
->ops
->last_tx_done(mhu
, chan
))
727 return priv
->ops
->send_data(mhu
, chan
, data
);
730 static int mhuv2_sender_startup(struct mbox_chan
*chan
)
732 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
733 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
735 if (priv
->ops
->tx_startup
)
736 priv
->ops
->tx_startup(mhu
, chan
);
740 static void mhuv2_sender_shutdown(struct mbox_chan
*chan
)
742 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
743 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
745 if (priv
->ops
->tx_shutdown
)
746 priv
->ops
->tx_shutdown(mhu
, chan
);
749 static const struct mbox_chan_ops mhuv2_sender_ops
= {
750 .send_data
= mhuv2_sender_send_data
,
751 .startup
= mhuv2_sender_startup
,
752 .shutdown
= mhuv2_sender_shutdown
,
753 .last_tx_done
= mhuv2_sender_last_tx_done
,
756 static int mhuv2_receiver_startup(struct mbox_chan
*chan
)
758 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
759 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
761 return priv
->ops
->rx_startup(mhu
, chan
);
764 static void mhuv2_receiver_shutdown(struct mbox_chan
*chan
)
766 struct mhuv2
*mhu
= mhu_from_mbox(chan
->mbox
);
767 struct mhuv2_mbox_chan_priv
*priv
= chan
->con_priv
;
769 priv
->ops
->rx_shutdown(mhu
, chan
);
772 static int mhuv2_receiver_send_data(struct mbox_chan
*chan
, void *data
)
774 dev_err(chan
->mbox
->dev
,
775 "Trying to transmit on a receiver MHU frame\n");
779 static bool mhuv2_receiver_last_tx_done(struct mbox_chan
*chan
)
781 dev_err(chan
->mbox
->dev
, "Trying to Tx poll on a receiver MHU frame\n");
785 static const struct mbox_chan_ops mhuv2_receiver_ops
= {
786 .send_data
= mhuv2_receiver_send_data
,
787 .startup
= mhuv2_receiver_startup
,
788 .shutdown
= mhuv2_receiver_shutdown
,
789 .last_tx_done
= mhuv2_receiver_last_tx_done
,
792 static struct mbox_chan
*mhuv2_mbox_of_xlate(struct mbox_controller
*mbox
,
793 const struct of_phandle_args
*pa
)
795 struct mhuv2
*mhu
= mhu_from_mbox(mbox
);
796 struct mbox_chan
*chans
= mbox
->chans
;
797 int channel
= 0, i
, offset
, doorbell
, protocol
, windows
;
799 if (pa
->args_count
!= 2)
800 return ERR_PTR(-EINVAL
);
802 offset
= pa
->args
[0];
803 doorbell
= pa
->args
[1];
804 if (doorbell
>= MHUV2_STAT_BITS
)
807 for (i
= 0; i
< mhu
->length
; i
+= 2) {
808 protocol
= mhu
->protocols
[i
];
809 windows
= mhu
->protocols
[i
+ 1];
811 if (protocol
== DOORBELL
) {
812 if (offset
< windows
)
813 return &chans
[channel
+ MHUV2_STAT_BITS
* offset
+ doorbell
];
815 channel
+= MHUV2_STAT_BITS
* windows
;
822 return &chans
[channel
];
831 dev_err(mbox
->dev
, "Couldn't xlate to a valid channel (%d: %d)\n",
832 pa
->args
[0], doorbell
);
833 return ERR_PTR(-ENODEV
);
836 static int mhuv2_verify_protocol(struct mhuv2
*mhu
)
838 struct device
*dev
= mhu
->mbox
.dev
;
839 int protocol
, windows
, channels
= 0, total_windows
= 0, i
;
841 for (i
= 0; i
< mhu
->length
; i
+= 2) {
842 protocol
= mhu
->protocols
[i
];
843 windows
= mhu
->protocols
[i
+ 1];
846 dev_err(dev
, "Window size can't be zero (%d)\n", i
);
849 total_windows
+= windows
;
851 if (protocol
== DOORBELL
) {
852 channels
+= MHUV2_STAT_BITS
* windows
;
853 } else if (protocol
== DATA_TRANSFER
) {
856 dev_err(dev
, "Invalid protocol (%d) present in %s property at index %d\n",
857 protocol
, MHUV2_PROTOCOL_PROP
, i
);
862 if (total_windows
> mhu
->windows
) {
863 dev_err(dev
, "Channel windows can't be more than what's implemented by the hardware ( %d: %d)\n",
864 total_windows
, mhu
->windows
);
868 mhu
->mbox
.num_chans
= channels
;
872 static int mhuv2_allocate_channels(struct mhuv2
*mhu
)
874 struct mbox_controller
*mbox
= &mhu
->mbox
;
875 struct mhuv2_mbox_chan_priv
*priv
;
876 struct device
*dev
= mbox
->dev
;
877 struct mbox_chan
*chans
;
878 int protocol
, windows
= 0, next_window
= 0, i
, j
, k
;
880 chans
= devm_kcalloc(dev
, mbox
->num_chans
, sizeof(*chans
), GFP_KERNEL
);
886 for (i
= 0; i
< mhu
->length
; i
+= 2) {
887 next_window
+= windows
;
889 protocol
= mhu
->protocols
[i
];
890 windows
= mhu
->protocols
[i
+ 1];
892 if (protocol
== DATA_TRANSFER
) {
893 priv
= devm_kmalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
897 priv
->ch_wn_idx
= next_window
;
898 priv
->ops
= &mhuv2_data_transfer_ops
;
899 priv
->windows
= windows
;
900 chans
++->con_priv
= priv
;
904 for (j
= 0; j
< windows
; j
++) {
905 for (k
= 0; k
< MHUV2_STAT_BITS
; k
++) {
906 priv
= devm_kmalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
910 priv
->ch_wn_idx
= next_window
+ j
;
911 priv
->ops
= &mhuv2_doorbell_ops
;
913 chans
++->con_priv
= priv
;
917 * Permanently enable interrupt as we can't
918 * control it per doorbell.
920 if (mhu
->frame
== SENDER_FRAME
&& mhu
->minor
)
921 writel_relaxed(0x1, &mhu
->send
->ch_wn
[priv
->ch_wn_idx
].int_en
);
925 /* Make sure we have initialized all channels */
926 BUG_ON(chans
- mbox
->chans
!= mbox
->num_chans
);
931 static int mhuv2_parse_channels(struct mhuv2
*mhu
)
933 struct device
*dev
= mhu
->mbox
.dev
;
934 const struct device_node
*np
= dev
->of_node
;
938 count
= of_property_count_u32_elems(np
, MHUV2_PROTOCOL_PROP
);
939 if (count
<= 0 || count
% 2) {
940 dev_err(dev
, "Invalid %s property (%d)\n", MHUV2_PROTOCOL_PROP
,
945 protocols
= devm_kmalloc_array(dev
, count
, sizeof(*protocols
), GFP_KERNEL
);
949 ret
= of_property_read_u32_array(np
, MHUV2_PROTOCOL_PROP
, protocols
, count
);
951 dev_err(dev
, "Failed to read %s property: %d\n",
952 MHUV2_PROTOCOL_PROP
, ret
);
956 mhu
->protocols
= protocols
;
959 ret
= mhuv2_verify_protocol(mhu
);
963 return mhuv2_allocate_channels(mhu
);
966 static int mhuv2_tx_init(struct amba_device
*adev
, struct mhuv2
*mhu
,
969 struct device
*dev
= mhu
->mbox
.dev
;
972 mhu
->frame
= SENDER_FRAME
;
973 mhu
->mbox
.ops
= &mhuv2_sender_ops
;
976 mhu
->windows
= readl_relaxed_bitfield(&mhu
->send
->mhu_cfg
, struct mhu_cfg_t
, num_ch
);
977 mhu
->minor
= readl_relaxed_bitfield(&mhu
->send
->aidr
, struct aidr_t
, arch_minor_rev
);
979 spin_lock_init(&mhu
->doorbell_pending_lock
);
982 * For minor version 1 and forward, tx interrupt is provided by
985 if (mhu
->minor
&& adev
->irq
[0]) {
986 ret
= devm_request_threaded_irq(dev
, adev
->irq
[0], NULL
,
987 mhuv2_sender_interrupt
,
988 IRQF_ONESHOT
, "mhuv2-tx", mhu
);
990 dev_err(dev
, "Failed to request tx IRQ, fallback to polling mode: %d\n",
993 mhu
->mbox
.txdone_irq
= true;
994 mhu
->mbox
.txdone_poll
= false;
995 mhu
->irq
= adev
->irq
[0];
997 writel_relaxed_bitfield(1, &mhu
->send
->int_en
, struct int_en_t
, chcomb
);
999 /* Disable all channel interrupts */
1000 for (i
= 0; i
< mhu
->windows
; i
++)
1001 writel_relaxed(0x0, &mhu
->send
->ch_wn
[i
].int_en
);
1007 mhu
->mbox
.txdone_irq
= false;
1008 mhu
->mbox
.txdone_poll
= true;
1009 mhu
->mbox
.txpoll_period
= 1;
1012 /* Wait for receiver to be ready */
1013 writel_relaxed(0x1, &mhu
->send
->access_request
);
1014 while (!readl_relaxed(&mhu
->send
->access_ready
))
1020 static int mhuv2_rx_init(struct amba_device
*adev
, struct mhuv2
*mhu
,
1023 struct device
*dev
= mhu
->mbox
.dev
;
1026 mhu
->frame
= RECEIVER_FRAME
;
1027 mhu
->mbox
.ops
= &mhuv2_receiver_ops
;
1030 mhu
->windows
= readl_relaxed_bitfield(&mhu
->recv
->mhu_cfg
, struct mhu_cfg_t
, num_ch
);
1031 mhu
->minor
= readl_relaxed_bitfield(&mhu
->recv
->aidr
, struct aidr_t
, arch_minor_rev
);
1033 mhu
->irq
= adev
->irq
[0];
1035 dev_err(dev
, "Missing receiver IRQ\n");
1039 ret
= devm_request_threaded_irq(dev
, mhu
->irq
, NULL
,
1040 mhuv2_receiver_interrupt
, IRQF_ONESHOT
,
1043 dev_err(dev
, "Failed to request rx IRQ\n");
1047 /* Mask all the channel windows */
1048 for (i
= 0; i
< mhu
->windows
; i
++)
1049 writel_relaxed(0xFFFFFFFF, &mhu
->recv
->ch_wn
[i
].mask_set
);
1052 writel_relaxed_bitfield(1, &mhu
->recv
->int_en
, struct int_en_t
, chcomb
);
1057 static int mhuv2_probe(struct amba_device
*adev
, const struct amba_id
*id
)
1059 struct device
*dev
= &adev
->dev
;
1060 const struct device_node
*np
= dev
->of_node
;
1065 reg
= devm_of_iomap(dev
, dev
->of_node
, 0, NULL
);
1067 return PTR_ERR(reg
);
1069 mhu
= devm_kzalloc(dev
, sizeof(*mhu
), GFP_KERNEL
);
1073 mhu
->mbox
.dev
= dev
;
1074 mhu
->mbox
.of_xlate
= mhuv2_mbox_of_xlate
;
1076 if (of_device_is_compatible(np
, "arm,mhuv2-tx"))
1077 ret
= mhuv2_tx_init(adev
, mhu
, reg
);
1078 else if (of_device_is_compatible(np
, "arm,mhuv2-rx"))
1079 ret
= mhuv2_rx_init(adev
, mhu
, reg
);
1081 dev_err(dev
, "Invalid compatible property\n");
1086 /* Channel windows can't be 0 */
1087 BUG_ON(!mhu
->windows
);
1089 ret
= mhuv2_parse_channels(mhu
);
1093 amba_set_drvdata(adev
, mhu
);
1095 ret
= devm_mbox_controller_register(dev
, &mhu
->mbox
);
1097 dev_err(dev
, "failed to register ARM MHUv2 driver %d\n", ret
);
1102 static void mhuv2_remove(struct amba_device
*adev
)
1104 struct mhuv2
*mhu
= amba_get_drvdata(adev
);
1106 if (mhu
->frame
== SENDER_FRAME
)
1107 writel_relaxed(0x0, &mhu
->send
->access_request
);
1110 static struct amba_id mhuv2_ids
[] = {
1123 MODULE_DEVICE_TABLE(amba
, mhuv2_ids
);
1125 static struct amba_driver mhuv2_driver
= {
1127 .name
= "arm-mhuv2",
1129 .id_table
= mhuv2_ids
,
1130 .probe
= mhuv2_probe
,
1131 .remove
= mhuv2_remove
,
1133 module_amba_driver(mhuv2_driver
);
1135 MODULE_LICENSE("GPL v2");
1136 MODULE_DESCRIPTION("ARM MHUv2 Driver");
1137 MODULE_AUTHOR("Viresh Kumar <viresh.kumar@linaro.org>");
1138 MODULE_AUTHOR("Tushar Khandelwal <tushar.khandelwal@arm.com>");