drivers/media/pci/ddbridge/ddbridge-regs.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  * ddbridge-regs.h: Digital Devices PCIe bridge driver
   4  *
   5  * Copyright (C) 2010-2017 Digital Devices GmbH
   6  */
   7
   8 #ifndef __DDBRIDGE_REGS_H__
   9 #define __DDBRIDGE_REGS_H__
  10
  11 /* ------------------------------------------------------------------------- */
  12 /* SPI Controller */
  13
  14 #define SPI_CONTROL     0x10
  15 #define SPI_DATA        0x14
  16
  17 /* ------------------------------------------------------------------------- */
  18 /* GPIO */
  19
  20 #define GPIO_OUTPUT      0x20
  21 #define GPIO_INPUT       0x24
  22 #define GPIO_DIRECTION   0x28
  23
  24 /* ------------------------------------------------------------------------- */
  25
  26 #define BOARD_CONTROL    0x30
  27
  28 /* ------------------------------------------------------------------------- */
  29
  30 /* Interrupt controller
  31  * How many MSI's are available depends on HW (Min 2 max 8)
  32  * How many are usable also depends on Host platform
  33  */
  34
  35 #define INTERRUPT_BASE   (0x40)
  36
  37 #define INTERRUPT_ENABLE (INTERRUPT_BASE + 0x00)
  38 #define MSI1_ENABLE      (INTERRUPT_BASE + 0x04)
  39 #define MSI2_ENABLE      (INTERRUPT_BASE + 0x08)
  40 #define MSI3_ENABLE      (INTERRUPT_BASE + 0x0C)
  41 #define MSI4_ENABLE      (INTERRUPT_BASE + 0x10)
  42 #define MSI5_ENABLE      (INTERRUPT_BASE + 0x14)
  43 #define MSI6_ENABLE      (INTERRUPT_BASE + 0x18)
  44 #define MSI7_ENABLE      (INTERRUPT_BASE + 0x1C)
  45
  46 #define INTERRUPT_STATUS (INTERRUPT_BASE + 0x20)
  47 #define INTERRUPT_ACK    (INTERRUPT_BASE + 0x20)
  48
  49 /* Temperature Monitor ( 2x LM75A @ 0x90,0x92 I2c ) */
  50 #define TEMPMON_BASE                    (0x1c0)
  51 #define TEMPMON_CONTROL                 (TEMPMON_BASE + 0x00)
  52
  53 #define TEMPMON_CONTROL_AUTOSCAN        (0x00000002)
  54 #define TEMPMON_CONTROL_INTENABLE       (0x00000004)
  55 #define TEMPMON_CONTROL_OVERTEMP        (0x00008000)
  56
  57 /* SHORT Temperature in Celsius x 256 */
  58 #define TEMPMON_SENSOR0                 (TEMPMON_BASE + 0x04)
  59 #define TEMPMON_SENSOR1                 (TEMPMON_BASE + 0x08)
  60
  61 #define TEMPMON_FANCONTROL              (TEMPMON_BASE + 0x10)
  62
  63 /* ------------------------------------------------------------------------- */
  64 /* I2C Master Controller */
  65
  66 #define I2C_COMMAND     (0x00)
  67 #define I2C_TIMING      (0x04)
  68 #define I2C_TASKLENGTH  (0x08)     /* High read, low write */
  69 #define I2C_TASKADDRESS (0x0C)     /* High read, low write */
  70 #define I2C_MONITOR     (0x1C)
  71
  72 #define I2C_SPEED_400   (0x04030404)
  73 #define I2C_SPEED_100   (0x13121313)
  74
  75 /* ------------------------------------------------------------------------- */
  76 /* DMA  Controller */
  77
  78 #define DMA_BASE_WRITE        (0x100)
  79 #define DMA_BASE_READ         (0x140)
  80
  81 #define TS_CONTROL(_io)         ((_io)->regs + 0x00)
  82 #define TS_CONTROL2(_io)        ((_io)->regs + 0x04)
  83
  84 /* ------------------------------------------------------------------------- */
  85 /* DMA  Buffer */
  86
  87 #define DMA_BUFFER_CONTROL(_dma)       ((_dma)->regs + 0x00)
  88 #define DMA_BUFFER_ACK(_dma)           ((_dma)->regs + 0x04)
  89 #define DMA_BUFFER_CURRENT(_dma)       ((_dma)->regs + 0x08)
  90 #define DMA_BUFFER_SIZE(_dma)          ((_dma)->regs + 0x0c)
  91
  92 /* ------------------------------------------------------------------------- */
  93 /* CI Interface (only CI-Bridge) */
  94
  95 #define CI_BASE                         (0x400)
  96 #define CI_CONTROL(i)                   (CI_BASE + (i) * 32 + 0x00)
  97
  98 #define CI_DO_ATTRIBUTE_RW(i)           (CI_BASE + (i) * 32 + 0x04)
  99 #define CI_DO_IO_RW(i)                  (CI_BASE + (i) * 32 + 0x08)
 100 #define CI_READDATA(i)                  (CI_BASE + (i) * 32 + 0x0c)
 101 #define CI_DO_READ_ATTRIBUTES(i)        (CI_BASE + (i) * 32 + 0x10)
 102
 103 #define CI_RESET_CAM                    (0x00000001)
 104 #define CI_POWER_ON                     (0x00000002)
 105 #define CI_ENABLE                       (0x00000004)
 106 #define CI_BYPASS_DISABLE               (0x00000010)
 107
 108 #define CI_CAM_READY                    (0x00010000)
 109 #define CI_CAM_DETECT                   (0x00020000)
 110 #define CI_READY                        (0x80000000)
 111
 112 #define CI_READ_CMD                     (0x40000000)
 113 #define CI_WRITE_CMD                    (0x80000000)
 114
 115 #define CI_BUFFER_BASE                  (0x3000)
 116 #define CI_BUFFER_SIZE                  (0x0800)
 117
 118 #define CI_BUFFER(i)                    (CI_BUFFER_BASE + (i) * CI_BUFFER_SIZE)
 119
 120 /* ------------------------------------------------------------------------- */
 121 /* LNB commands (mxl5xx / Max S8) */
 122
 123 #define LNB_BASE                        (0x400)
 124 #define LNB_CONTROL(i)                  (LNB_BASE + (i) * 0x20 + 0x00)
 125
 126 #define LNB_CMD                         (7ULL << 0)
 127 #define LNB_CMD_NOP                     0
 128 #define LNB_CMD_INIT                    1
 129 #define LNB_CMD_LOW                     3
 130 #define LNB_CMD_HIGH                    4
 131 #define LNB_CMD_OFF                     5
 132 #define LNB_CMD_DISEQC                  6
 133
 134 #define LNB_BUSY                        BIT_ULL(4)
 135 #define LNB_TONE                        BIT_ULL(15)
 136
 137 #define LNB_BUF_LEVEL(i)                (LNB_BASE + (i) * 0x20 + 0x10)
 138 #define LNB_BUF_WRITE(i)                (LNB_BASE + (i) * 0x20 + 0x14)
 139
 140 #endif /* __DDBRIDGE_REGS_H__ */