drm/panel: panel-himax-hx83102: support for csot-pna957qt1-1 MIPI-DSI panel
[drm/drm-misc.git] / drivers / media / platform / qcom / camss / camss-ispif.c
blob2dc585c6123dd248a5bacd9c7a88cb5375644311
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * camss-ispif.c
5 * Qualcomm MSM Camera Subsystem - ISPIF (ISP Interface) Module
7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
8 * Copyright (C) 2015-2018 Linaro Ltd.
9 */
10 #include <linux/clk.h>
11 #include <linux/completion.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/iopoll.h>
15 #include <linux/kernel.h>
16 #include <linux/mutex.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <media/media-entity.h>
20 #include <media/v4l2-device.h>
21 #include <media/v4l2-subdev.h>
23 #include "camss-ispif.h"
24 #include "camss.h"
26 #define MSM_ISPIF_NAME "msm_ispif"
28 #define ISPIF_RST_CMD_0 0x008
29 #define ISPIF_RST_CMD_1 0x00c
30 #define ISPIF_RST_CMD_0_STROBED_RST_EN (1 << 0)
31 #define ISPIF_RST_CMD_0_MISC_LOGIC_RST (1 << 1)
32 #define ISPIF_RST_CMD_0_SW_REG_RST (1 << 2)
33 #define ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST (1 << 3)
34 #define ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST (1 << 4)
35 #define ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST (1 << 5)
36 #define ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST (1 << 6)
37 #define ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST (1 << 7)
38 #define ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST (1 << 8)
39 #define ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST (1 << 9)
40 #define ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST (1 << 10)
41 #define ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST (1 << 11)
42 #define ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST (1 << 12)
43 #define ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST (1 << 16)
44 #define ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST (1 << 17)
45 #define ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST (1 << 18)
46 #define ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST (1 << 19)
47 #define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c
48 #define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))
49 #define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6)
50 #define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))
51 #define ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE 0x00001249
52 #define ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK 0x00001fff
53 #define ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE 0x02492000
54 #define ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK 0x03ffe000
55 #define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))
56 #define ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE 0x00001249
57 #define ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK 0x00001fff
58 #define ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE 0x02492000
59 #define ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK 0x03ffe000
60 #define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))
61 #define ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE 0x00001249
62 #define ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK 0x00001fff
63 #define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))
64 #define ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW (1 << 12)
65 #define ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW (1 << 25)
66 #define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))
67 #define ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW (1 << 12)
68 #define ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW (1 << 25)
69 #define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))
70 #define ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW (1 << 12)
71 #define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))
72 #define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m))
73 #define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m))
74 #define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m))
75 #define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m))
76 #define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m))
77 #define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) \
78 (0x254 + 0x200 * (m) + 0x4 * (n))
79 #define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) \
80 (0x264 + 0x200 * (m) + 0x4 * (n))
81 /* PACK_CFG registers are 8x96 only */
82 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(m, n) \
83 (0x270 + 0x200 * (m) + 0x4 * (n))
84 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(m, n) \
85 (0x27c + 0x200 * (m) + 0x4 * (n))
86 #define ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(c) \
87 (1 << ((cid % 8) * 4))
88 #define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) \
89 (0x2c0 + 0x200 * (m) + 0x4 * (n))
90 #define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) \
91 (0x2d0 + 0x200 * (m) + 0x4 * (n))
93 #define CSI_PIX_CLK_MUX_SEL 0x000
94 #define CSI_RDI_CLK_MUX_SEL 0x008
96 #define ISPIF_TIMEOUT_SLEEP_US 1000
97 #define ISPIF_TIMEOUT_ALL_US 1000000
98 #define ISPIF_RESET_TIMEOUT_MS 500
100 enum ispif_intf_cmd {
101 CMD_DISABLE_FRAME_BOUNDARY = 0x0,
102 CMD_ENABLE_FRAME_BOUNDARY = 0x1,
103 CMD_DISABLE_IMMEDIATELY = 0x2,
104 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa,
105 CMD_ALL_NO_CHANGE = 0xffffffff,
108 static const u32 ispif_formats_8x16[] = {
109 MEDIA_BUS_FMT_UYVY8_1X16,
110 MEDIA_BUS_FMT_VYUY8_1X16,
111 MEDIA_BUS_FMT_YUYV8_1X16,
112 MEDIA_BUS_FMT_YVYU8_1X16,
113 MEDIA_BUS_FMT_SBGGR8_1X8,
114 MEDIA_BUS_FMT_SGBRG8_1X8,
115 MEDIA_BUS_FMT_SGRBG8_1X8,
116 MEDIA_BUS_FMT_SRGGB8_1X8,
117 MEDIA_BUS_FMT_SBGGR10_1X10,
118 MEDIA_BUS_FMT_SGBRG10_1X10,
119 MEDIA_BUS_FMT_SGRBG10_1X10,
120 MEDIA_BUS_FMT_SRGGB10_1X10,
121 MEDIA_BUS_FMT_SBGGR12_1X12,
122 MEDIA_BUS_FMT_SGBRG12_1X12,
123 MEDIA_BUS_FMT_SGRBG12_1X12,
124 MEDIA_BUS_FMT_SRGGB12_1X12,
125 MEDIA_BUS_FMT_Y10_1X10,
128 static const u32 ispif_formats_8x96[] = {
129 MEDIA_BUS_FMT_UYVY8_1X16,
130 MEDIA_BUS_FMT_VYUY8_1X16,
131 MEDIA_BUS_FMT_YUYV8_1X16,
132 MEDIA_BUS_FMT_YVYU8_1X16,
133 MEDIA_BUS_FMT_SBGGR8_1X8,
134 MEDIA_BUS_FMT_SGBRG8_1X8,
135 MEDIA_BUS_FMT_SGRBG8_1X8,
136 MEDIA_BUS_FMT_SRGGB8_1X8,
137 MEDIA_BUS_FMT_SBGGR10_1X10,
138 MEDIA_BUS_FMT_SGBRG10_1X10,
139 MEDIA_BUS_FMT_SGRBG10_1X10,
140 MEDIA_BUS_FMT_SRGGB10_1X10,
141 MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE,
142 MEDIA_BUS_FMT_SBGGR12_1X12,
143 MEDIA_BUS_FMT_SGBRG12_1X12,
144 MEDIA_BUS_FMT_SGRBG12_1X12,
145 MEDIA_BUS_FMT_SRGGB12_1X12,
146 MEDIA_BUS_FMT_SBGGR14_1X14,
147 MEDIA_BUS_FMT_SGBRG14_1X14,
148 MEDIA_BUS_FMT_SGRBG14_1X14,
149 MEDIA_BUS_FMT_SRGGB14_1X14,
150 MEDIA_BUS_FMT_Y10_1X10,
151 MEDIA_BUS_FMT_Y10_2X8_PADHI_LE,
155 * ispif_isr_8x96 - ISPIF module interrupt handler for 8x96
156 * @irq: Interrupt line
157 * @dev: ISPIF device
159 * Return IRQ_HANDLED on success
161 static irqreturn_t ispif_isr_8x96(int irq, void *dev)
163 struct ispif_device *ispif = dev;
164 struct camss *camss = ispif->camss;
165 u32 value0, value1, value2, value3, value4, value5;
167 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
168 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
169 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
170 value3 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(1));
171 value4 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(1));
172 value5 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(1));
174 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
175 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
176 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
177 writel_relaxed(value3, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(1));
178 writel_relaxed(value4, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(1));
179 writel_relaxed(value5, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(1));
181 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
183 if ((value0 >> 27) & 0x1)
184 complete(&ispif->reset_complete[0]);
186 if ((value3 >> 27) & 0x1)
187 complete(&ispif->reset_complete[1]);
189 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
190 dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");
192 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
193 dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");
195 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
196 dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");
198 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
199 dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");
201 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
202 dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");
204 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
205 dev_err_ratelimited(camss->dev, "VFE1 pix0 overflow\n");
207 if (unlikely(value3 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
208 dev_err_ratelimited(camss->dev, "VFE1 rdi0 overflow\n");
210 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
211 dev_err_ratelimited(camss->dev, "VFE1 pix1 overflow\n");
213 if (unlikely(value4 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
214 dev_err_ratelimited(camss->dev, "VFE1 rdi1 overflow\n");
216 if (unlikely(value5 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
217 dev_err_ratelimited(camss->dev, "VFE1 rdi2 overflow\n");
219 return IRQ_HANDLED;
223 * ispif_isr_8x16 - ISPIF module interrupt handler for 8x16
224 * @irq: Interrupt line
225 * @dev: ISPIF device
227 * Return IRQ_HANDLED on success
229 static irqreturn_t ispif_isr_8x16(int irq, void *dev)
231 struct ispif_device *ispif = dev;
232 struct camss *camss = ispif->camss;
233 u32 value0, value1, value2;
235 value0 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
236 value1 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
237 value2 = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
239 writel_relaxed(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
240 writel_relaxed(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
241 writel_relaxed(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
243 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
245 if ((value0 >> 27) & 0x1)
246 complete(&ispif->reset_complete[0]);
248 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_PIX0_OVERFLOW))
249 dev_err_ratelimited(camss->dev, "VFE0 pix0 overflow\n");
251 if (unlikely(value0 & ISPIF_VFE_m_IRQ_STATUS_0_RDI0_OVERFLOW))
252 dev_err_ratelimited(camss->dev, "VFE0 rdi0 overflow\n");
254 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_PIX1_OVERFLOW))
255 dev_err_ratelimited(camss->dev, "VFE0 pix1 overflow\n");
257 if (unlikely(value1 & ISPIF_VFE_m_IRQ_STATUS_1_RDI1_OVERFLOW))
258 dev_err_ratelimited(camss->dev, "VFE0 rdi1 overflow\n");
260 if (unlikely(value2 & ISPIF_VFE_m_IRQ_STATUS_2_RDI2_OVERFLOW))
261 dev_err_ratelimited(camss->dev, "VFE0 rdi2 overflow\n");
263 return IRQ_HANDLED;
266 static int ispif_vfe_reset(struct ispif_device *ispif, u8 vfe_id)
268 struct camss *camss = ispif->camss;
270 unsigned long time;
271 u32 val;
273 if (vfe_id >= camss->res->vfe_num) {
274 dev_err(camss->dev,
275 "Error: asked reset for invalid VFE%d\n", vfe_id);
276 return -ENOENT;
279 reinit_completion(&ispif->reset_complete[vfe_id]);
281 val = ISPIF_RST_CMD_0_STROBED_RST_EN |
282 ISPIF_RST_CMD_0_MISC_LOGIC_RST |
283 ISPIF_RST_CMD_0_SW_REG_RST |
284 ISPIF_RST_CMD_0_PIX_INTF_0_CSID_RST |
285 ISPIF_RST_CMD_0_PIX_INTF_0_VFE_RST |
286 ISPIF_RST_CMD_0_PIX_INTF_1_CSID_RST |
287 ISPIF_RST_CMD_0_PIX_INTF_1_VFE_RST |
288 ISPIF_RST_CMD_0_RDI_INTF_0_CSID_RST |
289 ISPIF_RST_CMD_0_RDI_INTF_0_VFE_RST |
290 ISPIF_RST_CMD_0_RDI_INTF_1_CSID_RST |
291 ISPIF_RST_CMD_0_RDI_INTF_1_VFE_RST |
292 ISPIF_RST_CMD_0_RDI_INTF_2_CSID_RST |
293 ISPIF_RST_CMD_0_RDI_INTF_2_VFE_RST |
294 ISPIF_RST_CMD_0_PIX_OUTPUT_0_MISR_RST |
295 ISPIF_RST_CMD_0_RDI_OUTPUT_0_MISR_RST |
296 ISPIF_RST_CMD_0_RDI_OUTPUT_1_MISR_RST |
297 ISPIF_RST_CMD_0_RDI_OUTPUT_2_MISR_RST;
299 if (vfe_id == 1)
300 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_1);
301 else
302 writel_relaxed(val, ispif->base + ISPIF_RST_CMD_0);
304 time = wait_for_completion_timeout(&ispif->reset_complete[vfe_id],
305 msecs_to_jiffies(ISPIF_RESET_TIMEOUT_MS));
306 if (!time) {
307 dev_err(camss->dev,
308 "ISPIF for VFE%d reset timeout\n", vfe_id);
309 return -EIO;
312 return 0;
316 * ispif_reset - Trigger reset on ISPIF module and wait to complete
317 * @ispif: ISPIF device
319 * Return 0 on success or a negative error code otherwise
321 static int ispif_reset(struct ispif_device *ispif, u8 vfe_id)
323 struct camss *camss = ispif->camss;
324 int ret;
326 ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE0);
327 if (ret < 0)
328 return ret;
330 ret = camss_pm_domain_on(camss, PM_DOMAIN_VFE1);
331 if (ret < 0)
332 return ret;
334 ret = camss_enable_clocks(ispif->nclocks_for_reset,
335 ispif->clock_for_reset,
336 camss->dev);
337 if (ret < 0)
338 return ret;
340 ret = ispif_vfe_reset(ispif, vfe_id);
341 if (ret)
342 dev_dbg(camss->dev, "ISPIF Reset failed\n");
344 camss_disable_clocks(ispif->nclocks_for_reset, ispif->clock_for_reset);
346 camss_pm_domain_off(camss, PM_DOMAIN_VFE0);
347 camss_pm_domain_off(camss, PM_DOMAIN_VFE1);
349 return ret;
353 * ispif_set_power - Power on/off ISPIF module
354 * @sd: ISPIF V4L2 subdevice
355 * @on: Requested power state
357 * Return 0 on success or a negative error code otherwise
359 static int ispif_set_power(struct v4l2_subdev *sd, int on)
361 struct ispif_line *line = v4l2_get_subdevdata(sd);
362 struct ispif_device *ispif = line->ispif;
363 struct device *dev = ispif->camss->dev;
364 int ret = 0;
366 mutex_lock(&ispif->power_lock);
368 if (on) {
369 if (ispif->power_count) {
370 /* Power is already on */
371 ispif->power_count++;
372 goto exit;
375 ret = pm_runtime_resume_and_get(dev);
376 if (ret < 0)
377 goto exit;
379 ret = camss_enable_clocks(ispif->nclocks, ispif->clock, dev);
380 if (ret < 0) {
381 pm_runtime_put_sync(dev);
382 goto exit;
385 ret = ispif_reset(ispif, line->vfe_id);
386 if (ret < 0) {
387 pm_runtime_put_sync(dev);
388 camss_disable_clocks(ispif->nclocks, ispif->clock);
389 goto exit;
392 ispif->intf_cmd[line->vfe_id].cmd_0 = CMD_ALL_NO_CHANGE;
393 ispif->intf_cmd[line->vfe_id].cmd_1 = CMD_ALL_NO_CHANGE;
395 ispif->power_count++;
396 } else {
397 if (ispif->power_count == 0) {
398 dev_err(dev, "ispif power off on power_count == 0\n");
399 goto exit;
400 } else if (ispif->power_count == 1) {
401 camss_disable_clocks(ispif->nclocks, ispif->clock);
402 pm_runtime_put_sync(dev);
405 ispif->power_count--;
408 exit:
409 mutex_unlock(&ispif->power_lock);
411 return ret;
415 * ispif_select_clk_mux - Select clock for PIX/RDI interface
416 * @ispif: ISPIF device
417 * @intf: VFE interface
418 * @csid: CSID HW module id
419 * @vfe: VFE HW module id
420 * @enable: enable or disable the selected clock
422 static void ispif_select_clk_mux(struct ispif_device *ispif,
423 enum ispif_intf intf, u8 csid,
424 u8 vfe, u8 enable)
426 u32 val;
428 switch (intf) {
429 case PIX0:
430 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
431 val &= ~(0xf << (vfe * 8));
432 if (enable)
433 val |= (csid << (vfe * 8));
434 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
435 break;
437 case RDI0:
438 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
439 val &= ~(0xf << (vfe * 12));
440 if (enable)
441 val |= (csid << (vfe * 12));
442 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
443 break;
445 case PIX1:
446 val = readl_relaxed(ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
447 val &= ~(0xf << (4 + (vfe * 8)));
448 if (enable)
449 val |= (csid << (4 + (vfe * 8)));
450 writel_relaxed(val, ispif->base_clk_mux + CSI_PIX_CLK_MUX_SEL);
451 break;
453 case RDI1:
454 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
455 val &= ~(0xf << (4 + (vfe * 12)));
456 if (enable)
457 val |= (csid << (4 + (vfe * 12)));
458 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
459 break;
461 case RDI2:
462 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
463 val &= ~(0xf << (8 + (vfe * 12)));
464 if (enable)
465 val |= (csid << (8 + (vfe * 12)));
466 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
467 break;
470 mb();
474 * ispif_validate_intf_status - Validate current status of PIX/RDI interface
475 * @ispif: ISPIF device
476 * @intf: VFE interface
477 * @vfe: VFE HW module id
479 * Return 0 when interface is idle or -EBUSY otherwise
481 static int ispif_validate_intf_status(struct ispif_device *ispif,
482 enum ispif_intf intf, u8 vfe)
484 int ret = 0;
485 u32 val = 0;
487 switch (intf) {
488 case PIX0:
489 val = readl_relaxed(ispif->base +
490 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));
491 break;
492 case RDI0:
493 val = readl_relaxed(ispif->base +
494 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));
495 break;
496 case PIX1:
497 val = readl_relaxed(ispif->base +
498 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));
499 break;
500 case RDI1:
501 val = readl_relaxed(ispif->base +
502 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));
503 break;
504 case RDI2:
505 val = readl_relaxed(ispif->base +
506 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));
507 break;
510 if ((val & 0xf) != 0xf) {
511 dev_err(ispif->camss->dev, "%s: ispif is busy: 0x%x\n",
512 __func__, val);
513 ret = -EBUSY;
516 return ret;
520 * ispif_wait_for_stop - Wait for PIX/RDI interface to stop
521 * @ispif: ISPIF device
522 * @intf: VFE interface
523 * @vfe: VFE HW module id
525 * Return 0 on success or a negative error code otherwise
527 static int ispif_wait_for_stop(struct ispif_device *ispif,
528 enum ispif_intf intf, u8 vfe)
530 u32 addr = 0;
531 u32 stop_flag = 0;
532 int ret;
534 switch (intf) {
535 case PIX0:
536 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0);
537 break;
538 case RDI0:
539 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0);
540 break;
541 case PIX1:
542 addr = ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1);
543 break;
544 case RDI1:
545 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1);
546 break;
547 case RDI2:
548 addr = ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2);
549 break;
552 ret = readl_poll_timeout(ispif->base + addr,
553 stop_flag,
554 (stop_flag & 0xf) == 0xf,
555 ISPIF_TIMEOUT_SLEEP_US,
556 ISPIF_TIMEOUT_ALL_US);
557 if (ret < 0)
558 dev_err(ispif->camss->dev, "%s: ispif stop timeout\n",
559 __func__);
561 return ret;
565 * ispif_select_csid - Select CSID HW module for input from
566 * @ispif: ISPIF device
567 * @intf: VFE interface
568 * @csid: CSID HW module id
569 * @vfe: VFE HW module id
570 * @enable: enable or disable the selected input
572 static void ispif_select_csid(struct ispif_device *ispif, enum ispif_intf intf,
573 u8 csid, u8 vfe, u8 enable)
575 u32 val;
577 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
578 switch (intf) {
579 case PIX0:
580 val &= ~(BIT(1) | BIT(0));
581 if (enable)
582 val |= csid;
583 break;
584 case RDI0:
585 val &= ~(BIT(5) | BIT(4));
586 if (enable)
587 val |= (csid << 4);
588 break;
589 case PIX1:
590 val &= ~(BIT(9) | BIT(8));
591 if (enable)
592 val |= (csid << 8);
593 break;
594 case RDI1:
595 val &= ~(BIT(13) | BIT(12));
596 if (enable)
597 val |= (csid << 12);
598 break;
599 case RDI2:
600 val &= ~(BIT(21) | BIT(20));
601 if (enable)
602 val |= (csid << 20);
603 break;
606 writel(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
610 * ispif_select_cid - Enable/disable desired CID
611 * @ispif: ISPIF device
612 * @intf: VFE interface
613 * @cid: desired CID to enable/disable
614 * @vfe: VFE HW module id
615 * @enable: enable or disable the desired CID
617 static void ispif_select_cid(struct ispif_device *ispif, enum ispif_intf intf,
618 u8 cid, u8 vfe, u8 enable)
620 u32 cid_mask = 1 << cid;
621 u32 addr = 0;
622 u32 val;
624 switch (intf) {
625 case PIX0:
626 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);
627 break;
628 case RDI0:
629 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);
630 break;
631 case PIX1:
632 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);
633 break;
634 case RDI1:
635 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);
636 break;
637 case RDI2:
638 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);
639 break;
642 val = readl_relaxed(ispif->base + addr);
643 if (enable)
644 val |= cid_mask;
645 else
646 val &= ~cid_mask;
648 writel(val, ispif->base + addr);
652 * ispif_config_irq - Enable/disable interrupts for PIX/RDI interface
653 * @ispif: ISPIF device
654 * @intf: VFE interface
655 * @vfe: VFE HW module id
656 * @enable: enable or disable
658 static void ispif_config_irq(struct ispif_device *ispif, enum ispif_intf intf,
659 u8 vfe, u8 enable)
661 u32 val;
663 switch (intf) {
664 case PIX0:
665 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
666 val &= ~ISPIF_VFE_m_IRQ_MASK_0_PIX0_MASK;
667 if (enable)
668 val |= ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE;
669 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
670 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_PIX0_ENABLE,
671 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
672 break;
673 case RDI0:
674 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
675 val &= ~ISPIF_VFE_m_IRQ_MASK_0_RDI0_MASK;
676 if (enable)
677 val |= ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE;
678 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
679 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_0_RDI0_ENABLE,
680 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
681 break;
682 case PIX1:
683 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
684 val &= ~ISPIF_VFE_m_IRQ_MASK_1_PIX1_MASK;
685 if (enable)
686 val |= ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE;
687 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
688 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_PIX1_ENABLE,
689 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
690 break;
691 case RDI1:
692 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
693 val &= ~ISPIF_VFE_m_IRQ_MASK_1_RDI1_MASK;
694 if (enable)
695 val |= ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE;
696 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
697 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_1_RDI1_ENABLE,
698 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
699 break;
700 case RDI2:
701 val = readl_relaxed(ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
702 val &= ~ISPIF_VFE_m_IRQ_MASK_2_RDI2_MASK;
703 if (enable)
704 val |= ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE;
705 writel_relaxed(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
706 writel_relaxed(ISPIF_VFE_m_IRQ_MASK_2_RDI2_ENABLE,
707 ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));
708 break;
711 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
715 * ispif_config_pack - Config packing for PRDI mode
716 * @ispif: ISPIF device
717 * @code: media bus format code
718 * @intf: VFE interface
719 * @cid: desired CID to handle
720 * @vfe: VFE HW module id
721 * @enable: enable or disable
723 static void ispif_config_pack(struct ispif_device *ispif, u32 code,
724 enum ispif_intf intf, u8 cid, u8 vfe, u8 enable)
726 u32 addr, val;
728 if (code != MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE &&
729 code != MEDIA_BUS_FMT_Y10_2X8_PADHI_LE)
730 return;
732 switch (intf) {
733 case RDI0:
734 if (cid < 8)
735 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 0);
736 else
737 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 0);
738 break;
739 case RDI1:
740 if (cid < 8)
741 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 1);
742 else
743 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 1);
744 break;
745 case RDI2:
746 if (cid < 8)
747 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0(vfe, 2);
748 else
749 addr = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_1(vfe, 2);
750 break;
751 default:
752 return;
755 if (enable)
756 val = ISPIF_VFE_m_RDI_INTF_n_PACK_CFG_0_CID_c_PLAIN(cid);
757 else
758 val = 0;
760 writel_relaxed(val, ispif->base + addr);
764 * ispif_set_intf_cmd - Set command to enable/disable interface
765 * @ispif: ISPIF device
766 * @cmd: interface command
767 * @intf: VFE interface
768 * @vfe: VFE HW module id
769 * @vc: virtual channel
771 static void ispif_set_intf_cmd(struct ispif_device *ispif, u8 cmd,
772 enum ispif_intf intf, u8 vfe, u8 vc)
774 u32 *val;
776 if (intf == RDI2) {
777 val = &ispif->intf_cmd[vfe].cmd_1;
778 *val &= ~(0x3 << (vc * 2 + 8));
779 *val |= (cmd << (vc * 2 + 8));
780 wmb();
781 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
782 wmb();
783 } else {
784 val = &ispif->intf_cmd[vfe].cmd_0;
785 *val &= ~(0x3 << (vc * 2 + intf * 8));
786 *val |= (cmd << (vc * 2 + intf * 8));
787 wmb();
788 writel_relaxed(*val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
789 wmb();
794 * ispif_set_stream - Enable/disable streaming on ISPIF module
795 * @sd: ISPIF V4L2 subdevice
796 * @enable: Requested streaming state
798 * Main configuration of ISPIF module is also done here.
800 * Return 0 on success or a negative error code otherwise
802 static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
804 struct ispif_line *line = v4l2_get_subdevdata(sd);
805 struct ispif_device *ispif = line->ispif;
806 struct camss *camss = ispif->camss;
807 enum ispif_intf intf = line->interface;
808 u8 csid = line->csid_id;
809 u8 vfe = line->vfe_id;
810 u8 vc = 0; /* Virtual Channel 0 */
811 u8 cid = vc * 4; /* id of Virtual Channel and Data Type set */
812 int ret;
814 if (enable) {
815 if (!media_pad_remote_pad_first(&line->pads[MSM_ISPIF_PAD_SINK]))
816 return -ENOLINK;
818 /* Config */
820 mutex_lock(&ispif->config_lock);
821 ispif_select_clk_mux(ispif, intf, csid, vfe, 1);
823 ret = ispif_validate_intf_status(ispif, intf, vfe);
824 if (ret < 0) {
825 mutex_unlock(&ispif->config_lock);
826 return ret;
829 ispif_select_csid(ispif, intf, csid, vfe, 1);
830 ispif_select_cid(ispif, intf, cid, vfe, 1);
831 ispif_config_irq(ispif, intf, vfe, 1);
832 if (camss->res->version == CAMSS_8x96 ||
833 camss->res->version == CAMSS_8x53 ||
834 camss->res->version == CAMSS_660)
835 ispif_config_pack(ispif,
836 line->fmt[MSM_ISPIF_PAD_SINK].code,
837 intf, cid, vfe, 1);
838 ispif_set_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY,
839 intf, vfe, vc);
840 } else {
841 mutex_lock(&ispif->config_lock);
842 ispif_set_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY,
843 intf, vfe, vc);
844 mutex_unlock(&ispif->config_lock);
846 ret = ispif_wait_for_stop(ispif, intf, vfe);
847 if (ret < 0)
848 return ret;
850 mutex_lock(&ispif->config_lock);
851 if (camss->res->version == CAMSS_8x96 ||
852 camss->res->version == CAMSS_8x53 ||
853 camss->res->version == CAMSS_660)
854 ispif_config_pack(ispif,
855 line->fmt[MSM_ISPIF_PAD_SINK].code,
856 intf, cid, vfe, 0);
857 ispif_config_irq(ispif, intf, vfe, 0);
858 ispif_select_cid(ispif, intf, cid, vfe, 0);
859 ispif_select_csid(ispif, intf, csid, vfe, 0);
860 ispif_select_clk_mux(ispif, intf, csid, vfe, 0);
863 mutex_unlock(&ispif->config_lock);
865 return 0;
869 * __ispif_get_format - Get pointer to format structure
870 * @ispif: ISPIF line
871 * @sd_state: V4L2 subdev state
872 * @pad: pad from which format is requested
873 * @which: TRY or ACTIVE format
875 * Return pointer to TRY or ACTIVE format structure
877 static struct v4l2_mbus_framefmt *
878 __ispif_get_format(struct ispif_line *line,
879 struct v4l2_subdev_state *sd_state,
880 unsigned int pad,
881 enum v4l2_subdev_format_whence which)
883 if (which == V4L2_SUBDEV_FORMAT_TRY)
884 return v4l2_subdev_state_get_format(sd_state, pad);
886 return &line->fmt[pad];
890 * ispif_try_format - Handle try format by pad subdev method
891 * @ispif: ISPIF line
892 * @sd_state: V4L2 subdev state
893 * @pad: pad on which format is requested
894 * @fmt: pointer to v4l2 format structure
895 * @which: wanted subdev format
897 static void ispif_try_format(struct ispif_line *line,
898 struct v4l2_subdev_state *sd_state,
899 unsigned int pad,
900 struct v4l2_mbus_framefmt *fmt,
901 enum v4l2_subdev_format_whence which)
903 unsigned int i;
905 switch (pad) {
906 case MSM_ISPIF_PAD_SINK:
907 /* Set format on sink pad */
909 for (i = 0; i < line->nformats; i++)
910 if (fmt->code == line->formats[i])
911 break;
913 /* If not found, use UYVY as default */
914 if (i >= line->nformats)
915 fmt->code = MEDIA_BUS_FMT_UYVY8_1X16;
917 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
918 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
920 fmt->field = V4L2_FIELD_NONE;
921 fmt->colorspace = V4L2_COLORSPACE_SRGB;
923 break;
925 case MSM_ISPIF_PAD_SRC:
926 /* Set and return a format same as sink pad */
928 *fmt = *__ispif_get_format(line, sd_state, MSM_ISPIF_PAD_SINK,
929 which);
931 break;
934 fmt->colorspace = V4L2_COLORSPACE_SRGB;
938 * ispif_enum_mbus_code - Handle pixel format enumeration
939 * @sd: ISPIF V4L2 subdevice
940 * @sd_state: V4L2 subdev state
941 * @code: pointer to v4l2_subdev_mbus_code_enum structure
942 * return -EINVAL or zero on success
944 static int ispif_enum_mbus_code(struct v4l2_subdev *sd,
945 struct v4l2_subdev_state *sd_state,
946 struct v4l2_subdev_mbus_code_enum *code)
948 struct ispif_line *line = v4l2_get_subdevdata(sd);
949 struct v4l2_mbus_framefmt *format;
951 if (code->pad == MSM_ISPIF_PAD_SINK) {
952 if (code->index >= line->nformats)
953 return -EINVAL;
955 code->code = line->formats[code->index];
956 } else {
957 if (code->index > 0)
958 return -EINVAL;
960 format = __ispif_get_format(line, sd_state,
961 MSM_ISPIF_PAD_SINK,
962 code->which);
964 code->code = format->code;
967 return 0;
971 * ispif_enum_frame_size - Handle frame size enumeration
972 * @sd: ISPIF V4L2 subdevice
973 * @sd_state: V4L2 subdev state
974 * @fse: pointer to v4l2_subdev_frame_size_enum structure
975 * return -EINVAL or zero on success
977 static int ispif_enum_frame_size(struct v4l2_subdev *sd,
978 struct v4l2_subdev_state *sd_state,
979 struct v4l2_subdev_frame_size_enum *fse)
981 struct ispif_line *line = v4l2_get_subdevdata(sd);
982 struct v4l2_mbus_framefmt format;
984 if (fse->index != 0)
985 return -EINVAL;
987 format.code = fse->code;
988 format.width = 1;
989 format.height = 1;
990 ispif_try_format(line, sd_state, fse->pad, &format, fse->which);
991 fse->min_width = format.width;
992 fse->min_height = format.height;
994 if (format.code != fse->code)
995 return -EINVAL;
997 format.code = fse->code;
998 format.width = -1;
999 format.height = -1;
1000 ispif_try_format(line, sd_state, fse->pad, &format, fse->which);
1001 fse->max_width = format.width;
1002 fse->max_height = format.height;
1004 return 0;
1008 * ispif_get_format - Handle get format by pads subdev method
1009 * @sd: ISPIF V4L2 subdevice
1010 * @sd_state: V4L2 subdev state
1011 * @fmt: pointer to v4l2 subdev format structure
1013 * Return -EINVAL or zero on success
1015 static int ispif_get_format(struct v4l2_subdev *sd,
1016 struct v4l2_subdev_state *sd_state,
1017 struct v4l2_subdev_format *fmt)
1019 struct ispif_line *line = v4l2_get_subdevdata(sd);
1020 struct v4l2_mbus_framefmt *format;
1022 format = __ispif_get_format(line, sd_state, fmt->pad, fmt->which);
1023 if (format == NULL)
1024 return -EINVAL;
1026 fmt->format = *format;
1028 return 0;
1032 * ispif_set_format - Handle set format by pads subdev method
1033 * @sd: ISPIF V4L2 subdevice
1034 * @sd_state: V4L2 subdev state
1035 * @fmt: pointer to v4l2 subdev format structure
1037 * Return -EINVAL or zero on success
1039 static int ispif_set_format(struct v4l2_subdev *sd,
1040 struct v4l2_subdev_state *sd_state,
1041 struct v4l2_subdev_format *fmt)
1043 struct ispif_line *line = v4l2_get_subdevdata(sd);
1044 struct v4l2_mbus_framefmt *format;
1046 format = __ispif_get_format(line, sd_state, fmt->pad, fmt->which);
1047 if (format == NULL)
1048 return -EINVAL;
1050 ispif_try_format(line, sd_state, fmt->pad, &fmt->format, fmt->which);
1051 *format = fmt->format;
1053 /* Propagate the format from sink to source */
1054 if (fmt->pad == MSM_ISPIF_PAD_SINK) {
1055 format = __ispif_get_format(line, sd_state, MSM_ISPIF_PAD_SRC,
1056 fmt->which);
1058 *format = fmt->format;
1059 ispif_try_format(line, sd_state, MSM_ISPIF_PAD_SRC, format,
1060 fmt->which);
1063 return 0;
1067 * ispif_init_formats - Initialize formats on all pads
1068 * @sd: ISPIF V4L2 subdevice
1069 * @fh: V4L2 subdev file handle
1071 * Initialize all pad formats with default values.
1073 * Return 0 on success or a negative error code otherwise
1075 static int ispif_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1077 struct v4l2_subdev_format format = {
1078 .pad = MSM_ISPIF_PAD_SINK,
1079 .which = fh ? V4L2_SUBDEV_FORMAT_TRY :
1080 V4L2_SUBDEV_FORMAT_ACTIVE,
1081 .format = {
1082 .code = MEDIA_BUS_FMT_UYVY8_1X16,
1083 .width = 1920,
1084 .height = 1080
1088 return ispif_set_format(sd, fh ? fh->state : NULL, &format);
1092 * msm_ispif_subdev_init - Initialize ISPIF device structure and resources
1093 * @ispif: ISPIF device
1094 * @res: ISPIF module resources table
1096 * Return 0 on success or a negative error code otherwise
1098 int msm_ispif_subdev_init(struct camss *camss,
1099 const struct camss_subdev_resources *res)
1101 struct device *dev = camss->dev;
1102 struct ispif_device *ispif = camss->ispif;
1103 struct platform_device *pdev = to_platform_device(dev);
1104 int i;
1105 int ret;
1107 if (!camss->ispif)
1108 return 0;
1110 ispif->camss = camss;
1112 /* Number of ISPIF lines - same as number of CSID hardware modules */
1113 if (camss->res->version == CAMSS_8x16)
1114 ispif->line_num = 2;
1115 else if (camss->res->version == CAMSS_8x96 ||
1116 camss->res->version == CAMSS_8x53 ||
1117 camss->res->version == CAMSS_660)
1118 ispif->line_num = 4;
1119 else
1120 return -EINVAL;
1122 ispif->line = devm_kcalloc(dev, ispif->line_num,
1123 sizeof(*ispif->line), GFP_KERNEL);
1124 if (!ispif->line)
1125 return -ENOMEM;
1127 for (i = 0; i < ispif->line_num; i++) {
1128 ispif->line[i].ispif = ispif;
1129 ispif->line[i].id = i;
1131 if (camss->res->version == CAMSS_8x16) {
1132 ispif->line[i].formats = ispif_formats_8x16;
1133 ispif->line[i].nformats =
1134 ARRAY_SIZE(ispif_formats_8x16);
1135 } else if (camss->res->version == CAMSS_8x96 ||
1136 camss->res->version == CAMSS_8x53 ||
1137 camss->res->version == CAMSS_660) {
1138 ispif->line[i].formats = ispif_formats_8x96;
1139 ispif->line[i].nformats =
1140 ARRAY_SIZE(ispif_formats_8x96);
1141 } else {
1142 return -EINVAL;
1146 /* Memory */
1148 ispif->base = devm_platform_ioremap_resource_byname(pdev, res->reg[0]);
1149 if (IS_ERR(ispif->base))
1150 return PTR_ERR(ispif->base);
1152 ispif->base_clk_mux = devm_platform_ioremap_resource_byname(pdev, res->reg[1]);
1153 if (IS_ERR(ispif->base_clk_mux))
1154 return PTR_ERR(ispif->base_clk_mux);
1156 /* Interrupt */
1158 ret = platform_get_irq_byname(pdev, res->interrupt[0]);
1159 if (ret < 0)
1160 return ret;
1162 ispif->irq = ret;
1163 snprintf(ispif->irq_name, sizeof(ispif->irq_name), "%s_%s",
1164 dev_name(dev), MSM_ISPIF_NAME);
1165 if (camss->res->version == CAMSS_8x16)
1166 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x16,
1167 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1168 else if (camss->res->version == CAMSS_8x96 ||
1169 camss->res->version == CAMSS_8x53 ||
1170 camss->res->version == CAMSS_660)
1171 ret = devm_request_irq(dev, ispif->irq, ispif_isr_8x96,
1172 IRQF_TRIGGER_RISING, ispif->irq_name, ispif);
1173 else
1174 ret = -EINVAL;
1176 if (ret < 0) {
1177 dev_err(dev, "request_irq failed: %d\n", ret);
1178 return ret;
1181 /* Clocks */
1183 ispif->nclocks = 0;
1184 while (res->clock[ispif->nclocks])
1185 ispif->nclocks++;
1187 ispif->clock = devm_kcalloc(dev,
1188 ispif->nclocks, sizeof(*ispif->clock),
1189 GFP_KERNEL);
1190 if (!ispif->clock)
1191 return -ENOMEM;
1193 for (i = 0; i < ispif->nclocks; i++) {
1194 struct camss_clock *clock = &ispif->clock[i];
1196 clock->clk = devm_clk_get(dev, res->clock[i]);
1197 if (IS_ERR(clock->clk))
1198 return PTR_ERR(clock->clk);
1200 clock->freq = NULL;
1201 clock->nfreqs = 0;
1204 ispif->nclocks_for_reset = 0;
1205 while (res->clock_for_reset[ispif->nclocks_for_reset])
1206 ispif->nclocks_for_reset++;
1208 ispif->clock_for_reset = devm_kcalloc(dev,
1209 ispif->nclocks_for_reset,
1210 sizeof(*ispif->clock_for_reset),
1211 GFP_KERNEL);
1212 if (!ispif->clock_for_reset)
1213 return -ENOMEM;
1215 for (i = 0; i < ispif->nclocks_for_reset; i++) {
1216 struct camss_clock *clock = &ispif->clock_for_reset[i];
1218 clock->clk = devm_clk_get(dev, res->clock_for_reset[i]);
1219 if (IS_ERR(clock->clk))
1220 return PTR_ERR(clock->clk);
1222 clock->freq = NULL;
1223 clock->nfreqs = 0;
1226 mutex_init(&ispif->power_lock);
1227 ispif->power_count = 0;
1229 mutex_init(&ispif->config_lock);
1231 for (i = 0; i < MSM_ISPIF_VFE_NUM; i++)
1232 init_completion(&ispif->reset_complete[i]);
1234 return 0;
1238 * ispif_get_intf - Get ISPIF interface to use by VFE line id
1239 * @line_id: VFE line id that the ISPIF line is connected to
1241 * Return ISPIF interface to use
1243 static enum ispif_intf ispif_get_intf(enum vfe_line_id line_id)
1245 switch (line_id) {
1246 case (VFE_LINE_RDI0):
1247 return RDI0;
1248 case (VFE_LINE_RDI1):
1249 return RDI1;
1250 case (VFE_LINE_RDI2):
1251 return RDI2;
1252 case (VFE_LINE_PIX):
1253 return PIX0;
1254 default:
1255 return RDI0;
1260 * ispif_get_vfe_id - Get VFE HW module id
1261 * @entity: Pointer to VFE media entity structure
1262 * @id: Return CSID HW module id here
1264 static void ispif_get_vfe_id(struct media_entity *entity, u8 *id)
1266 struct v4l2_subdev *sd;
1267 struct vfe_line *line;
1268 struct vfe_device *vfe;
1270 sd = media_entity_to_v4l2_subdev(entity);
1271 line = v4l2_get_subdevdata(sd);
1272 vfe = to_vfe(line);
1274 *id = vfe->id;
1278 * ispif_get_vfe_line_id - Get VFE line id by media entity
1279 * @entity: Pointer to VFE media entity structure
1280 * @id: Return VFE line id here
1282 static void ispif_get_vfe_line_id(struct media_entity *entity,
1283 enum vfe_line_id *id)
1285 struct v4l2_subdev *sd;
1286 struct vfe_line *line;
1288 sd = media_entity_to_v4l2_subdev(entity);
1289 line = v4l2_get_subdevdata(sd);
1291 *id = line->id;
1295 * ispif_link_setup - Setup ISPIF connections
1296 * @entity: Pointer to media entity structure
1297 * @local: Pointer to local pad
1298 * @remote: Pointer to remote pad
1299 * @flags: Link flags
1301 * Return 0 on success
1303 static int ispif_link_setup(struct media_entity *entity,
1304 const struct media_pad *local,
1305 const struct media_pad *remote, u32 flags)
1307 if (flags & MEDIA_LNK_FL_ENABLED) {
1308 if (media_pad_remote_pad_first(local))
1309 return -EBUSY;
1311 if (local->flags & MEDIA_PAD_FL_SINK) {
1312 struct v4l2_subdev *sd;
1313 struct ispif_line *line;
1315 sd = media_entity_to_v4l2_subdev(entity);
1316 line = v4l2_get_subdevdata(sd);
1318 msm_csid_get_csid_id(remote->entity, &line->csid_id);
1319 } else { /* MEDIA_PAD_FL_SOURCE */
1320 struct v4l2_subdev *sd;
1321 struct ispif_line *line;
1322 enum vfe_line_id id;
1324 sd = media_entity_to_v4l2_subdev(entity);
1325 line = v4l2_get_subdevdata(sd);
1327 ispif_get_vfe_id(remote->entity, &line->vfe_id);
1328 ispif_get_vfe_line_id(remote->entity, &id);
1329 line->interface = ispif_get_intf(id);
1333 return 0;
1336 static const struct v4l2_subdev_core_ops ispif_core_ops = {
1337 .s_power = ispif_set_power,
1340 static const struct v4l2_subdev_video_ops ispif_video_ops = {
1341 .s_stream = ispif_set_stream,
1344 static const struct v4l2_subdev_pad_ops ispif_pad_ops = {
1345 .enum_mbus_code = ispif_enum_mbus_code,
1346 .enum_frame_size = ispif_enum_frame_size,
1347 .get_fmt = ispif_get_format,
1348 .set_fmt = ispif_set_format,
1351 static const struct v4l2_subdev_ops ispif_v4l2_ops = {
1352 .core = &ispif_core_ops,
1353 .video = &ispif_video_ops,
1354 .pad = &ispif_pad_ops,
1357 static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops = {
1358 .open = ispif_init_formats,
1361 static const struct media_entity_operations ispif_media_ops = {
1362 .link_setup = ispif_link_setup,
1363 .link_validate = v4l2_subdev_link_validate,
1367 * msm_ispif_register_entities - Register subdev node for ISPIF module
1368 * @ispif: ISPIF device
1369 * @v4l2_dev: V4L2 device
1371 * Return 0 on success or a negative error code otherwise
1373 int msm_ispif_register_entities(struct ispif_device *ispif,
1374 struct v4l2_device *v4l2_dev)
1376 struct camss *camss;
1377 int ret;
1378 int i;
1380 if (!ispif)
1381 return 0;
1383 camss = ispif->camss;
1385 for (i = 0; i < ispif->line_num; i++) {
1386 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1387 struct media_pad *pads = ispif->line[i].pads;
1389 v4l2_subdev_init(sd, &ispif_v4l2_ops);
1390 sd->internal_ops = &ispif_v4l2_internal_ops;
1391 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1392 snprintf(sd->name, ARRAY_SIZE(sd->name), "%s%d",
1393 MSM_ISPIF_NAME, i);
1394 v4l2_set_subdevdata(sd, &ispif->line[i]);
1396 ret = ispif_init_formats(sd, NULL);
1397 if (ret < 0) {
1398 dev_err(camss->dev, "Failed to init format: %d\n", ret);
1399 goto error;
1402 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
1403 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
1405 sd->entity.function = MEDIA_ENT_F_PROC_VIDEO_PIXEL_FORMATTER;
1406 sd->entity.ops = &ispif_media_ops;
1407 ret = media_entity_pads_init(&sd->entity, MSM_ISPIF_PADS_NUM,
1408 pads);
1409 if (ret < 0) {
1410 dev_err(camss->dev, "Failed to init media entity: %d\n",
1411 ret);
1412 goto error;
1415 ret = v4l2_device_register_subdev(v4l2_dev, sd);
1416 if (ret < 0) {
1417 dev_err(camss->dev, "Failed to register subdev: %d\n",
1418 ret);
1419 media_entity_cleanup(&sd->entity);
1420 goto error;
1424 return 0;
1426 error:
1427 for (i--; i >= 0; i--) {
1428 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1430 v4l2_device_unregister_subdev(sd);
1431 media_entity_cleanup(&sd->entity);
1434 return ret;
1438 * msm_ispif_unregister_entities - Unregister ISPIF module subdev node
1439 * @ispif: ISPIF device
1441 void msm_ispif_unregister_entities(struct ispif_device *ispif)
1443 int i;
1445 if (!ispif)
1446 return;
1448 mutex_destroy(&ispif->power_lock);
1449 mutex_destroy(&ispif->config_lock);
1451 for (i = 0; i < ispif->line_num; i++) {
1452 struct v4l2_subdev *sd = &ispif->line[i].subdev;
1454 v4l2_device_unregister_subdev(sd);
1455 media_entity_cleanup(&sd->entity);