drivers/media/platform/samsung/exynos4-is/fimc-is.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Samsung EXYNOS4x12 FIMC-IS (Imaging Subsystem) driver
   4  *
   5  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
   6  *
   7  * Authors: Younghwan Joo <yhwan.joo@samsung.com>
   8  *          Sylwester Nawrocki <s.nawrocki@samsung.com>
   9  */
  10 #ifndef FIMC_IS_H_
  11 #define FIMC_IS_H_
  12
  13 #include <asm/barrier.h>
  14 #include <linux/clk.h>
  15 #include <linux/device.h>
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/sizes.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/types.h>
  21 #include <media/videobuf2-v4l2.h>
  22 #include <media/v4l2-ctrls.h>
  23
  24 #include "fimc-isp.h"
  25 #include "fimc-is-command.h"
  26 #include "fimc-is-sensor.h"
  27 #include "fimc-is-param.h"
  28 #include "fimc-is-regs.h"
  29
  30 #define FIMC_IS_DRV_NAME                "exynos4-fimc-is"
  31
  32 #define FIMC_IS_FW_FILENAME             "exynos4_fimc_is_fw.bin"
  33 #define FIMC_IS_SETFILE_6A3             "exynos4_s5k6a3_setfile.bin"
  34
  35 #define FIMC_IS_FW_LOAD_TIMEOUT         1000 /* ms */
  36 #define FIMC_IS_POWER_ON_TIMEOUT        1000 /* us */
  37
  38 #define FIMC_IS_SENSORS_NUM             2
  39
  40 /* Memory definitions */
  41 #define FIMC_IS_CPU_MEM_SIZE            (0xa00000)
  42 #define FIMC_IS_CPU_BASE_MASK           ((1 << 26) - 1)
  43 #define FIMC_IS_REGION_SIZE             0x5000
  44
  45 #define FIMC_IS_DEBUG_REGION_OFFSET     0x0084b000
  46 #define FIMC_IS_SHARED_REGION_OFFSET    0x008c0000
  47 #define FIMC_IS_FW_INFO_LEN             31
  48 #define FIMC_IS_FW_VER_LEN              7
  49 #define FIMC_IS_FW_DESC_LEN             (FIMC_IS_FW_INFO_LEN + \
  50                                          FIMC_IS_FW_VER_LEN)
  51 #define FIMC_IS_SETFILE_INFO_LEN        39
  52
  53 #define FIMC_IS_EXTRA_MEM_SIZE          (FIMC_IS_EXTRA_FW_SIZE + \
  54                                          FIMC_IS_EXTRA_SETFILE_SIZE + 0x1000)
  55 #define FIMC_IS_EXTRA_FW_SIZE           0x180000
  56 #define FIMC_IS_EXTRA_SETFILE_SIZE      0x4b000
  57
  58 /* TODO: revisit */
  59 #define FIMC_IS_FW_ADDR_MASK            ((1 << 26) - 1)
  60 #define FIMC_IS_FW_SIZE_MAX             (SZ_4M)
  61 #define FIMC_IS_FW_SIZE_MIN             (SZ_32K)
  62
  63 #define ATCLK_MCUISP_FREQUENCY          100000000UL
  64 #define ACLK_AXI_FREQUENCY              100000000UL
  65
  66 enum {
  67         ISS_CLK_PPMUISPX,
  68         ISS_CLK_PPMUISPMX,
  69         ISS_CLK_LITE0,
  70         ISS_CLK_LITE1,
  71         ISS_CLK_MPLL,
  72         ISS_CLK_ISP,
  73         ISS_CLK_DRC,
  74         ISS_CLK_FD,
  75         ISS_CLK_MCUISP,
  76         ISS_CLK_GICISP,
  77         ISS_CLK_PWM_ISP,
  78         ISS_CLK_MCUCTL_ISP,
  79         ISS_CLK_UART,
  80         ISS_GATE_CLKS_MAX,
  81         ISS_CLK_ISP_DIV0 = ISS_GATE_CLKS_MAX,
  82         ISS_CLK_ISP_DIV1,
  83         ISS_CLK_MCUISP_DIV0,
  84         ISS_CLK_MCUISP_DIV1,
  85         ISS_CLK_ACLK200,
  86         ISS_CLK_ACLK200_DIV,
  87         ISS_CLK_ACLK400MCUISP,
  88         ISS_CLK_ACLK400MCUISP_DIV,
  89         ISS_CLKS_MAX
  90 };
  91
  92 /* The driver's internal state flags */
  93 enum {
  94         IS_ST_IDLE,
  95         IS_ST_PWR_ON,
  96         IS_ST_A5_PWR_ON,
  97         IS_ST_FW_LOADED,
  98         IS_ST_OPEN_SENSOR,
  99         IS_ST_SETFILE_LOADED,
 100         IS_ST_INIT_DONE,
 101         IS_ST_STREAM_ON,
 102         IS_ST_STREAM_OFF,
 103         IS_ST_CHANGE_MODE,
 104         IS_ST_BLOCK_CMD_CLEARED,
 105         IS_ST_SET_ZOOM,
 106         IS_ST_PWR_SUBIP_ON,
 107         IS_ST_END,
 108 };
 109
 110 enum af_state {
 111         FIMC_IS_AF_IDLE         = 0,
 112         FIMC_IS_AF_SETCONFIG    = 1,
 113         FIMC_IS_AF_RUNNING      = 2,
 114         FIMC_IS_AF_LOCK         = 3,
 115         FIMC_IS_AF_ABORT        = 4,
 116         FIMC_IS_AF_FAILED       = 5,
 117 };
 118
 119 enum af_lock_state {
 120         FIMC_IS_AF_UNLOCKED     = 0,
 121         FIMC_IS_AF_LOCKED       = 2
 122 };
 123
 124 enum ae_lock_state {
 125         FIMC_IS_AE_UNLOCKED     = 0,
 126         FIMC_IS_AE_LOCKED       = 1
 127 };
 128
 129 enum awb_lock_state {
 130         FIMC_IS_AWB_UNLOCKED    = 0,
 131         FIMC_IS_AWB_LOCKED      = 1
 132 };
 133
 134 enum {
 135         IS_METERING_CONFIG_CMD,
 136         IS_METERING_CONFIG_WIN_POS_X,
 137         IS_METERING_CONFIG_WIN_POS_Y,
 138         IS_METERING_CONFIG_WIN_WIDTH,
 139         IS_METERING_CONFIG_WIN_HEIGHT,
 140         IS_METERING_CONFIG_MAX
 141 };
 142
 143 struct is_setfile {
 144         const struct firmware *info;
 145         int state;
 146         u32 sub_index;
 147         u32 base;
 148         size_t size;
 149 };
 150
 151 struct is_fd_result_header {
 152         u32 offset;
 153         u32 count;
 154         u32 index;
 155         u32 curr_index;
 156         u32 width;
 157         u32 height;
 158 };
 159
 160 struct is_af_info {
 161         u16 mode;
 162         u32 af_state;
 163         u32 af_lock_state;
 164         u32 ae_lock_state;
 165         u32 awb_lock_state;
 166         u16 pos_x;
 167         u16 pos_y;
 168         u16 prev_pos_x;
 169         u16 prev_pos_y;
 170         u16 use_af;
 171 };
 172
 173 struct fimc_is_firmware {
 174         const struct firmware *f_w;
 175
 176         dma_addr_t addr;
 177         void *vaddr;
 178         unsigned int size;
 179
 180         char info[FIMC_IS_FW_INFO_LEN + 1];
 181         char version[FIMC_IS_FW_VER_LEN + 1];
 182         char setfile_info[FIMC_IS_SETFILE_INFO_LEN + 1];
 183         u8 state;
 184 };
 185
 186 struct fimc_is_memory {
 187         /* DMA base address */
 188         dma_addr_t addr;
 189         /* virtual base address */
 190         void *vaddr;
 191         /* total length */
 192         unsigned int size;
 193 };
 194
 195 #define FIMC_IS_I2H_MAX_ARGS    12
 196
 197 struct i2h_cmd {
 198         u32 cmd;
 199         u32 sensor_id;
 200         u16 num_args;
 201         u32 args[FIMC_IS_I2H_MAX_ARGS];
 202 };
 203
 204 struct h2i_cmd {
 205         u16 cmd_type;
 206         u32 entry_id;
 207 };
 208
 209 #define FIMC_IS_DEBUG_MSG       0x3f
 210 #define FIMC_IS_DEBUG_LEVEL     3
 211
 212 struct fimc_is_setfile {
 213         const struct firmware *info;
 214         unsigned int state;
 215         unsigned int size;
 216         u32 sub_index;
 217         u32 base;
 218 };
 219
 220 struct chain_config {
 221         struct global_param     global;
 222         struct sensor_param     sensor;
 223         struct isp_param        isp;
 224         struct drc_param        drc;
 225         struct fd_param         fd;
 226
 227         unsigned long           p_region_index[2];
 228 };
 229
 230 /**
 231  * struct fimc_is - fimc-is data structure
 232  * @pdev: pointer to FIMC-IS platform device
 233  * @v4l2_dev: pointer to the top level v4l2_device
 234  * @fw: data structure describing the FIMC-IS firmware binary
 235  * @memory: memory region assigned for the FIMC-IS (firmware)
 236  * @isp: the ISP block data structure
 237  * @sensor: fimc-is sensor subdevice array
 238  * @setfile: descriptor of the imaging pipeline calibration data
 239  * @ctrl_handler: the v4l2 controls handler
 240  * @lock: mutex serializing video device and the subdev operations
 241  * @slock: spinlock protecting this data structure and the hw registers
 242  * @clocks: FIMC-LITE gate clock
 243  * @regs: MCUCTL mmapped registers region
 244  * @pmu_regs: PMU ISP mmapped registers region
 245  * @irq: FIMC-IS interrupt
 246  * @irq_queue: interrupt handling waitqueue
 247  * @lpm: low power mode flag
 248  * @state: internal driver's state flags
 249  * @sensor_index: image sensor index for the firmware
 250  * @i2h_cmd: FIMC-IS to the host (CPU) mailbox command data structure
 251  * @h2i_cmd: the host (CPU) to FIMC-IS mailbox command data structure
 252  * @fd_header: the face detection result data structure
 253  * @config: shared HW pipeline configuration data
 254  * @config_index: index to the @config entry currently in use
 255  * @is_p_region: pointer to the shared parameter memory region
 256  * @is_dma_p_region: DMA address of the shared parameter memory region
 257  * @is_shared_region: pointer to the IS shared region data structure
 258  * @af: auto focus data
 259  * @debugfs_entry: debugfs entry for the firmware log
 260  */
 261 struct fimc_is {
 262         struct platform_device          *pdev;
 263         struct v4l2_device              *v4l2_dev;
 264
 265         struct fimc_is_firmware         fw;
 266         struct fimc_is_memory           memory;
 267
 268         struct fimc_isp                 isp;
 269         struct fimc_is_sensor           sensor[FIMC_IS_SENSORS_NUM];
 270         struct fimc_is_setfile          setfile;
 271
 272         struct v4l2_ctrl_handler        ctrl_handler;
 273
 274         struct mutex                    lock;
 275         spinlock_t                      slock;
 276
 277         struct clk                      *clocks[ISS_CLKS_MAX];
 278         void __iomem                    *regs;
 279         void __iomem                    *pmu_regs;
 280         int                             irq;
 281         wait_queue_head_t               irq_queue;
 282         u8                              lpm;
 283
 284         unsigned long                   state;
 285         unsigned int                    sensor_index;
 286
 287         struct i2h_cmd                  i2h_cmd;
 288         struct h2i_cmd                  h2i_cmd;
 289         struct is_fd_result_header      fd_header;
 290
 291         struct chain_config             config[IS_SC_MAX];
 292         unsigned                        config_index;
 293
 294         struct is_region                *is_p_region;
 295         dma_addr_t                      is_dma_p_region;
 296         struct is_share_region          *is_shared_region;
 297         struct is_af_info               af;
 298
 299         struct dentry                   *debugfs_entry;
 300 };
 301
 302 static inline struct fimc_is *fimc_isp_to_is(struct fimc_isp *isp)
 303 {
 304         return container_of(isp, struct fimc_is, isp);
 305 }
 306
 307 static inline struct chain_config *__get_curr_is_config(struct fimc_is *is)
 308 {
 309         return &is->config[is->config_index];
 310 }
 311
 312 static inline void fimc_is_mem_barrier(void)
 313 {
 314         mb();
 315 }
 316
 317 static inline void fimc_is_set_param_bit(struct fimc_is *is, int num)
 318 {
 319         struct chain_config *cfg = &is->config[is->config_index];
 320
 321         set_bit(num, &cfg->p_region_index[0]);
 322 }
 323
 324 static inline void fimc_is_set_param_ctrl_cmd(struct fimc_is *is, int cmd)
 325 {
 326         is->is_p_region->parameter.isp.control.cmd = cmd;
 327 }
 328
 329 static inline void mcuctl_write(u32 v, struct fimc_is *is, unsigned int offset)
 330 {
 331         writel(v, is->regs + offset);
 332 }
 333
 334 static inline u32 mcuctl_read(struct fimc_is *is, unsigned int offset)
 335 {
 336         return readl(is->regs + offset);
 337 }
 338
 339 static inline void pmuisp_write(u32 v, struct fimc_is *is, unsigned int offset)
 340 {
 341         writel(v, is->pmu_regs + offset);
 342 }
 343
 344 static inline u32 pmuisp_read(struct fimc_is *is, unsigned int offset)
 345 {
 346         return readl(is->pmu_regs + offset);
 347 }
 348
 349 int fimc_is_wait_event(struct fimc_is *is, unsigned long bit,
 350                        unsigned int state, unsigned int timeout);
 351 int fimc_is_cpu_set_power(struct fimc_is *is, int on);
 352 int fimc_is_start_firmware(struct fimc_is *is);
 353 int fimc_is_hw_initialize(struct fimc_is *is);
 354 void fimc_is_log_dump(const char *level, const void *buf, size_t len);
 355
 356 #endif /* FIMC_IS_H_ */