1 // SPDX-License-Identifier: GPL-2.0-only
3 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
5 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
8 #include <linux/module.h>
9 #include <linux/delay.h>
10 #include <linux/mmc/mmc.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/pm_opp.h>
13 #include <linux/slab.h>
14 #include <linux/iopoll.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/interconnect.h>
18 #include <linux/pinctrl/consumer.h>
19 #include <linux/reset.h>
21 #include <soc/qcom/ice.h>
23 #include "sdhci-cqhci.h"
24 #include "sdhci-pltfm.h"
27 #define CORE_MCI_VERSION 0x50
28 #define CORE_VERSION_MAJOR_SHIFT 28
29 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
30 #define CORE_VERSION_MINOR_MASK 0xff
32 #define CORE_MCI_GENERICS 0x70
33 #define SWITCHABLE_SIGNALING_VOLTAGE BIT(29)
35 #define HC_MODE_EN 0x1
36 #define CORE_POWER 0x0
37 #define CORE_SW_RST BIT(7)
38 #define FF_CLK_SW_RST_DIS BIT(13)
40 #define CORE_PWRCTL_BUS_OFF BIT(0)
41 #define CORE_PWRCTL_BUS_ON BIT(1)
42 #define CORE_PWRCTL_IO_LOW BIT(2)
43 #define CORE_PWRCTL_IO_HIGH BIT(3)
44 #define CORE_PWRCTL_BUS_SUCCESS BIT(0)
45 #define CORE_PWRCTL_BUS_FAIL BIT(1)
46 #define CORE_PWRCTL_IO_SUCCESS BIT(2)
47 #define CORE_PWRCTL_IO_FAIL BIT(3)
48 #define REQ_BUS_OFF BIT(0)
49 #define REQ_BUS_ON BIT(1)
50 #define REQ_IO_LOW BIT(2)
51 #define REQ_IO_HIGH BIT(3)
54 #define CORE_DLL_LOCK BIT(7)
55 #define CORE_DDR_DLL_LOCK BIT(11)
56 #define CORE_DLL_EN BIT(16)
57 #define CORE_CDR_EN BIT(17)
58 #define CORE_CK_OUT_EN BIT(18)
59 #define CORE_CDR_EXT_EN BIT(19)
60 #define CORE_DLL_PDN BIT(29)
61 #define CORE_DLL_RST BIT(30)
62 #define CORE_CMD_DAT_TRACK_SEL BIT(0)
64 #define CORE_DDR_CAL_EN BIT(0)
65 #define CORE_FLL_CYCLE_CNT BIT(18)
66 #define CORE_DLL_CLOCK_DISABLE BIT(21)
68 #define DLL_USR_CTL_POR_VAL 0x10800
69 #define ENABLE_DLL_LOCK_STATUS BIT(26)
70 #define FINE_TUNE_MODE_EN BIT(27)
71 #define BIAS_OK_SIGNAL BIT(29)
73 #define DLL_CONFIG_3_LOW_FREQ_VAL 0x08
74 #define DLL_CONFIG_3_HIGH_FREQ_VAL 0x10
76 #define CORE_VENDOR_SPEC_POR_VAL 0xa9c
77 #define CORE_CLK_PWRSAVE BIT(1)
78 #define CORE_HC_MCLK_SEL_DFLT (2 << 8)
79 #define CORE_HC_MCLK_SEL_HS400 (3 << 8)
80 #define CORE_HC_MCLK_SEL_MASK (3 << 8)
81 #define CORE_IO_PAD_PWR_SWITCH_EN BIT(15)
82 #define CORE_IO_PAD_PWR_SWITCH BIT(16)
83 #define CORE_HC_SELECT_IN_EN BIT(18)
84 #define CORE_HC_SELECT_IN_HS400 (6 << 19)
85 #define CORE_HC_SELECT_IN_MASK (7 << 19)
87 #define CORE_3_0V_SUPPORT BIT(25)
88 #define CORE_1_8V_SUPPORT BIT(26)
89 #define CORE_VOLT_SUPPORT (CORE_3_0V_SUPPORT | CORE_1_8V_SUPPORT)
91 #define CORE_CSR_CDC_CTLR_CFG0 0x130
92 #define CORE_SW_TRIG_FULL_CALIB BIT(16)
93 #define CORE_HW_AUTOCAL_ENA BIT(17)
95 #define CORE_CSR_CDC_CTLR_CFG1 0x134
96 #define CORE_CSR_CDC_CAL_TIMER_CFG0 0x138
97 #define CORE_TIMER_ENA BIT(16)
99 #define CORE_CSR_CDC_CAL_TIMER_CFG1 0x13C
100 #define CORE_CSR_CDC_REFCOUNT_CFG 0x140
101 #define CORE_CSR_CDC_COARSE_CAL_CFG 0x144
102 #define CORE_CDC_OFFSET_CFG 0x14C
103 #define CORE_CSR_CDC_DELAY_CFG 0x150
104 #define CORE_CDC_SLAVE_DDA_CFG 0x160
105 #define CORE_CSR_CDC_STATUS0 0x164
106 #define CORE_CALIBRATION_DONE BIT(0)
108 #define CORE_CDC_ERROR_CODE_MASK 0x7000000
110 #define CORE_CSR_CDC_GEN_CFG 0x178
111 #define CORE_CDC_SWITCH_BYPASS_OFF BIT(0)
112 #define CORE_CDC_SWITCH_RC_EN BIT(1)
114 #define CORE_CDC_T4_DLY_SEL BIT(0)
115 #define CORE_CMDIN_RCLK_EN BIT(1)
116 #define CORE_START_CDC_TRAFFIC BIT(6)
118 #define CORE_PWRSAVE_DLL BIT(3)
120 #define DDR_CONFIG_POR_VAL 0x80040873
123 #define INVALID_TUNING_PHASE -1
124 #define SDHCI_MSM_MIN_CLOCK 400000
125 #define CORE_FREQ_100MHZ (100 * 1000 * 1000)
127 #define CDR_SELEXT_SHIFT 20
128 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
129 #define CMUX_SHIFT_PHASE_SHIFT 24
130 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
132 #define MSM_MMC_AUTOSUSPEND_DELAY_MS 50
134 /* Timeout value to avoid infinite waiting for pwr_irq */
135 #define MSM_PWR_IRQ_TIMEOUT_MS 5000
137 /* Max load for eMMC Vdd supply */
138 #define MMC_VMMC_MAX_LOAD_UA 570000
140 /* Max load for eMMC Vdd-io supply */
141 #define MMC_VQMMC_MAX_LOAD_UA 325000
143 /* Max load for SD Vdd supply */
144 #define SD_VMMC_MAX_LOAD_UA 800000
146 /* Max load for SD Vdd-io supply */
147 #define SD_VQMMC_MAX_LOAD_UA 22000
149 #define msm_host_readl(msm_host, host, offset) \
150 msm_host->var_ops->msm_readl_relaxed(host, offset)
152 #define msm_host_writel(msm_host, val, host, offset) \
153 msm_host->var_ops->msm_writel_relaxed(val, host, offset)
155 /* CQHCI vendor specific registers */
156 #define CQHCI_VENDOR_CFG1 0xA00
157 #define CQHCI_VENDOR_DIS_RST_ON_CQ_EN (0x3 << 13)
159 struct sdhci_msm_offset
{
161 u32 core_mci_data_cnt
;
163 u32 core_mci_fifo_cnt
;
164 u32 core_mci_version
;
166 u32 core_testbus_config
;
167 u32 core_testbus_sel2_bit
;
168 u32 core_testbus_ena
;
169 u32 core_testbus_sel2
;
170 u32 core_pwrctl_status
;
171 u32 core_pwrctl_mask
;
172 u32 core_pwrctl_clear
;
174 u32 core_sdcc_debug_reg
;
177 u32 core_vendor_spec
;
178 u32 core_vendor_spec_adma_err_addr0
;
179 u32 core_vendor_spec_adma_err_addr1
;
180 u32 core_vendor_spec_func2
;
181 u32 core_vendor_spec_capabilities0
;
182 u32 core_ddr_200_cfg
;
183 u32 core_vendor_spec3
;
184 u32 core_dll_config_2
;
185 u32 core_dll_config_3
;
186 u32 core_ddr_config_old
; /* Applicable to sdcc minor ver < 0x49 */
188 u32 core_dll_usr_ctl
; /* Present on SDCC5.1 onwards */
191 static const struct sdhci_msm_offset sdhci_msm_v5_offset
= {
192 .core_mci_data_cnt
= 0x35c,
193 .core_mci_status
= 0x324,
194 .core_mci_fifo_cnt
= 0x308,
195 .core_mci_version
= 0x318,
196 .core_generics
= 0x320,
197 .core_testbus_config
= 0x32c,
198 .core_testbus_sel2_bit
= 3,
199 .core_testbus_ena
= (1 << 31),
200 .core_testbus_sel2
= (1 << 3),
201 .core_pwrctl_status
= 0x240,
202 .core_pwrctl_mask
= 0x244,
203 .core_pwrctl_clear
= 0x248,
204 .core_pwrctl_ctl
= 0x24c,
205 .core_sdcc_debug_reg
= 0x358,
206 .core_dll_config
= 0x200,
207 .core_dll_status
= 0x208,
208 .core_vendor_spec
= 0x20c,
209 .core_vendor_spec_adma_err_addr0
= 0x214,
210 .core_vendor_spec_adma_err_addr1
= 0x218,
211 .core_vendor_spec_func2
= 0x210,
212 .core_vendor_spec_capabilities0
= 0x21c,
213 .core_ddr_200_cfg
= 0x224,
214 .core_vendor_spec3
= 0x250,
215 .core_dll_config_2
= 0x254,
216 .core_dll_config_3
= 0x258,
217 .core_ddr_config
= 0x25c,
218 .core_dll_usr_ctl
= 0x388,
221 static const struct sdhci_msm_offset sdhci_msm_mci_offset
= {
222 .core_hc_mode
= 0x78,
223 .core_mci_data_cnt
= 0x30,
224 .core_mci_status
= 0x34,
225 .core_mci_fifo_cnt
= 0x44,
226 .core_mci_version
= 0x050,
227 .core_generics
= 0x70,
228 .core_testbus_config
= 0x0cc,
229 .core_testbus_sel2_bit
= 4,
230 .core_testbus_ena
= (1 << 3),
231 .core_testbus_sel2
= (1 << 4),
232 .core_pwrctl_status
= 0xdc,
233 .core_pwrctl_mask
= 0xe0,
234 .core_pwrctl_clear
= 0xe4,
235 .core_pwrctl_ctl
= 0xe8,
236 .core_sdcc_debug_reg
= 0x124,
237 .core_dll_config
= 0x100,
238 .core_dll_status
= 0x108,
239 .core_vendor_spec
= 0x10c,
240 .core_vendor_spec_adma_err_addr0
= 0x114,
241 .core_vendor_spec_adma_err_addr1
= 0x118,
242 .core_vendor_spec_func2
= 0x110,
243 .core_vendor_spec_capabilities0
= 0x11c,
244 .core_ddr_200_cfg
= 0x184,
245 .core_vendor_spec3
= 0x1b0,
246 .core_dll_config_2
= 0x1b4,
247 .core_ddr_config_old
= 0x1b8,
248 .core_ddr_config
= 0x1bc,
251 struct sdhci_msm_variant_ops
{
252 u32 (*msm_readl_relaxed
)(struct sdhci_host
*host
, u32 offset
);
253 void (*msm_writel_relaxed
)(u32 val
, struct sdhci_host
*host
,
258 * From V5, register spaces have changed. Wrap this info in a structure
259 * and choose the data_structure based on version info mentioned in DT.
261 struct sdhci_msm_variant_info
{
263 bool restore_dll_config
;
264 const struct sdhci_msm_variant_ops
*var_ops
;
265 const struct sdhci_msm_offset
*offset
;
268 struct sdhci_msm_host
{
269 struct platform_device
*pdev
;
270 void __iomem
*core_mem
; /* MSM SDCC mapped address */
271 int pwr_irq
; /* power irq */
272 struct clk
*bus_clk
; /* SDHC bus voter clock */
273 struct clk
*xo_clk
; /* TCXO clk needed for FLL feature of cm_dll*/
274 /* core, iface, cal and sleep clocks */
275 struct clk_bulk_data bulk_clks
[4];
276 #ifdef CONFIG_MMC_CRYPTO
277 struct qcom_ice
*ice
;
279 unsigned long clk_rate
;
280 struct mmc_host
*mmc
;
281 bool use_14lpp_dll_reset
;
283 bool calibration_done
;
284 u8 saved_tuning_phase
;
288 wait_queue_head_t pwr_irq_wait
;
292 bool restore_dll_config
;
293 const struct sdhci_msm_variant_ops
*var_ops
;
294 const struct sdhci_msm_offset
*offset
;
297 bool updated_ddr_cfg
;
298 bool uses_tassadar_dll
;
304 static const struct sdhci_msm_offset
*sdhci_priv_msm_offset(struct sdhci_host
*host
)
306 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
307 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
309 return msm_host
->offset
;
313 * APIs to read/write to vendor specific registers which were there in the
314 * core_mem region before MCI was removed.
316 static u32
sdhci_msm_mci_variant_readl_relaxed(struct sdhci_host
*host
,
319 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
320 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
322 return readl_relaxed(msm_host
->core_mem
+ offset
);
325 static u32
sdhci_msm_v5_variant_readl_relaxed(struct sdhci_host
*host
,
328 return readl_relaxed(host
->ioaddr
+ offset
);
331 static void sdhci_msm_mci_variant_writel_relaxed(u32 val
,
332 struct sdhci_host
*host
, u32 offset
)
334 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
335 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
337 writel_relaxed(val
, msm_host
->core_mem
+ offset
);
340 static void sdhci_msm_v5_variant_writel_relaxed(u32 val
,
341 struct sdhci_host
*host
, u32 offset
)
343 writel_relaxed(val
, host
->ioaddr
+ offset
);
346 static unsigned int msm_get_clock_mult_for_bus_mode(struct sdhci_host
*host
)
348 struct mmc_ios ios
= host
->mmc
->ios
;
350 * The SDHC requires internal clock frequency to be double the
351 * actual clock that will be set for DDR mode. The controller
352 * uses the faster clock(100/400MHz) for some of its parts and
353 * send the actual required clock (50/200MHz) to the card.
355 if (ios
.timing
== MMC_TIMING_UHS_DDR50
||
356 ios
.timing
== MMC_TIMING_MMC_DDR52
||
357 ios
.timing
== MMC_TIMING_MMC_HS400
||
358 host
->flags
& SDHCI_HS400_TUNING
)
363 static void msm_set_clock_rate_for_bus_mode(struct sdhci_host
*host
,
366 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
367 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
368 struct mmc_ios curr_ios
= host
->mmc
->ios
;
369 struct clk
*core_clk
= msm_host
->bulk_clks
[0].clk
;
370 unsigned long achieved_rate
;
371 unsigned int desired_rate
;
375 mult
= msm_get_clock_mult_for_bus_mode(host
);
376 desired_rate
= clock
* mult
;
377 rc
= dev_pm_opp_set_rate(mmc_dev(host
->mmc
), desired_rate
);
379 pr_err("%s: Failed to set clock at rate %u at timing %d\n",
380 mmc_hostname(host
->mmc
), desired_rate
, curr_ios
.timing
);
385 * Qualcomm clock drivers by default round clock _up_ if they can't
386 * make the requested rate. This is not good for SD. Yell if we
389 achieved_rate
= clk_get_rate(core_clk
);
390 if (achieved_rate
> desired_rate
)
391 pr_warn("%s: Card appears overclocked; req %u Hz, actual %lu Hz\n",
392 mmc_hostname(host
->mmc
), desired_rate
, achieved_rate
);
393 host
->mmc
->actual_clock
= achieved_rate
/ mult
;
395 /* Stash the rate we requested to use in sdhci_msm_runtime_resume() */
396 msm_host
->clk_rate
= desired_rate
;
398 pr_debug("%s: Setting clock at rate %lu at timing %d\n",
399 mmc_hostname(host
->mmc
), achieved_rate
, curr_ios
.timing
);
402 /* Platform specific tuning */
403 static inline int msm_dll_poll_ck_out_en(struct sdhci_host
*host
, u8 poll
)
407 struct mmc_host
*mmc
= host
->mmc
;
408 const struct sdhci_msm_offset
*msm_offset
=
409 sdhci_priv_msm_offset(host
);
411 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
412 ck_out_en
= !!(readl_relaxed(host
->ioaddr
+
413 msm_offset
->core_dll_config
) & CORE_CK_OUT_EN
);
415 while (ck_out_en
!= poll
) {
416 if (--wait_cnt
== 0) {
417 dev_err(mmc_dev(mmc
), "%s: CK_OUT_EN bit is not %d\n",
418 mmc_hostname(mmc
), poll
);
423 ck_out_en
= !!(readl_relaxed(host
->ioaddr
+
424 msm_offset
->core_dll_config
) & CORE_CK_OUT_EN
);
430 static int msm_config_cm_dll_phase(struct sdhci_host
*host
, u8 phase
)
433 static const u8 grey_coded_phase_table
[] = {
434 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
435 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
439 struct mmc_host
*mmc
= host
->mmc
;
440 const struct sdhci_msm_offset
*msm_offset
=
441 sdhci_priv_msm_offset(host
);
446 spin_lock_irqsave(&host
->lock
, flags
);
448 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
449 config
&= ~(CORE_CDR_EN
| CORE_CK_OUT_EN
);
450 config
|= (CORE_CDR_EXT_EN
| CORE_DLL_EN
);
451 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
453 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
454 rc
= msm_dll_poll_ck_out_en(host
, 0);
459 * Write the selected DLL clock output phase (0 ... 15)
460 * to CDR_SELEXT bit field of DLL_CONFIG register.
462 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
463 config
&= ~CDR_SELEXT_MASK
;
464 config
|= grey_coded_phase_table
[phase
] << CDR_SELEXT_SHIFT
;
465 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
467 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
468 config
|= CORE_CK_OUT_EN
;
469 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
471 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
472 rc
= msm_dll_poll_ck_out_en(host
, 1);
476 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
477 config
|= CORE_CDR_EN
;
478 config
&= ~CORE_CDR_EXT_EN
;
479 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
483 dev_err(mmc_dev(mmc
), "%s: Failed to set DLL phase: %d\n",
484 mmc_hostname(mmc
), phase
);
486 spin_unlock_irqrestore(&host
->lock
, flags
);
491 * Find out the greatest range of consecuitive selected
492 * DLL clock output phases that can be used as sampling
493 * setting for SD3.0 UHS-I card read operation (in SDR104
494 * timing mode) or for eMMC4.5 card read operation (in
495 * HS400/HS200 timing mode).
496 * Select the 3/4 of the range and configure the DLL with the
497 * selected DLL clock output phase.
500 static int msm_find_most_appropriate_phase(struct sdhci_host
*host
,
501 u8
*phase_table
, u8 total_phases
)
504 u8 ranges
[MAX_PHASES
][MAX_PHASES
] = { {0}, {0} };
505 u8 phases_per_row
[MAX_PHASES
] = { 0 };
506 int row_index
= 0, col_index
= 0, selected_row_index
= 0, curr_max
= 0;
507 int i
, cnt
, phase_0_raw_index
= 0, phase_15_raw_index
= 0;
508 bool phase_0_found
= false, phase_15_found
= false;
509 struct mmc_host
*mmc
= host
->mmc
;
511 if (!total_phases
|| (total_phases
> MAX_PHASES
)) {
512 dev_err(mmc_dev(mmc
), "%s: Invalid argument: total_phases=%d\n",
513 mmc_hostname(mmc
), total_phases
);
517 for (cnt
= 0; cnt
< total_phases
; cnt
++) {
518 ranges
[row_index
][col_index
] = phase_table
[cnt
];
519 phases_per_row
[row_index
] += 1;
522 if ((cnt
+ 1) == total_phases
) {
524 /* check if next phase in phase_table is consecutive or not */
525 } else if ((phase_table
[cnt
] + 1) != phase_table
[cnt
+ 1]) {
531 if (row_index
>= MAX_PHASES
)
534 /* Check if phase-0 is present in first valid window? */
536 phase_0_found
= true;
537 phase_0_raw_index
= 0;
538 /* Check if cycle exist between 2 valid windows */
539 for (cnt
= 1; cnt
<= row_index
; cnt
++) {
540 if (phases_per_row
[cnt
]) {
541 for (i
= 0; i
< phases_per_row
[cnt
]; i
++) {
542 if (ranges
[cnt
][i
] == 15) {
543 phase_15_found
= true;
544 phase_15_raw_index
= cnt
;
552 /* If 2 valid windows form cycle then merge them as single window */
553 if (phase_0_found
&& phase_15_found
) {
554 /* number of phases in raw where phase 0 is present */
555 u8 phases_0
= phases_per_row
[phase_0_raw_index
];
556 /* number of phases in raw where phase 15 is present */
557 u8 phases_15
= phases_per_row
[phase_15_raw_index
];
559 if (phases_0
+ phases_15
>= MAX_PHASES
)
561 * If there are more than 1 phase windows then total
562 * number of phases in both the windows should not be
563 * more than or equal to MAX_PHASES.
567 /* Merge 2 cyclic windows */
569 for (cnt
= 0; cnt
< phases_0
; cnt
++) {
570 ranges
[phase_15_raw_index
][i
] =
571 ranges
[phase_0_raw_index
][cnt
];
572 if (++i
>= MAX_PHASES
)
576 phases_per_row
[phase_0_raw_index
] = 0;
577 phases_per_row
[phase_15_raw_index
] = phases_15
+ phases_0
;
580 for (cnt
= 0; cnt
<= row_index
; cnt
++) {
581 if (phases_per_row
[cnt
] > curr_max
) {
582 curr_max
= phases_per_row
[cnt
];
583 selected_row_index
= cnt
;
587 i
= (curr_max
* 3) / 4;
591 ret
= ranges
[selected_row_index
][i
];
593 if (ret
>= MAX_PHASES
) {
595 dev_err(mmc_dev(mmc
), "%s: Invalid phase selected=%d\n",
596 mmc_hostname(mmc
), ret
);
602 static inline void msm_cm_dll_set_freq(struct sdhci_host
*host
)
604 u32 mclk_freq
= 0, config
;
605 const struct sdhci_msm_offset
*msm_offset
=
606 sdhci_priv_msm_offset(host
);
608 /* Program the MCLK value to MCLK_FREQ bit field */
609 if (host
->clock
<= 112000000)
611 else if (host
->clock
<= 125000000)
613 else if (host
->clock
<= 137000000)
615 else if (host
->clock
<= 150000000)
617 else if (host
->clock
<= 162000000)
619 else if (host
->clock
<= 175000000)
621 else if (host
->clock
<= 187000000)
623 else if (host
->clock
<= 200000000)
626 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
627 config
&= ~CMUX_SHIFT_PHASE_MASK
;
628 config
|= mclk_freq
<< CMUX_SHIFT_PHASE_SHIFT
;
629 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
632 /* Initialize the DLL (Programmable Delay Line) */
633 static int msm_init_cm_dll(struct sdhci_host
*host
)
635 struct mmc_host
*mmc
= host
->mmc
;
636 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
637 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
639 unsigned long flags
, xo_clk
= 0;
641 const struct sdhci_msm_offset
*msm_offset
=
644 if (msm_host
->use_14lpp_dll_reset
&& !IS_ERR_OR_NULL(msm_host
->xo_clk
))
645 xo_clk
= clk_get_rate(msm_host
->xo_clk
);
647 spin_lock_irqsave(&host
->lock
, flags
);
650 * Make sure that clock is always enabled when DLL
651 * tuning is in progress. Keeping PWRSAVE ON may
652 * turn off the clock.
654 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec
);
655 config
&= ~CORE_CLK_PWRSAVE
;
656 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_vendor_spec
);
658 if (msm_host
->dll_config
)
659 writel_relaxed(msm_host
->dll_config
,
660 host
->ioaddr
+ msm_offset
->core_dll_config
);
662 if (msm_host
->use_14lpp_dll_reset
) {
663 config
= readl_relaxed(host
->ioaddr
+
664 msm_offset
->core_dll_config
);
665 config
&= ~CORE_CK_OUT_EN
;
666 writel_relaxed(config
, host
->ioaddr
+
667 msm_offset
->core_dll_config
);
669 config
= readl_relaxed(host
->ioaddr
+
670 msm_offset
->core_dll_config_2
);
671 config
|= CORE_DLL_CLOCK_DISABLE
;
672 writel_relaxed(config
, host
->ioaddr
+
673 msm_offset
->core_dll_config_2
);
676 config
= readl_relaxed(host
->ioaddr
+
677 msm_offset
->core_dll_config
);
678 config
|= CORE_DLL_RST
;
679 writel_relaxed(config
, host
->ioaddr
+
680 msm_offset
->core_dll_config
);
682 config
= readl_relaxed(host
->ioaddr
+
683 msm_offset
->core_dll_config
);
684 config
|= CORE_DLL_PDN
;
685 writel_relaxed(config
, host
->ioaddr
+
686 msm_offset
->core_dll_config
);
688 if (!msm_host
->dll_config
)
689 msm_cm_dll_set_freq(host
);
691 if (msm_host
->use_14lpp_dll_reset
&&
692 !IS_ERR_OR_NULL(msm_host
->xo_clk
)) {
695 config
= readl_relaxed(host
->ioaddr
+
696 msm_offset
->core_dll_config_2
);
697 config
&= CORE_FLL_CYCLE_CNT
;
699 mclk_freq
= DIV_ROUND_CLOSEST_ULL((host
->clock
* 8),
702 mclk_freq
= DIV_ROUND_CLOSEST_ULL((host
->clock
* 4),
705 config
= readl_relaxed(host
->ioaddr
+
706 msm_offset
->core_dll_config_2
);
707 config
&= ~(0xFF << 10);
708 config
|= mclk_freq
<< 10;
710 writel_relaxed(config
, host
->ioaddr
+
711 msm_offset
->core_dll_config_2
);
712 /* wait for 5us before enabling DLL clock */
716 config
= readl_relaxed(host
->ioaddr
+
717 msm_offset
->core_dll_config
);
718 config
&= ~CORE_DLL_RST
;
719 writel_relaxed(config
, host
->ioaddr
+
720 msm_offset
->core_dll_config
);
722 config
= readl_relaxed(host
->ioaddr
+
723 msm_offset
->core_dll_config
);
724 config
&= ~CORE_DLL_PDN
;
725 writel_relaxed(config
, host
->ioaddr
+
726 msm_offset
->core_dll_config
);
728 if (msm_host
->use_14lpp_dll_reset
) {
729 if (!msm_host
->dll_config
)
730 msm_cm_dll_set_freq(host
);
731 config
= readl_relaxed(host
->ioaddr
+
732 msm_offset
->core_dll_config_2
);
733 config
&= ~CORE_DLL_CLOCK_DISABLE
;
734 writel_relaxed(config
, host
->ioaddr
+
735 msm_offset
->core_dll_config_2
);
739 * Configure DLL user control register to enable DLL status.
740 * This setting is applicable to SDCC v5.1 onwards only.
742 if (msm_host
->uses_tassadar_dll
) {
743 config
= DLL_USR_CTL_POR_VAL
| FINE_TUNE_MODE_EN
|
744 ENABLE_DLL_LOCK_STATUS
| BIAS_OK_SIGNAL
;
745 writel_relaxed(config
, host
->ioaddr
+
746 msm_offset
->core_dll_usr_ctl
);
748 config
= readl_relaxed(host
->ioaddr
+
749 msm_offset
->core_dll_config_3
);
751 if (msm_host
->clk_rate
< 150000000)
752 config
|= DLL_CONFIG_3_LOW_FREQ_VAL
;
754 config
|= DLL_CONFIG_3_HIGH_FREQ_VAL
;
755 writel_relaxed(config
, host
->ioaddr
+
756 msm_offset
->core_dll_config_3
);
759 config
= readl_relaxed(host
->ioaddr
+
760 msm_offset
->core_dll_config
);
761 config
|= CORE_DLL_EN
;
762 writel_relaxed(config
, host
->ioaddr
+
763 msm_offset
->core_dll_config
);
765 config
= readl_relaxed(host
->ioaddr
+
766 msm_offset
->core_dll_config
);
767 config
|= CORE_CK_OUT_EN
;
768 writel_relaxed(config
, host
->ioaddr
+
769 msm_offset
->core_dll_config
);
771 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
772 while (!(readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_status
) &
774 /* max. wait for 50us sec for LOCK bit to be set */
775 if (--wait_cnt
== 0) {
776 dev_err(mmc_dev(mmc
), "%s: DLL failed to LOCK\n",
778 spin_unlock_irqrestore(&host
->lock
, flags
);
784 spin_unlock_irqrestore(&host
->lock
, flags
);
788 static void msm_hc_select_default(struct sdhci_host
*host
)
790 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
791 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
793 const struct sdhci_msm_offset
*msm_offset
=
796 if (!msm_host
->use_cdclp533
) {
797 config
= readl_relaxed(host
->ioaddr
+
798 msm_offset
->core_vendor_spec3
);
799 config
&= ~CORE_PWRSAVE_DLL
;
800 writel_relaxed(config
, host
->ioaddr
+
801 msm_offset
->core_vendor_spec3
);
804 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec
);
805 config
&= ~CORE_HC_MCLK_SEL_MASK
;
806 config
|= CORE_HC_MCLK_SEL_DFLT
;
807 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_vendor_spec
);
810 * Disable HC_SELECT_IN to be able to use the UHS mode select
811 * configuration from Host Control2 register for all other
813 * Write 0 to HC_SELECT_IN and HC_SELECT_IN_EN field
814 * in VENDOR_SPEC_FUNC
816 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec
);
817 config
&= ~CORE_HC_SELECT_IN_EN
;
818 config
&= ~CORE_HC_SELECT_IN_MASK
;
819 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_vendor_spec
);
822 * Make sure above writes impacting free running MCLK are completed
823 * before changing the clk_rate at GCC.
828 static void msm_hc_select_hs400(struct sdhci_host
*host
)
830 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
831 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
832 struct mmc_ios ios
= host
->mmc
->ios
;
833 u32 config
, dll_lock
;
835 const struct sdhci_msm_offset
*msm_offset
=
838 /* Select the divided clock (free running MCLK/2) */
839 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec
);
840 config
&= ~CORE_HC_MCLK_SEL_MASK
;
841 config
|= CORE_HC_MCLK_SEL_HS400
;
843 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_vendor_spec
);
845 * Select HS400 mode using the HC_SELECT_IN from VENDOR SPEC
848 if ((msm_host
->tuning_done
|| ios
.enhanced_strobe
) &&
849 !msm_host
->calibration_done
) {
850 config
= readl_relaxed(host
->ioaddr
+
851 msm_offset
->core_vendor_spec
);
852 config
|= CORE_HC_SELECT_IN_HS400
;
853 config
|= CORE_HC_SELECT_IN_EN
;
854 writel_relaxed(config
, host
->ioaddr
+
855 msm_offset
->core_vendor_spec
);
857 if (!msm_host
->clk_rate
&& !msm_host
->use_cdclp533
) {
859 * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
860 * core_dll_status to be set. This should get set
861 * within 15 us at 200 MHz.
863 rc
= readl_relaxed_poll_timeout(host
->ioaddr
+
864 msm_offset
->core_dll_status
,
868 CORE_DDR_DLL_LOCK
)), 10,
870 if (rc
== -ETIMEDOUT
)
871 pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
872 mmc_hostname(host
->mmc
), dll_lock
);
875 * Make sure above writes impacting free running MCLK are completed
876 * before changing the clk_rate at GCC.
882 * sdhci_msm_hc_select_mode :- In general all timing modes are
883 * controlled via UHS mode select in Host Control2 register.
884 * eMMC specific HS200/HS400 doesn't have their respective modes
885 * defined here, hence we use these values.
887 * HS200 - SDR104 (Since they both are equivalent in functionality)
888 * HS400 - This involves multiple configurations
889 * Initially SDR104 - when tuning is required as HS200
890 * Then when switching to DDR @ 400MHz (HS400) we use
891 * the vendor specific HC_SELECT_IN to control the mode.
893 * In addition to controlling the modes we also need to select the
894 * correct input clock for DLL depending on the mode.
896 * HS400 - divided clock (free running MCLK/2)
897 * All other modes - default (free running MCLK)
899 static void sdhci_msm_hc_select_mode(struct sdhci_host
*host
)
901 struct mmc_ios ios
= host
->mmc
->ios
;
903 if (ios
.timing
== MMC_TIMING_MMC_HS400
||
904 host
->flags
& SDHCI_HS400_TUNING
)
905 msm_hc_select_hs400(host
);
907 msm_hc_select_default(host
);
910 static int sdhci_msm_cdclp533_calibration(struct sdhci_host
*host
)
912 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
913 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
914 u32 config
, calib_done
;
916 const struct sdhci_msm_offset
*msm_offset
=
919 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
922 * Retuning in HS400 (DDR mode) will fail, just reset the
923 * tuning block and restore the saved tuning phase.
925 ret
= msm_init_cm_dll(host
);
929 /* Set the selected phase in delay line hw block */
930 ret
= msm_config_cm_dll_phase(host
, msm_host
->saved_tuning_phase
);
934 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
);
935 config
|= CORE_CMD_DAT_TRACK_SEL
;
936 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config
);
938 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
939 config
&= ~CORE_CDC_T4_DLY_SEL
;
940 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
942 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
943 config
&= ~CORE_CDC_SWITCH_BYPASS_OFF
;
944 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
946 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
947 config
|= CORE_CDC_SWITCH_RC_EN
;
948 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_GEN_CFG
);
950 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
951 config
&= ~CORE_START_CDC_TRAFFIC
;
952 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
954 /* Perform CDC Register Initialization Sequence */
956 writel_relaxed(0x11800EC, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
957 writel_relaxed(0x3011111, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG1
);
958 writel_relaxed(0x1201000, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
959 writel_relaxed(0x4, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG1
);
960 writel_relaxed(0xCB732020, host
->ioaddr
+ CORE_CSR_CDC_REFCOUNT_CFG
);
961 writel_relaxed(0xB19, host
->ioaddr
+ CORE_CSR_CDC_COARSE_CAL_CFG
);
962 writel_relaxed(0x4E2, host
->ioaddr
+ CORE_CSR_CDC_DELAY_CFG
);
963 writel_relaxed(0x0, host
->ioaddr
+ CORE_CDC_OFFSET_CFG
);
964 writel_relaxed(0x16334, host
->ioaddr
+ CORE_CDC_SLAVE_DDA_CFG
);
966 /* CDC HW Calibration */
968 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
969 config
|= CORE_SW_TRIG_FULL_CALIB
;
970 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
972 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
973 config
&= ~CORE_SW_TRIG_FULL_CALIB
;
974 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
976 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
977 config
|= CORE_HW_AUTOCAL_ENA
;
978 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CTLR_CFG0
);
980 config
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
981 config
|= CORE_TIMER_ENA
;
982 writel_relaxed(config
, host
->ioaddr
+ CORE_CSR_CDC_CAL_TIMER_CFG0
);
984 ret
= readl_relaxed_poll_timeout(host
->ioaddr
+ CORE_CSR_CDC_STATUS0
,
986 (calib_done
& CORE_CALIBRATION_DONE
),
989 if (ret
== -ETIMEDOUT
) {
990 pr_err("%s: %s: CDC calibration was not completed\n",
991 mmc_hostname(host
->mmc
), __func__
);
995 ret
= readl_relaxed(host
->ioaddr
+ CORE_CSR_CDC_STATUS0
)
996 & CORE_CDC_ERROR_CODE_MASK
;
998 pr_err("%s: %s: CDC error code %d\n",
999 mmc_hostname(host
->mmc
), __func__
, ret
);
1004 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
1005 config
|= CORE_START_CDC_TRAFFIC
;
1006 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_ddr_200_cfg
);
1008 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
1013 static int sdhci_msm_cm_dll_sdc4_calibration(struct sdhci_host
*host
)
1015 struct mmc_host
*mmc
= host
->mmc
;
1016 u32 dll_status
, config
, ddr_cfg_offset
;
1018 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1019 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1020 const struct sdhci_msm_offset
*msm_offset
=
1021 sdhci_priv_msm_offset(host
);
1023 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
1026 * Currently the core_ddr_config register defaults to desired
1027 * configuration on reset. Currently reprogramming the power on
1028 * reset (POR) value in case it might have been modified by
1029 * bootloaders. In the future, if this changes, then the desired
1030 * values will need to be programmed appropriately.
1032 if (msm_host
->updated_ddr_cfg
)
1033 ddr_cfg_offset
= msm_offset
->core_ddr_config
;
1035 ddr_cfg_offset
= msm_offset
->core_ddr_config_old
;
1036 writel_relaxed(msm_host
->ddr_config
, host
->ioaddr
+ ddr_cfg_offset
);
1038 if (mmc
->ios
.enhanced_strobe
) {
1039 config
= readl_relaxed(host
->ioaddr
+
1040 msm_offset
->core_ddr_200_cfg
);
1041 config
|= CORE_CMDIN_RCLK_EN
;
1042 writel_relaxed(config
, host
->ioaddr
+
1043 msm_offset
->core_ddr_200_cfg
);
1046 config
= readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config_2
);
1047 config
|= CORE_DDR_CAL_EN
;
1048 writel_relaxed(config
, host
->ioaddr
+ msm_offset
->core_dll_config_2
);
1050 ret
= readl_relaxed_poll_timeout(host
->ioaddr
+
1051 msm_offset
->core_dll_status
,
1053 (dll_status
& CORE_DDR_DLL_LOCK
),
1056 if (ret
== -ETIMEDOUT
) {
1057 pr_err("%s: %s: CM_DLL_SDC4 calibration was not completed\n",
1058 mmc_hostname(host
->mmc
), __func__
);
1063 * Set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3.
1064 * When MCLK is gated OFF, it is not gated for less than 0.5us
1065 * and MCLK must be switched on for at-least 1us before DATA
1066 * starts coming. Controllers with 14lpp and later tech DLL cannot
1067 * guarantee above requirement. So PWRSAVE_DLL should not be
1068 * turned on for host controllers using this DLL.
1070 if (!msm_host
->use_14lpp_dll_reset
) {
1071 config
= readl_relaxed(host
->ioaddr
+
1072 msm_offset
->core_vendor_spec3
);
1073 config
|= CORE_PWRSAVE_DLL
;
1074 writel_relaxed(config
, host
->ioaddr
+
1075 msm_offset
->core_vendor_spec3
);
1079 * Drain writebuffer to ensure above DLL calibration
1080 * and PWRSAVE DLL is enabled.
1084 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
1089 static int sdhci_msm_hs400_dll_calibration(struct sdhci_host
*host
)
1091 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1092 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1093 struct mmc_host
*mmc
= host
->mmc
;
1096 const struct sdhci_msm_offset
*msm_offset
=
1099 pr_debug("%s: %s: Enter\n", mmc_hostname(host
->mmc
), __func__
);
1102 * Retuning in HS400 (DDR mode) will fail, just reset the
1103 * tuning block and restore the saved tuning phase.
1105 ret
= msm_init_cm_dll(host
);
1109 if (!mmc
->ios
.enhanced_strobe
) {
1110 /* Set the selected phase in delay line hw block */
1111 ret
= msm_config_cm_dll_phase(host
,
1112 msm_host
->saved_tuning_phase
);
1115 config
= readl_relaxed(host
->ioaddr
+
1116 msm_offset
->core_dll_config
);
1117 config
|= CORE_CMD_DAT_TRACK_SEL
;
1118 writel_relaxed(config
, host
->ioaddr
+
1119 msm_offset
->core_dll_config
);
1122 if (msm_host
->use_cdclp533
)
1123 ret
= sdhci_msm_cdclp533_calibration(host
);
1125 ret
= sdhci_msm_cm_dll_sdc4_calibration(host
);
1127 pr_debug("%s: %s: Exit, ret %d\n", mmc_hostname(host
->mmc
),
1132 static bool sdhci_msm_is_tuning_needed(struct sdhci_host
*host
)
1134 struct mmc_ios
*ios
= &host
->mmc
->ios
;
1137 * Tuning is required for SDR104, HS200 and HS400 cards and
1138 * if clock frequency is greater than 100MHz in these modes.
1140 if (host
->clock
<= CORE_FREQ_100MHZ
||
1141 !(ios
->timing
== MMC_TIMING_MMC_HS400
||
1142 ios
->timing
== MMC_TIMING_MMC_HS200
||
1143 ios
->timing
== MMC_TIMING_UHS_SDR104
) ||
1144 ios
->enhanced_strobe
)
1150 static int sdhci_msm_restore_sdr_dll_config(struct sdhci_host
*host
)
1152 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1153 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1157 * SDR DLL comes into picture only for timing modes which needs
1160 if (!sdhci_msm_is_tuning_needed(host
))
1163 /* Reset the tuning block */
1164 ret
= msm_init_cm_dll(host
);
1168 /* Restore the tuning block */
1169 ret
= msm_config_cm_dll_phase(host
, msm_host
->saved_tuning_phase
);
1174 static void sdhci_msm_set_cdr(struct sdhci_host
*host
, bool enable
)
1176 const struct sdhci_msm_offset
*msm_offset
= sdhci_priv_msm_offset(host
);
1177 u32 config
, oldconfig
= readl_relaxed(host
->ioaddr
+
1178 msm_offset
->core_dll_config
);
1182 config
|= CORE_CDR_EN
;
1183 config
&= ~CORE_CDR_EXT_EN
;
1185 config
&= ~CORE_CDR_EN
;
1186 config
|= CORE_CDR_EXT_EN
;
1189 if (config
!= oldconfig
) {
1190 writel_relaxed(config
, host
->ioaddr
+
1191 msm_offset
->core_dll_config
);
1195 static int sdhci_msm_execute_tuning(struct mmc_host
*mmc
, u32 opcode
)
1197 struct sdhci_host
*host
= mmc_priv(mmc
);
1198 int tuning_seq_cnt
= 10;
1199 u8 phase
, tuned_phases
[16], tuned_phase_cnt
= 0;
1201 struct mmc_ios ios
= host
->mmc
->ios
;
1202 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1203 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1205 if (!sdhci_msm_is_tuning_needed(host
)) {
1206 msm_host
->use_cdr
= false;
1207 sdhci_msm_set_cdr(host
, false);
1211 /* Clock-Data-Recovery used to dynamically adjust RX sampling point */
1212 msm_host
->use_cdr
= true;
1215 * Clear tuning_done flag before tuning to ensure proper
1218 msm_host
->tuning_done
= 0;
1221 * For HS400 tuning in HS200 timing requires:
1222 * - select MCLK/2 in VENDOR_SPEC
1223 * - program MCLK to 400MHz (or nearest supported) in GCC
1225 if (host
->flags
& SDHCI_HS400_TUNING
) {
1226 sdhci_msm_hc_select_mode(host
);
1227 msm_set_clock_rate_for_bus_mode(host
, ios
.clock
);
1228 host
->flags
&= ~SDHCI_HS400_TUNING
;
1232 /* First of all reset the tuning block */
1233 rc
= msm_init_cm_dll(host
);
1239 /* Set the phase in delay line hw block */
1240 rc
= msm_config_cm_dll_phase(host
, phase
);
1244 rc
= mmc_send_tuning(mmc
, opcode
, NULL
);
1246 /* Tuning is successful at this tuning point */
1247 tuned_phases
[tuned_phase_cnt
++] = phase
;
1248 dev_dbg(mmc_dev(mmc
), "%s: Found good phase = %d\n",
1249 mmc_hostname(mmc
), phase
);
1251 } while (++phase
< ARRAY_SIZE(tuned_phases
));
1253 if (tuned_phase_cnt
) {
1254 if (tuned_phase_cnt
== ARRAY_SIZE(tuned_phases
)) {
1256 * All phases valid is _almost_ as bad as no phases
1257 * valid. Probably all phases are not really reliable
1258 * but we didn't detect where the unreliable place is.
1259 * That means we'll essentially be guessing and hoping
1260 * we get a good phase. Better to try a few times.
1262 dev_dbg(mmc_dev(mmc
), "%s: All phases valid; try again\n",
1264 if (--tuning_seq_cnt
) {
1265 tuned_phase_cnt
= 0;
1270 rc
= msm_find_most_appropriate_phase(host
, tuned_phases
,
1278 * Finally set the selected phase in delay
1281 rc
= msm_config_cm_dll_phase(host
, phase
);
1284 msm_host
->saved_tuning_phase
= phase
;
1285 dev_dbg(mmc_dev(mmc
), "%s: Setting the tuning phase to %d\n",
1286 mmc_hostname(mmc
), phase
);
1288 if (--tuning_seq_cnt
)
1291 dev_dbg(mmc_dev(mmc
), "%s: No tuning point found\n",
1297 msm_host
->tuning_done
= true;
1302 * sdhci_msm_hs400 - Calibrate the DLL for HS400 bus speed mode operation.
1303 * This needs to be done for both tuning and enhanced_strobe mode.
1304 * DLL operation is only needed for clock > 100MHz. For clock <= 100MHz
1305 * fixed feedback clock is used.
1307 static void sdhci_msm_hs400(struct sdhci_host
*host
, struct mmc_ios
*ios
)
1309 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1310 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1313 if (host
->clock
> CORE_FREQ_100MHZ
&&
1314 (msm_host
->tuning_done
|| ios
->enhanced_strobe
) &&
1315 !msm_host
->calibration_done
) {
1316 ret
= sdhci_msm_hs400_dll_calibration(host
);
1318 msm_host
->calibration_done
= true;
1320 pr_err("%s: Failed to calibrate DLL for hs400 mode (%d)\n",
1321 mmc_hostname(host
->mmc
), ret
);
1325 static void sdhci_msm_set_uhs_signaling(struct sdhci_host
*host
,
1328 struct mmc_host
*mmc
= host
->mmc
;
1329 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1330 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1333 const struct sdhci_msm_offset
*msm_offset
=
1336 ctrl_2
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
1337 /* Select Bus Speed Mode for host */
1338 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1340 case MMC_TIMING_UHS_SDR12
:
1341 ctrl_2
|= SDHCI_CTRL_UHS_SDR12
;
1343 case MMC_TIMING_UHS_SDR25
:
1344 ctrl_2
|= SDHCI_CTRL_UHS_SDR25
;
1346 case MMC_TIMING_UHS_SDR50
:
1347 ctrl_2
|= SDHCI_CTRL_UHS_SDR50
;
1349 case MMC_TIMING_MMC_HS400
:
1350 case MMC_TIMING_MMC_HS200
:
1351 case MMC_TIMING_UHS_SDR104
:
1352 ctrl_2
|= SDHCI_CTRL_UHS_SDR104
;
1354 case MMC_TIMING_UHS_DDR50
:
1355 case MMC_TIMING_MMC_DDR52
:
1356 ctrl_2
|= SDHCI_CTRL_UHS_DDR50
;
1361 * When clock frequency is less than 100MHz, the feedback clock must be
1362 * provided and DLL must not be used so that tuning can be skipped. To
1363 * provide feedback clock, the mode selection can be any value less
1364 * than 3'b011 in bits [2:0] of HOST CONTROL2 register.
1366 if (host
->clock
<= CORE_FREQ_100MHZ
) {
1367 if (uhs
== MMC_TIMING_MMC_HS400
||
1368 uhs
== MMC_TIMING_MMC_HS200
||
1369 uhs
== MMC_TIMING_UHS_SDR104
)
1370 ctrl_2
&= ~SDHCI_CTRL_UHS_MASK
;
1372 * DLL is not required for clock <= 100MHz
1373 * Thus, make sure DLL it is disabled when not required
1375 config
= readl_relaxed(host
->ioaddr
+
1376 msm_offset
->core_dll_config
);
1377 config
|= CORE_DLL_RST
;
1378 writel_relaxed(config
, host
->ioaddr
+
1379 msm_offset
->core_dll_config
);
1381 config
= readl_relaxed(host
->ioaddr
+
1382 msm_offset
->core_dll_config
);
1383 config
|= CORE_DLL_PDN
;
1384 writel_relaxed(config
, host
->ioaddr
+
1385 msm_offset
->core_dll_config
);
1388 * The DLL needs to be restored and CDCLP533 recalibrated
1389 * when the clock frequency is set back to 400MHz.
1391 msm_host
->calibration_done
= false;
1394 dev_dbg(mmc_dev(mmc
), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
1395 mmc_hostname(host
->mmc
), host
->clock
, uhs
, ctrl_2
);
1396 sdhci_writew(host
, ctrl_2
, SDHCI_HOST_CONTROL2
);
1398 if (mmc
->ios
.timing
== MMC_TIMING_MMC_HS400
)
1399 sdhci_msm_hs400(host
, &mmc
->ios
);
1402 static int sdhci_msm_set_pincfg(struct sdhci_msm_host
*msm_host
, bool level
)
1404 struct platform_device
*pdev
= msm_host
->pdev
;
1408 ret
= pinctrl_pm_select_default_state(&pdev
->dev
);
1410 ret
= pinctrl_pm_select_sleep_state(&pdev
->dev
);
1415 static void msm_config_vmmc_regulator(struct mmc_host
*mmc
, bool hpm
)
1421 else if (!mmc
->card
)
1422 load
= max(MMC_VMMC_MAX_LOAD_UA
, SD_VMMC_MAX_LOAD_UA
);
1423 else if (mmc_card_mmc(mmc
->card
))
1424 load
= MMC_VMMC_MAX_LOAD_UA
;
1425 else if (mmc_card_sd(mmc
->card
))
1426 load
= SD_VMMC_MAX_LOAD_UA
;
1430 regulator_set_load(mmc
->supply
.vmmc
, load
);
1433 static void msm_config_vqmmc_regulator(struct mmc_host
*mmc
, bool hpm
)
1439 else if (!mmc
->card
)
1440 load
= max(MMC_VQMMC_MAX_LOAD_UA
, SD_VQMMC_MAX_LOAD_UA
);
1441 else if (mmc_card_sd(mmc
->card
))
1442 load
= SD_VQMMC_MAX_LOAD_UA
;
1446 regulator_set_load(mmc
->supply
.vqmmc
, load
);
1449 static int sdhci_msm_set_vmmc(struct sdhci_msm_host
*msm_host
,
1450 struct mmc_host
*mmc
, bool hpm
)
1452 if (IS_ERR(mmc
->supply
.vmmc
))
1455 msm_config_vmmc_regulator(mmc
, hpm
);
1457 return mmc_regulator_set_ocr(mmc
, mmc
->supply
.vmmc
, mmc
->ios
.vdd
);
1460 static int msm_toggle_vqmmc(struct sdhci_msm_host
*msm_host
,
1461 struct mmc_host
*mmc
, bool level
)
1466 if (msm_host
->vqmmc_enabled
== level
)
1469 msm_config_vqmmc_regulator(mmc
, level
);
1472 /* Set the IO voltage regulator to default voltage level */
1473 if (msm_host
->caps_0
& CORE_3_0V_SUPPORT
)
1474 ios
.signal_voltage
= MMC_SIGNAL_VOLTAGE_330
;
1475 else if (msm_host
->caps_0
& CORE_1_8V_SUPPORT
)
1476 ios
.signal_voltage
= MMC_SIGNAL_VOLTAGE_180
;
1478 if (msm_host
->caps_0
& CORE_VOLT_SUPPORT
) {
1479 ret
= mmc_regulator_set_vqmmc(mmc
, &ios
);
1481 dev_err(mmc_dev(mmc
), "%s: vqmmc set volgate failed: %d\n",
1482 mmc_hostname(mmc
), ret
);
1486 ret
= regulator_enable(mmc
->supply
.vqmmc
);
1488 ret
= regulator_disable(mmc
->supply
.vqmmc
);
1492 dev_err(mmc_dev(mmc
), "%s: vqmm %sable failed: %d\n",
1493 mmc_hostname(mmc
), level
? "en":"dis", ret
);
1495 msm_host
->vqmmc_enabled
= level
;
1500 static int msm_config_vqmmc_mode(struct sdhci_msm_host
*msm_host
,
1501 struct mmc_host
*mmc
, bool hpm
)
1505 load
= hpm
? MMC_VQMMC_MAX_LOAD_UA
: 0;
1506 ret
= regulator_set_load(mmc
->supply
.vqmmc
, load
);
1508 dev_err(mmc_dev(mmc
), "%s: vqmmc set load failed: %d\n",
1509 mmc_hostname(mmc
), ret
);
1513 static int sdhci_msm_set_vqmmc(struct sdhci_msm_host
*msm_host
,
1514 struct mmc_host
*mmc
, bool level
)
1519 if (IS_ERR(mmc
->supply
.vqmmc
) ||
1520 (mmc
->ios
.power_mode
== MMC_POWER_UNDEFINED
))
1523 * For eMMC don't turn off Vqmmc, Instead just configure it in LPM
1524 * and HPM modes by setting the corresponding load.
1526 * Till eMMC is initialized (i.e. always_on == 0), just turn on/off
1527 * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off
1528 * gets invoked. Once eMMC is initialized (i.e. always_on == 1),
1529 * Vqmmc should remain ON, So just set the load instead of turning it
1532 always_on
= !mmc_card_is_removable(mmc
) &&
1533 mmc
->card
&& mmc_card_mmc(mmc
->card
);
1536 ret
= msm_config_vqmmc_mode(msm_host
, mmc
, level
);
1538 ret
= msm_toggle_vqmmc(msm_host
, mmc
, level
);
1543 static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host
*msm_host
)
1545 init_waitqueue_head(&msm_host
->pwr_irq_wait
);
1548 static inline void sdhci_msm_complete_pwr_irq_wait(
1549 struct sdhci_msm_host
*msm_host
)
1551 wake_up(&msm_host
->pwr_irq_wait
);
1555 * sdhci_msm_check_power_status API should be called when registers writes
1556 * which can toggle sdhci IO bus ON/OFF or change IO lines HIGH/LOW happens.
1557 * To what state the register writes will change the IO lines should be passed
1558 * as the argument req_type. This API will check whether the IO line's state
1559 * is already the expected state and will wait for power irq only if
1560 * power irq is expected to be triggered based on the current IO line state
1561 * and expected IO line state.
1563 static void sdhci_msm_check_power_status(struct sdhci_host
*host
, u32 req_type
)
1565 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1566 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1568 u32 val
= SWITCHABLE_SIGNALING_VOLTAGE
;
1569 const struct sdhci_msm_offset
*msm_offset
=
1572 pr_debug("%s: %s: request %d curr_pwr_state %x curr_io_level %x\n",
1573 mmc_hostname(host
->mmc
), __func__
, req_type
,
1574 msm_host
->curr_pwr_state
, msm_host
->curr_io_level
);
1577 * The power interrupt will not be generated for signal voltage
1578 * switches if SWITCHABLE_SIGNALING_VOLTAGE in MCI_GENERICS is not set.
1579 * Since sdhci-msm-v5, this bit has been removed and SW must consider
1582 if (!msm_host
->mci_removed
)
1583 val
= msm_host_readl(msm_host
, host
,
1584 msm_offset
->core_generics
);
1585 if ((req_type
& REQ_IO_HIGH
|| req_type
& REQ_IO_LOW
) &&
1586 !(val
& SWITCHABLE_SIGNALING_VOLTAGE
)) {
1591 * The IRQ for request type IO High/LOW will be generated when -
1592 * there is a state change in 1.8V enable bit (bit 3) of
1593 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0
1594 * which indicates 3.3V IO voltage. So, when MMC core layer tries
1595 * to set it to 3.3V before card detection happens, the
1596 * IRQ doesn't get triggered as there is no state change in this bit.
1597 * The driver already handles this case by changing the IO voltage
1598 * level to high as part of controller power up sequence. Hence, check
1599 * for host->pwr to handle a case where IO voltage high request is
1600 * issued even before controller power up.
1602 if ((req_type
& REQ_IO_HIGH
) && !host
->pwr
) {
1603 pr_debug("%s: do not wait for power IRQ that never comes, req_type: %d\n",
1604 mmc_hostname(host
->mmc
), req_type
);
1607 if ((req_type
& msm_host
->curr_pwr_state
) ||
1608 (req_type
& msm_host
->curr_io_level
))
1611 * This is needed here to handle cases where register writes will
1612 * not change the current bus state or io level of the controller.
1613 * In this case, no power irq will be triggerred and we should
1617 if (!wait_event_timeout(msm_host
->pwr_irq_wait
,
1618 msm_host
->pwr_irq_flag
,
1619 msecs_to_jiffies(MSM_PWR_IRQ_TIMEOUT_MS
)))
1620 dev_warn(&msm_host
->pdev
->dev
,
1621 "%s: pwr_irq for req: (%d) timed out\n",
1622 mmc_hostname(host
->mmc
), req_type
);
1624 pr_debug("%s: %s: request %d done\n", mmc_hostname(host
->mmc
),
1625 __func__
, req_type
);
1628 static void sdhci_msm_dump_pwr_ctrl_regs(struct sdhci_host
*host
)
1630 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1631 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1632 const struct sdhci_msm_offset
*msm_offset
=
1635 pr_err("%s: PWRCTL_STATUS: 0x%08x | PWRCTL_MASK: 0x%08x | PWRCTL_CTL: 0x%08x\n",
1636 mmc_hostname(host
->mmc
),
1637 msm_host_readl(msm_host
, host
, msm_offset
->core_pwrctl_status
),
1638 msm_host_readl(msm_host
, host
, msm_offset
->core_pwrctl_mask
),
1639 msm_host_readl(msm_host
, host
, msm_offset
->core_pwrctl_ctl
));
1642 static void sdhci_msm_handle_pwr_irq(struct sdhci_host
*host
, int irq
)
1644 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1645 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1646 struct mmc_host
*mmc
= host
->mmc
;
1647 u32 irq_status
, irq_ack
= 0;
1648 int retry
= 10, ret
;
1649 u32 pwr_state
= 0, io_level
= 0;
1651 const struct sdhci_msm_offset
*msm_offset
= msm_host
->offset
;
1653 irq_status
= msm_host_readl(msm_host
, host
,
1654 msm_offset
->core_pwrctl_status
);
1655 irq_status
&= INT_MASK
;
1657 msm_host_writel(msm_host
, irq_status
, host
,
1658 msm_offset
->core_pwrctl_clear
);
1661 * There is a rare HW scenario where the first clear pulse could be
1662 * lost when actual reset and clear/read of status register is
1663 * happening at a time. Hence, retry for at least 10 times to make
1664 * sure status register is cleared. Otherwise, this will result in
1665 * a spurious power IRQ resulting in system instability.
1667 while (irq_status
& msm_host_readl(msm_host
, host
,
1668 msm_offset
->core_pwrctl_status
)) {
1670 pr_err("%s: Timedout clearing (0x%x) pwrctl status register\n",
1671 mmc_hostname(host
->mmc
), irq_status
);
1672 sdhci_msm_dump_pwr_ctrl_regs(host
);
1676 msm_host_writel(msm_host
, irq_status
, host
,
1677 msm_offset
->core_pwrctl_clear
);
1682 /* Handle BUS ON/OFF*/
1683 if (irq_status
& CORE_PWRCTL_BUS_ON
) {
1684 pwr_state
= REQ_BUS_ON
;
1685 io_level
= REQ_IO_HIGH
;
1687 if (irq_status
& CORE_PWRCTL_BUS_OFF
) {
1688 pwr_state
= REQ_BUS_OFF
;
1689 io_level
= REQ_IO_LOW
;
1693 ret
= sdhci_msm_set_vmmc(msm_host
, mmc
,
1694 pwr_state
& REQ_BUS_ON
);
1696 ret
= sdhci_msm_set_vqmmc(msm_host
, mmc
,
1697 pwr_state
& REQ_BUS_ON
);
1699 ret
= sdhci_msm_set_pincfg(msm_host
,
1700 pwr_state
& REQ_BUS_ON
);
1702 irq_ack
|= CORE_PWRCTL_BUS_SUCCESS
;
1704 irq_ack
|= CORE_PWRCTL_BUS_FAIL
;
1707 /* Handle IO LOW/HIGH */
1708 if (irq_status
& CORE_PWRCTL_IO_LOW
)
1709 io_level
= REQ_IO_LOW
;
1711 if (irq_status
& CORE_PWRCTL_IO_HIGH
)
1712 io_level
= REQ_IO_HIGH
;
1715 irq_ack
|= CORE_PWRCTL_IO_SUCCESS
;
1717 if (io_level
&& !IS_ERR(mmc
->supply
.vqmmc
) && !pwr_state
) {
1718 ret
= mmc_regulator_set_vqmmc(mmc
, &mmc
->ios
);
1720 dev_err(mmc_dev(mmc
), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n",
1721 mmc_hostname(mmc
), ret
,
1722 mmc
->ios
.signal_voltage
, mmc
->ios
.vdd
,
1724 irq_ack
|= CORE_PWRCTL_IO_FAIL
;
1729 * The driver has to acknowledge the interrupt, switch voltages and
1730 * report back if it succeded or not to this register. The voltage
1731 * switches are handled by the sdhci core, so just report success.
1733 msm_host_writel(msm_host
, irq_ack
, host
,
1734 msm_offset
->core_pwrctl_ctl
);
1737 * If we don't have info regarding the voltage levels supported by
1738 * regulators, don't change the IO PAD PWR SWITCH.
1740 if (msm_host
->caps_0
& CORE_VOLT_SUPPORT
) {
1743 * We should unset IO PAD PWR switch only if the register write
1744 * can set IO lines high and the regulator also switches to 3 V.
1745 * Else, we should keep the IO PAD PWR switch set.
1746 * This is applicable to certain targets where eMMC vccq supply
1747 * is only 1.8V. In such targets, even during REQ_IO_HIGH, the
1748 * IO PAD PWR switch must be kept set to reflect actual
1749 * regulator voltage. This way, during initialization of
1750 * controllers with only 1.8V, we will set the IO PAD bit
1751 * without waiting for a REQ_IO_LOW.
1753 config
= readl_relaxed(host
->ioaddr
+
1754 msm_offset
->core_vendor_spec
);
1755 new_config
= config
;
1757 if ((io_level
& REQ_IO_HIGH
) &&
1758 (msm_host
->caps_0
& CORE_3_0V_SUPPORT
))
1759 new_config
&= ~CORE_IO_PAD_PWR_SWITCH
;
1760 else if ((io_level
& REQ_IO_LOW
) ||
1761 (msm_host
->caps_0
& CORE_1_8V_SUPPORT
))
1762 new_config
|= CORE_IO_PAD_PWR_SWITCH
;
1764 if (config
^ new_config
)
1765 writel_relaxed(new_config
, host
->ioaddr
+
1766 msm_offset
->core_vendor_spec
);
1770 msm_host
->curr_pwr_state
= pwr_state
;
1772 msm_host
->curr_io_level
= io_level
;
1774 dev_dbg(mmc_dev(mmc
), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n",
1775 mmc_hostname(msm_host
->mmc
), __func__
, irq
, irq_status
,
1779 static irqreturn_t
sdhci_msm_pwr_irq(int irq
, void *data
)
1781 struct sdhci_host
*host
= (struct sdhci_host
*)data
;
1782 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1783 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1785 sdhci_msm_handle_pwr_irq(host
, irq
);
1786 msm_host
->pwr_irq_flag
= 1;
1787 sdhci_msm_complete_pwr_irq_wait(msm_host
);
1793 static unsigned int sdhci_msm_get_max_clock(struct sdhci_host
*host
)
1795 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1796 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1797 struct clk
*core_clk
= msm_host
->bulk_clks
[0].clk
;
1799 return clk_round_rate(core_clk
, ULONG_MAX
);
1802 static unsigned int sdhci_msm_get_min_clock(struct sdhci_host
*host
)
1804 return SDHCI_MSM_MIN_CLOCK
;
1808 * __sdhci_msm_set_clock - sdhci_msm clock control.
1811 * MSM controller does not use internal divider and
1812 * instead directly control the GCC clock as per
1813 * HW recommendation.
1815 static void __sdhci_msm_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1819 sdhci_writew(host
, 0, SDHCI_CLOCK_CONTROL
);
1825 * MSM controller do not use clock divider.
1826 * Thus read SDHCI_CLOCK_CONTROL and only enable
1827 * clock with no divider value programmed.
1829 clk
= sdhci_readw(host
, SDHCI_CLOCK_CONTROL
);
1830 sdhci_enable_clk(host
, clk
);
1833 /* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
1834 static void sdhci_msm_set_clock(struct sdhci_host
*host
, unsigned int clock
)
1836 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1837 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1840 host
->mmc
->actual_clock
= msm_host
->clk_rate
= 0;
1844 sdhci_msm_hc_select_mode(host
);
1846 msm_set_clock_rate_for_bus_mode(host
, clock
);
1848 __sdhci_msm_set_clock(host
, clock
);
1851 /*****************************************************************************\
1853 * Inline Crypto Engine (ICE) support *
1855 \*****************************************************************************/
1857 #ifdef CONFIG_MMC_CRYPTO
1859 static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops
; /* forward decl */
1861 static int sdhci_msm_ice_init(struct sdhci_msm_host
*msm_host
,
1862 struct cqhci_host
*cq_host
)
1864 struct mmc_host
*mmc
= msm_host
->mmc
;
1865 struct blk_crypto_profile
*profile
= &mmc
->crypto_profile
;
1866 struct device
*dev
= mmc_dev(mmc
);
1867 struct qcom_ice
*ice
;
1868 union cqhci_crypto_capabilities caps
;
1869 union cqhci_crypto_cap_entry cap
;
1873 if (!(cqhci_readl(cq_host
, CQHCI_CAP
) & CQHCI_CAP_CS
))
1876 ice
= of_qcom_ice_get(dev
);
1877 if (ice
== ERR_PTR(-EOPNOTSUPP
)) {
1878 dev_warn(dev
, "Disabling inline encryption support\n");
1882 if (IS_ERR_OR_NULL(ice
))
1883 return PTR_ERR_OR_ZERO(ice
);
1885 msm_host
->ice
= ice
;
1887 /* Initialize the blk_crypto_profile */
1889 caps
.reg_val
= cpu_to_le32(cqhci_readl(cq_host
, CQHCI_CCAP
));
1891 /* The number of keyslots supported is (CFGC+1) */
1892 err
= devm_blk_crypto_profile_init(dev
, profile
, caps
.config_count
+ 1);
1896 profile
->ll_ops
= sdhci_msm_crypto_ops
;
1897 profile
->max_dun_bytes_supported
= 4;
1901 * Currently this driver only supports AES-256-XTS. All known versions
1902 * of ICE support it, but to be safe make sure it is really declared in
1903 * the crypto capability registers. The crypto capability registers
1904 * also give the supported data unit size(s).
1906 for (i
= 0; i
< caps
.num_crypto_cap
; i
++) {
1907 cap
.reg_val
= cpu_to_le32(cqhci_readl(cq_host
,
1909 i
* sizeof(__le32
)));
1910 if (cap
.algorithm_id
== CQHCI_CRYPTO_ALG_AES_XTS
&&
1911 cap
.key_size
== CQHCI_CRYPTO_KEY_SIZE_256
)
1912 profile
->modes_supported
[BLK_ENCRYPTION_MODE_AES_256_XTS
] |=
1913 cap
.sdus_mask
* 512;
1916 mmc
->caps2
|= MMC_CAP2_CRYPTO
;
1920 static void sdhci_msm_ice_enable(struct sdhci_msm_host
*msm_host
)
1922 if (msm_host
->mmc
->caps2
& MMC_CAP2_CRYPTO
)
1923 qcom_ice_enable(msm_host
->ice
);
1926 static __maybe_unused
int sdhci_msm_ice_resume(struct sdhci_msm_host
*msm_host
)
1928 if (msm_host
->mmc
->caps2
& MMC_CAP2_CRYPTO
)
1929 return qcom_ice_resume(msm_host
->ice
);
1934 static __maybe_unused
int sdhci_msm_ice_suspend(struct sdhci_msm_host
*msm_host
)
1936 if (msm_host
->mmc
->caps2
& MMC_CAP2_CRYPTO
)
1937 return qcom_ice_suspend(msm_host
->ice
);
1942 static inline struct sdhci_msm_host
*
1943 sdhci_msm_host_from_crypto_profile(struct blk_crypto_profile
*profile
)
1945 struct mmc_host
*mmc
= mmc_from_crypto_profile(profile
);
1946 struct sdhci_host
*host
= mmc_priv(mmc
);
1947 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
1948 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
1954 * Program a key into a QC ICE keyslot. QC ICE requires a QC-specific SCM call
1955 * for this; it doesn't support the standard way.
1957 static int sdhci_msm_ice_keyslot_program(struct blk_crypto_profile
*profile
,
1958 const struct blk_crypto_key
*key
,
1961 struct sdhci_msm_host
*msm_host
=
1962 sdhci_msm_host_from_crypto_profile(profile
);
1964 /* Only AES-256-XTS has been tested so far. */
1965 if (key
->crypto_cfg
.crypto_mode
!= BLK_ENCRYPTION_MODE_AES_256_XTS
)
1968 return qcom_ice_program_key(msm_host
->ice
,
1969 QCOM_ICE_CRYPTO_ALG_AES_XTS
,
1970 QCOM_ICE_CRYPTO_KEY_SIZE_256
,
1972 key
->crypto_cfg
.data_unit_size
/ 512,
1976 static int sdhci_msm_ice_keyslot_evict(struct blk_crypto_profile
*profile
,
1977 const struct blk_crypto_key
*key
,
1980 struct sdhci_msm_host
*msm_host
=
1981 sdhci_msm_host_from_crypto_profile(profile
);
1983 return qcom_ice_evict_key(msm_host
->ice
, slot
);
1986 static const struct blk_crypto_ll_ops sdhci_msm_crypto_ops
= {
1987 .keyslot_program
= sdhci_msm_ice_keyslot_program
,
1988 .keyslot_evict
= sdhci_msm_ice_keyslot_evict
,
1991 #else /* CONFIG_MMC_CRYPTO */
1993 static inline int sdhci_msm_ice_init(struct sdhci_msm_host
*msm_host
,
1994 struct cqhci_host
*cq_host
)
1999 static inline void sdhci_msm_ice_enable(struct sdhci_msm_host
*msm_host
)
2003 static inline __maybe_unused
int
2004 sdhci_msm_ice_resume(struct sdhci_msm_host
*msm_host
)
2009 static inline __maybe_unused
int
2010 sdhci_msm_ice_suspend(struct sdhci_msm_host
*msm_host
)
2014 #endif /* !CONFIG_MMC_CRYPTO */
2016 /*****************************************************************************\
2018 * MSM Command Queue Engine (CQE) *
2020 \*****************************************************************************/
2022 static u32
sdhci_msm_cqe_irq(struct sdhci_host
*host
, u32 intmask
)
2027 if (!sdhci_cqe_irq(host
, intmask
, &cmd_error
, &data_error
))
2030 cqhci_irq(host
->mmc
, intmask
, cmd_error
, data_error
);
2034 static void sdhci_msm_cqe_enable(struct mmc_host
*mmc
)
2036 struct sdhci_host
*host
= mmc_priv(mmc
);
2037 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
2038 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
2040 sdhci_cqe_enable(mmc
);
2041 sdhci_msm_ice_enable(msm_host
);
2044 static void sdhci_msm_cqe_disable(struct mmc_host
*mmc
, bool recovery
)
2046 struct sdhci_host
*host
= mmc_priv(mmc
);
2047 unsigned long flags
;
2051 * When CQE is halted, the legacy SDHCI path operates only
2052 * on 16-byte descriptors in 64bit mode.
2054 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
2057 spin_lock_irqsave(&host
->lock
, flags
);
2060 * During CQE command transfers, command complete bit gets latched.
2061 * So s/w should clear command complete interrupt status when CQE is
2062 * either halted or disabled. Otherwise unexpected SDCHI legacy
2063 * interrupt gets triggered when CQE is halted/disabled.
2065 ctrl
= sdhci_readl(host
, SDHCI_INT_ENABLE
);
2066 ctrl
|= SDHCI_INT_RESPONSE
;
2067 sdhci_writel(host
, ctrl
, SDHCI_INT_ENABLE
);
2068 sdhci_writel(host
, SDHCI_INT_RESPONSE
, SDHCI_INT_STATUS
);
2070 spin_unlock_irqrestore(&host
->lock
, flags
);
2072 sdhci_cqe_disable(mmc
, recovery
);
2075 static void sdhci_msm_set_timeout(struct sdhci_host
*host
, struct mmc_command
*cmd
)
2077 u32 count
, start
= 15;
2079 __sdhci_set_timeout(host
, cmd
);
2080 count
= sdhci_readb(host
, SDHCI_TIMEOUT_CONTROL
);
2082 * Update software timeout value if its value is less than hardware data
2083 * timeout value. Qcom SoC hardware data timeout value was calculated
2084 * using 4 * MCLK * 2^(count + 13). where MCLK = 1 / host->clock.
2086 if (cmd
&& cmd
->data
&& host
->clock
> 400000 &&
2087 host
->clock
<= 50000000 &&
2088 ((1 << (count
+ start
)) > (10 * host
->clock
)))
2089 host
->data_timeout
= 22LL * NSEC_PER_SEC
;
2092 static const struct cqhci_host_ops sdhci_msm_cqhci_ops
= {
2093 .enable
= sdhci_msm_cqe_enable
,
2094 .disable
= sdhci_msm_cqe_disable
,
2095 #ifdef CONFIG_MMC_CRYPTO
2096 .uses_custom_crypto_profile
= true,
2100 static int sdhci_msm_cqe_add_host(struct sdhci_host
*host
,
2101 struct platform_device
*pdev
)
2103 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
2104 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
2105 struct cqhci_host
*cq_host
;
2111 * When CQE is halted, SDHC operates only on 16byte ADMA descriptors.
2112 * So ensure ADMA table is allocated for 16byte descriptors.
2114 if (host
->caps
& SDHCI_CAN_64BIT
)
2115 host
->alloc_desc_sz
= 16;
2117 ret
= sdhci_setup_host(host
);
2121 cq_host
= cqhci_pltfm_init(pdev
);
2122 if (IS_ERR(cq_host
)) {
2123 ret
= PTR_ERR(cq_host
);
2124 dev_err(&pdev
->dev
, "cqhci-pltfm init: failed: %d\n", ret
);
2128 msm_host
->mmc
->caps2
|= MMC_CAP2_CQE
| MMC_CAP2_CQE_DCMD
;
2129 cq_host
->ops
= &sdhci_msm_cqhci_ops
;
2131 dma64
= host
->flags
& SDHCI_USE_64_BIT_DMA
;
2133 ret
= sdhci_msm_ice_init(msm_host
, cq_host
);
2137 ret
= cqhci_init(cq_host
, host
->mmc
, dma64
);
2139 dev_err(&pdev
->dev
, "%s: CQE init: failed (%d)\n",
2140 mmc_hostname(host
->mmc
), ret
);
2144 /* Disable cqe reset due to cqe enable signal */
2145 cqcfg
= cqhci_readl(cq_host
, CQHCI_VENDOR_CFG1
);
2146 cqcfg
|= CQHCI_VENDOR_DIS_RST_ON_CQ_EN
;
2147 cqhci_writel(cq_host
, cqcfg
, CQHCI_VENDOR_CFG1
);
2150 * SDHC expects 12byte ADMA descriptors till CQE is enabled.
2151 * So limit desc_sz to 12 so that the data commands that are sent
2152 * during card initialization (before CQE gets enabled) would
2153 * get executed without any issues.
2155 if (host
->flags
& SDHCI_USE_64_BIT_DMA
)
2158 ret
= __sdhci_add_host(host
);
2162 dev_info(&pdev
->dev
, "%s: CQE init: success\n",
2163 mmc_hostname(host
->mmc
));
2167 sdhci_cleanup_host(host
);
2172 * Platform specific register write functions. This is so that, if any
2173 * register write needs to be followed up by platform specific actions,
2174 * they can be added here. These functions can go to sleep when writes
2175 * to certain registers are done.
2176 * These functions are relying on sdhci_set_ios not using spinlock.
2178 static int __sdhci_msm_check_write(struct sdhci_host
*host
, u16 val
, int reg
)
2180 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
2181 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
2185 case SDHCI_HOST_CONTROL2
:
2186 req_type
= (val
& SDHCI_CTRL_VDD_180
) ? REQ_IO_LOW
:
2189 case SDHCI_SOFTWARE_RESET
:
2190 if (host
->pwr
&& (val
& SDHCI_RESET_ALL
))
2191 req_type
= REQ_BUS_OFF
;
2193 case SDHCI_POWER_CONTROL
:
2194 req_type
= !val
? REQ_BUS_OFF
: REQ_BUS_ON
;
2196 case SDHCI_TRANSFER_MODE
:
2197 msm_host
->transfer_mode
= val
;
2200 if (!msm_host
->use_cdr
)
2202 if ((msm_host
->transfer_mode
& SDHCI_TRNS_READ
) &&
2203 !mmc_op_tuning(SDHCI_GET_CMD(val
)))
2204 sdhci_msm_set_cdr(host
, true);
2206 sdhci_msm_set_cdr(host
, false);
2211 msm_host
->pwr_irq_flag
= 0;
2213 * Since this register write may trigger a power irq, ensure
2214 * all previous register writes are complete by this point.
2221 /* This function may sleep*/
2222 static void sdhci_msm_writew(struct sdhci_host
*host
, u16 val
, int reg
)
2226 req_type
= __sdhci_msm_check_write(host
, val
, reg
);
2227 writew_relaxed(val
, host
->ioaddr
+ reg
);
2230 sdhci_msm_check_power_status(host
, req_type
);
2233 /* This function may sleep*/
2234 static void sdhci_msm_writeb(struct sdhci_host
*host
, u8 val
, int reg
)
2238 req_type
= __sdhci_msm_check_write(host
, val
, reg
);
2240 writeb_relaxed(val
, host
->ioaddr
+ reg
);
2243 sdhci_msm_check_power_status(host
, req_type
);
2246 static void sdhci_msm_set_regulator_caps(struct sdhci_msm_host
*msm_host
)
2248 struct mmc_host
*mmc
= msm_host
->mmc
;
2249 struct regulator
*supply
= mmc
->supply
.vqmmc
;
2250 u32 caps
= 0, config
;
2251 struct sdhci_host
*host
= mmc_priv(mmc
);
2252 const struct sdhci_msm_offset
*msm_offset
= msm_host
->offset
;
2254 if (!IS_ERR(mmc
->supply
.vqmmc
)) {
2255 if (regulator_is_supported_voltage(supply
, 1700000, 1950000))
2256 caps
|= CORE_1_8V_SUPPORT
;
2257 if (regulator_is_supported_voltage(supply
, 2700000, 3600000))
2258 caps
|= CORE_3_0V_SUPPORT
;
2261 pr_warn("%s: 1.8/3V not supported for vqmmc\n",
2267 * Set the PAD_PWR_SWITCH_EN bit so that the PAD_PWR_SWITCH
2268 * bit can be used as required later on.
2270 u32 io_level
= msm_host
->curr_io_level
;
2272 config
= readl_relaxed(host
->ioaddr
+
2273 msm_offset
->core_vendor_spec
);
2274 config
|= CORE_IO_PAD_PWR_SWITCH_EN
;
2276 if ((io_level
& REQ_IO_HIGH
) && (caps
& CORE_3_0V_SUPPORT
))
2277 config
&= ~CORE_IO_PAD_PWR_SWITCH
;
2278 else if ((io_level
& REQ_IO_LOW
) || (caps
& CORE_1_8V_SUPPORT
))
2279 config
|= CORE_IO_PAD_PWR_SWITCH
;
2281 writel_relaxed(config
,
2282 host
->ioaddr
+ msm_offset
->core_vendor_spec
);
2284 msm_host
->caps_0
|= caps
;
2285 pr_debug("%s: supported caps: 0x%08x\n", mmc_hostname(mmc
), caps
);
2288 static int sdhci_msm_register_vreg(struct sdhci_msm_host
*msm_host
)
2292 ret
= mmc_regulator_get_supply(msm_host
->mmc
);
2296 sdhci_msm_set_regulator_caps(msm_host
);
2301 static int sdhci_msm_start_signal_voltage_switch(struct mmc_host
*mmc
,
2302 struct mmc_ios
*ios
)
2304 struct sdhci_host
*host
= mmc_priv(mmc
);
2308 * Signal Voltage Switching is only applicable for Host Controllers
2311 if (host
->version
< SDHCI_SPEC_300
)
2314 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2316 switch (ios
->signal_voltage
) {
2317 case MMC_SIGNAL_VOLTAGE_330
:
2318 if (!(host
->flags
& SDHCI_SIGNALING_330
))
2321 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
2322 ctrl
&= ~SDHCI_CTRL_VDD_180
;
2324 case MMC_SIGNAL_VOLTAGE_180
:
2325 if (!(host
->flags
& SDHCI_SIGNALING_180
))
2328 /* Enable 1.8V Signal Enable in the Host Control2 register */
2329 ctrl
|= SDHCI_CTRL_VDD_180
;
2336 sdhci_writew(host
, ctrl
, SDHCI_HOST_CONTROL2
);
2339 usleep_range(5000, 5500);
2341 /* regulator output should be stable within 5 ms */
2342 status
= ctrl
& SDHCI_CTRL_VDD_180
;
2343 ctrl
= sdhci_readw(host
, SDHCI_HOST_CONTROL2
);
2344 if ((ctrl
& SDHCI_CTRL_VDD_180
) == status
)
2347 dev_warn(mmc_dev(mmc
), "%s: Regulator output did not became stable\n",
2353 #define DRIVER_NAME "sdhci_msm"
2354 #define SDHCI_MSM_DUMP(f, x...) \
2355 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)
2357 static void sdhci_msm_dump_vendor_regs(struct sdhci_host
*host
)
2359 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
2360 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
2361 const struct sdhci_msm_offset
*msm_offset
= msm_host
->offset
;
2363 SDHCI_MSM_DUMP("----------- VENDOR REGISTER DUMP -----------\n");
2366 "DLL sts: 0x%08x | DLL cfg: 0x%08x | DLL cfg2: 0x%08x\n",
2367 readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_status
),
2368 readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config
),
2369 readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config_2
));
2371 "DLL cfg3: 0x%08x | DLL usr ctl: 0x%08x | DDR cfg: 0x%08x\n",
2372 readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_config_3
),
2373 readl_relaxed(host
->ioaddr
+ msm_offset
->core_dll_usr_ctl
),
2374 readl_relaxed(host
->ioaddr
+ msm_offset
->core_ddr_config
));
2376 "Vndr func: 0x%08x | Vndr func2 : 0x%08x Vndr func3: 0x%08x\n",
2377 readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec
),
2378 readl_relaxed(host
->ioaddr
+
2379 msm_offset
->core_vendor_spec_func2
),
2380 readl_relaxed(host
->ioaddr
+ msm_offset
->core_vendor_spec3
));
2383 static const struct sdhci_msm_variant_ops mci_var_ops
= {
2384 .msm_readl_relaxed
= sdhci_msm_mci_variant_readl_relaxed
,
2385 .msm_writel_relaxed
= sdhci_msm_mci_variant_writel_relaxed
,
2388 static const struct sdhci_msm_variant_ops v5_var_ops
= {
2389 .msm_readl_relaxed
= sdhci_msm_v5_variant_readl_relaxed
,
2390 .msm_writel_relaxed
= sdhci_msm_v5_variant_writel_relaxed
,
2393 static const struct sdhci_msm_variant_info sdhci_msm_mci_var
= {
2394 .var_ops
= &mci_var_ops
,
2395 .offset
= &sdhci_msm_mci_offset
,
2398 static const struct sdhci_msm_variant_info sdhci_msm_v5_var
= {
2399 .mci_removed
= true,
2400 .var_ops
= &v5_var_ops
,
2401 .offset
= &sdhci_msm_v5_offset
,
2404 static const struct sdhci_msm_variant_info sdm845_sdhci_var
= {
2405 .mci_removed
= true,
2406 .restore_dll_config
= true,
2407 .var_ops
= &v5_var_ops
,
2408 .offset
= &sdhci_msm_v5_offset
,
2411 static const struct of_device_id sdhci_msm_dt_match
[] = {
2413 * Do not add new variants to the driver which are compatible with
2414 * generic ones, unless they need customization.
2416 {.compatible
= "qcom,sdhci-msm-v4", .data
= &sdhci_msm_mci_var
},
2417 {.compatible
= "qcom,sdhci-msm-v5", .data
= &sdhci_msm_v5_var
},
2418 {.compatible
= "qcom,sdm670-sdhci", .data
= &sdm845_sdhci_var
},
2419 {.compatible
= "qcom,sdm845-sdhci", .data
= &sdm845_sdhci_var
},
2420 {.compatible
= "qcom,sc7180-sdhci", .data
= &sdm845_sdhci_var
},
2424 MODULE_DEVICE_TABLE(of
, sdhci_msm_dt_match
);
2426 static const struct sdhci_ops sdhci_msm_ops
= {
2427 .reset
= sdhci_and_cqhci_reset
,
2428 .set_clock
= sdhci_msm_set_clock
,
2429 .get_min_clock
= sdhci_msm_get_min_clock
,
2430 .get_max_clock
= sdhci_msm_get_max_clock
,
2431 .set_bus_width
= sdhci_set_bus_width
,
2432 .set_uhs_signaling
= sdhci_msm_set_uhs_signaling
,
2433 .write_w
= sdhci_msm_writew
,
2434 .write_b
= sdhci_msm_writeb
,
2435 .irq
= sdhci_msm_cqe_irq
,
2436 .dump_vendor_regs
= sdhci_msm_dump_vendor_regs
,
2437 .set_power
= sdhci_set_power_noreg
,
2438 .set_timeout
= sdhci_msm_set_timeout
,
2441 static const struct sdhci_pltfm_data sdhci_msm_pdata
= {
2442 .quirks
= SDHCI_QUIRK_BROKEN_CARD_DETECTION
|
2443 SDHCI_QUIRK_SINGLE_POWER_WRITE
|
2444 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN
|
2445 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12
,
2447 .quirks2
= SDHCI_QUIRK2_PRESET_VALUE_BROKEN
,
2448 .ops
= &sdhci_msm_ops
,
2451 static inline void sdhci_msm_get_of_property(struct platform_device
*pdev
,
2452 struct sdhci_host
*host
)
2454 struct device_node
*node
= pdev
->dev
.of_node
;
2455 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
2456 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
2458 if (of_property_read_u32(node
, "qcom,ddr-config",
2459 &msm_host
->ddr_config
))
2460 msm_host
->ddr_config
= DDR_CONFIG_POR_VAL
;
2462 of_property_read_u32(node
, "qcom,dll-config", &msm_host
->dll_config
);
2464 if (of_device_is_compatible(node
, "qcom,msm8916-sdhci"))
2465 host
->quirks2
|= SDHCI_QUIRK2_BROKEN_64_BIT_DMA
;
2468 static int sdhci_msm_gcc_reset(struct device
*dev
, struct sdhci_host
*host
)
2470 struct reset_control
*reset
;
2473 reset
= reset_control_get_optional_exclusive(dev
, NULL
);
2475 return dev_err_probe(dev
, PTR_ERR(reset
),
2476 "unable to acquire core_reset\n");
2481 ret
= reset_control_assert(reset
);
2483 reset_control_put(reset
);
2484 return dev_err_probe(dev
, ret
, "core_reset assert failed\n");
2488 * The hardware requirement for delay between assert/deassert
2489 * is at least 3-4 sleep clock (32.7KHz) cycles, which comes to
2490 * ~125us (4/32768). To be on the safe side add 200us delay.
2492 usleep_range(200, 210);
2494 ret
= reset_control_deassert(reset
);
2496 reset_control_put(reset
);
2497 return dev_err_probe(dev
, ret
, "core_reset deassert failed\n");
2500 usleep_range(200, 210);
2501 reset_control_put(reset
);
2506 static int sdhci_msm_probe(struct platform_device
*pdev
)
2508 struct sdhci_host
*host
;
2509 struct sdhci_pltfm_host
*pltfm_host
;
2510 struct sdhci_msm_host
*msm_host
;
2513 u16 host_version
, core_minor
;
2514 u32 core_version
, config
;
2516 const struct sdhci_msm_offset
*msm_offset
;
2517 const struct sdhci_msm_variant_info
*var_info
;
2518 struct device_node
*node
= pdev
->dev
.of_node
;
2520 host
= sdhci_pltfm_init(pdev
, &sdhci_msm_pdata
, sizeof(*msm_host
));
2522 return PTR_ERR(host
);
2524 host
->sdma_boundary
= 0;
2525 pltfm_host
= sdhci_priv(host
);
2526 msm_host
= sdhci_pltfm_priv(pltfm_host
);
2527 msm_host
->mmc
= host
->mmc
;
2528 msm_host
->pdev
= pdev
;
2530 ret
= mmc_of_parse(host
->mmc
);
2535 * Based on the compatible string, load the required msm host info from
2536 * the data associated with the version info.
2538 var_info
= of_device_get_match_data(&pdev
->dev
);
2540 msm_host
->mci_removed
= var_info
->mci_removed
;
2541 msm_host
->restore_dll_config
= var_info
->restore_dll_config
;
2542 msm_host
->var_ops
= var_info
->var_ops
;
2543 msm_host
->offset
= var_info
->offset
;
2545 msm_offset
= msm_host
->offset
;
2547 sdhci_get_of_property(pdev
);
2548 sdhci_msm_get_of_property(pdev
, host
);
2550 msm_host
->saved_tuning_phase
= INVALID_TUNING_PHASE
;
2552 ret
= sdhci_msm_gcc_reset(&pdev
->dev
, host
);
2556 /* Setup SDCC bus voter clock. */
2557 msm_host
->bus_clk
= devm_clk_get(&pdev
->dev
, "bus");
2558 if (!IS_ERR(msm_host
->bus_clk
)) {
2559 /* Vote for max. clk rate for max. performance */
2560 ret
= clk_set_rate(msm_host
->bus_clk
, INT_MAX
);
2563 ret
= clk_prepare_enable(msm_host
->bus_clk
);
2568 /* Setup main peripheral bus clock */
2569 clk
= devm_clk_get(&pdev
->dev
, "iface");
2572 dev_err(&pdev
->dev
, "Peripheral clk setup failed (%d)\n", ret
);
2573 goto bus_clk_disable
;
2575 msm_host
->bulk_clks
[1].clk
= clk
;
2577 /* Setup SDC MMC clock */
2578 clk
= devm_clk_get(&pdev
->dev
, "core");
2581 dev_err(&pdev
->dev
, "SDC MMC clk setup failed (%d)\n", ret
);
2582 goto bus_clk_disable
;
2584 msm_host
->bulk_clks
[0].clk
= clk
;
2586 /* Check for optional interconnect paths */
2587 ret
= dev_pm_opp_of_find_icc_paths(&pdev
->dev
, NULL
);
2589 goto bus_clk_disable
;
2591 ret
= devm_pm_opp_set_clkname(&pdev
->dev
, "core");
2593 goto bus_clk_disable
;
2595 /* OPP table is optional */
2596 ret
= devm_pm_opp_of_add_table(&pdev
->dev
);
2597 if (ret
&& ret
!= -ENODEV
) {
2598 dev_err(&pdev
->dev
, "Invalid OPP table in Device tree\n");
2599 goto bus_clk_disable
;
2602 /* Vote for maximum clock rate for maximum performance */
2603 ret
= dev_pm_opp_set_rate(&pdev
->dev
, INT_MAX
);
2605 dev_warn(&pdev
->dev
, "core clock boost failed\n");
2607 clk
= devm_clk_get(&pdev
->dev
, "cal");
2610 msm_host
->bulk_clks
[2].clk
= clk
;
2612 clk
= devm_clk_get(&pdev
->dev
, "sleep");
2615 msm_host
->bulk_clks
[3].clk
= clk
;
2617 ret
= clk_bulk_prepare_enable(ARRAY_SIZE(msm_host
->bulk_clks
),
2618 msm_host
->bulk_clks
);
2620 goto bus_clk_disable
;
2623 * xo clock is needed for FLL feature of cm_dll.
2624 * In case if xo clock is not mentioned in DT, warn and proceed.
2626 msm_host
->xo_clk
= devm_clk_get(&pdev
->dev
, "xo");
2627 if (IS_ERR(msm_host
->xo_clk
)) {
2628 ret
= PTR_ERR(msm_host
->xo_clk
);
2629 dev_warn(&pdev
->dev
, "TCXO clk not present (%d)\n", ret
);
2632 if (!msm_host
->mci_removed
) {
2633 msm_host
->core_mem
= devm_platform_ioremap_resource(pdev
, 1);
2634 if (IS_ERR(msm_host
->core_mem
)) {
2635 ret
= PTR_ERR(msm_host
->core_mem
);
2640 /* Reset the vendor spec register to power on reset state */
2641 writel_relaxed(CORE_VENDOR_SPEC_POR_VAL
,
2642 host
->ioaddr
+ msm_offset
->core_vendor_spec
);
2644 if (!msm_host
->mci_removed
) {
2645 /* Set HC_MODE_EN bit in HC_MODE register */
2646 msm_host_writel(msm_host
, HC_MODE_EN
, host
,
2647 msm_offset
->core_hc_mode
);
2648 config
= msm_host_readl(msm_host
, host
,
2649 msm_offset
->core_hc_mode
);
2650 config
|= FF_CLK_SW_RST_DIS
;
2651 msm_host_writel(msm_host
, config
, host
,
2652 msm_offset
->core_hc_mode
);
2655 host_version
= readw_relaxed((host
->ioaddr
+ SDHCI_HOST_VERSION
));
2656 dev_dbg(&pdev
->dev
, "Host Version: 0x%x Vendor Version 0x%x\n",
2657 host_version
, ((host_version
& SDHCI_VENDOR_VER_MASK
) >>
2658 SDHCI_VENDOR_VER_SHIFT
));
2660 core_version
= msm_host_readl(msm_host
, host
,
2661 msm_offset
->core_mci_version
);
2662 core_major
= (core_version
& CORE_VERSION_MAJOR_MASK
) >>
2663 CORE_VERSION_MAJOR_SHIFT
;
2664 core_minor
= core_version
& CORE_VERSION_MINOR_MASK
;
2665 dev_dbg(&pdev
->dev
, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
2666 core_version
, core_major
, core_minor
);
2668 if (core_major
== 1 && core_minor
>= 0x42)
2669 msm_host
->use_14lpp_dll_reset
= true;
2672 * SDCC 5 controller with major version 1, minor version 0x34 and later
2673 * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
2675 if (core_major
== 1 && core_minor
< 0x34)
2676 msm_host
->use_cdclp533
= true;
2679 * Support for some capabilities is not advertised by newer
2680 * controller versions and must be explicitly enabled.
2682 if (core_major
>= 1 && core_minor
!= 0x11 && core_minor
!= 0x12) {
2683 config
= readl_relaxed(host
->ioaddr
+ SDHCI_CAPABILITIES
);
2684 config
|= SDHCI_CAN_VDD_300
| SDHCI_CAN_DO_8BIT
;
2685 writel_relaxed(config
, host
->ioaddr
+
2686 msm_offset
->core_vendor_spec_capabilities0
);
2689 if (core_major
== 1 && core_minor
>= 0x49)
2690 msm_host
->updated_ddr_cfg
= true;
2692 if (core_major
== 1 && core_minor
>= 0x71)
2693 msm_host
->uses_tassadar_dll
= true;
2695 ret
= sdhci_msm_register_vreg(msm_host
);
2700 * Power on reset state may trigger power irq if previous status of
2701 * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq
2702 * interrupt in GIC, any pending power irq interrupt should be
2703 * acknowledged. Otherwise power irq interrupt handler would be
2704 * fired prematurely.
2706 sdhci_msm_handle_pwr_irq(host
, 0);
2709 * Ensure that above writes are propagated before interrupt enablement
2714 /* Setup IRQ for handling power/voltage tasks with PMIC */
2715 msm_host
->pwr_irq
= platform_get_irq_byname(pdev
, "pwr_irq");
2716 if (msm_host
->pwr_irq
< 0) {
2717 ret
= msm_host
->pwr_irq
;
2721 sdhci_msm_init_pwr_irq_wait(msm_host
);
2722 /* Enable pwr irq interrupts */
2723 msm_host_writel(msm_host
, INT_MASK
, host
,
2724 msm_offset
->core_pwrctl_mask
);
2726 ret
= devm_request_threaded_irq(&pdev
->dev
, msm_host
->pwr_irq
, NULL
,
2727 sdhci_msm_pwr_irq
, IRQF_ONESHOT
,
2728 dev_name(&pdev
->dev
), host
);
2730 dev_err(&pdev
->dev
, "Request IRQ failed (%d)\n", ret
);
2734 msm_host
->mmc
->caps
|= MMC_CAP_WAIT_WHILE_BUSY
| MMC_CAP_NEED_RSP_BUSY
;
2736 /* Set the timeout value to max possible */
2737 host
->max_timeout_count
= 0xF;
2739 pm_runtime_get_noresume(&pdev
->dev
);
2740 pm_runtime_set_active(&pdev
->dev
);
2741 pm_runtime_enable(&pdev
->dev
);
2742 pm_runtime_set_autosuspend_delay(&pdev
->dev
,
2743 MSM_MMC_AUTOSUSPEND_DELAY_MS
);
2744 pm_runtime_use_autosuspend(&pdev
->dev
);
2746 host
->mmc_host_ops
.start_signal_voltage_switch
=
2747 sdhci_msm_start_signal_voltage_switch
;
2748 host
->mmc_host_ops
.execute_tuning
= sdhci_msm_execute_tuning
;
2749 if (of_property_read_bool(node
, "supports-cqe"))
2750 ret
= sdhci_msm_cqe_add_host(host
, pdev
);
2752 ret
= sdhci_add_host(host
);
2754 goto pm_runtime_disable
;
2756 pm_runtime_mark_last_busy(&pdev
->dev
);
2757 pm_runtime_put_autosuspend(&pdev
->dev
);
2762 pm_runtime_disable(&pdev
->dev
);
2763 pm_runtime_set_suspended(&pdev
->dev
);
2764 pm_runtime_put_noidle(&pdev
->dev
);
2766 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host
->bulk_clks
),
2767 msm_host
->bulk_clks
);
2769 if (!IS_ERR(msm_host
->bus_clk
))
2770 clk_disable_unprepare(msm_host
->bus_clk
);
2772 sdhci_pltfm_free(pdev
);
2776 static void sdhci_msm_remove(struct platform_device
*pdev
)
2778 struct sdhci_host
*host
= platform_get_drvdata(pdev
);
2779 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
2780 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
2781 int dead
= (readl_relaxed(host
->ioaddr
+ SDHCI_INT_STATUS
) ==
2784 sdhci_remove_host(host
, dead
);
2786 pm_runtime_get_sync(&pdev
->dev
);
2787 pm_runtime_disable(&pdev
->dev
);
2788 pm_runtime_put_noidle(&pdev
->dev
);
2790 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host
->bulk_clks
),
2791 msm_host
->bulk_clks
);
2792 if (!IS_ERR(msm_host
->bus_clk
))
2793 clk_disable_unprepare(msm_host
->bus_clk
);
2794 sdhci_pltfm_free(pdev
);
2797 static __maybe_unused
int sdhci_msm_runtime_suspend(struct device
*dev
)
2799 struct sdhci_host
*host
= dev_get_drvdata(dev
);
2800 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
2801 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
2802 unsigned long flags
;
2804 spin_lock_irqsave(&host
->lock
, flags
);
2805 host
->runtime_suspended
= true;
2806 spin_unlock_irqrestore(&host
->lock
, flags
);
2808 /* Drop the performance vote */
2809 dev_pm_opp_set_rate(dev
, 0);
2810 clk_bulk_disable_unprepare(ARRAY_SIZE(msm_host
->bulk_clks
),
2811 msm_host
->bulk_clks
);
2813 return sdhci_msm_ice_suspend(msm_host
);
2816 static __maybe_unused
int sdhci_msm_runtime_resume(struct device
*dev
)
2818 struct sdhci_host
*host
= dev_get_drvdata(dev
);
2819 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
2820 struct sdhci_msm_host
*msm_host
= sdhci_pltfm_priv(pltfm_host
);
2821 unsigned long flags
;
2824 ret
= clk_bulk_prepare_enable(ARRAY_SIZE(msm_host
->bulk_clks
),
2825 msm_host
->bulk_clks
);
2829 * Whenever core-clock is gated dynamically, it's needed to
2830 * restore the SDR DLL settings when the clock is ungated.
2832 if (msm_host
->restore_dll_config
&& msm_host
->clk_rate
) {
2833 ret
= sdhci_msm_restore_sdr_dll_config(host
);
2838 dev_pm_opp_set_rate(dev
, msm_host
->clk_rate
);
2840 ret
= sdhci_msm_ice_resume(msm_host
);
2844 spin_lock_irqsave(&host
->lock
, flags
);
2845 host
->runtime_suspended
= false;
2846 spin_unlock_irqrestore(&host
->lock
, flags
);
2851 static const struct dev_pm_ops sdhci_msm_pm_ops
= {
2852 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend
,
2853 pm_runtime_force_resume
)
2854 SET_RUNTIME_PM_OPS(sdhci_msm_runtime_suspend
,
2855 sdhci_msm_runtime_resume
,
2859 static struct platform_driver sdhci_msm_driver
= {
2860 .probe
= sdhci_msm_probe
,
2861 .remove
= sdhci_msm_remove
,
2863 .name
= "sdhci_msm",
2864 .of_match_table
= sdhci_msm_dt_match
,
2865 .pm
= &sdhci_msm_pm_ops
,
2866 .probe_type
= PROBE_PREFER_ASYNCHRONOUS
,
2870 module_platform_driver(sdhci_msm_driver
);
2872 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
2873 MODULE_LICENSE("GPL v2");