drivers/mtd/spi-nor/gigadevice.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2005, Intec Automation Inc.
   4  * Copyright (C) 2014, Freescale Semiconductor, Inc.
   5  */
   6
   7 #include <linux/mtd/spi-nor.h>
   8
   9 #include "core.h"
  10
  11 static int
  12 gd25q256_post_bfpt(struct spi_nor *nor,
  13                    const struct sfdp_parameter_header *bfpt_header,
  14                    const struct sfdp_bfpt *bfpt)
  15 {
  16         /*
  17          * GD25Q256C supports the first version of JESD216 which does not define
  18          * the Quad Enable methods. Overwrite the default Quad Enable method.
  19          *
  20          * GD25Q256 GENERATION | SFDP MAJOR VERSION | SFDP MINOR VERSION
  21          *      GD25Q256C      | SFDP_JESD216_MAJOR | SFDP_JESD216_MINOR
  22          *      GD25Q256D      | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
  23          *      GD25Q256E      | SFDP_JESD216_MAJOR | SFDP_JESD216B_MINOR
  24          */
  25         if (bfpt_header->major == SFDP_JESD216_MAJOR &&
  26             bfpt_header->minor == SFDP_JESD216_MINOR)
  27                 nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
  28
  29         return 0;
  30 }
  31
  32 static const struct spi_nor_fixups gd25q256_fixups = {
  33         .post_bfpt = gd25q256_post_bfpt,
  34 };
  35
  36 static const struct flash_info gigadevice_nor_parts[] = {
  37         {
  38                 .id = SNOR_ID(0xc8, 0x40, 0x15),
  39                 .name = "gd25q16",
  40                 .size = SZ_2M,
  41                 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
  42                 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
  43         }, {
  44                 .id = SNOR_ID(0xc8, 0x40, 0x16),
  45                 .name = "gd25q32",
  46                 .size = SZ_4M,
  47                 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
  48                 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
  49         }, {
  50                 .id = SNOR_ID(0xc8, 0x40, 0x17),
  51                 .name = "gd25q64",
  52                 .size = SZ_8M,
  53                 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
  54                 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
  55         }, {
  56                 .id = SNOR_ID(0xc8, 0x40, 0x18),
  57                 .name = "gd25q128",
  58                 .size = SZ_16M,
  59                 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
  60                 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
  61         }, {
  62                 .id = SNOR_ID(0xc8, 0x40, 0x19),
  63                 .name = "gd25q256",
  64                 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB | SPI_NOR_TB_SR_BIT6,
  65                 .fixups = &gd25q256_fixups,
  66                 .fixup_flags = SPI_NOR_4B_OPCODES,
  67         }, {
  68                 .id = SNOR_ID(0xc8, 0x60, 0x16),
  69                 .name = "gd25lq32",
  70                 .size = SZ_4M,
  71                 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
  72                 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
  73         }, {
  74                 .id = SNOR_ID(0xc8, 0x60, 0x17),
  75                 .name = "gd25lq64c",
  76                 .size = SZ_8M,
  77                 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
  78                 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
  79         }, {
  80                 .id = SNOR_ID(0xc8, 0x60, 0x18),
  81                 .name = "gd25lq128d",
  82                 .size = SZ_16M,
  83                 .flags = SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB,
  84                 .no_sfdp_flags = SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ,
  85         },
  86 };
  87
  88 const struct spi_nor_manufacturer spi_nor_gigadevice = {
  89         .name = "gigadevice",
  90         .parts = gigadevice_nor_parts,
  91         .nparts = ARRAY_SIZE(gigadevice_nor_parts),
  92 };