drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /* Copyright (c) 2018-2019 Hisilicon Limited. */
   3
   4 #ifndef __HCLGE_DEBUGFS_H
   5 #define __HCLGE_DEBUGFS_H
   6
   7 #include <linux/etherdevice.h>
   8 #include "hclge_cmd.h"
   9
  10 #define HCLGE_DBG_MNG_TBL_MAX      64
  11
  12 #define HCLGE_DBG_MNG_VLAN_MASK_B  BIT(0)
  13 #define HCLGE_DBG_MNG_MAC_MASK_B   BIT(1)
  14 #define HCLGE_DBG_MNG_ETHER_MASK_B BIT(2)
  15 #define HCLGE_DBG_MNG_E_TYPE_B     BIT(11)
  16 #define HCLGE_DBG_MNG_DROP_B       BIT(13)
  17 #define HCLGE_DBG_MNG_VLAN_TAG     0x0FFF
  18 #define HCLGE_DBG_MNG_PF_ID        0x0007
  19 #define HCLGE_DBG_MNG_VF_ID        0x00FF
  20
  21 /* Get DFX BD number offset */
  22 #define HCLGE_DBG_DFX_BIOS_OFFSET  1
  23 #define HCLGE_DBG_DFX_SSU_0_OFFSET 2
  24 #define HCLGE_DBG_DFX_SSU_1_OFFSET 3
  25 #define HCLGE_DBG_DFX_IGU_OFFSET   4
  26 #define HCLGE_DBG_DFX_RPU_0_OFFSET 5
  27
  28 #define HCLGE_DBG_DFX_RPU_1_OFFSET 6
  29 #define HCLGE_DBG_DFX_NCSI_OFFSET  7
  30 #define HCLGE_DBG_DFX_RTC_OFFSET   8
  31 #define HCLGE_DBG_DFX_PPP_OFFSET   9
  32 #define HCLGE_DBG_DFX_RCB_OFFSET   10
  33 #define HCLGE_DBG_DFX_TQP_OFFSET   11
  34
  35 #define HCLGE_DBG_DFX_SSU_2_OFFSET 12
  36
  37 struct hclge_qos_pri_map_cmd {
  38         u8 pri0_tc  : 4,
  39            pri1_tc  : 4;
  40         u8 pri2_tc  : 4,
  41            pri3_tc  : 4;
  42         u8 pri4_tc  : 4,
  43            pri5_tc  : 4;
  44         u8 pri6_tc  : 4,
  45            pri7_tc  : 4;
  46         u8 vlan_pri : 4,
  47            rev      : 4;
  48 };
  49
  50 struct hclge_dbg_bitmap_cmd {
  51         union {
  52                 u8 bitmap;
  53                 struct {
  54                         u8 bit0 : 1,
  55                            bit1 : 1,
  56                            bit2 : 1,
  57                            bit3 : 1,
  58                            bit4 : 1,
  59                            bit5 : 1,
  60                            bit6 : 1,
  61                            bit7 : 1;
  62                 };
  63         };
  64 };
  65
  66 struct hclge_dbg_reg_common_msg {
  67         int msg_num;
  68         int offset;
  69         enum hclge_opcode_type cmd;
  70 };
  71
  72 struct hclge_dbg_tcam_msg {
  73         u8 stage;
  74         u32 loc;
  75 };
  76
  77 #define HCLGE_DBG_MAX_DFX_MSG_LEN       60
  78 struct hclge_dbg_dfx_message {
  79         int flag;
  80         char message[HCLGE_DBG_MAX_DFX_MSG_LEN];
  81 };
  82
  83 #define HCLGE_DBG_MAC_REG_TYPE_LEN      32
  84 struct hclge_dbg_reg_type_info {
  85         enum hnae3_dbg_cmd cmd;
  86         const struct hclge_dbg_dfx_message *dfx_msg;
  87         struct hclge_dbg_reg_common_msg reg_msg;
  88 };
  89
  90 struct hclge_dbg_func {
  91         enum hnae3_dbg_cmd cmd;
  92         int (*dbg_dump)(struct hclge_dev *hdev, char *buf, int len);
  93         int (*dbg_dump_reg)(struct hclge_dev *hdev, enum hnae3_dbg_cmd cmd,
  94                             char *buf, int len);
  95 };
  96
  97 struct hclge_dbg_status_dfx_info {
  98         u32  offset;
  99         char message[HCLGE_DBG_MAX_DFX_MSG_LEN];
 100 };
 101
 102 #define HCLGE_DBG_INFO_LEN                      256
 103 #define HCLGE_DBG_VLAN_FLTR_INFO_LEN            256
 104 #define HCLGE_DBG_VLAN_OFFLOAD_INFO_LEN         512
 105 #define HCLGE_DBG_ID_LEN                        16
 106 #define HCLGE_DBG_ITEM_NAME_LEN                 32
 107 #define HCLGE_DBG_DATA_STR_LEN                  32
 108 #define HCLGE_DBG_TM_INFO_LEN                   256
 109
 110 #define HCLGE_BILLION_NANO_SECONDS      1000000000
 111
 112 struct hclge_dbg_item {
 113         char name[HCLGE_DBG_ITEM_NAME_LEN];
 114         u16 interval; /* blank numbers after the item */
 115 };
 116
 117 struct hclge_dbg_vlan_cfg {
 118         u16 pvid;
 119         u8 accept_tag1;
 120         u8 accept_tag2;
 121         u8 accept_untag1;
 122         u8 accept_untag2;
 123         u8 insert_tag1;
 124         u8 insert_tag2;
 125         u8 shift_tag;
 126         u8 strip_tag1;
 127         u8 strip_tag2;
 128         u8 drop_tag1;
 129         u8 drop_tag2;
 130         u8 pri_only1;
 131         u8 pri_only2;
 132 };
 133
 134 int hclge_dbg_cmd_send(struct hclge_dev *hdev, struct hclge_desc *desc_src,
 135                        int index, int bd_num, enum hclge_opcode_type cmd);
 136
 137 #endif