drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*  Copyright (c) 2016-2017 Hisilicon Limited. */
   3
   4 #ifndef __HCLGE_ERR_H
   5 #define __HCLGE_ERR_H
   6
   7 #include "hclge_main.h"
   8 #include "hclge_debugfs.h"
   9 #include "hnae3.h"
  10
  11 #define HCLGE_MPF_RAS_INT_MIN_BD_NUM    10
  12 #define HCLGE_PF_RAS_INT_MIN_BD_NUM     4
  13 #define HCLGE_MPF_MSIX_INT_MIN_BD_NUM   10
  14 #define HCLGE_PF_MSIX_INT_MIN_BD_NUM    4
  15
  16 #define HCLGE_RAS_PF_OTHER_INT_STS_REG   0x20B00
  17 #define HCLGE_RAS_REG_NFE_MASK   0xFF00
  18 #define HCLGE_RAS_REG_ROCEE_ERR_MASK   0x3000000
  19 #define HCLGE_RAS_REG_ERR_MASK \
  20         (HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK)
  21
  22 #define HCLGE_VECTOR0_REG_MSIX_MASK   0x1FF00
  23
  24 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN    0xFFFF0000
  25 #define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK       0xFFFF0000
  26 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN  0x300
  27 #define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK     0x300
  28 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN   0xFFFF
  29 #define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK      0xFFFF
  30 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000
  31 #define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK    0xFFFF0000
  32 #define HCLGE_IMP_RD_POISON_ERR_INT_EN  0x0100
  33 #define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK     0x0100
  34 #define HCLGE_TQP_ECC_ERR_INT_EN        0x0FFF
  35 #define HCLGE_TQP_ECC_ERR_INT_EN_MASK   0x0FFF
  36 #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK     0x0F000000
  37 #define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN  0x0F000000
  38 #define HCLGE_IGU_ERR_INT_EN    0x0000000F
  39 #define HCLGE_IGU_ERR_INT_TYPE  0x00000660
  40 #define HCLGE_IGU_ERR_INT_EN_MASK       0x000F
  41 #define HCLGE_IGU_TNL_ERR_INT_EN    0x0002AABF
  42 #define HCLGE_IGU_TNL_ERR_INT_EN_MASK  0x003F
  43 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN   0xFFFFFFFF
  44 #define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK      0xFFFFFFFF
  45 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN   0xFFFFFFFF
  46 #define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK      0xFFFFFFFF
  47 #define HCLGE_PPP_PF_ERR_INT_EN 0x0003
  48 #define HCLGE_PPP_PF_ERR_INT_EN_MASK    0x0003
  49 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN   0x003F
  50 #define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK      0x003F
  51 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN   0x003F
  52 #define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK      0x003F
  53 #define HCLGE_TM_SCH_ECC_ERR_INT_EN     0x3
  54 #define HCLGE_TM_QCN_ERR_INT_TYPE       0x29
  55 #define HCLGE_TM_QCN_FIFO_INT_EN        0xFFFF00
  56 #define HCLGE_TM_QCN_MEM_ERR_INT_EN     0xFFFFFF
  57 #define HCLGE_NCSI_ERR_INT_EN   0x3
  58 #define HCLGE_NCSI_ERR_INT_TYPE 0x9
  59 #define HCLGE_MAC_COMMON_ERR_INT_EN             0x107FF
  60 #define HCLGE_MAC_COMMON_ERR_INT_EN_MASK        0x107FF
  61 #define HCLGE_MAC_TNL_INT_EN                    GENMASK(9, 0)
  62 #define HCLGE_MAC_TNL_INT_EN_MASK               GENMASK(9, 0)
  63 #define HCLGE_MAC_TNL_INT_CLR                   GENMASK(9, 0)
  64 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN          GENMASK(31, 0)
  65 #define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK     GENMASK(31, 0)
  66 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN          GENMASK(31, 0)
  67 #define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK     GENMASK(31, 0)
  68 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN          0x3FFF3FFF
  69 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK     0x3FFF3FFF
  70 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2         0xB
  71 #define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK    0xB
  72 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN          GENMASK(7, 0)
  73 #define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK     GENMASK(23, 16)
  74 #define HCLGE_PPU_PF_ABNORMAL_INT_EN            GENMASK(5, 0)
  75 #define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK       GENMASK(5, 0)
  76 #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN           GENMASK(31, 0)
  77 #define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK      GENMASK(31, 0)
  78 #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN      GENMASK(31, 0)
  79 #define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
  80 #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN          0x0101
  81 #define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK     0x0101
  82 #define HCLGE_SSU_COMMON_INT_EN                 GENMASK(9, 0)
  83 #define HCLGE_SSU_COMMON_INT_EN_MASK            GENMASK(9, 0)
  84 #define HCLGE_SSU_PORT_BASED_ERR_INT_EN         0x0BFF
  85 #define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK    0x0BFF0000
  86 #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN      GENMASK(23, 0)
  87 #define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
  88
  89 #define HCLGE_SSU_COMMON_ERR_INT_MASK   GENMASK(9, 0)
  90 #define HCLGE_SSU_PORT_INT_MSIX_MASK    0x7BFF
  91 #define HCLGE_IGU_INT_MASK              GENMASK(3, 0)
  92 #define HCLGE_IGU_EGU_TNL_INT_MASK      GENMASK(5, 0)
  93 #define HCLGE_PPP_MPF_INT_ST3_MASK      GENMASK(5, 0)
  94 #define HCLGE_PPU_MPF_INT_ST3_MASK      GENMASK(7, 0)
  95 #define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK BIT(29)
  96 #define HCLGE_PPU_PF_INT_RAS_MASK       0x18
  97 #define HCLGE_PPU_PF_INT_MSIX_MASK      0x26
  98 #define HCLGE_PPU_PF_OVER_8BD_ERR_MASK  0x01
  99 #define HCLGE_QCN_FIFO_INT_MASK         GENMASK(17, 0)
 100 #define HCLGE_QCN_ECC_INT_MASK          GENMASK(21, 0)
 101 #define HCLGE_NCSI_ECC_INT_MASK         GENMASK(1, 0)
 102
 103 #define HCLGE_ROCEE_RAS_NFE_INT_EN              0xF
 104 #define HCLGE_ROCEE_RAS_CE_INT_EN               0x1
 105 #define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK         0xF
 106 #define HCLGE_ROCEE_RAS_CE_INT_EN_MASK          0x1
 107 #define HCLGE_ROCEE_RERR_INT_MASK               BIT(0)
 108 #define HCLGE_ROCEE_BERR_INT_MASK               BIT(1)
 109 #define HCLGE_ROCEE_AXI_ERR_INT_MASK            GENMASK(1, 0)
 110 #define HCLGE_ROCEE_ECC_INT_MASK                BIT(2)
 111 #define HCLGE_ROCEE_OVF_INT_MASK                BIT(3)
 112 #define HCLGE_ROCEE_OVF_ERR_INT_MASK            0x10000
 113 #define HCLGE_ROCEE_OVF_ERR_TYPE_MASK           0x3F
 114
 115 #define HCLGE_DESC_DATA_MAX                     8
 116 #define HCLGE_REG_NUM_MAX                       256
 117 #define HCLGE_DESC_NO_DATA_LEN                  8
 118
 119 #define HCLGE_BD_NUM_SSU_REG_0          10
 120 #define HCLGE_BD_NUM_SSU_REG_1          15
 121 #define HCLGE_BD_NUM_RPU_REG_0          1
 122 #define HCLGE_BD_NUM_RPU_REG_1          2
 123 #define HCLGE_BD_NUM_IGU_EGU_REG        9
 124 #define HCLGE_BD_NUM_GEN_REG            8
 125 #define HCLGE_MOD_REG_INFO_LEN_MAX      256
 126 #define HCLGE_MOD_REG_EXTRA_LEN         11
 127 #define HCLGE_MOD_REG_VALUE_LEN         9
 128 #define HCLGE_MOD_REG_GROUP_MAX_SIZE    6
 129 #define HCLGE_MOD_MSG_PARA_ARRAY_MAX_SIZE       8
 130
 131 enum hclge_err_int_type {
 132         HCLGE_ERR_INT_MSIX = 0,
 133         HCLGE_ERR_INT_RAS_CE = 1,
 134         HCLGE_ERR_INT_RAS_NFE = 2,
 135         HCLGE_ERR_INT_RAS_FE = 3,
 136 };
 137
 138 enum hclge_mod_name_list {
 139         MODULE_NONE             = 0,
 140         MODULE_BIOS_COMMON      = 1,
 141         MODULE_GE               = 2,
 142         MODULE_IGU_EGU          = 3,
 143         MODULE_LGE              = 4,
 144         MODULE_NCSI             = 5,
 145         MODULE_PPP              = 6,
 146         MODULE_QCN              = 7,
 147         MODULE_RCB_RX           = 8,
 148         MODULE_RTC              = 9,
 149         MODULE_SSU              = 10,
 150         MODULE_TM               = 11,
 151         MODULE_RCB_TX           = 12,
 152         MODULE_TXDMA            = 13,
 153         MODULE_MASTER           = 14,
 154         MODULE_HIMAC            = 15,
 155         /* add new MODULE NAME for NIC here in order */
 156         MODULE_ROCEE_TOP        = 40,
 157         MODULE_ROCEE_TIMER      = 41,
 158         MODULE_ROCEE_MDB        = 42,
 159         MODULE_ROCEE_TSP        = 43,
 160         MODULE_ROCEE_TRP        = 44,
 161         MODULE_ROCEE_SCC        = 45,
 162         MODULE_ROCEE_CAEP       = 46,
 163         MODULE_ROCEE_GEN_AC     = 47,
 164         MODULE_ROCEE_QMM        = 48,
 165         MODULE_ROCEE_LSAN       = 49,
 166         /* add new MODULE NAME for RoCEE here in order */
 167 };
 168
 169 enum hclge_err_type_list {
 170         NONE_ERROR              = 0,
 171         FIFO_ERROR              = 1,
 172         MEMORY_ERROR            = 2,
 173         POISON_ERROR            = 3,
 174         MSIX_ECC_ERROR          = 4,
 175         TQP_INT_ECC_ERROR       = 5,
 176         PF_ABNORMAL_INT_ERROR   = 6,
 177         MPF_ABNORMAL_INT_ERROR  = 7,
 178         COMMON_ERROR            = 8,
 179         PORT_ERROR              = 9,
 180         ETS_ERROR               = 10,
 181         NCSI_ERROR              = 11,
 182         GLB_ERROR               = 12,
 183         LINK_ERROR              = 13,
 184         PTP_ERROR               = 14,
 185         /* add new ERROR TYPE for NIC here in order */
 186         ROCEE_NORMAL_ERR        = 40,
 187         ROCEE_OVF_ERR           = 41,
 188         ROCEE_BUS_ERR           = 42,
 189         /* add new ERROR TYPE for ROCEE here in order */
 190 };
 191
 192 struct hclge_hw_blk {
 193         u32 msk;
 194         const char *name;
 195         int (*config_err_int)(struct hclge_dev *hdev, bool en);
 196 };
 197
 198 struct hclge_hw_error {
 199         u32 int_msk;
 200         const char *msg;
 201         enum hnae3_reset_type reset_level;
 202 };
 203
 204 struct hclge_hw_module_id {
 205         enum hclge_mod_name_list module_id;
 206         const char *msg;
 207         void (*query_reg_info)(struct hclge_dev *hdev);
 208 };
 209
 210 struct hclge_hw_type_id {
 211         enum hclge_err_type_list type_id;
 212         const char *msg;
 213         bool cause_by_vf; /* indicate the error may from vf exception */
 214 };
 215
 216 struct hclge_sum_err_info {
 217         u8 reset_type;
 218         u8 mod_num;
 219         u8 rsv[2];
 220 };
 221
 222 struct hclge_mod_err_info {
 223         u8 mod_id;
 224         u8 err_num;
 225         u8 rsv[2];
 226 };
 227
 228 struct hclge_type_reg_err_info {
 229         u8 type_id;
 230         u8 reg_num;
 231         u8 rsv[2];
 232         u32 hclge_reg[HCLGE_REG_NUM_MAX];
 233 };
 234
 235 struct hclge_mod_reg_info {
 236         const char *reg_name;
 237         bool has_suffix; /* add suffix for register name */
 238         /* the positions of reg values in hclge_desc.data */
 239         u8 reg_offset_group[HCLGE_MOD_REG_GROUP_MAX_SIZE];
 240         u8 group_size;
 241 };
 242
 243 /* This structure defines cmdq used to query the hardware module debug
 244  * regisgers.
 245  */
 246 struct hclge_mod_reg_common_msg {
 247         enum hclge_opcode_type cmd;
 248         struct hclge_desc *desc;
 249         u8 bd_num; /* the bd number of hclge_desc used */
 250         bool need_para; /* whether this cmdq needs to add para */
 251
 252         /* the regs need to print */
 253         const struct hclge_mod_reg_info *result_regs;
 254         u16 result_regs_size;
 255 };
 256
 257 int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
 258 int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
 259 int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
 260 void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);
 261 bool hclge_find_error_source(struct hclge_dev *hdev);
 262 void hclge_handle_occurred_error(struct hclge_dev *hdev);
 263 pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
 264 int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
 265                                unsigned long *reset_requests);
 266 int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev);
 267 int hclge_handle_mac_tnl(struct hclge_dev *hdev);
 268 int hclge_handle_vf_queue_err_ras(struct hclge_dev *hdev);
 269 #endif