| blob | 286155efcedf7ac0c1d12d0cb1098673ddfdf568 |
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
6 #include <linux/module.h>
7 #include <linux/types.h>
8 #include <linux/init.h>
9 #include <linux/pci.h>
10 #include <linux/vmalloc.h>
11 #include <linux/pagemap.h>
12 #include <linux/delay.h>
13 #include <linux/netdevice.h>
14 #include <linux/interrupt.h>
15 #include <linux/tcp.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/ethtool.h>
21 #include <linux/if_vlan.h>
22 #include <linux/cpu.h>
23 #include <linux/smp.h>
24 #include <linux/pm_qos.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/prefetch.h>
27 #include <linux/suspend.h>
30 #define CREATE_TRACE_POINTS
35 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
58 };
61 u32 ofs;
63 };
66 /* General Registers */
71 /* Interrupt Registers */
74 /* Rx Registers */
90 /* Tx Registers */
107 /* List Terminator */
109 };
111 /**
112 * __ew32_prepare - prepare to write to MAC CSR register on certain parts
113 * @hw: pointer to the HW structure
114 *
115 * When updating the MAC CSR registers, the Manageability Engine (ME) could
116 * be accessing the registers at the same time. Normally, this is handled in
117 * h/w by an arbiter but on some parts there is a bug that acknowledges Host
118 * accesses later than it should which could result in the register to have
119 * an incorrect value. Workaround this by checking the FWSM register which
120 * has bit 24 set while ME is accessing MAC CSR registers, wait if it is set
121 * and try again a number of times.
122 **/
124 {
129 }
132 {
137 }
139 /**
140 * e1000_regdump - register printout routine
141 * @hw: pointer to the HW structure
142 * @reginfo: pointer to the register info table
143 **/
145 {
167 }
171 }
175 {
187 }
188 }
189 }
191 /**
192 * e1000e_dump - Print registers, Tx-ring and Rx-ring
193 * @adapter: board private structure
194 **/
196 {
203 __le64 a;
204 __le64 b;
211 __le64 a;
212 __le64 b;
213 __le64 c;
214 __le64 d;
216 u32 staterr;
222 /* Print netdevice Info */
228 }
230 /* Print Registers */
236 }
238 /* Print Tx Ring Summary */
252 /* Print Tx Ring */
258 /* Transmit Descriptor Formats - DEXT[29] is 0 (Legacy) or 1 (Extended)
259 *
260 * Legacy Transmit Descriptor
261 * +--------------------------------------------------------------+
262 * 0 | Buffer Address [63:0] (Reserved on Write Back) |
263 * +--------------------------------------------------------------+
264 * 8 | Special | CSS | Status | CMD | CSO | Length |
265 * +--------------------------------------------------------------+
266 * 63 48 47 36 35 32 31 24 23 16 15 0
267 *
268 * Extended Context Descriptor (DTYP=0x0) for TSO or checksum offload
269 * 63 48 47 40 39 32 31 16 15 8 7 0
270 * +----------------------------------------------------------------+
271 * 0 | TUCSE | TUCS0 | TUCSS | IPCSE | IPCS0 | IPCSS |
272 * +----------------------------------------------------------------+
273 * 8 | MSS | HDRLEN | RSV | STA | TUCMD | DTYP | PAYLEN |
274 * +----------------------------------------------------------------+
275 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
276 *
277 * Extended Data Descriptor (DTYP=0x1)
278 * +----------------------------------------------------------------+
279 * 0 | Buffer Address [63:0] |
280 * +----------------------------------------------------------------+
281 * 8 | VLAN tag | POPTS | Rsvd | Status | Command | DTYP | DTALEN |
282 * +----------------------------------------------------------------+
283 * 63 48 47 40 39 36 35 32 31 24 23 20 19 0
284 */
285 pr_info("Tl[desc] [address 63:0 ] [SpeCssSCmCsLen] [bi->dma ] leng ntw timestamp bi->skb <-- Legacy format\n");
286 pr_info("Tc[desc] [Ce CoCsIpceCoS] [MssHlRSCm0Plen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Context format\n");
287 pr_info("Td[desc] [address 63:0 ] [VlaPoRSCm1Dlen] [bi->dma ] leng ntw timestamp bi->skb <-- Ext Data format\n");
299 else
304 i,
316 }
318 /* Print Rx Ring Summary */
319 rx_ring_summary:
325 /* Print Rx Ring */
334 /* [Extended] Packet Split Receive Descriptor Format
335 *
336 * +-----------------------------------------------------+
337 * 0 | Buffer Address 0 [63:0] |
338 * +-----------------------------------------------------+
339 * 8 | Buffer Address 1 [63:0] |
340 * +-----------------------------------------------------+
341 * 16 | Buffer Address 2 [63:0] |
342 * +-----------------------------------------------------+
343 * 24 | Buffer Address 3 [63:0] |
344 * +-----------------------------------------------------+
345 */
346 pr_info("R [desc] [buffer 0 63:0 ] [buffer 1 63:0 ] [buffer 2 63:0 ] [buffer 3 63:0 ] [bi->dma ] [bi->skb] <-- Ext Pkt Split format\n");
347 /* [Extended] Receive Descriptor (Write-Back) Format
348 *
349 * 63 48 47 32 31 13 12 8 7 4 3 0
350 * +------------------------------------------------------+
351 * 0 | Packet | IP | Rsvd | MRQ | Rsvd | MRQ RSS |
352 * | Checksum | Ident | | Queue | | Type |
353 * +------------------------------------------------------+
354 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
355 * +------------------------------------------------------+
356 * 63 48 47 32 31 20 19 0
357 */
358 pr_info("RWB[desc] [ck ipid mrqhsh] [vl l0 ee es] [ l3 l2 l1 hs] [reserved ] ---------------- [bi->skb] <-- Ext Rx Write-Back format\n");
364 staterr =
371 else
375 /* Descriptor Done */
395 buffer_info);
396 }
397 }
401 /* Extended Receive Descriptor (Read) Format
402 *
403 * +-----------------------------------------------------+
404 * 0 | Buffer Address [63:0] |
405 * +-----------------------------------------------------+
406 * 8 | Reserved |
407 * +-----------------------------------------------------+
408 */
409 pr_info("R [desc] [buf addr 63:0 ] [reserved 63:0 ] [bi->dma ] [bi->skb] <-- Ext (Read) format\n");
410 /* Extended Receive Descriptor (Write-Back) Format
411 *
412 * 63 48 47 32 31 24 23 4 3 0
413 * +------------------------------------------------------+
414 * | RSS Hash | | | |
415 * 0 +-------------------+ Rsvd | Reserved | MRQ RSS |
416 * | Packet | IP | | | Type |
417 * | Checksum | Ident | | | |
418 * +------------------------------------------------------+
419 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
420 * +------------------------------------------------------+
421 * 63 48 47 32 31 20 19 0
422 */
437 else
441 /* Descriptor Done */
463 }
464 }
465 }
466 }
468 /**
469 * e1000_desc_unused - calculate if we have unused descriptors
470 * @ring: pointer to ring struct to perform calculation on
471 **/
473 {
478 }
480 /**
481 * e1000e_systim_to_hwtstamp - convert system time value to hw time stamp
482 * @adapter: board private structure
483 * @hwtstamps: time stamp structure to update
484 * @systim: unsigned 64bit system time value.
485 *
486 * Convert the system time value stored in the RX/TXSTMP registers into a
487 * hwtstamp which can be used by the upper level time stamping functions.
488 *
489 * The 'systim_lock' spinlock is used to protect the consistency of the
490 * system time value. This is needed because reading the 64 bit time
491 * value involves reading two 32 bit registers. The first read latches the
492 * value.
493 **/
496 u64 systim)
497 {
498 u64 ns;
507 }
509 /**
510 * e1000e_rx_hwtstamp - utility function which checks for Rx time stamp
511 * @adapter: board private structure
512 * @status: descriptor extended error and status field
513 * @skb: particular skb to include time stamp
514 *
515 * If the time stamp is valid, convert it into the timecounter ns value
516 * and store that result into the shhwtstamps structure which is passed
517 * up the network stack.
518 **/
521 {
523 u64 rxstmp;
530 /* The Rx time stamp registers contain the time stamp. No other
531 * received packet will be time stamped until the Rx time stamp
532 * registers are read. Because only one packet can be time stamped
533 * at a time, the register values must belong to this packet and
534 * therefore none of the other additional attributes need to be
535 * compared.
536 */
542 }
544 /**
545 * e1000_receive_skb - helper function to handle Rx indications
546 * @adapter: board private structure
547 * @netdev: pointer to netdev struct
548 * @staterr: descriptor extended error and status field as written by hardware
549 * @vlan: descriptor vlan field as written by hardware (no le/be conversion)
550 * @skb: pointer to sk_buff to be indicated to stack
551 **/
555 {
566 }
568 /**
569 * e1000_rx_checksum - Receive Checksum Offload
570 * @adapter: board private structure
571 * @status_err: receive descriptor status and error fields
572 * @skb: socket buffer with received data
573 **/
576 {
582 /* Rx checksum disabled */
586 /* Ignore Checksum bit is set */
590 /* TCP/UDP checksum error bit or IP checksum error bit is set */
592 /* let the stack verify checksum errors */
595 }
597 /* TCP/UDP Checksum has not been calculated */
601 /* It must be a TCP or UDP packet with a valid checksum */
604 }
607 {
620 }
621 }
624 {
637 }
638 }
640 /**
641 * e1000_alloc_rx_buffers - Replace used receive buffers
642 * @rx_ring: Rx descriptor ring
643 * @cleaned_count: number to reallocate
644 * @gfp: flags for allocation
645 **/
648 {
666 }
670 /* Better luck next round */
673 }
676 map_skb:
679 DMA_FROM_DEVICE);
684 }
690 /* Force memory writes to complete before letting h/w
691 * know there are new descriptors to fetch. (Only
692 * applicable for weak-ordered memory model archs,
693 * such as IA-64).
694 */
698 else
700 }
701 i++;
705 }
708 }
710 /**
711 * e1000_alloc_rx_buffers_ps - Replace used receive buffers; packet split
712 * @rx_ring: Rx descriptor ring
713 * @cleaned_count: number to reallocate
714 * @gfp: flags for allocation
715 **/
718 {
737 /* all unused desc entries get hw null ptr */
741 }
747 }
751 DMA_FROM_DEVICE);
758 }
759 }
760 /* Refresh the desc even if buffer_addrs
761 * didn't change because each write-back
762 * erases this info.
763 */
766 }
769 gfp);
774 }
779 DMA_FROM_DEVICE);
783 /* cleanup skb */
787 }
792 /* Force memory writes to complete before letting h/w
793 * know there are new descriptors to fetch. (Only
794 * applicable for weak-ordered memory model archs,
795 * such as IA-64).
796 */
800 else
802 }
804 i++;
808 }
810 no_buffers:
812 }
814 /**
815 * e1000_alloc_jumbo_rx_buffers - Replace used jumbo receive buffers
816 * @rx_ring: Rx descriptor ring
817 * @cleaned_count: number of buffers to allocate this pass
818 * @gfp: flags for allocation
819 **/
823 {
841 }
845 /* Better luck next round */
848 }
851 check_page:
852 /* allocate a new page if necessary */
858 }
859 }
864 PAGE_SIZE,
865 DMA_FROM_DEVICE);
869 }
870 }
878 }
885 /* Force memory writes to complete before letting h/w
886 * know there are new descriptors to fetch. (Only
887 * applicable for weak-ordered memory model archs,
888 * such as IA-64).
889 */
893 else
895 }
896 }
900 {
903 }
905 /**
906 * e1000_clean_rx_irq - Send received data up the network stack
907 * @rx_ring: Rx descriptor ring
908 * @work_done: output parameter for indicating completed work
909 * @work_to_do: how many packets we can clean
910 *
911 * the return value indicates whether actual cleaning was done, there
912 * is no guarantee that everything was cleaned
913 **/
916 {
947 i++;
956 cleaned_count++;
963 /* !EOP means multiple descriptors were used to store a single
964 * packet, if that's the case we need to toss it. In fact, we
965 * need to toss every packet with the EOP bit clear and the
966 * next frame that _does_ have the EOP bit set, as it is by
967 * definition only a frame fragment
968 */
973 /* All receives must fit into a single buffer */
975 /* recycle */
980 }
984 /* recycle */
987 }
989 /* adjust length to remove Ethernet CRC */
991 /* If configured to store CRC, don't subtract FCS,
992 * but keep the FCS bytes out of the total_rx_bytes
993 * counter
994 */
997 else
999 }
1002 total_rx_packets++;
1004 /* code added for copybreak, this should improve
1005 * performance for small packets with large amounts
1006 * of reassembly being done in the stack
1007 */
1015 NET_IP_ALIGN),
1017 NET_IP_ALIGN));
1018 /* save the skb in buffer_info as good */
1021 }
1022 /* else just continue with the old one */
1023 }
1024 /* end copybreak code */
1027 /* Receive Checksum Offload */
1035 next_desc:
1038 /* return some buffers to hardware, one at a time is too slow */
1041 GFP_ATOMIC);
1043 }
1045 /* use prefetched values */
1050 }
1060 }
1065 {
1072 else
1076 }
1080 else
1083 }
1085 }
1088 {
1091 print_hang_task);
1099 u16 pci_status;
1105 /* May be block on write-back, flush and detect again
1106 * flush pending descriptor writebacks to memory
1107 */
1109 /* execute the writes immediately */
1111 /* Due to rare timing issues, write to TIDV again to ensure
1112 * the write is successful
1113 */
1115 /* execute the writes immediately */
1119 }
1125 }
1127 /* Real hang detected */
1136 /* detected Hardware unit hang */
1159 /* Suggest workaround for known h/w issue */
1162 }
1164 /**
1165 * e1000e_tx_hwtstamp_work - check for Tx time stamp
1166 * @work: pointer to work struct
1167 *
1168 * This work function polls the TSYNCTXCTL valid bit to determine when a
1169 * timestamp has been taken for the current stored skb. The timestamp must
1170 * be for this skb because only one such packet is allowed in the queue.
1171 */
1173 {
1175 tx_hwtstamp_work);
1181 u64 txstmp;
1188 /* Clear the global tx_hwtstamp_skb pointer and force writes
1189 * prior to notifying the stack of a Tx timestamp.
1190 */
1203 /* reschedule to check later */
1205 }
1206 }
1208 /**
1209 * e1000_clean_tx_irq - Reclaim resources after transmit completes
1210 * @tx_ring: Tx descriptor ring
1211 *
1212 * the return value indicates whether actual cleaning was done, there
1213 * is no guarantee that everything was cleaned
1214 **/
1216 {
1246 pkts_compl++;
1247 }
1248 }
1253 i++;
1256 }
1262 }
1268 #define TX_WAKE_THRESHOLD 32
1271 /* Make sure that anybody stopping the queue after this
1272 * sees the new next_to_clean.
1273 */
1280 }
1281 }
1284 /* Detect a transmit hang in hardware, this serializes the
1285 * check with the clearing of time_stamp and movement of i
1286 */
1293 else
1295 }
1299 }
1301 /**
1302 * e1000_clean_rx_irq_ps - Send received data up the network stack; packet split
1303 * @rx_ring: Rx descriptor ring
1304 * @work_done: output parameter for indicating completed work
1305 * @work_to_do: how many packets we can clean
1306 *
1307 * the return value indicates whether actual cleaning was done, there
1308 * is no guarantee that everything was cleaned
1309 **/
1312 {
1339 /* in the packet split case this is header only */
1342 i++;
1351 cleaned_count++;
1356 /* see !EOP comment in other Rx routine */
1366 }
1372 }
1380 }
1382 /* Good Receive */
1385 {
1386 /* this looks ugly, but it seems compiler issues make
1387 * it more efficient than reusing j
1388 */
1391 /* page alloc/put takes too long and effects small
1392 * packet throughput, so unsplit small packets and
1393 * save the alloc/put
1394 */
1401 PAGE_SIZE,
1402 DMA_FROM_DEVICE);
1407 PAGE_SIZE,
1408 DMA_FROM_DEVICE);
1410 /* remove the CRC */
1414 }
1419 }
1428 DMA_FROM_DEVICE);
1435 }
1437 /* strip the ethernet crc, problem is we're using pages now so
1438 * this whole operation can get a little cpu intensive
1439 */
1443 }
1445 copydone:
1447 total_rx_packets++;
1460 next_desc:
1464 /* return some buffers to hardware, one at a time is too slow */
1467 GFP_ATOMIC);
1469 }
1471 /* use prefetched values */
1476 }
1486 }
1489 u16 length)
1490 {
1495 }
1497 /**
1498 * e1000_clean_jumbo_rx_irq - Send received data up the network stack; legacy
1499 * @rx_ring: Rx descriptor ring
1500 * @work_done: output parameter for indicating completed work
1501 * @work_to_do: how many packets we can clean
1502 *
1503 * the return value indicates whether actual cleaning was done, there
1504 * is no guarantee that everything was cleaned
1505 **/
1508 {
1546 cleaned_count++;
1548 DMA_FROM_DEVICE);
1553 /* errors is only valid for DD + EOP descriptors */
1557 /* recycle both page and skb */
1559 /* an error means any chain goes out the window too */
1564 }
1565 #define rxtop (rx_ring->rx_skb_top)
1567 /* this descriptor is only the beginning (or middle) */
1569 /* this is the beginning of a chain */
1574 /* this is the middle of a chain */
1578 length);
1579 /* re-use the skb, only consumed the page */
1581 }
1586 /* end of the chain */
1590 length);
1591 /* re-use the current skb, we only consumed the
1592 * page
1593 */
1599 /* no chain, got EOP, this buf is the packet
1600 * copybreak to save the put_page/alloc_page
1601 */
1606 length);
1607 /* re-use the page, so don't erase
1608 * buffer_info->page
1609 */
1614 length);
1616 length);
1617 }
1618 }
1619 }
1621 /* Receive Checksum Offload */
1626 /* probably a little skewed due to removing CRC */
1628 total_rx_packets++;
1630 /* eth type trans needs skb->data to point to something */
1635 }
1640 next_desc:
1643 /* return some buffers to hardware, one at a time is too slow */
1646 GFP_ATOMIC);
1648 }
1650 /* use prefetched values */
1655 }
1665 }
1667 /**
1668 * e1000_clean_rx_ring - Free Rx Buffers per Queue
1669 * @rx_ring: Rx descriptor ring
1670 **/
1672 {
1679 /* Free all the Rx ring sk_buffs */
1686 DMA_FROM_DEVICE);
1693 DMA_FROM_DEVICE);
1695 }
1700 }
1705 }
1712 DMA_FROM_DEVICE);
1716 }
1717 }
1719 /* there also may be some cached data from a chained receive */
1723 }
1725 /* Zero out the descriptor ring */
1731 }
1734 {
1737 downshift_task);
1743 }
1745 /**
1746 * e1000_intr_msi - Interrupt Handler
1747 * @irq: interrupt number
1748 * @data: pointer to a network interface device structure
1749 **/
1751 {
1757 /* read ICR disables interrupts using IAM */
1760 /* ICH8 workaround-- Call gig speed drop workaround on cable
1761 * disconnect (LSC) before accessing any PHY registers
1762 */
1767 /* 80003ES2LAN workaround-- For packet buffer work-around on
1768 * link down event; disable receives here in the ISR and reset
1769 * adapter in watchdog
1770 */
1773 /* disable receives */
1778 }
1779 /* guard against interrupt when we're going down */
1782 }
1784 /* Reset on uncorrectable ECC error */
1793 /* Do the reset outside of interrupt context */
1796 /* return immediately since reset is imminent */
1798 }
1806 }
1809 }
1811 /**
1812 * e1000_intr - Interrupt Handler
1813 * @irq: interrupt number
1814 * @data: pointer to a network interface device structure
1815 **/
1817 {
1826 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
1827 * not set, then the adapter didn't send an interrupt
1828 */
1832 /* Interrupt Auto-Mask...upon reading ICR,
1833 * interrupts are masked. No need for the
1834 * IMC write
1835 */
1839 /* ICH8 workaround-- Call gig speed drop workaround on cable
1840 * disconnect (LSC) before accessing any PHY registers
1841 */
1846 /* 80003ES2LAN workaround--
1847 * For packet buffer work-around on link down event;
1848 * disable receives here in the ISR and
1849 * reset adapter in watchdog
1850 */
1853 /* disable receives */
1857 }
1858 /* guard against interrupt when we're going down */
1861 }
1863 /* Reset on uncorrectable ECC error */
1872 /* Do the reset outside of interrupt context */
1875 /* return immediately since reset is imminent */
1877 }
1885 }
1888 }
1891 {
1902 /* guard against interrupt when we're going down */
1905 }
1911 }
1914 {
1924 /* Ring was not completely cleaned, so fire another interrupt */
1931 }
1934 {
1939 /* Write the ITR value calculated at the end of the
1940 * previous interrupt.
1941 */
1948 }
1954 }
1956 }
1958 /**
1959 * e1000_configure_msix - Configure MSI-X hardware
1960 * @adapter: board private structure
1961 *
1962 * e1000_configure_msix sets up the hardware to properly
1963 * generate MSI-X interrupts.
1964 **/
1966 {
1975 /* Workaround issue with spurious interrupts on 82574 in MSI-X mode */
1981 }
1983 /* Configure Rx vector */
1989 else
1993 /* Configure Tx vector */
1995 vector++;
1999 else
2004 /* set vector for Other Causes, e.g. link changes */
2005 vector++;
2010 else
2013 /* Cause Tx interrupts on every write back */
2018 /* enable MSI-X PBA support */
2023 }
2026 {
2034 }
2035 }
2037 /**
2038 * e1000e_set_interrupt_capability - set MSI or MSI-X if supported
2039 * @adapter: board private structure
2040 *
2041 * Attempt to configure interrupts using the best available
2042 * capabilities of the hardware and kernel.
2043 **/
2045 {
2055 msix_entry),
2056 GFP_KERNEL);
2069 }
2070 /* MSI-X failed, so fall through and try MSI */
2073 }
2075 fallthrough;
2082 }
2083 fallthrough;
2085 /* Don't do anything; this is the system default */
2087 }
2089 /* store the number of vectors being used */
2091 }
2093 /**
2094 * e1000_request_msix - Initialize MSI-X interrupts
2095 * @adapter: board private structure
2096 *
2097 * e1000_request_msix allocates MSI-X vectors and requests interrupts from the
2098 * kernel.
2099 **/
2101 {
2109 else
2113 netdev);
2119 vector++;
2125 else
2129 netdev);
2135 vector++;
2145 }
2147 /**
2148 * e1000_request_irq - initialize interrupts
2149 * @adapter: board private structure
2150 *
2151 * Attempts to configure interrupts using the best available
2152 * capabilities of the hardware and kernel.
2153 **/
2155 {
2163 /* fall back to MSI */
2167 }
2174 /* fall back to legacy interrupt */
2177 }
2185 }
2188 {
2195 vector++;
2198 vector++;
2200 /* Other Causes interrupt vector */
2203 }
2206 }
2208 /**
2209 * e1000_irq_disable - Mask off interrupt generation on the NIC
2210 * @adapter: board private structure
2211 **/
2213 {
2228 }
2229 }
2231 /**
2232 * e1000_irq_enable - Enable default interrupt generation settings
2233 * @adapter: board private structure
2234 **/
2236 {
2242 IMS_OTHER_MASK);
2247 }
2249 }
2251 /**
2252 * e1000e_get_hw_control - get control of the h/w from f/w
2253 * @adapter: address of board private structure
2254 *
2255 * e1000e_get_hw_control sets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2256 * For ASF and Pass Through versions of f/w this means that
2257 * the driver is loaded. For AMT version (only with 82573)
2258 * of the f/w this means that the network i/f is open.
2259 **/
2261 {
2263 u32 ctrl_ext;
2264 u32 swsm;
2266 /* Let firmware know the driver has taken over */
2273 }
2274 }
2276 /**
2277 * e1000e_release_hw_control - release control of the h/w to f/w
2278 * @adapter: address of board private structure
2279 *
2280 * e1000e_release_hw_control resets {CTRL_EXT|SWSM}:DRV_LOAD bit.
2281 * For ASF and Pass Through versions of f/w this means that the
2282 * driver is no longer loaded. For AMT version (only with 82573) i
2283 * of the f/w this means that the network i/f is closed.
2284 *
2285 **/
2287 {
2289 u32 ctrl_ext;
2290 u32 swsm;
2292 /* Let firmware taken over control of h/w */
2299 }
2300 }
2302 /**
2303 * e1000_alloc_ring_dma - allocate memory for a ring structure
2304 * @adapter: board private structure
2305 * @ring: ring struct for which to allocate dma
2306 **/
2309 {
2313 GFP_KERNEL);
2318 }
2320 /**
2321 * e1000e_setup_tx_resources - allocate Tx resources (Descriptors)
2322 * @tx_ring: Tx descriptor ring
2323 *
2324 * Return 0 on success, negative on failure
2325 **/
2327 {
2336 /* round up to nearest 4K */
2348 err:
2352 }
2354 /**
2355 * e1000e_setup_rx_resources - allocate Rx resources (Descriptors)
2356 * @rx_ring: Rx descriptor ring
2357 *
2358 * Returns 0 on success, negative on failure
2359 **/
2361 {
2375 GFP_KERNEL);
2378 }
2382 /* Round up to nearest 4K */
2396 err_pages:
2400 }
2401 err:
2405 }
2407 /**
2408 * e1000_clean_tx_ring - Free Tx Buffers
2409 * @tx_ring: Tx descriptor ring
2410 **/
2412 {
2421 }
2431 }
2433 /**
2434 * e1000e_free_tx_resources - Free Tx Resources per Queue
2435 * @tx_ring: Tx descriptor ring
2436 *
2437 * Free all transmit software resources
2438 **/
2440 {
2452 }
2454 /**
2455 * e1000e_free_rx_resources - Free Rx Resources
2456 * @rx_ring: Rx descriptor ring
2457 *
2458 * Free all receive software resources
2459 **/
2461 {
2477 }
2479 /**
2480 * e1000_update_itr - update the dynamic ITR value based on statistics
2481 * @itr_setting: current adapter->itr
2482 * @packets: the number of packets during this measurement interval
2483 * @bytes: the number of bytes during this measurement interval
2484 *
2485 * Stores a new ITR value based on packets and byte
2486 * counts during the last interrupt. The advantage of per interrupt
2487 * computation is faster updates and more accurate ITR for the current
2488 * traffic pattern. Constants in this function were computed
2489 * based on theoretical maximum wire speed and thresholds were set based
2490 * on testing data as well as attempting to minimize response time
2491 * while increasing bulk throughput. This functionality is controlled
2492 * by the InterruptThrottleRate module parameter.
2493 **/
2495 {
2503 /* handle TSO and jumbo frames */
2511 /* this if handles the TSO accounting */
2522 }
2530 }
2532 }
2535 }
2538 {
2539 u16 current_itr;
2542 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
2546 }
2551 }
2556 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2563 /* conservative mode (itr 3) eliminates the lowest_latency setting */
2569 /* counts and packets in update_itr are dependent on these numbers */
2582 }
2584 set_itr_now:
2586 /* this attempts to bias the interrupt rate towards Bulk
2587 * by adding intermediate steps when interrupt rate is
2588 * increasing
2589 */
2596 else
2598 }
2599 }
2601 /**
2602 * e1000e_write_itr - write the ITR value to the appropriate registers
2603 * @adapter: address of board private structure
2604 * @itr: new ITR value to program
2605 *
2606 * e1000e_write_itr determines if the adapter is in MSI-X mode
2607 * and, if so, writes the EITR registers with the ITR value.
2608 * Otherwise, it writes the ITR value into the ITR register.
2609 **/
2611 {
2622 }
2623 }
2625 /**
2626 * e1000_alloc_queues - Allocate memory for all rings
2627 * @adapter: board private structure to initialize
2628 **/
2630 {
2646 err:
2651 }
2653 /**
2654 * e1000e_poll - NAPI Rx polling callback
2655 * @napi: struct associated with this polling callback
2656 * @budget: number of packets driver is allowed to process this poll
2657 **/
2659 {
2661 napi);
2677 /* Exit the polling mode, but don't re-enable interrupts if stack might
2678 * poll us due to busy-polling
2679 */
2686 else
2688 }
2689 }
2692 }
2696 {
2701 /* don't update vlan cookie if already programmed */
2703 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2707 /* add VID to filter table */
2713 }
2718 }
2722 {
2728 E1000_MNG_DHCP_COOKIE_STATUS_VLAN) &&
2730 /* release control to f/w */
2733 }
2735 /* remove VID from filter table */
2741 }
2746 }
2748 /**
2749 * e1000e_vlan_filter_disable - helper to disable hw VLAN filtering
2750 * @adapter: board private structure to initialize
2751 **/
2753 {
2756 u32 rctl;
2759 /* disable VLAN receive filtering */
2768 }
2769 }
2770 }
2772 /**
2773 * e1000e_vlan_filter_enable - helper to enable HW VLAN filtering
2774 * @adapter: board private structure to initialize
2775 **/
2777 {
2779 u32 rctl;
2782 /* enable VLAN receive filtering */
2787 }
2788 }
2790 /**
2791 * e1000e_vlan_strip_disable - helper to disable HW VLAN stripping
2792 * @adapter: board private structure to initialize
2793 **/
2795 {
2797 u32 ctrl;
2799 /* disable VLAN tag insert/strip */
2803 }
2805 /**
2806 * e1000e_vlan_strip_enable - helper to enable HW VLAN stripping
2807 * @adapter: board private structure to initialize
2808 **/
2810 {
2812 u32 ctrl;
2814 /* enable VLAN tag insert/strip */
2818 }
2821 {
2829 }
2833 }
2836 {
2837 u16 vid;
2843 }
2846 {
2855 /* enable receiving management packets to the host. this will probably
2856 * generate destination unreachable messages from the host OS, but
2857 * the packets will be handled on SMBUS
2858 */
2868 /* Check if IPMI pass-through decision filter already exists;
2869 * if so, enable it.
2870 */
2874 /* Ignore filters with anything other than IPMI ports */
2878 /* Enable this decision filter in MANC2H */
2883 }
2888 /* Create new decision filter in an empty filter */
2892 E1000_MDEF_PORT_664));
2894 j++;
2896 }
2901 }
2905 }
2907 /**
2908 * e1000_configure_tx - Configure Transmit Unit after Reset
2909 * @adapter: board private structure
2910 *
2911 * Configure the Tx unit of the MAC after a reset.
2912 **/
2914 {
2917 u64 tdba;
2920 /* Setup the HW Tx Head and Tail descriptor pointers */
2934 /* Set the Tx Interrupt Delay register */
2936 /* Tx irq moderation */
2943 E1000_TXDCTL_WTHRESH);
2944 /* set up some performance related parameters to encourage the
2945 * hardware to use the bus more efficiently in bursts, depends
2946 * on the tx_int_delay to be enabled,
2947 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2948 * hthresh = 1 ==> prefetch when one or more available
2949 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2950 * BEWARE: this seems to work but should be considered first if
2951 * there are Tx hangs or other Tx related bugs
2952 */
2955 }
2956 /* erratum work around: set txdctl the same for both queues */
2959 /* Program the Transmit Control Register */
2967 /* set the speed mode bit, we'll clear it if we're not at
2968 * gigabit link later
2969 */
2970 #define SPEED_MODE_BIT BIT(21)
2973 }
2975 /* errata: program both queues to unweighted RR */
2983 }
2985 /* Setup Transmit Descriptor Settings for eop descriptor */
2988 /* only set IDE if we are delaying interrupts using the timers */
2992 /* enable Report Status bit */
2999 /* SPT and KBL Si errata workaround to avoid data corruption */
3001 u32 reg_val;
3008 /* SPT and KBL Si errata workaround to avoid Tx hang.
3009 * Dropping the number of outstanding requests from
3010 * 3 to 2 in order to avoid a buffer overrun.
3011 */
3015 }
3016 }
3018 #define PAGE_USE_COUNT(S) (((S) >> PAGE_SHIFT) + \
3019 (((S) & (PAGE_SIZE - 1)) ? 1 : 0))
3021 /**
3022 * e1000_setup_rctl - configure the receive control registers
3023 * @adapter: Board private structure
3024 **/
3026 {
3031 /* Workaround Si errata on PCHx - configure jumbo frame flow.
3032 * If jumbo frames not set, program related MAC/PHY registers
3033 * to h/w defaults
3034 */
3036 s32 ret_val;
3040 else
3045 }
3047 /* Program MC offset vector base */
3054 /* Do not Store bad packets */
3057 /* Enable Long Packet receive */
3060 else
3063 /* Some systems expect that the CRC is included in SMBUS traffic. The
3064 * hardware strips the CRC before sending to both SMBUS (BMC) and to
3065 * host memory when this is enabled
3066 */
3070 /* Workaround Si errata on 82577 PHY - configure IPG for jumbos */
3072 u16 phy_data;
3085 }
3087 /* Setup buffer sizes */
3105 }
3107 /* Enable Extended Status in all Receive Descriptors */
3112 /* 82571 and greater support packet-split where the protocol
3113 * header is placed in skb->data and the packet data is
3114 * placed in pages hanging off of skb_shinfo(skb)->nr_frags.
3115 * In the case of a non-split, skb->data is linearly filled,
3116 * followed by the page buffers. Therefore, skb->data is
3117 * sized to hold the largest protocol header.
3118 *
3119 * allocations using alloc_page take too long for regular MTU
3120 * so only enable packet split for jumbo frames
3121 *
3122 * Using pages when the page size is greater than 16k wastes
3123 * a lot of memory, since we allocate 3 pages at all times
3124 * per packet.
3125 */
3129 else
3135 /* Enable Packet split descriptors */
3143 fallthrough;
3146 fallthrough;
3150 }
3153 }
3155 /* This is useful for sniffing bad packets. */
3157 /* UPE and MPE will be handled by normal PROMISC logic
3158 * in e1000e_set_rx_mode
3159 */
3167 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3168 * and that breaks VLANs.
3169 */
3170 }
3173 /* just started the receive unit, no need to restart */
3175 }
3177 /**
3178 * e1000_configure_rx - Configure Receive Unit after Reset
3179 * @adapter: board private structure
3180 *
3181 * Configure the Rx unit of the MAC after a reset.
3182 **/
3184 {
3187 u64 rdba;
3191 /* this is a 32 byte descriptor */
3204 }
3206 /* disable receives while setting up the descriptors */
3214 /* set the writeback threshold (only takes effect if the RDTR
3215 * is set). set GRAN=1 and write back up to 0x4 worth, and
3216 * enable prefetching of 0x20 Rx descriptors
3217 * granularity = 01
3218 * wthresh = 04,
3219 * hthresh = 04,
3220 * pthresh = 0x20
3221 */
3224 }
3226 /* set the Receive Delay Timer Register */
3229 /* irq moderation */
3235 /* Auto-Mask interrupts upon ICR access */
3241 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3242 * the Base and Length of the Rx Descriptor Ring
3243 */
3256 /* Enable Receive Checksum Offload for TCP and UDP */
3260 else
3264 /* With jumbo frames, excessive C-state transition latencies result
3265 * in dropped transactions.
3266 */
3268 u32 lat =
3276 }
3283 PM_QOS_DEFAULT_VALUE);
3284 }
3286 /* Enable Receives */
3288 }
3290 /**
3291 * e1000e_write_mc_addr_list - write multicast addresses to MTA
3292 * @netdev: network interface device structure
3293 *
3294 * Writes multicast address list to the MTA hash table.
3295 * Returns: -ENOMEM on failure
3296 * 0 on no addresses written
3297 * X on writing X addresses to MTA
3298 */
3300 {
3308 /* nothing to program, so clear mc list */
3311 }
3317 /* update_mc_addr_list expects a packed array of only addresses. */
3326 }
3328 /**
3329 * e1000e_write_uc_addr_list - write unicast addresses to RAR table
3330 * @netdev: network interface device structure
3331 *
3332 * Writes unicast address list to the RAR table.
3333 * Returns: -ENOMEM on failure/insufficient address space
3334 * 0 on no addresses written
3335 * X on writing X addresses to the RAR table
3336 **/
3338 {
3346 /* save a rar entry for our hardware address */
3347 rar_entries--;
3349 /* save a rar entry for the LAA workaround */
3351 rar_entries--;
3353 /* return ENOMEM indicating insufficient memory for addresses */
3360 /* write the addresses in reverse order to avoid write
3361 * combining
3362 */
3371 count++;
3372 }
3373 }
3375 /* zero out the remaining RAR entries not used above */
3379 }
3383 }
3385 /**
3386 * e1000e_set_rx_mode - secondary unicast, Multicast and Promiscuous mode set
3387 * @netdev: network interface device structure
3388 *
3389 * The ndo_set_rx_mode entry point is called whenever the unicast or multicast
3390 * address list or the network interface flags are updated. This routine is
3391 * responsible for configuring the hardware for proper unicast, multicast,
3392 * promiscuous mode, and all-multi behavior.
3393 **/
3395 {
3398 u32 rctl;
3403 /* Check for Promiscuous and All Multicast modes */
3406 /* clear the affected bits */
3411 /* Do not hardware filter VLANs in promisc mode */
3419 /* Write addresses to the MTA, if the attempt fails
3420 * then we should just turn on promiscuous mode so
3421 * that we can at least receive multicast traffic
3422 */
3426 }
3428 /* Write addresses to available RAR registers, if there is not
3429 * sufficient space to store all the addresses then enable
3430 * unicast promiscuous mode
3431 */
3435 }
3441 else
3443 }
3446 {
3456 /* Direct all traffic to queue 0 */
3460 /* Disable raw packet checksumming so that RSS hash is placed in
3461 * descriptor on writeback.
3462 */
3469 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3470 E1000_MRQC_RSS_FIELD_IPV6 |
3471 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3472 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
3475 }
3477 /**
3478 * e1000e_get_base_timinca - get default SYSTIM time increment attributes
3479 * @adapter: board private structure
3480 * @timinca: pointer to returned time increment attributes
3481 *
3482 * Get attributes for incrementing the System Time Register SYSTIML/H at
3483 * the default base frequency, and set the cyclecounter shift value.
3484 **/
3486 {
3490 /* Make sure clock is enabled on I217/I218/I219 before checking
3491 * the frequency
3492 */
3501 }
3502 }
3506 /* Stable 96MHz frequency */
3514 /* Stable 96MHz frequency */
3520 /* Stable 25MHz frequency */
3525 }
3528 /* Stable 24MHz frequency */
3542 /* Stable 24MHz frequency */
3548 /* Stable 38400KHz frequency */
3553 }
3557 /* Stable 25MHz frequency */
3565 }
3571 }
3573 /**
3574 * e1000e_config_hwtstamp - configure the hwtstamp registers and enable/disable
3575 * @adapter: board private structure
3576 * @config: timestamp configuration
3577 *
3578 * Outgoing time stamping can be enabled and disabled. Play nice and
3579 * disable it when requested, although it shouldn't cause any overhead
3580 * when no packet needs it. At most one packet in the queue may be
3581 * marked for time stamping, otherwise it would be impossible to tell
3582 * for sure to which packet the hardware time stamp belongs.
3583 *
3584 * Incoming time stamping has to be configured via the hardware filters.
3585 * Not all combinations are supported, in particular event type has to be
3586 * specified. Matching the kind of event packet is not supported, with the
3587 * exception of "all V2 events regardless of level 2 or 4".
3588 **/
3591 {
3599 u32 regval;
3612 }
3629 /* Also time stamps V2 L2 Path Delay Request/Response */
3635 /* Also time stamps V2 L2 Path Delay Request/Response. */
3641 /* Hardware cannot filter just V2 L4 Sync messages */
3642 fallthrough;
3644 /* Also time stamps V2 Path Delay Request/Response. */
3651 /* Hardware cannot filter just V2 L4 Delay Request messages */
3652 fallthrough;
3654 /* Also time stamps V2 Path Delay Request/Response. */
3662 /* Hardware cannot filter just V2 L4 or L2 Event messages */
3663 fallthrough;
3671 /* For V1, the hardware can only filter Sync messages or
3672 * Delay Request messages but not both so fall-through to
3673 * time stamp all packets.
3674 */
3675 fallthrough;
3685 }
3689 /* enable/disable Tx h/w time stamping */
3698 }
3700 /* enable/disable Rx h/w time stamping */
3706 E1000_TSYNCRXCTL_TYPE_MASK)) !=
3708 E1000_TSYNCRXCTL_TYPE_MASK))) {
3711 }
3713 /* L2: define ethertype filter for time stamped packets */
3717 /* define which PTP packets get time stamped */
3720 /* Filter by destination port */
3724 }
3729 /* Clear TSYNCRXCTL_VALID & TSYNCTXCTL_VALID bit */
3734 }
3736 /**
3737 * e1000_configure - configure the hardware for Rx and Tx
3738 * @adapter: private board structure
3739 **/
3741 {
3756 }
3758 /**
3759 * e1000e_power_up_phy - restore link in case the phy was powered down
3760 * @adapter: address of board private structure
3761 *
3762 * The phy may be powered down to save power and turn off link when the
3763 * driver is unloaded and wake on lan is not enabled (among others)
3764 * *** this routine MUST be followed by a call to e1000e_reset ***
3765 **/
3767 {
3772 }
3774 /**
3775 * e1000_power_down_phy - Power down the PHY
3776 * @adapter: board private structure
3777 *
3778 * Power down the PHY so no link is implied when interface is down.
3779 * The PHY cannot be powered down if management or WoL is active.
3780 */
3782 {
3785 }
3787 /**
3788 * e1000_flush_tx_ring - remove all descriptors from the tx_ring
3789 * @adapter: board private structure
3790 *
3791 * We want to clear all pending descriptors from the TX ring.
3792 * zeroing happens when the HW reads the regs. We assign the ring itself as
3793 * the data of the next descriptor. We don't care about the data we are about
3794 * to reset the HW.
3795 */
3797 {
3813 /* flush descriptors to memory before notifying the HW */
3820 }
3822 /**
3823 * e1000_flush_rx_ring - remove all descriptors from the rx_ring
3824 * @adapter: board private structure
3825 *
3826 * Mark all descriptors in the RX ring as consumed and disable the rx ring
3827 */
3829 {
3839 /* zero the lower 14 bits (prefetch and host thresholds) */
3842 /* update thresholds: prefetch threshold to 31, host threshold to 1
3843 * and make sure the granularity is "descriptors" and not "cache lines"
3844 */
3848 /* momentarily enable the RX ring for the changes to take effect */
3853 }
3855 /**
3856 * e1000_flush_desc_rings - remove all descriptors from the descriptor rings
3857 * @adapter: board private structure
3858 *
3859 * In i219, the descriptor rings must be emptied before resetting the HW
3860 * or before changing the device state to D3 during runtime (runtime PM).
3861 *
3862 * Failure to do this will cause the HW to enter a unit hang state which can
3863 * only be released by PCI reset on the device
3864 *
3865 */
3868 {
3869 u16 hang_state;
3873 /* First, disable MULR fix in FEXTNVM11 */
3877 /* do nothing if we're not in faulty state, or if the queue is empty */
3884 /* recheck, maybe the fault is caused by the rx ring */
3889 }
3891 /**
3892 * e1000e_systim_reset - reset the timesync registers after a hardware reset
3893 * @adapter: board private structure
3894 *
3895 * When the MAC is reset, all hardware bits for timesync will be reset to the
3896 * default values. This function will restore the settings last in place.
3897 * Since the clock SYSTIME registers are reset, we will simply restore the
3898 * cyclecounter to the kernel real clock time.
3899 **/
3901 {
3905 u32 timinca;
3906 s32 ret_val;
3912 /* restore the previous ptp frequency delta */
3915 /* set the default base frequency if no adjustment possible */
3919 }
3924 ret_val);
3926 }
3928 /* reset the systim ns time counter */
3934 /* restore the previous hwtstamp configuration settings */
3936 }
3938 /**
3939 * e1000e_reset - bring the hardware into a known good state
3940 * @adapter: board private structure
3941 *
3942 * This function boots the hardware and enables some settings that
3943 * require a configuration cycle of the hardware - those cannot be
3944 * set/changed during runtime. After reset the device needs to be
3945 * properly configured for Rx, Tx etc.
3946 */
3948 {
3954 u16 hwm;
3956 /* reset Packet Buffer Allocation to default */
3960 /* To maintain wire speed transmits, the Tx FIFO should be
3961 * large enough to accommodate two full transmit packets,
3962 * rounded up to the next 1KB and expressed in KB. Likewise,
3963 * the Rx FIFO should be large enough to accommodate at least
3964 * one full receive packet and is similarly rounded up and
3965 * expressed in KB.
3966 */
3968 /* upper 16 bits has Tx packet buffer allocation size in KB */
3970 /* lower 16 bits has Rx packet buffer allocation size in KB */
3972 /* the Tx fifo also stores 16 bytes of information about the Tx
3973 * but don't include ethernet FCS because hardware appends it
3974 */
3979 /* software strips receive CRC, so leave room for it */
3984 /* If current Tx allocation is less than the min Tx FIFO size,
3985 * and the min Tx FIFO size is less than the current Rx FIFO
3986 * allocation, take space away from current Rx allocation
3987 */
3992 /* if short on Rx space, Rx wins and must trump Tx
3993 * adjustment
3994 */
3997 }
4000 }
4002 /* flow control settings
4003 *
4004 * The high water mark must be low enough to fit one full frame
4005 * (or the size used for early receive) above it in the Rx FIFO.
4006 * Set it to the lower of:
4007 * - 90% of the Rx FIFO size, and
4008 * - the full Rx FIFO size minus one full frame
4009 */
4012 else
4026 }
4027 fallthrough;
4036 /* Workaround PCH LOM adapter hangs with certain network
4037 * loads. If hangs persist, try disabling Tx flow control.
4038 */
4045 }
4065 }
4072 }
4074 /* Alignment of Tx data is on an arbitrary byte boundary with the
4075 * maximum size per Tx descriptor limited only to the transmit
4076 * allocation of the packet buffer minus 96 bytes with an upper
4077 * limit of 24KB due to receive synchronization limitations.
4078 */
4082 /* Disable Adaptive Interrupt Moderation if 2 full packets cannot
4083 * fit in receive buffer.
4084 */
4092 }
4099 }
4100 }
4104 /* Allow time for pending master requests to run */
4107 /* For parts with AMT enabled, let the firmware know
4108 * that the network interface is in control
4109 */
4120 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
4125 /* restore systim and hwtstamp settings */
4128 /* Set EEE advertisement as appropriate */
4130 s32 ret_val;
4131 u16 adv_addr;
4144 }
4151 }
4158 }
4169 /* speed up time to link by disabling smart power down, ignore
4170 * the return value of this function because there is nothing
4171 * different we would do if it failed
4172 */
4176 }
4178 u32 reg;
4180 /* Fextnvm7 @ 0xe4[2] = 1 */
4184 /* Fextnvm9 @ 0x5bb4[13:12] = 11 */
4187 E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS;
4189 }
4191 }
4193 /**
4194 * e1000e_trigger_lsc - trigger an LSC interrupt
4195 * @adapter: board private structure
4196 *
4197 * Fire a link status change interrupt to start the watchdog.
4198 **/
4200 {
4205 else
4207 }
4210 {
4211 /* hardware has been reset, we need to reload some things */
4220 /* Tx queue started by watchdog timer when link is up */
4223 }
4226 {
4232 /* flush pending descriptor writebacks to memory */
4236 /* execute the writes immediately */
4239 /* due to rare timing issues, write to TIDV/RDTR again to ensure the
4240 * write is successful
4241 */
4245 /* execute the writes immediately */
4247 }
4251 /**
4252 * e1000e_down - quiesce the device and optionally reset the hardware
4253 * @adapter: board private structure
4254 * @reset: boolean flag to reset the hardware or not
4255 */
4257 {
4262 /* signal that we're down so the interrupt handler does not
4263 * reschedule our watchdog timer
4264 */
4269 /* disable receives in the hardware */
4273 /* flush and sleep below */
4277 /* disable transmits in the hardware */
4282 /* flush both disables and wait for them to finish */
4302 /* Disable Si errata workaround on PCHx for jumbo frame flow */
4313 }
4316 }
4319 {
4326 }
4328 /**
4329 * e1000e_sanitize_systim - sanitize raw cycle counter reads
4330 * @hw: pointer to the HW structure
4331 * @systim: PHC time value read, sanitized and returned
4332 * @sts: structure to hold system time before and after reading SYSTIML,
4333 * may be NULL
4334 *
4335 * Errata for 82574/82583 possible bad bits read from SYSTIMH/L:
4336 * check to see that the time is incrementing at a reasonable
4337 * rate and is a multiple of incvalue.
4338 **/
4341 {
4343 u64 systim_next;
4344 u32 incvalue;
4349 /* latch SYSTIMH on read of SYSTIML */
4357 /* VMWare users have seen incvalue of zero, don't div / 0 */
4364 }
4367 }
4369 /**
4370 * e1000e_read_systim - read SYSTIM register
4371 * @adapter: board private structure
4372 * @sts: structure which will contain system time before and after reading
4373 * SYSTIML, may be NULL
4374 **/
4377 {
4380 u64 systim;
4381 /* SYSTIMH latching upon SYSTIML read does not work well.
4382 * This means that if SYSTIML overflows after we read it but before
4383 * we read SYSTIMH, the value of SYSTIMH has been incremented and we
4384 * will experience a huge non linear increment in the systime value
4385 * to fix that we test for overflow and if true, we re-read systime.
4386 */
4391 /* Is systimel is so large that overflow is possible? */
4397 /* There was an overflow, read again SYSTIMH, and use
4398 * systimel_2
4399 */
4402 }
4403 }
4411 }
4413 /**
4414 * e1000e_cyclecounter_read - read raw cycle counter (used by time counter)
4415 * @cc: cyclecounter structure
4416 **/
4418 {
4420 cc);
4423 }
4425 /**
4426 * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
4427 * @adapter: board private structure to initialize
4428 *
4429 * e1000_sw_init initializes the Adapter private data structure.
4430 * Fields are initialized based on PCI device information and
4431 * OS network device settings (MTU size).
4432 **/
4434 {
4451 /* Setup hardware time stamping cyclecounter */
4456 /* cc.shift set in e1000e_get_base_tininca() */
4460 }
4462 /* Explicitly disable IRQ since the NIC can be in any state. */
4467 }
4469 /**
4470 * e1000_intr_msi_test - Interrupt Handler
4471 * @irq: interrupt number
4472 * @data: pointer to a network interface device structure
4473 **/
4475 {
4484 /* Force memory writes to complete before acknowledging the
4485 * interrupt is handled.
4486 */
4488 }
4491 }
4493 /**
4494 * e1000_test_msi_interrupt - Returns 0 for successful test
4495 * @adapter: board private struct
4496 *
4497 * code flow taken from tg3.c
4498 **/
4500 {
4505 /* poll_enable hasn't been called yet, so don't need disable */
4506 /* clear any pending events */
4509 /* free the real vector and request a test handler */
4513 /* Assume that the test fails, if it succeeds then the test
4514 * MSI irq handler will unset this flag
4515 */
4527 }
4529 /* Force memory writes to complete before enabling and firing an
4530 * interrupt.
4531 */
4536 /* fire an unusual interrupt on the test handler */
4550 }
4555 msi_test_failed:
4558 }
4560 /**
4561 * e1000_test_msi - Returns 0 if MSI test succeeds or INTx mode is restored
4562 * @adapter: board private struct
4563 *
4564 * code flow taken from tg3.c, called with e1000 interrupts disabled.
4565 **/
4567 {
4569 u16 pci_cmd;
4574 /* disable SERR in case the MSI write causes a master abort */
4582 /* re-enable SERR */
4587 }
4590 }
4592 /**
4593 * e1000e_open - Called when a network interface is made active
4594 * @netdev: network interface device structure
4595 *
4596 * Returns 0 on success, negative value on failure
4597 *
4598 * The open entry point is called when a network interface is made
4599 * active by the system (IFF_UP). At this point all resources needed
4600 * for transmit and receive operations are allocated, the interrupt
4601 * handler is registered with the OS, the watchdog timer is started,
4602 * and the stack is notified that the interface is ready.
4603 **/
4605 {
4612 /* disallow open during test */
4621 /* allocate transmit descriptors */
4626 /* allocate receive descriptors */
4631 /* If AMT is enabled, let the firmware know that the network
4632 * interface is now open and reset the part to a known state.
4633 */
4637 }
4645 /* DMA latency requirement to workaround jumbo issue */
4648 /* before we allocate an interrupt, we must be ready to handle it.
4649 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
4650 * as soon as we call pci_request_irq, so we have to setup our
4651 * clean_rx handler before we do so.
4652 */
4659 /* Work around PCIe errata with MSI interrupts causing some chipsets to
4660 * ignore e1000e MSI messages, which means we need to test our MSI
4661 * interrupt now
4662 */
4668 }
4669 }
4671 /* From here on the code is the same as e1000e_up() */
4676 else
4695 err_req_irq:
4700 err_setup_rx:
4702 err_setup_tx:
4707 }
4709 /**
4710 * e1000e_close - Disables a network interface
4711 * @netdev: network interface device structure
4712 *
4713 * Returns 0, this is not allowed to fail
4714 *
4715 * The close entry point is called when an interface is de-activated
4716 * by the OS. The hardware is still under the drivers control, but
4717 * needs to be disabled. A global MAC reset is issued to stop the
4718 * hardware, and all transmit and receive resources are freed.
4719 **/
4721 {
4737 /* Link status message must follow this format */
4739 }
4748 /* kill manageability vlan ID if supported, but not if a vlan with
4749 * the same ID is registered on the host OS (let 8021q kill it)
4750 */
4755 /* If AMT is enabled, let the firmware know that the network
4756 * interface is now closed
4757 */
4767 }
4769 /**
4770 * e1000_set_mac - Change the Ethernet Address of the NIC
4771 * @netdev: network interface device structure
4772 * @p: pointer to an address structure
4773 *
4774 * Returns 0 on success, negative on failure
4775 **/
4777 {
4791 /* activate the work around */
4794 /* Hold a copy of the LAA in RAR[14] This is done so that
4795 * between the time RAR[0] gets clobbered and the time it
4796 * gets fixed (in e1000_watchdog), the actual LAA is in one
4797 * of the RARs and no incoming packets directed to this port
4798 * are dropped. Eventually the LAA will be in RAR[0] and
4799 * RAR[14]
4800 */
4803 }
4806 }
4808 /**
4809 * e1000e_update_phy_task - work thread to update phy
4810 * @work: pointer to our work struct
4811 *
4812 * this worker thread exists because we must acquire a
4813 * semaphore to read the phy, which we could msleep while
4814 * waiting for it, and we can't msleep in a timer.
4815 **/
4817 {
4820 update_phy_task);
4828 /* Enable EEE on 82579 after link up */
4831 }
4833 /**
4834 * e1000_update_phy_info - timre call-back to update PHY info
4835 * @t: pointer to timer_list containing private info adapter
4836 *
4837 * Need to wait a few seconds after link up to get diagnostic information from
4838 * the phy
4839 **/
4841 {
4848 }
4850 /**
4851 * e1000e_update_phy_stats - Update the PHY statistics counters
4852 * @adapter: board private structure
4853 *
4854 * Read/clear the upper 16-bit PHY registers and read/accumulate lower
4855 **/
4857 {
4859 s32 ret_val;
4860 u16 phy_data;
4866 /* A page set is expensive so check if already on desired page.
4867 * If not, set to the page with the PHY status registers.
4868 */
4879 }
4881 /* Single Collision Count */
4887 /* Excessive Collision Count */
4893 /* Multiple Collision Count */
4899 /* Late Collision Count */
4905 /* Collision Count - also used for adaptive IFS */
4911 /* Defer Count */
4917 /* Transmit with no CRS */
4923 release:
4925 }
4927 /**
4928 * e1000e_update_stats - Update the board statistics counters
4929 * @adapter: board private structure
4930 **/
4932 {
4937 /* Prevent stats update while adapter is being reset, or if the pci
4938 * connection is down.
4939 */
4955 /* Half-duplex statistics */
4971 }
4973 }
4988 /* used for adaptive IFS */
4999 /* Fill out the OS statistics structure */
5003 /* Rx Errors */
5005 /* RLEC on some newer hardware can be incorrect so build
5006 * our own version based on RUC and ROC
5007 */
5017 /* Tx Errors */
5023 /* Tx Dropped needs to be maintained elsewhere */
5025 /* Management Stats */
5030 /* Correctable ECC Errors */
5038 }
5039 }
5041 /**
5042 * e1000_phy_read_status - Update the PHY register status snapshot
5043 * @adapter: board private structure
5044 **/
5046 {
5066 /* Do not read PHY registers if link is not up
5067 * Set values to typical power-on defaults
5068 */
5072 BMSR_ERCAP);
5080 }
5081 }
5084 {
5088 /* Link status message must follow this format for user tools */
5096 }
5099 {
5104 /* get_link_status is set on LSC (link status) interrupt or
5105 * Rx sequence error interrupt. get_link_status will stay
5106 * true until the check_for_link establishes link
5107 * for copper adapters ONLY
5108 */
5116 }
5129 }
5133 /* See e1000_kmrn_lock_loss_workaround_ich8lan() */
5135 }
5138 }
5141 {
5142 /* make sure the receive unit is started */
5150 }
5151 }
5154 {
5157 /* With 82574 controllers, PHY needs to be checked periodically
5158 * for hung state and reset, if two calls return true
5159 */
5162 else
5169 }
5170 }
5172 /**
5173 * e1000_watchdog - Timer Call-back
5174 * @t: pointer to timer_list containing private info adapter
5175 **/
5177 {
5180 /* Do the rest outside of interrupt context */
5183 /* TODO: make this use queue_delayed_work() */
5184 }
5187 {
5190 watchdog_task);
5204 /* Cancel scheduled suspend requests. */
5209 }
5219 /* Cancel scheduled suspend requests. */
5222 /* Checking if MAC is in DMoff state*/
5229 }
5233 /* Checking if MAC exited DMoff state */
5236 }
5237 }
5239 /* update snapshot of PHY registers on LSC */
5246 /* check if SmartSpeed worked */
5252 /* On supported PHYs, check for duplex mismatch only
5253 * if link has autonegotiated at 10/100 half
5254 */
5261 u16 autoneg_exp;
5266 e_info("Autonegotiated half duplex but link partner cannot autoneg. Try forcing full duplex if link gets many collisions.\n");
5267 }
5269 /* adjust timeout factor according to speed/duplex */
5280 }
5282 /* workaround: re-program speed mode bit after
5283 * link-up event
5284 */
5287 u32 tarc0;
5292 }
5294 /* enable transmits in the hardware, need to do this
5295 * after setting TARC(0)
5296 */
5301 /* Perform any post-link-up configuration before
5302 * reporting link up.
5303 */
5313 }
5318 /* Link status message must follow this format */
5326 /* 8000ES2LAN requires a Rx packet buffer work-around
5327 * on link down event; reset the controller to flush
5328 * the Rx packet buffer.
5329 */
5332 else
5334 LINK_TIMEOUT);
5335 }
5336 }
5338 link_up:
5353 /* If the link is lost the controller stops DMA, but
5354 * if there is queued Tx work it cannot be done. So
5355 * reset the controller to flush the Tx packet buffers.
5356 */
5361 /* If reset is necessary, do it outside of interrupt context. */
5364 /* return immediately since reset is imminent */
5366 }
5370 /* Simple mode for Interrupt Throttle Rate (ITR) */
5372 /* Symmetric Tx/Rx gets a reduced ITR=2000;
5373 * Total asymmetrical Tx or Rx gets ITR=8000;
5374 * everyone else is between 2000-8000.
5375 */
5383 }
5385 /* Cause software interrupt to ensure Rx ring is cleaned */
5388 else
5391 /* flush pending descriptors to memory before detecting Tx hang */
5394 /* Force detection of hung controller every watchdog period */
5397 /* With 82571 controllers, LAA may be overwritten due to controller
5398 * reset from the other port. Set the appropriate LAA in RAR[0]
5399 */
5406 /* Clear valid timestamp stuck in RXSTMPL/H due to a Rx error */
5414 }
5415 }
5417 /* Reset the timer */
5421 }
5423 #define E1000_TX_FLAGS_CSUM 0x00000001
5424 #define E1000_TX_FLAGS_VLAN 0x00000002
5425 #define E1000_TX_FLAGS_TSO 0x00000004
5426 #define E1000_TX_FLAGS_IPV4 0x00000008
5427 #define E1000_TX_FLAGS_NO_FCS 0x00000010
5428 #define E1000_TX_FLAGS_HWTSTAMP 0x00000020
5429 #define E1000_TX_FLAGS_VLAN_MASK 0xffff0000
5430 #define E1000_TX_FLAGS_VLAN_SHIFT 16
5433 __be16 protocol)
5434 {
5463 }
5489 i++;
5495 }
5498 __be16 protocol)
5499 {
5504 u8 css;
5516 /* XXX not handling all IPV6 headers */
5525 }
5543 i++;
5549 }
5554 {
5580 count++;
5583 i++;
5586 }
5587 }
5596 i++;
5608 DMA_TO_DEVICE);
5615 count++;
5616 }
5617 }
5620 /* multiply data chunks by size of headers */
5630 dma_error:
5634 count--;
5639 i--;
5642 }
5645 }
5648 {
5657 E1000_TXD_CMD_TSE;
5662 }
5667 }
5672 }
5680 }
5692 i++;
5699 /* txd_cmd re-enables FCS, so we'll re-disable it here as desired. */
5703 /* Force memory writes to complete before letting h/w
5704 * know there are new descriptors to fetch. (Only
5705 * applicable for weak-ordered memory model archs,
5706 * such as IA-64).
5707 */
5711 }
5713 #define MINIMUM_DHCP_PACKET_SIZE 282
5716 {
5723 E1000_MNG_DHCP_COOKIE_STATUS_VLAN)))
5732 {
5746 }
5749 }
5752 {
5756 /* Herbert's original patch had:
5757 * smp_mb__after_netif_stop_queue();
5758 * but since that doesn't exist yet, just open code it.
5759 */
5762 /* We need to check again in a case another CPU has just
5763 * made room available.
5764 */
5768 /* A reprieve! */
5772 }
5775 {
5781 }
5785 {
5801 }
5806 }
5808 /* The minimum packet size with TCTL.PSP set is 17 bytes so
5809 * pad skb in order to meet this minimum size requirement
5810 */
5816 u8 hdr_len;
5818 /* TSO Workaround for 82571/2/3 Controllers -- if skb->data
5819 * points to just header, pull a few bytes of payload from
5820 * frags into skb->data
5821 */
5823 /* we do this workaround for ES2LAN, but it is un-necessary,
5824 * avoiding it could save a lot of cycles
5825 */
5834 }
5836 }
5837 }
5839 /* reserve a descriptor for the offload context */
5841 count++;
5842 count++;
5854 /* need: count + 2 desc gap to keep tail from touching
5855 * head, otherwise try next time
5856 */
5863 E1000_TX_FLAGS_VLAN_SHIFT);
5864 }
5872 }
5879 /* Old method was to assume IPv4 packet by default if TSO was enabled.
5880 * 82571 hardware supports TSO capabilities for IPv6 as well...
5881 * no longer assume, we must.
5882 */
5889 /* if count is 0 then mapping error has occurred */
5891 nr_frags);
5903 }
5904 }
5910 /* Make sure there is space in the ring for the next send. */
5921 else
5923 }
5928 }
5931 }
5933 /**
5934 * e1000_tx_timeout - Respond to a Tx Hang
5935 * @netdev: network interface device structure
5936 * @txqueue: index of the hung queue (unused)
5937 **/
5939 {
5942 /* Do the reset outside of interrupt context */
5945 }
5948 {
5953 /* don't run the task if already down */
5957 }
5962 }
5965 }
5967 /**
5968 * e1000e_get_stats64 - Get System Network Statistics
5969 * @netdev: network interface device structure
5970 * @stats: rtnl_link_stats64 pointer
5971 *
5972 * Returns the address of the device statistics structure.
5973 **/
5976 {
5981 /* Fill out the OS statistics structure */
5989 /* Rx Errors */
5991 /* RLEC on some newer hardware can be incorrect so build
5992 * our own version based on RUC and ROC
5993 */
6002 /* Tx Errors */
6008 /* Tx Dropped needs to be maintained elsewhere */
6011 }
6013 /**
6014 * e1000_change_mtu - Change the Maximum Transfer Unit
6015 * @netdev: network interface device structure
6016 * @new_mtu: new value for maximum frame size
6017 *
6018 * Returns 0 on success, negative on failure
6019 **/
6021 {
6025 /* Jumbo frame support */
6030 }
6032 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
6038 }
6042 /* e1000e_down -> e1000e_reset dependent on max_frame_size & mtu */
6053 /* NOTE: netdev_alloc_skb reserves 16 bytes, and typically NET_IP_ALIGN
6054 * means we reserve 2 more, this pushes us to allocate from the next
6055 * larger slab size.
6056 * i.e. RXBUFFER_2048 --> size-4096 slab
6057 * However with the new *_jumbo_rx* routines, jumbo receives will use
6058 * fragmented skbs
6059 */
6063 else
6066 /* adjust allocation if LPE protects us, and we aren't using SBP */
6072 else
6080 }
6084 {
6131 }
6136 }
6138 }
6140 /**
6141 * e1000e_hwtstamp_set - control hardware time stamping
6142 * @netdev: network interface device structure
6143 * @ifr: interface request
6144 *
6145 * Outgoing time stamping can be enabled and disabled. Play nice and
6146 * disable it when requested, although it shouldn't cause any overhead
6147 * when no packet needs it. At most one packet in the queue may be
6148 * marked for time stamping, otherwise it would be impossible to tell
6149 * for sure to which packet the hardware time stamp belongs.
6150 *
6151 * Incoming time stamping has to be configured via the hardware filters.
6152 * Not all combinations are supported, in particular event type has to be
6153 * specified. Matching the kind of event packet is not supported, with the
6154 * exception of "all V2 events regardless of level 2 or 4".
6155 **/
6157 {
6176 /* With V2 type filters which specify a Sync or Delay Request,
6177 * Path Delay Request/Response messages are also time stamped
6178 * by hardware so notify the caller the requested packets plus
6179 * some others are time stamped.
6180 */
6185 }
6189 }
6192 {
6197 }
6200 {
6212 }
6213 }
6216 {
6222 /* copy MAC RARs to PHY RARs */
6229 }
6231 /* Enable access to wakeup registers on and set page to BM_WUC_PAGE */
6236 /* copy MAC MTA to PHY MTA - only needed for pchlan */
6243 }
6245 /* configure PHY Rx Control register */
6269 /* enable PHY wakeup in MAC register */
6274 /* configure and enable PHY wakeup in PHY registers */
6278 /* activate PHY wakeup */
6283 release:
6287 }
6290 {
6294 u32 ret_val;
6307 fl_out:
6309 }
6311 /* S0ix implementation */
6313 {
6315 u32 mac_data;
6316 u16 phy_data;
6320 /* Request ME configure the device for S0ix */
6327 /* Request driver configure the device to S0ix */
6328 /* Disable the periodic inband message,
6329 * don't request PCIe clock in K1 page770_17[10:9] = 10b
6330 */
6336 /* Make sure we don't exit K1 every time a new packet arrives
6337 * 772_29[5] = 1 CS_Mode_Stay_In_K1
6338 */
6343 /* Change the MAC/PHY interface to SMBus
6344 * Force the SMBus in PHY page769_23[0] = 1
6345 * Force the SMBus in MAC CTRL_EXT[11] = 1
6346 */
6354 /* DFT control: PHY bit: page769_20[0] = 1
6355 * page769_20[7] - PHY PLL stop
6356 * page769_20[8] - PHY go to the electrical idle
6357 * page769_20[9] - PHY serdes disable
6358 * Gate PPW via EXTCNF_CTRL - set 0x0F00[7] = 1
6359 */
6371 /* Disable disconnected cable conditioning for Power Gating */
6376 /* Enable the Dynamic Clock Gating in the DMA and MAC */
6380 }
6382 /* Enable the Dynamic Power Gating in the MAC */
6387 /* Don't wake from dynamic Power Gating with clock request */
6392 /* Ungate PGCB clock */
6397 /* Enable K1 off to enable mPHY Power Gating */
6402 /* Enable mPHY power gating for any link and speed */
6407 /* No MAC DPG gating SLP_S0 in modern standby
6408 * Switch the logic of the lanphypc to use PMC counter
6409 */
6414 /* Disable the time synchronization clock */
6420 /* Dynamic Power Gating Enable */
6425 /* Check MAC Tx/Rx packet buffer pointers.
6426 * Reset MAC Tx/Rx packet buffer pointers to suppress any
6427 * pending traffic indication that would prevent power gating.
6428 */
6459 }
6462 {
6465 u32 mac_data;
6466 u16 phy_data;
6471 /* Keep the GPT clock enabled for CSME */
6475 /* Request ME unconfigure the device from S0ix */
6482 /* Poll up to 2.5 seconds for ME to unconfigure DPG.
6483 * If this takes more than 1 second, show a warning indicating a
6484 * firmware bug
6485 */
6494 }
6497 }
6501 else
6504 /* Request driver unconfigure the device from S0ix */
6506 /* Cancel disable disconnected cable conditioning
6507 * for Power Gating
6508 */
6513 /* Disable the Dynamic Clock Gating in the DMA and MAC */
6518 /* Enable the periodic inband message,
6519 * Request PCIe clock in K1 page770_17[10:9] =01b
6520 */
6526 /* Return back configuration
6527 * 772_29[5] = 0 CS_Mode_Stay_In_K1
6528 */
6533 /* Change the MAC/PHY interface to Kumeran
6534 * Unforce the SMBus in PHY page769_23[0] = 0
6535 * Unforce the SMBus in MAC CTRL_EXT[11] = 0
6536 */
6543 }
6545 /* Disable Dynamic Power Gating */
6550 /* Enable the time synchronization clock */
6556 /* Disable the Dynamic Power Gating in the MAC */
6561 /* Disable mPHY power gating for any link and speed */
6566 /* Disable K1 off */
6571 /* Disable Ungate PGCB clock */
6576 /* Cancel not waking from dynamic
6577 * Power Gating with clock request
6578 */
6583 /* Revert the lanphypc logic to use the internal Gbe counter
6584 * and not the PMC counter
6585 */
6589 }
6592 {
6610 /* Quiesce the device without resetting the hardware */
6613 }
6618 /* Allow time for pending master requests to run */
6622 }
6625 {
6632 /* Runtime suspend should only enable wakeup for link changes */
6637 else
6648 /* turn on all-multi mode if wake on multicast is enabled */
6653 }
6663 e1000_media_type_internal_serdes) {
6664 /* keep the laser running in D3 */
6668 }
6677 /* enable wakeup by the PHY */
6682 }
6684 /* enable wakeup by the MAC */
6687 }
6693 }
6699 /* ULP does not support wake from unicast, multicast
6700 * or broadcast.
6701 */
6706 }
6707 }
6708 }
6710 /* Ensure that the appropriate bits are set in LPI_CTRL
6711 * for EEE in Sx
6712 */
6724 I82579_EEE_100_SUPPORTED)
6728 I82579_EEE_1000_SUPPORTED)
6732 lpi_ctrl);
6733 }
6734 }
6736 }
6738 skip_phy_configurations:
6739 /* Release control of h/w to f/w. If f/w is AMT enabled, this
6740 * would have already happened in close and is redundant.
6741 */
6746 /* The pci-e switch on some quad port adapters will report a
6747 * correctable error when the MAC transitions from D0 to D3. To
6748 * prevent this we need to mask off the correctable errors on the
6749 * downstream port of the pci-e switch.
6750 *
6751 * We don't have the associated upstream bridge while assigning
6752 * the PCI device into guest. For example, the KVM on power is
6753 * one of the cases.
6754 */
6757 u16 devctl;
6770 }
6773 }
6775 /**
6776 * __e1000e_disable_aspm - Disable ASPM states
6777 * @pdev: pointer to PCI device struct
6778 * @state: bit-mask of ASPM states to disable
6779 * @locked: indication if this context holds pci_bus_sem locked.
6780 *
6781 * Some devices *must* have certain ASPM states disabled per hardware errata.
6782 **/
6784 {
6799 }
6808 }
6810 /* Nothing to do if the ASPM states to be disabled already are */
6821 #ifdef CONFIG_PCIEASPM
6824 else
6827 /* Double-check ASPM control. If not disabled by the above, the
6828 * BIOS is preventing that from happening (or CONFIG_PCIEASPM is
6829 * not enabled); override by writing PCI config space directly.
6830 */
6836 #endif
6838 /* Both device and parent should have the same ASPM setting.
6839 * Disable ASPM in downstream component first and then upstream.
6840 */
6845 aspm_dis_mask);
6846 }
6848 /**
6849 * e1000e_disable_aspm - Disable ASPM states.
6850 * @pdev: pointer to PCI device struct
6851 * @state: bit-mask of ASPM states to disable
6852 *
6853 * This function acquires the pci_bus_sem!
6854 * Some devices *must* have certain ASPM states disabled per hardware errata.
6855 **/
6857 {
6859 }
6861 /**
6862 * e1000e_disable_aspm_locked - Disable ASPM states.
6863 * @pdev: pointer to PCI device struct
6864 * @state: bit-mask of ASPM states to disable
6865 *
6866 * This function must be called with pci_bus_sem acquired!
6867 * Some devices *must* have certain ASPM states disabled per hardware errata.
6868 **/
6870 {
6872 }
6875 {
6889 }
6892 err_irq:
6896 }
6899 {
6919 /* report the system wakeup cause from S3/S4 */
6921 u16 phy_data;
6932 }
6945 }
6947 }
6953 /* If the controller has AMT, do not set DRV_LOAD until the interface
6954 * is up. For all other cases, let the f/w know that the h/w is now
6955 * under the control of the driver.
6956 */
6961 }
6964 {
6967 }
6970 {
6982 /* Introduce S0ix implementation */
6985 }
6988 }
6991 {
6997 /* Introduce S0ix implementation */
7006 }
7009 {
7012 u16 eee_lp;
7019 }
7022 }
7025 {
7041 }
7044 {
7057 /* Down the device without resetting the hardware */
7059 }
7064 }
7067 }
7070 {
7076 }
7078 #ifdef CONFIG_NET_POLL_CONTROLLER
7081 {
7094 vector++;
7100 vector++;
7105 }
7108 }
7110 /**
7111 * e1000_netpoll
7112 * @netdev: network interface device structure
7113 *
7114 * Polling 'interrupt' - used by things like netconsole to send skbs
7115 * without having to re-enable interrupts. It's not called while
7116 * the interrupt routine is executing.
7117 */
7119 {
7136 }
7137 }
7138 #endif
7140 /**
7141 * e1000_io_error_detected - called when PCI error is detected
7142 * @pdev: Pointer to PCI device
7143 * @state: The current pci connection state
7144 *
7145 * This function is called after a PCI bus error affecting
7146 * this device has been detected.
7147 */
7149 pci_channel_state_t state)
7150 {
7158 /* Request a slot reset. */
7160 }
7162 /**
7163 * e1000_io_slot_reset - called after the pci bus has been reset.
7164 * @pdev: Pointer to PCI device
7165 *
7166 * Restart the card from scratch, as if from a cold-boot. Implementation
7167 * resembles the first-half of the e1000e_pm_resume routine.
7168 */
7170 {
7176 pci_ers_result_t result;
7201 }
7204 }
7206 /**
7207 * e1000_io_resume - called when traffic can start flowing again.
7208 * @pdev: Pointer to PCI device
7209 *
7210 * This callback is called when the error recovery driver tells us that
7211 * its OK to resume normal operation. Implementation resembles the
7212 * second-half of the e1000e_pm_resume routine.
7213 */
7215 {
7223 /* If the controller has AMT, do not set DRV_LOAD until the interface
7224 * is up. For all other cases, let the f/w know that the h/w is now
7225 * under the control of the driver.
7226 */
7229 }
7232 {
7235 u32 ret_val;
7238 /* print bus type/speed/width info */
7240 /* bus width */
7243 /* MAC address */
7248 E1000_PBANUM_LENGTH);
7253 }
7256 {
7267 /* Deep Smart Power Down (DSPD) */
7270 }
7271 }
7274 netdev_features_t features)
7275 {
7279 /* Jumbo frame workaround on 82579 and newer requires CRC be stripped */
7283 /* Since there is no support for separate Rx/Tx vlan accel
7284 * enable/disable make sure Tx flag is always in same state as Rx.
7285 */
7288 else
7292 }
7295 netdev_features_t features)
7296 {
7305 NETIF_F_RXALL)))
7312 /* We need to take it back to defaults, which might mean
7313 * stripping is still disabled at the adapter level.
7314 */
7317 else
7319 }
7320 }
7326 else
7330 }
7346 #ifdef CONFIG_NET_POLL_CONTROLLER
7348 #endif
7352 };
7354 /**
7355 * e1000_probe - Device Initialization Routine
7356 * @pdev: PCI device information struct
7357 * @ent: entry in e1000_pci_tbl
7358 *
7359 * Returns 0 on success, negative on failure
7360 *
7361 * e1000_probe initializes an adapter identified by a pci_dev structure.
7362 * The OS initialization, configuring of the adapter private structure,
7363 * and a hardware reset occur.
7364 **/
7366 {
7396 }
7400 e1000e_driver_name);
7405 /* PCI config space info */
7449 }
7451 /* Set default EEE advertisement */
7455 /* construct the net_device struct */
7469 /* setup adapter struct */
7491 /* Copper options */
7496 }
7502 /* Set initial default active device features */
7504 NETIF_F_HW_VLAN_CTAG_RX |
7505 NETIF_F_HW_VLAN_CTAG_TX |
7506 NETIF_F_TSO |
7507 NETIF_F_TSO6 |
7508 NETIF_F_RXHASH |
7509 NETIF_F_RXCSUM |
7510 NETIF_F_HW_CSUM);
7512 /* disable TSO for pcie and 10/100 speeds to avoid
7513 * some hardware issues and for i219 to fix transfer
7514 * speed being capped at 60%
7515 */
7529 /* oops */
7531 }
7535 }
7536 }
7538 /* Set user-changeable features (subset of all device features) */
7548 NETIF_F_TSO |
7549 NETIF_F_TSO6 |
7550 NETIF_F_HW_CSUM);
7557 /* MTU range: 68 - max_hw_frame_size */
7565 /* before reading the NVM, reset the controller to
7566 * put the device in a known good starting state
7567 */
7570 /* systems with ASPM and others may see the checksum fail on the first
7571 * attempt. Let's give it a few tries
7572 */
7580 }
7581 }
7585 /* copy the MAC address */
7597 }
7608 /* Initialize link parameters. User can change them with ethtool */
7615 /* Initial Wake on LAN setting - If APM wake is enabled in
7616 * the EEPROM, enable the ACPI Magic Packet filter
7617 */
7619 /* APME bit in EEPROM is mapped to WUC.APME */
7629 NVM_INIT_CONTROL3_PORT_B,
7631 else
7633 NVM_INIT_CONTROL3_PORT_A,
7635 }
7637 /* fetch WoL from EEPROM */
7643 /* now that we have the eeprom settings, apply the special cases
7644 * where the eeprom may be wrong or the board simply won't support
7645 * wake on lan on a particular port
7646 */
7650 /* initialize the wol settings based on the eeprom settings */
7653 /* make sure adapter isn't asleep if manageability is enabled */
7658 /* save off EEPROM version number */
7664 }
7666 /* init PTP hardware clock */
7669 /* reset the hardware with the new settings */
7672 /* If the controller has AMT, do not set DRV_LOAD until the interface
7673 * is up. For all other cases, let the f/w know that the h/w is now
7674 * under the control of the driver.
7675 */
7687 /* carrier off reporting is important to ethtool even BEFORE open */
7699 err_register:
7702 err_eeprom:
7705 err_hw_init:
7708 err_sw_init:
7712 err_flashmap:
7714 err_ioremap:
7716 err_alloc_etherdev:
7718 err_pci_reg:
7719 err_dma:
7722 }
7724 /**
7725 * e1000_remove - Device Removal Routine
7726 * @pdev: PCI device information struct
7727 *
7728 * e1000_remove is called by the PCI subsystem to alert the driver
7729 * that it should release a PCI device. This could be caused by a
7730 * Hot-Plug event, or because the driver is going to be removed from
7731 * memory.
7732 **/
7734 {
7740 /* The timers may be rescheduled, so explicitly disable them
7741 * from being rescheduled.
7742 */
7758 }
7759 }
7766 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7767 * would have already happened in close and is redundant.
7768 */
7784 }
7786 /* PCI Error Recovery (ERS) */
7791 };
7798 board_82571 },
7819 board_80003es2lan },
7821 board_80003es2lan },
7823 board_80003es2lan },
7825 board_80003es2lan },
7927 };
7939 e1000e_pm_runtime_idle)
7940 };
7942 /* PCI Device API Driver */
7951 };
7953 /**
7954 * e1000_init_module - Driver Registration Routine
7955 *
7956 * e1000_init_module is the first routine called when the driver is
7957 * loaded. All it does is register with the PCI subsystem.
7958 **/
7960 {
7965 }
7968 /**
7969 * e1000_exit_module - Driver Exit Cleanup Routine
7970 *
7971 * e1000_exit_module is called just before the driver is removed
7972 * from memory.
7973 **/
7975 {
7977 }
7983 /* netdev.c */