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drm/rockchip: Don't change hdmi reference clock rate
[drm/drm-misc.git] / drivers / net / ethernet / intel / ixgbe / ixgbe_main.c
blob2e38e8f6fac18d43f054aa1a3fac0cf3b8a0f451
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
3
4 #include <linux/types.h>
5 #include <linux/module.h>
6 #include <linux/pci.h>
7 #include <linux/netdevice.h>
8 #include <linux/vmalloc.h>
9 #include <linux/string.h>
10 #include <linux/in.h>
11 #include <linux/interrupt.h>
12 #include <linux/ip.h>
13 #include <linux/tcp.h>
14 #include <linux/sctp.h>
15 #include <linux/pkt_sched.h>
16 #include <linux/ipv6.h>
17 #include <linux/slab.h>
18 #include <net/checksum.h>
19 #include <net/ip6_checksum.h>
20 #include <linux/etherdevice.h>
21 #include <linux/ethtool.h>
22 #include <linux/if.h>
23 #include <linux/if_vlan.h>
24 #include <linux/if_macvlan.h>
25 #include <linux/if_bridge.h>
26 #include <linux/prefetch.h>
27 #include <linux/bpf.h>
28 #include <linux/bpf_trace.h>
29 #include <linux/atomic.h>
30 #include <linux/numa.h>
31 #include <generated/utsrelease.h>
32 #include <scsi/fc/fc_fcoe.h>
33 #include <net/udp_tunnel.h>
34 #include <net/pkt_cls.h>
35 #include <net/tc_act/tc_gact.h>
36 #include <net/tc_act/tc_mirred.h>
37 #include <net/vxlan.h>
38 #include <net/mpls.h>
39 #include <net/netdev_queues.h>
40 #include <net/xdp_sock_drv.h>
41 #include <net/xfrm.h>
42
43 #include "ixgbe.h"
44 #include "ixgbe_common.h"
45 #include "ixgbe_dcb_82599.h"
46 #include "ixgbe_mbx.h"
47 #include "ixgbe_phy.h"
48 #include "ixgbe_sriov.h"
49 #include "ixgbe_model.h"
50 #include "ixgbe_txrx_common.h"
51
52 char ixgbe_driver_name[] = "ixgbe";
53 static const char ixgbe_driver_string[] =
54 "Intel(R) 10 Gigabit PCI Express Network Driver";
55 #ifdef IXGBE_FCOE
56 char ixgbe_default_device_descr[] =
57 "Intel(R) 10 Gigabit Network Connection";
58 #else
59 static char ixgbe_default_device_descr[] =
60 "Intel(R) 10 Gigabit Network Connection";
61 #endif
62 static const char ixgbe_copyright[] =
63 "Copyright (c) 1999-2016 Intel Corporation.";
64
65 static const char ixgbe_overheat_msg[] = "Network adapter has been stopped because it has over heated. Restart the computer. If the problem persists, power off the system and replace the adapter";
66
67 static const struct ixgbe_info *ixgbe_info_tbl[] = {
68 [board_82598] = &ixgbe_82598_info,
69 [board_82599] = &ixgbe_82599_info,
70 [board_X540] = &ixgbe_X540_info,
71 [board_X550] = &ixgbe_X550_info,
72 [board_X550EM_x] = &ixgbe_X550EM_x_info,
73 [board_x550em_x_fw] = &ixgbe_x550em_x_fw_info,
74 [board_x550em_a] = &ixgbe_x550em_a_info,
75 [board_x550em_a_fw] = &ixgbe_x550em_a_fw_info,
76 };
77
78 /* ixgbe_pci_tbl - PCI Device ID Table
79 *
80 * Wildcard entries (PCI_ANY_ID) should come last
81 * Last entry must be all 0s
82 *
83 * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
84 * Class, Class Mask, private data (not used) }
85 */
86 static const struct pci_device_id ixgbe_pci_tbl[] = {
87 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598), board_82598 },
88 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT), board_82598 },
89 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT), board_82598 },
90 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT), board_82598 },
91 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2), board_82598 },
92 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4), board_82598 },
93 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT), board_82598 },
94 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT), board_82598 },
95 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM), board_82598 },
96 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR), board_82598 },
97 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM), board_82598 },
98 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX), board_82598 },
99 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4), board_82599 },
100 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM), board_82599 },
101 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR), board_82599 },
102 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP), board_82599 },
103 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM), board_82599 },
104 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ), board_82599 },
105 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4), board_82599 },
106 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE), board_82599 },
107 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE), board_82599 },
108 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM), board_82599 },
109 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE), board_82599 },
110 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T), board_X540 },
111 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2), board_82599 },
112 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS), board_82599 },
113 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_QSFP_SF_QP), board_82599 },
114 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599EN_SFP), board_82599 },
115 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF_QP), board_82599 },
116 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T1), board_X540 },
117 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T), board_X550},
118 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550T1), board_X550},
119 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KX4), board_X550EM_x},
120 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_XFI), board_X550EM_x},
121 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_KR), board_X550EM_x},
122 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_10G_T), board_X550EM_x},
123 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_SFP), board_X550EM_x},
124 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_X_1G_T), board_x550em_x_fw},
125 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR), board_x550em_a },
126 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_KR_L), board_x550em_a },
127 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP_N), board_x550em_a },
128 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII), board_x550em_a },
129 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SGMII_L), board_x550em_a },
130 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_10G_T), board_x550em_a},
131 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_SFP), board_x550em_a },
132 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T), board_x550em_a_fw },
133 {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X550EM_A_1G_T_L), board_x550em_a_fw },
134 /* required last entry */
135 {0, }
136 };
137 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
138
139 #ifdef CONFIG_IXGBE_DCA
140 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
141 void *p);
142 static struct notifier_block dca_notifier = {
143 .notifier_call = ixgbe_notify_dca,
144 .next = NULL,
145 .priority = 0
146 };
147 #endif
148
149 #ifdef CONFIG_PCI_IOV
150 static unsigned int max_vfs;
151 module_param(max_vfs, uint, 0);
152 MODULE_PARM_DESC(max_vfs,
153 "Maximum number of virtual functions to allocate per physical function - default is zero and maximum value is 63. (Deprecated)");
154 #endif /* CONFIG_PCI_IOV */
155
156 static bool allow_unsupported_sfp;
157 module_param(allow_unsupported_sfp, bool, 0444);
158 MODULE_PARM_DESC(allow_unsupported_sfp,
159 "Allow unsupported and untested SFP+ modules on 82599-based adapters");
160
161 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
162 static int debug = -1;
163 module_param(debug, int, 0);
164 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
165
166 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
167 MODULE_LICENSE("GPL v2");
168
169 DEFINE_STATIC_KEY_FALSE(ixgbe_xdp_locking_key);
170 EXPORT_SYMBOL(ixgbe_xdp_locking_key);
171
172 static struct workqueue_struct *ixgbe_wq;
173
174 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev);
175 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *);
176
177 static const struct net_device_ops ixgbe_netdev_ops;
178
179 static bool netif_is_ixgbe(struct net_device *dev)
180 {
181 return dev && (dev->netdev_ops == &ixgbe_netdev_ops);
182 }
183
184 static int ixgbe_read_pci_cfg_word_parent(struct ixgbe_adapter *adapter,
185 u32 reg, u16 *value)
186 {
187 struct pci_dev *parent_dev;
188 struct pci_bus *parent_bus;
189
190 parent_bus = adapter->pdev->bus->parent;
191 if (!parent_bus)
192 return -1;
193
194 parent_dev = parent_bus->self;
195 if (!parent_dev)
196 return -1;
197
198 if (!pci_is_pcie(parent_dev))
199 return -1;
200
201 pcie_capability_read_word(parent_dev, reg, value);
202 if (*value == IXGBE_FAILED_READ_CFG_WORD &&
203 ixgbe_check_cfg_remove(&adapter->hw, parent_dev))
204 return -1;
205 return 0;
206 }
207
208 static int ixgbe_get_parent_bus_info(struct ixgbe_adapter *adapter)
209 {
210 struct ixgbe_hw *hw = &adapter->hw;
211 u16 link_status = 0;
212 int err;
213
214 hw->bus.type = ixgbe_bus_type_pci_express;
215
216 /* Get the negotiated link width and speed from PCI config space of the
217 * parent, as this device is behind a switch
218 */
219 err = ixgbe_read_pci_cfg_word_parent(adapter, 18, &link_status);
220
221 /* assume caller will handle error case */
222 if (err)
223 return err;
224
225 hw->bus.width = ixgbe_convert_bus_width(link_status);
226 hw->bus.speed = ixgbe_convert_bus_speed(link_status);
227
228 return 0;
229 }
230
231 /**
232 * ixgbe_pcie_from_parent - Determine whether PCIe info should come from parent
233 * @hw: hw specific details
234 *
235 * This function is used by probe to determine whether a device's PCI-Express
236 * bandwidth details should be gathered from the parent bus instead of from the
237 * device. Used to ensure that various locations all have the correct device ID
238 * checks.
239 */
240 static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
241 {
242 switch (hw->device_id) {
243 case IXGBE_DEV_ID_82599_SFP_SF_QP:
244 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
245 return true;
246 default:
247 return false;
248 }
249 }
250
251 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
252 int expected_gts)
253 {
254 struct ixgbe_hw *hw = &adapter->hw;
255 struct pci_dev *pdev;
256
257 /* Some devices are not connected over PCIe and thus do not negotiate
258 * speed. These devices do not have valid bus info, and thus any report
259 * we generate may not be correct.
260 */
261 if (hw->bus.type == ixgbe_bus_type_internal)
262 return;
263
264 /* determine whether to use the parent device */
265 if (ixgbe_pcie_from_parent(&adapter->hw))
266 pdev = adapter->pdev->bus->parent->self;
267 else
268 pdev = adapter->pdev;
269
270 pcie_print_link_status(pdev);
271 }
272
273 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
274 {
275 if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
276 !test_bit(__IXGBE_REMOVING, &adapter->state) &&
277 !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
278 queue_work(ixgbe_wq, &adapter->service_task);
279 }
280
281 static void ixgbe_remove_adapter(struct ixgbe_hw *hw)
282 {
283 struct ixgbe_adapter *adapter = hw->back;
284
285 if (!hw->hw_addr)
286 return;
287 hw->hw_addr = NULL;
288 e_dev_err("Adapter removed\n");
289 if (test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
290 ixgbe_service_event_schedule(adapter);
291 }
292
293 static u32 ixgbe_check_remove(struct ixgbe_hw *hw, u32 reg)
294 {
295 u8 __iomem *reg_addr;
296 u32 value;
297 int i;
298
299 reg_addr = READ_ONCE(hw->hw_addr);
300 if (ixgbe_removed(reg_addr))
301 return IXGBE_FAILED_READ_REG;
302
303 /* Register read of 0xFFFFFFF can indicate the adapter has been removed,
304 * so perform several status register reads to determine if the adapter
305 * has been removed.
306 */
307 for (i = 0; i < IXGBE_FAILED_READ_RETRIES; i++) {
308 value = readl(reg_addr + IXGBE_STATUS);
309 if (value != IXGBE_FAILED_READ_REG)
310 break;
311 mdelay(3);
312 }
313
314 if (value == IXGBE_FAILED_READ_REG)
315 ixgbe_remove_adapter(hw);
316 else
317 value = readl(reg_addr + reg);
318 return value;
319 }
320
321 /**
322 * ixgbe_read_reg - Read from device register
323 * @hw: hw specific details
324 * @reg: offset of register to read
325 *
326 * Returns : value read or IXGBE_FAILED_READ_REG if removed
327 *
328 * This function is used to read device registers. It checks for device
329 * removal by confirming any read that returns all ones by checking the
330 * status register value for all ones. This function avoids reading from
331 * the hardware if a removal was previously detected in which case it
332 * returns IXGBE_FAILED_READ_REG (all ones).
333 */
334 u32 ixgbe_read_reg(struct ixgbe_hw *hw, u32 reg)
335 {
336 u8 __iomem *reg_addr = READ_ONCE(hw->hw_addr);
337 u32 value;
338
339 if (ixgbe_removed(reg_addr))
340 return IXGBE_FAILED_READ_REG;
341 if (unlikely(hw->phy.nw_mng_if_sel &
342 IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE)) {
343 struct ixgbe_adapter *adapter;
344 int i;
345
346 for (i = 0; i < 200; ++i) {
347 value = readl(reg_addr + IXGBE_MAC_SGMII_BUSY);
348 if (likely(!value))
349 goto writes_completed;
350 if (value == IXGBE_FAILED_READ_REG) {
351 ixgbe_remove_adapter(hw);
352 return IXGBE_FAILED_READ_REG;
353 }
354 udelay(5);
355 }
356
357 adapter = hw->back;
358 e_warn(hw, "register writes incomplete %08x\n", value);
359 }
360
361 writes_completed:
362 value = readl(reg_addr + reg);
363 if (unlikely(value == IXGBE_FAILED_READ_REG))
364 value = ixgbe_check_remove(hw, reg);
365 return value;
366 }
367
368 static bool ixgbe_check_cfg_remove(struct ixgbe_hw *hw, struct pci_dev *pdev)
369 {
370 u16 value;
371
372 pci_read_config_word(pdev, PCI_VENDOR_ID, &value);
373 if (value == IXGBE_FAILED_READ_CFG_WORD) {
374 ixgbe_remove_adapter(hw);
375 return true;
376 }
377 return false;
378 }
379
380 u16 ixgbe_read_pci_cfg_word(struct ixgbe_hw *hw, u32 reg)
381 {
382 struct ixgbe_adapter *adapter = hw->back;
383 u16 value;
384
385 if (ixgbe_removed(hw->hw_addr))
386 return IXGBE_FAILED_READ_CFG_WORD;
387 pci_read_config_word(adapter->pdev, reg, &value);
388 if (value == IXGBE_FAILED_READ_CFG_WORD &&
389 ixgbe_check_cfg_remove(hw, adapter->pdev))
390 return IXGBE_FAILED_READ_CFG_WORD;
391 return value;
392 }
393
394 #ifdef CONFIG_PCI_IOV
395 static u32 ixgbe_read_pci_cfg_dword(struct ixgbe_hw *hw, u32 reg)
396 {
397 struct ixgbe_adapter *adapter = hw->back;
398 u32 value;
399
400 if (ixgbe_removed(hw->hw_addr))
401 return IXGBE_FAILED_READ_CFG_DWORD;
402 pci_read_config_dword(adapter->pdev, reg, &value);
403 if (value == IXGBE_FAILED_READ_CFG_DWORD &&
404 ixgbe_check_cfg_remove(hw, adapter->pdev))
405 return IXGBE_FAILED_READ_CFG_DWORD;
406 return value;
407 }
408 #endif /* CONFIG_PCI_IOV */
409
410 void ixgbe_write_pci_cfg_word(struct ixgbe_hw *hw, u32 reg, u16 value)
411 {
412 struct ixgbe_adapter *adapter = hw->back;
413
414 if (ixgbe_removed(hw->hw_addr))
415 return;
416 pci_write_config_word(adapter->pdev, reg, value);
417 }
418
419 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
420 {
421 BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
422
423 /* flush memory to make sure state is correct before next watchdog */
424 smp_mb__before_atomic();
425 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
426 }
427
428 struct ixgbe_reg_info {
429 u32 ofs;
430 char *name;
431 };
432
433 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
434
435 /* General Registers */
436 {IXGBE_CTRL, "CTRL"},
437 {IXGBE_STATUS, "STATUS"},
438 {IXGBE_CTRL_EXT, "CTRL_EXT"},
439
440 /* Interrupt Registers */
441 {IXGBE_EICR, "EICR"},
442
443 /* RX Registers */
444 {IXGBE_SRRCTL(0), "SRRCTL"},
445 {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
446 {IXGBE_RDLEN(0), "RDLEN"},
447 {IXGBE_RDH(0), "RDH"},
448 {IXGBE_RDT(0), "RDT"},
449 {IXGBE_RXDCTL(0), "RXDCTL"},
450 {IXGBE_RDBAL(0), "RDBAL"},
451 {IXGBE_RDBAH(0), "RDBAH"},
452
453 /* TX Registers */
454 {IXGBE_TDBAL(0), "TDBAL"},
455 {IXGBE_TDBAH(0), "TDBAH"},
456 {IXGBE_TDLEN(0), "TDLEN"},
457 {IXGBE_TDH(0), "TDH"},
458 {IXGBE_TDT(0), "TDT"},
459 {IXGBE_TXDCTL(0), "TXDCTL"},
460
461 /* List Terminator */
462 { .name = NULL }
463 };
464
465
466 /*
467 * ixgbe_regdump - register printout routine
468 */
469 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
470 {
471 int i;
472 char rname[16];
473 u32 regs[64];
474
475 switch (reginfo->ofs) {
476 case IXGBE_SRRCTL(0):
477 for (i = 0; i < 64; i++)
478 regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
479 break;
480 case IXGBE_DCA_RXCTRL(0):
481 for (i = 0; i < 64; i++)
482 regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
483 break;
484 case IXGBE_RDLEN(0):
485 for (i = 0; i < 64; i++)
486 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
487 break;
488 case IXGBE_RDH(0):
489 for (i = 0; i < 64; i++)
490 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
491 break;
492 case IXGBE_RDT(0):
493 for (i = 0; i < 64; i++)
494 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
495 break;
496 case IXGBE_RXDCTL(0):
497 for (i = 0; i < 64; i++)
498 regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
499 break;
500 case IXGBE_RDBAL(0):
501 for (i = 0; i < 64; i++)
502 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
503 break;
504 case IXGBE_RDBAH(0):
505 for (i = 0; i < 64; i++)
506 regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
507 break;
508 case IXGBE_TDBAL(0):
509 for (i = 0; i < 64; i++)
510 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
511 break;
512 case IXGBE_TDBAH(0):
513 for (i = 0; i < 64; i++)
514 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
515 break;
516 case IXGBE_TDLEN(0):
517 for (i = 0; i < 64; i++)
518 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
519 break;
520 case IXGBE_TDH(0):
521 for (i = 0; i < 64; i++)
522 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
523 break;
524 case IXGBE_TDT(0):
525 for (i = 0; i < 64; i++)
526 regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
527 break;
528 case IXGBE_TXDCTL(0):
529 for (i = 0; i < 64; i++)
530 regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
531 break;
532 default:
533 pr_info("%-15s %08x\n",
534 reginfo->name, IXGBE_READ_REG(hw, reginfo->ofs));
535 return;
536 }
537
538 i = 0;
539 while (i < 64) {
540 int j;
541 char buf[9 * 8 + 1];
542 char *p = buf;
543
544 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i, i + 7);
545 for (j = 0; j < 8; j++)
546 p += sprintf(p, " %08x", regs[i++]);
547 pr_err("%-15s%s\n", rname, buf);
548 }
549
550 }
551
552 static void ixgbe_print_buffer(struct ixgbe_ring *ring, int n)
553 {
554 struct ixgbe_tx_buffer *tx_buffer;
555
556 tx_buffer = &ring->tx_buffer_info[ring->next_to_clean];
557 pr_info(" %5d %5X %5X %016llX %08X %p %016llX\n",
558 n, ring->next_to_use, ring->next_to_clean,
559 (u64)dma_unmap_addr(tx_buffer, dma),
560 dma_unmap_len(tx_buffer, len),
561 tx_buffer->next_to_watch,
562 (u64)tx_buffer->time_stamp);
563 }
564
565 /*
566 * ixgbe_dump - Print registers, tx-rings and rx-rings
567 */
568 static void ixgbe_dump(struct ixgbe_adapter *adapter)
569 {
570 struct net_device *netdev = adapter->netdev;
571 struct ixgbe_hw *hw = &adapter->hw;
572 struct ixgbe_reg_info *reginfo;
573 int n = 0;
574 struct ixgbe_ring *ring;
575 struct ixgbe_tx_buffer *tx_buffer;
576 union ixgbe_adv_tx_desc *tx_desc;
577 struct my_u0 { u64 a; u64 b; } *u0;
578 struct ixgbe_ring *rx_ring;
579 union ixgbe_adv_rx_desc *rx_desc;
580 struct ixgbe_rx_buffer *rx_buffer_info;
581 int i = 0;
582
583 if (!netif_msg_hw(adapter))
584 return;
585
586 /* Print netdevice Info */
587 if (netdev) {
588 dev_info(&adapter->pdev->dev, "Net device Info\n");
589 pr_info("Device Name state "
590 "trans_start\n");
591 pr_info("%-15s %016lX %016lX\n",
592 netdev->name,
593 netdev->state,
594 dev_trans_start(netdev));
595 }
596
597 /* Print Registers */
598 dev_info(&adapter->pdev->dev, "Register Dump\n");
599 pr_info(" Register Name Value\n");
600 for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
601 reginfo->name; reginfo++) {
602 ixgbe_regdump(hw, reginfo);
603 }
604
605 /* Print TX Ring Summary */
606 if (!netdev || !netif_running(netdev))
607 return;
608
609 dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
610 pr_info(" %s %s %s %s\n",
611 "Queue [NTU] [NTC] [bi(ntc)->dma ]",
612 "leng", "ntw", "timestamp");
613 for (n = 0; n < adapter->num_tx_queues; n++) {
614 ring = adapter->tx_ring[n];
615 ixgbe_print_buffer(ring, n);
616 }
617
618 for (n = 0; n < adapter->num_xdp_queues; n++) {
619 ring = adapter->xdp_ring[n];
620 ixgbe_print_buffer(ring, n);
621 }
622
623 /* Print TX Rings */
624 if (!netif_msg_tx_done(adapter))
625 goto rx_ring_summary;
626
627 dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
628
629 /* Transmit Descriptor Formats
630 *
631 * 82598 Advanced Transmit Descriptor
632 * +--------------------------------------------------------------+
633 * 0 | Buffer Address [63:0] |
634 * +--------------------------------------------------------------+
635 * 8 | PAYLEN | POPTS | IDX | STA | DCMD |DTYP | RSV | DTALEN |
636 * +--------------------------------------------------------------+
637 * 63 46 45 40 39 36 35 32 31 24 23 20 19 0
638 *
639 * 82598 Advanced Transmit Descriptor (Write-Back Format)
640 * +--------------------------------------------------------------+
641 * 0 | RSV [63:0] |
642 * +--------------------------------------------------------------+
643 * 8 | RSV | STA | NXTSEQ |
644 * +--------------------------------------------------------------+
645 * 63 36 35 32 31 0
646 *
647 * 82599+ Advanced Transmit Descriptor
648 * +--------------------------------------------------------------+
649 * 0 | Buffer Address [63:0] |
650 * +--------------------------------------------------------------+
651 * 8 |PAYLEN |POPTS|CC|IDX |STA |DCMD |DTYP |MAC |RSV |DTALEN |
652 * +--------------------------------------------------------------+
653 * 63 46 45 40 39 38 36 35 32 31 24 23 20 19 18 17 16 15 0
654 *
655 * 82599+ Advanced Transmit Descriptor (Write-Back Format)
656 * +--------------------------------------------------------------+
657 * 0 | RSV [63:0] |
658 * +--------------------------------------------------------------+
659 * 8 | RSV | STA | RSV |
660 * +--------------------------------------------------------------+
661 * 63 36 35 32 31 0
662 */
663
664 for (n = 0; n < adapter->num_tx_queues; n++) {
665 ring = adapter->tx_ring[n];
666 pr_info("------------------------------------\n");
667 pr_info("TX QUEUE INDEX = %d\n", ring->queue_index);
668 pr_info("------------------------------------\n");
669 pr_info("%s%s %s %s %s %s\n",
670 "T [desc] [address 63:0 ] ",
671 "[PlPOIdStDDt Ln] [bi->dma ] ",
672 "leng", "ntw", "timestamp", "bi->skb");
673
674 for (i = 0; ring->desc && (i < ring->count); i++) {
675 tx_desc = IXGBE_TX_DESC(ring, i);
676 tx_buffer = &ring->tx_buffer_info[i];
677 u0 = (struct my_u0 *)tx_desc;
678 if (dma_unmap_len(tx_buffer, len) > 0) {
679 const char *ring_desc;
680
681 if (i == ring->next_to_use &&
682 i == ring->next_to_clean)
683 ring_desc = " NTC/U";
684 else if (i == ring->next_to_use)
685 ring_desc = " NTU";
686 else if (i == ring->next_to_clean)
687 ring_desc = " NTC";
688 else
689 ring_desc = "";
690 pr_info("T [0x%03X] %016llX %016llX %016llX %08X %p %016llX %p%s",
691 i,
692 le64_to_cpu((__force __le64)u0->a),
693 le64_to_cpu((__force __le64)u0->b),
694 (u64)dma_unmap_addr(tx_buffer, dma),
695 dma_unmap_len(tx_buffer, len),
696 tx_buffer->next_to_watch,
697 (u64)tx_buffer->time_stamp,
698 tx_buffer->skb,
699 ring_desc);
700
701 if (netif_msg_pktdata(adapter) &&
702 tx_buffer->skb)
703 print_hex_dump(KERN_INFO, "",
704 DUMP_PREFIX_ADDRESS, 16, 1,
705 tx_buffer->skb->data,
706 dma_unmap_len(tx_buffer, len),
707 true);
708 }
709 }
710 }
711
712 /* Print RX Rings Summary */
713 rx_ring_summary:
714 dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
715 pr_info("Queue [NTU] [NTC]\n");
716 for (n = 0; n < adapter->num_rx_queues; n++) {
717 rx_ring = adapter->rx_ring[n];
718 pr_info("%5d %5X %5X\n",
719 n, rx_ring->next_to_use, rx_ring->next_to_clean);
720 }
721
722 /* Print RX Rings */
723 if (!netif_msg_rx_status(adapter))
724 return;
725
726 dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
727
728 /* Receive Descriptor Formats
729 *
730 * 82598 Advanced Receive Descriptor (Read) Format
731 * 63 1 0
732 * +-----------------------------------------------------+
733 * 0 | Packet Buffer Address [63:1] |A0/NSE|
734 * +----------------------------------------------+------+
735 * 8 | Header Buffer Address [63:1] | DD |
736 * +-----------------------------------------------------+
737 *
738 *
739 * 82598 Advanced Receive Descriptor (Write-Back) Format
740 *
741 * 63 48 47 32 31 30 21 20 16 15 4 3 0
742 * +------------------------------------------------------+
743 * 0 | RSS Hash / |SPH| HDR_LEN | RSV |Packet| RSS |
744 * | Packet | IP | | | | Type | Type |
745 * | Checksum | Ident | | | | | |
746 * +------------------------------------------------------+
747 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
748 * +------------------------------------------------------+
749 * 63 48 47 32 31 20 19 0
750 *
751 * 82599+ Advanced Receive Descriptor (Read) Format
752 * 63 1 0
753 * +-----------------------------------------------------+
754 * 0 | Packet Buffer Address [63:1] |A0/NSE|
755 * +----------------------------------------------+------+
756 * 8 | Header Buffer Address [63:1] | DD |
757 * +-----------------------------------------------------+
758 *
759 *
760 * 82599+ Advanced Receive Descriptor (Write-Back) Format
761 *
762 * 63 48 47 32 31 30 21 20 17 16 4 3 0
763 * +------------------------------------------------------+
764 * 0 |RSS / Frag Checksum|SPH| HDR_LEN |RSC- |Packet| RSS |
765 * |/ RTT / PCoE_PARAM | | | CNT | Type | Type |
766 * |/ Flow Dir Flt ID | | | | | |
767 * +------------------------------------------------------+
768 * 8 | VLAN Tag | Length |Extended Error| Xtnd Status/NEXTP |
769 * +------------------------------------------------------+
770 * 63 48 47 32 31 20 19 0
771 */
772
773 for (n = 0; n < adapter->num_rx_queues; n++) {
774 rx_ring = adapter->rx_ring[n];
775 pr_info("------------------------------------\n");
776 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
777 pr_info("------------------------------------\n");
778 pr_info("%s%s%s\n",
779 "R [desc] [ PktBuf A0] ",
780 "[ HeadBuf DD] [bi->dma ] [bi->skb ] ",
781 "<-- Adv Rx Read format");
782 pr_info("%s%s%s\n",
783 "RWB[desc] [PcsmIpSHl PtRs] ",
784 "[vl er S cks ln] ---------------- [bi->skb ] ",
785 "<-- Adv Rx Write-Back format");
786
787 for (i = 0; i < rx_ring->count; i++) {
788 const char *ring_desc;
789
790 if (i == rx_ring->next_to_use)
791 ring_desc = " NTU";
792 else if (i == rx_ring->next_to_clean)
793 ring_desc = " NTC";
794 else
795 ring_desc = "";
796
797 rx_buffer_info = &rx_ring->rx_buffer_info[i];
798 rx_desc = IXGBE_RX_DESC(rx_ring, i);
799 u0 = (struct my_u0 *)rx_desc;
800 if (rx_desc->wb.upper.length) {
801 /* Descriptor Done */
802 pr_info("RWB[0x%03X] %016llX %016llX ---------------- %p%s\n",
803 i,
804 le64_to_cpu((__force __le64)u0->a),
805 le64_to_cpu((__force __le64)u0->b),
806 rx_buffer_info->skb,
807 ring_desc);
808 } else {
809 pr_info("R [0x%03X] %016llX %016llX %016llX %p%s\n",
810 i,
811 le64_to_cpu((__force __le64)u0->a),
812 le64_to_cpu((__force __le64)u0->b),
813 (u64)rx_buffer_info->dma,
814 rx_buffer_info->skb,
815 ring_desc);
816
817 if (netif_msg_pktdata(adapter) &&
818 rx_buffer_info->dma) {
819 print_hex_dump(KERN_INFO, "",
820 DUMP_PREFIX_ADDRESS, 16, 1,
821 page_address(rx_buffer_info->page) +
822 rx_buffer_info->page_offset,
823 ixgbe_rx_bufsz(rx_ring), true);
824 }
825 }
826 }
827 }
828 }
829
830 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
831 {
832 u32 ctrl_ext;
833
834 /* Let firmware take over control of h/w */
835 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
836 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
837 ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
838 }
839
840 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
841 {
842 u32 ctrl_ext;
843
844 /* Let firmware know the driver has taken over */
845 ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
846 IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
847 ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
848 }
849
850 /**
851 * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
852 * @adapter: pointer to adapter struct
853 * @direction: 0 for Rx, 1 for Tx, -1 for other causes
854 * @queue: queue to map the corresponding interrupt to
855 * @msix_vector: the vector to map to the corresponding queue
856 *
857 */
858 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
859 u8 queue, u8 msix_vector)
860 {
861 u32 ivar, index;
862 struct ixgbe_hw *hw = &adapter->hw;
863 switch (hw->mac.type) {
864 case ixgbe_mac_82598EB:
865 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
866 if (direction == -1)
867 direction = 0;
868 index = (((direction * 64) + queue) >> 2) & 0x1F;
869 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
870 ivar &= ~(0xFF << (8 * (queue & 0x3)));
871 ivar |= (msix_vector << (8 * (queue & 0x3)));
872 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
873 break;
874 case ixgbe_mac_82599EB:
875 case ixgbe_mac_X540:
876 case ixgbe_mac_X550:
877 case ixgbe_mac_X550EM_x:
878 case ixgbe_mac_x550em_a:
879 if (direction == -1) {
880 /* other causes */
881 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
882 index = ((queue & 1) * 8);
883 ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
884 ivar &= ~(0xFF << index);
885 ivar |= (msix_vector << index);
886 IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
887 break;
888 } else {
889 /* tx or rx causes */
890 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
891 index = ((16 * (queue & 1)) + (8 * direction));
892 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
893 ivar &= ~(0xFF << index);
894 ivar |= (msix_vector << index);
895 IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
896 break;
897 }
898 default:
899 break;
900 }
901 }
902
903 void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
904 u64 qmask)
905 {
906 u32 mask;
907
908 switch (adapter->hw.mac.type) {
909 case ixgbe_mac_82598EB:
910 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
911 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
912 break;
913 case ixgbe_mac_82599EB:
914 case ixgbe_mac_X540:
915 case ixgbe_mac_X550:
916 case ixgbe_mac_X550EM_x:
917 case ixgbe_mac_x550em_a:
918 mask = (qmask & 0xFFFFFFFF);
919 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
920 mask = (qmask >> 32);
921 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
922 break;
923 default:
924 break;
925 }
926 }
927
928 static void ixgbe_update_xoff_rx_lfc(struct ixgbe_adapter *adapter)
929 {
930 struct ixgbe_hw *hw = &adapter->hw;
931 struct ixgbe_hw_stats *hwstats = &adapter->stats;
932 int i;
933 u32 data;
934
935 if ((hw->fc.current_mode != ixgbe_fc_full) &&
936 (hw->fc.current_mode != ixgbe_fc_rx_pause))
937 return;
938
939 switch (hw->mac.type) {
940 case ixgbe_mac_82598EB:
941 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
942 break;
943 default:
944 data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
945 }
946 hwstats->lxoffrxc += data;
947
948 /* refill credits (no tx hang) if we received xoff */
949 if (!data)
950 return;
951
952 for (i = 0; i < adapter->num_tx_queues; i++)
953 clear_bit(__IXGBE_HANG_CHECK_ARMED,
954 &adapter->tx_ring[i]->state);
955
956 for (i = 0; i < adapter->num_xdp_queues; i++)
957 clear_bit(__IXGBE_HANG_CHECK_ARMED,
958 &adapter->xdp_ring[i]->state);
959 }
960
961 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
962 {
963 struct ixgbe_hw *hw = &adapter->hw;
964 struct ixgbe_hw_stats *hwstats = &adapter->stats;
965 u32 xoff[8] = {0};
966 u8 tc;
967 int i;
968 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
969
970 if (adapter->ixgbe_ieee_pfc)
971 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
972
973 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED) || !pfc_en) {
974 ixgbe_update_xoff_rx_lfc(adapter);
975 return;
976 }
977
978 /* update stats for each tc, only valid with PFC enabled */
979 for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
980 u32 pxoffrxc;
981
982 switch (hw->mac.type) {
983 case ixgbe_mac_82598EB:
984 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
985 break;
986 default:
987 pxoffrxc = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
988 }
989 hwstats->pxoffrxc[i] += pxoffrxc;
990 /* Get the TC for given UP */
991 tc = netdev_get_prio_tc_map(adapter->netdev, i);
992 xoff[tc] += pxoffrxc;
993 }
994
995 /* disarm tx queues that have received xoff frames */
996 for (i = 0; i < adapter->num_tx_queues; i++) {
997 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
998
999 tc = tx_ring->dcb_tc;
1000 if (xoff[tc])
1001 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1002 }
1003
1004 for (i = 0; i < adapter->num_xdp_queues; i++) {
1005 struct ixgbe_ring *xdp_ring = adapter->xdp_ring[i];
1006
1007 tc = xdp_ring->dcb_tc;
1008 if (xoff[tc])
1009 clear_bit(__IXGBE_HANG_CHECK_ARMED, &xdp_ring->state);
1010 }
1011 }
1012
1013 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
1014 {
1015 return ring->stats.packets;
1016 }
1017
1018 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
1019 {
1020 unsigned int head, tail;
1021
1022 head = ring->next_to_clean;
1023 tail = ring->next_to_use;
1024
1025 return ((head <= tail) ? tail : tail + ring->count) - head;
1026 }
1027
1028 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
1029 {
1030 u32 tx_done = ixgbe_get_tx_completed(tx_ring);
1031 u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
1032 u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
1033
1034 clear_check_for_tx_hang(tx_ring);
1035
1036 /*
1037 * Check for a hung queue, but be thorough. This verifies
1038 * that a transmit has been completed since the previous
1039 * check AND there is at least one packet pending. The
1040 * ARMED bit is set to indicate a potential hang. The
1041 * bit is cleared if a pause frame is received to remove
1042 * false hang detection due to PFC or 802.3x frames. By
1043 * requiring this to fail twice we avoid races with
1044 * pfc clearing the ARMED bit and conditions where we
1045 * run the check_tx_hang logic with a transmit completion
1046 * pending but without time to complete it yet.
1047 */
1048 if (tx_done_old == tx_done && tx_pending)
1049 /* make sure it is true for two checks in a row */
1050 return test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
1051 &tx_ring->state);
1052 /* update completed stats and continue */
1053 tx_ring->tx_stats.tx_done_old = tx_done;
1054 /* reset the countdown */
1055 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
1056
1057 return false;
1058 }
1059
1060 /**
1061 * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
1062 * @adapter: driver private struct
1063 **/
1064 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
1065 {
1066
1067 /* Do the reset outside of interrupt context */
1068 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1069 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
1070 e_warn(drv, "initiating reset due to tx timeout\n");
1071 ixgbe_service_event_schedule(adapter);
1072 }
1073 }
1074
1075 /**
1076 * ixgbe_tx_maxrate - callback to set the maximum per-queue bitrate
1077 * @netdev: network interface device structure
1078 * @queue_index: Tx queue to set
1079 * @maxrate: desired maximum transmit bitrate
1080 **/
1081 static int ixgbe_tx_maxrate(struct net_device *netdev,
1082 int queue_index, u32 maxrate)
1083 {
1084 struct ixgbe_adapter *adapter = netdev_priv(netdev);
1085 struct ixgbe_hw *hw = &adapter->hw;
1086 u32 bcnrc_val = ixgbe_link_mbps(adapter);
1087
1088 if (!maxrate)
1089 return 0;
1090
1091 /* Calculate the rate factor values to set */
1092 bcnrc_val <<= IXGBE_RTTBCNRC_RF_INT_SHIFT;
1093 bcnrc_val /= maxrate;
1094
1095 /* clear everything but the rate factor */
1096 bcnrc_val &= IXGBE_RTTBCNRC_RF_INT_MASK |
1097 IXGBE_RTTBCNRC_RF_DEC_MASK;
1098
1099 /* enable the rate scheduler */
1100 bcnrc_val |= IXGBE_RTTBCNRC_RS_ENA;
1101
1102 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, queue_index);
1103 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, bcnrc_val);
1104
1105 return 0;
1106 }
1107
1108 /**
1109 * ixgbe_update_tx_ring_stats - Update Tx ring specific counters
1110 * @tx_ring: ring to update
1111 * @q_vector: queue vector ring belongs to
1112 * @pkts: number of processed packets
1113 * @bytes: number of processed bytes
1114 */
1115 void ixgbe_update_tx_ring_stats(struct ixgbe_ring *tx_ring,
1116 struct ixgbe_q_vector *q_vector, u64 pkts,
1117 u64 bytes)
1118 {
1119 u64_stats_update_begin(&tx_ring->syncp);
1120 tx_ring->stats.bytes += bytes;
1121 tx_ring->stats.packets += pkts;
1122 u64_stats_update_end(&tx_ring->syncp);
1123 q_vector->tx.total_bytes += bytes;
1124 q_vector->tx.total_packets += pkts;
1125 }
1126
1127 /**
1128 * ixgbe_update_rx_ring_stats - Update Rx ring specific counters
1129 * @rx_ring: ring to update
1130 * @q_vector: queue vector ring belongs to
1131 * @pkts: number of processed packets
1132 * @bytes: number of processed bytes
1133 */
1134 void ixgbe_update_rx_ring_stats(struct ixgbe_ring *rx_ring,
1135 struct ixgbe_q_vector *q_vector, u64 pkts,
1136 u64 bytes)
1137 {
1138 u64_stats_update_begin(&rx_ring->syncp);
1139 rx_ring->stats.bytes += bytes;
1140 rx_ring->stats.packets += pkts;
1141 u64_stats_update_end(&rx_ring->syncp);
1142 q_vector->rx.total_bytes += bytes;
1143 q_vector->rx.total_packets += pkts;
1144 }
1145
1146 /**
1147 * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
1148 * @q_vector: structure containing interrupt and ring information
1149 * @tx_ring: tx ring to clean
1150 * @napi_budget: Used to determine if we are in netpoll
1151 **/
1152 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
1153 struct ixgbe_ring *tx_ring, int napi_budget)
1154 {
1155 struct ixgbe_adapter *adapter = q_vector->adapter;
1156 struct ixgbe_tx_buffer *tx_buffer;
1157 union ixgbe_adv_tx_desc *tx_desc;
1158 unsigned int total_bytes = 0, total_packets = 0, total_ipsec = 0;
1159 unsigned int budget = q_vector->tx.work_limit;
1160 unsigned int i = tx_ring->next_to_clean;
1161 struct netdev_queue *txq;
1162
1163 if (test_bit(__IXGBE_DOWN, &adapter->state))
1164 return true;
1165
1166 tx_buffer = &tx_ring->tx_buffer_info[i];
1167 tx_desc = IXGBE_TX_DESC(tx_ring, i);
1168 i -= tx_ring->count;
1169
1170 do {
1171 union ixgbe_adv_tx_desc *eop_desc = tx_buffer->next_to_watch;
1172
1173 /* if next_to_watch is not set then there is no work pending */
1174 if (!eop_desc)
1175 break;
1176
1177 /* prevent any other reads prior to eop_desc */
1178 smp_rmb();
1179
1180 /* if DD is not set pending work has not been completed */
1181 if (!(eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)))
1182 break;
1183
1184 /* clear next_to_watch to prevent false hangs */
1185 tx_buffer->next_to_watch = NULL;
1186
1187 /* update the statistics for this packet */
1188 total_bytes += tx_buffer->bytecount;
1189 total_packets += tx_buffer->gso_segs;
1190 if (tx_buffer->tx_flags & IXGBE_TX_FLAGS_IPSEC)
1191 total_ipsec++;
1192
1193 /* free the skb */
1194 if (ring_is_xdp(tx_ring))
1195 xdp_return_frame(tx_buffer->xdpf);
1196 else
1197 napi_consume_skb(tx_buffer->skb, napi_budget);
1198
1199 /* unmap skb header data */
1200 dma_unmap_single(tx_ring->dev,
1201 dma_unmap_addr(tx_buffer, dma),
1202 dma_unmap_len(tx_buffer, len),
1203 DMA_TO_DEVICE);
1204
1205 /* clear tx_buffer data */
1206 dma_unmap_len_set(tx_buffer, len, 0);
1207
1208 /* unmap remaining buffers */
1209 while (tx_desc != eop_desc) {
1210 tx_buffer++;
1211 tx_desc++;
1212 i++;
1213 if (unlikely(!i)) {
1214 i -= tx_ring->count;
1215 tx_buffer = tx_ring->tx_buffer_info;
1216 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1217 }
1218
1219 /* unmap any remaining paged data */
1220 if (dma_unmap_len(tx_buffer, len)) {
1221 dma_unmap_page(tx_ring->dev,
1222 dma_unmap_addr(tx_buffer, dma),
1223 dma_unmap_len(tx_buffer, len),
1224 DMA_TO_DEVICE);
1225 dma_unmap_len_set(tx_buffer, len, 0);
1226 }
1227 }
1228
1229 /* move us one more past the eop_desc for start of next pkt */
1230 tx_buffer++;
1231 tx_desc++;
1232 i++;
1233 if (unlikely(!i)) {
1234 i -= tx_ring->count;
1235 tx_buffer = tx_ring->tx_buffer_info;
1236 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
1237 }
1238
1239 /* issue prefetch for next Tx descriptor */
1240 prefetch(tx_desc);
1241
1242 /* update budget accounting */
1243 budget--;
1244 } while (likely(budget));
1245
1246 i += tx_ring->count;
1247 tx_ring->next_to_clean = i;
1248 ixgbe_update_tx_ring_stats(tx_ring, q_vector, total_packets,
1249 total_bytes);
1250 adapter->tx_ipsec += total_ipsec;
1251
1252 if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
1253 /* schedule immediate reset if we believe we hung */
1254 struct ixgbe_hw *hw = &adapter->hw;
1255 e_err(drv, "Detected Tx Unit Hang %s\n"
1256 " Tx Queue <%d>\n"
1257 " TDH, TDT <%x>, <%x>\n"
1258 " next_to_use <%x>\n"
1259 " next_to_clean <%x>\n"
1260 "tx_buffer_info[next_to_clean]\n"
1261 " time_stamp <%lx>\n"
1262 " jiffies <%lx>\n",
1263 ring_is_xdp(tx_ring) ? "(XDP)" : "",
1264 tx_ring->queue_index,
1265 IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
1266 IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
1267 tx_ring->next_to_use, i,
1268 tx_ring->tx_buffer_info[i].time_stamp, jiffies);
1269
1270 if (!ring_is_xdp(tx_ring))
1271 netif_stop_subqueue(tx_ring->netdev,
1272 tx_ring->queue_index);
1273
1274 e_info(probe,
1275 "tx hang %d detected on queue %d, resetting adapter\n",
1276 adapter->tx_timeout_count + 1, tx_ring->queue_index);
1277
1278 /* schedule immediate reset if we believe we hung */
1279 ixgbe_tx_timeout_reset(adapter);
1280
1281 /* the adapter is about to reset, no point in enabling stuff */
1282 return true;
1283 }
1284
1285 if (ring_is_xdp(tx_ring))
1286 return !!budget;
1287
1288 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
1289 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->queue_index);
1290 if (!__netif_txq_completed_wake(txq, total_packets, total_bytes,
1291 ixgbe_desc_unused(tx_ring),
1292 TX_WAKE_THRESHOLD,
1293 !netif_carrier_ok(tx_ring->netdev) ||
1294 test_bit(__IXGBE_DOWN, &adapter->state)))
1295 ++tx_ring->tx_stats.restart_queue;
1296
1297 return !!budget;
1298 }
1299
1300 #ifdef CONFIG_IXGBE_DCA
1301 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
1302 struct ixgbe_ring *tx_ring,
1303 int cpu)
1304 {
1305 struct ixgbe_hw *hw = &adapter->hw;
1306 u32 txctrl = 0;
1307 u16 reg_offset;
1308
1309 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1310 txctrl = dca3_get_tag(tx_ring->dev, cpu);
1311
1312 switch (hw->mac.type) {
1313 case ixgbe_mac_82598EB:
1314 reg_offset = IXGBE_DCA_TXCTRL(tx_ring->reg_idx);
1315 break;
1316 case ixgbe_mac_82599EB:
1317 case ixgbe_mac_X540:
1318 reg_offset = IXGBE_DCA_TXCTRL_82599(tx_ring->reg_idx);
1319 txctrl <<= IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599;
1320 break;
1321 default:
1322 /* for unknown hardware do not write register */
1323 return;
1324 }
1325
1326 /*
1327 * We can enable relaxed ordering for reads, but not writes when
1328 * DCA is enabled. This is due to a known issue in some chipsets
1329 * which will cause the DCA tag to be cleared.
1330 */
1331 txctrl |= IXGBE_DCA_TXCTRL_DESC_RRO_EN |
1332 IXGBE_DCA_TXCTRL_DATA_RRO_EN |
1333 IXGBE_DCA_TXCTRL_DESC_DCA_EN;
1334
1335 IXGBE_WRITE_REG(hw, reg_offset, txctrl);
1336 }
1337
1338 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
1339 struct ixgbe_ring *rx_ring,
1340 int cpu)
1341 {
1342 struct ixgbe_hw *hw = &adapter->hw;
1343 u32 rxctrl = 0;
1344 u8 reg_idx = rx_ring->reg_idx;
1345
1346 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1347 rxctrl = dca3_get_tag(rx_ring->dev, cpu);
1348
1349 switch (hw->mac.type) {
1350 case ixgbe_mac_82599EB:
1351 case ixgbe_mac_X540:
1352 rxctrl <<= IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599;
1353 break;
1354 default:
1355 break;
1356 }
1357
1358 /*
1359 * We can enable relaxed ordering for reads, but not writes when
1360 * DCA is enabled. This is due to a known issue in some chipsets
1361 * which will cause the DCA tag to be cleared.
1362 */
1363 rxctrl |= IXGBE_DCA_RXCTRL_DESC_RRO_EN |
1364 IXGBE_DCA_RXCTRL_DATA_DCA_EN |
1365 IXGBE_DCA_RXCTRL_DESC_DCA_EN;
1366
1367 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
1368 }
1369
1370 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
1371 {
1372 struct ixgbe_adapter *adapter = q_vector->adapter;
1373 struct ixgbe_ring *ring;
1374 int cpu = get_cpu();
1375
1376 if (q_vector->cpu == cpu)
1377 goto out_no_update;
1378
1379 ixgbe_for_each_ring(ring, q_vector->tx)
1380 ixgbe_update_tx_dca(adapter, ring, cpu);
1381
1382 ixgbe_for_each_ring(ring, q_vector->rx)
1383 ixgbe_update_rx_dca(adapter, ring, cpu);
1384
1385 q_vector->cpu = cpu;
1386 out_no_update:
1387 put_cpu();
1388 }
1389
1390 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
1391 {
1392 int i;
1393
1394 /* always use CB2 mode, difference is masked in the CB driver */
1395 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1396 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1397 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1398 else
1399 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1400 IXGBE_DCA_CTRL_DCA_DISABLE);
1401
1402 for (i = 0; i < adapter->num_q_vectors; i++) {
1403 adapter->q_vector[i]->cpu = -1;
1404 ixgbe_update_dca(adapter->q_vector[i]);
1405 }
1406 }
1407
1408 static int __ixgbe_notify_dca(struct device *dev, void *data)
1409 {
1410 struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1411 unsigned long event = *(unsigned long *)data;
1412
1413 if (!(adapter->flags & IXGBE_FLAG_DCA_CAPABLE))
1414 return 0;
1415
1416 switch (event) {
1417 case DCA_PROVIDER_ADD:
1418 /* if we're already enabled, don't do it again */
1419 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1420 break;
1421 if (dca_add_requester(dev) == 0) {
1422 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1423 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1424 IXGBE_DCA_CTRL_DCA_MODE_CB2);
1425 break;
1426 }
1427 fallthrough; /* DCA is disabled. */
1428 case DCA_PROVIDER_REMOVE:
1429 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1430 dca_remove_requester(dev);
1431 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1432 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
1433 IXGBE_DCA_CTRL_DCA_DISABLE);
1434 }
1435 break;
1436 }
1437
1438 return 0;
1439 }
1440
1441 #endif /* CONFIG_IXGBE_DCA */
1442
1443 #define IXGBE_RSS_L4_TYPES_MASK \
1444 ((1ul << IXGBE_RXDADV_RSSTYPE_IPV4_TCP) | \
1445 (1ul << IXGBE_RXDADV_RSSTYPE_IPV4_UDP) | \
1446 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_TCP) | \
1447 (1ul << IXGBE_RXDADV_RSSTYPE_IPV6_UDP))
1448
1449 static inline void ixgbe_rx_hash(struct ixgbe_ring *ring,
1450 union ixgbe_adv_rx_desc *rx_desc,
1451 struct sk_buff *skb)
1452 {
1453 u16 rss_type;
1454
1455 if (!(ring->netdev->features & NETIF_F_RXHASH))
1456 return;
1457
1458 rss_type = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.pkt_info) &
1459 IXGBE_RXDADV_RSSTYPE_MASK;
1460
1461 if (!rss_type)
1462 return;
1463
1464 skb_set_hash(skb, le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
1465 (IXGBE_RSS_L4_TYPES_MASK & (1ul << rss_type)) ?
1466 PKT_HASH_TYPE_L4 : PKT_HASH_TYPE_L3);
1467 }
1468
1469 #ifdef IXGBE_FCOE
1470 /**
1471 * ixgbe_rx_is_fcoe - check the rx desc for incoming pkt type
1472 * @ring: structure containing ring specific data
1473 * @rx_desc: advanced rx descriptor
1474 *
1475 * Returns : true if it is FCoE pkt
1476 */
1477 static inline bool ixgbe_rx_is_fcoe(struct ixgbe_ring *ring,
1478 union ixgbe_adv_rx_desc *rx_desc)
1479 {
1480 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1481
1482 return test_bit(__IXGBE_RX_FCOE, &ring->state) &&
1483 ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_ETQF_MASK)) ==
1484 (cpu_to_le16(IXGBE_ETQF_FILTER_FCOE <<
1485 IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT)));
1486 }
1487
1488 #endif /* IXGBE_FCOE */
1489 /**
1490 * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1491 * @ring: structure containing ring specific data
1492 * @rx_desc: current Rx descriptor being processed
1493 * @skb: skb currently being received and modified
1494 **/
1495 static inline void ixgbe_rx_checksum(struct ixgbe_ring *ring,
1496 union ixgbe_adv_rx_desc *rx_desc,
1497 struct sk_buff *skb)
1498 {
1499 __le16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1500 bool encap_pkt = false;
1501
1502 skb_checksum_none_assert(skb);
1503
1504 /* Rx csum disabled */
1505 if (!(ring->netdev->features & NETIF_F_RXCSUM))
1506 return;
1507
1508 /* check for VXLAN and Geneve packets */
1509 if (pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_VXLAN)) {
1510 encap_pkt = true;
1511 skb->encapsulation = 1;
1512 }
1513
1514 /* if IP and error */
1515 if (ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_IPCS) &&
1516 ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_IPE)) {
1517 ring->rx_stats.csum_err++;
1518 return;
1519 }
1520
1521 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_L4CS))
1522 return;
1523
1524 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_TCPE)) {
1525 /*
1526 * 82599 errata, UDP frames with a 0 checksum can be marked as
1527 * checksum errors.
1528 */
1529 if ((pkt_info & cpu_to_le16(IXGBE_RXDADV_PKTTYPE_UDP)) &&
1530 test_bit(__IXGBE_RX_CSUM_UDP_ZERO_ERR, &ring->state))
1531 return;
1532
1533 ring->rx_stats.csum_err++;
1534 return;
1535 }
1536
1537 /* It must be a TCP or UDP packet with a valid checksum */
1538 skb->ip_summed = CHECKSUM_UNNECESSARY;
1539 if (encap_pkt) {
1540 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_OUTERIPCS))
1541 return;
1542
1543 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_ERR_OUTERIPER)) {
1544 skb->ip_summed = CHECKSUM_NONE;
1545 return;
1546 }
1547 /* If we checked the outer header let the stack know */
1548 skb->csum_level = 1;
1549 }
1550 }
1551
1552 static unsigned int ixgbe_rx_offset(struct ixgbe_ring *rx_ring)
1553 {
1554 return ring_uses_build_skb(rx_ring) ? IXGBE_SKB_PAD : 0;
1555 }
1556
1557 static bool ixgbe_alloc_mapped_page(struct ixgbe_ring *rx_ring,
1558 struct ixgbe_rx_buffer *bi)
1559 {
1560 struct page *page = bi->page;
1561 dma_addr_t dma;
1562
1563 /* since we are recycling buffers we should seldom need to alloc */
1564 if (likely(page))
1565 return true;
1566
1567 /* alloc new page for storage */
1568 page = dev_alloc_pages(ixgbe_rx_pg_order(rx_ring));
1569 if (unlikely(!page)) {
1570 rx_ring->rx_stats.alloc_rx_page_failed++;
1571 return false;
1572 }
1573
1574 /* map page for use */
1575 dma = dma_map_page_attrs(rx_ring->dev, page, 0,
1576 ixgbe_rx_pg_size(rx_ring),
1577 DMA_FROM_DEVICE,
1578 IXGBE_RX_DMA_ATTR);
1579
1580 /*
1581 * if mapping failed free memory back to system since
1582 * there isn't much point in holding memory we can't use
1583 */
1584 if (dma_mapping_error(rx_ring->dev, dma)) {
1585 __free_pages(page, ixgbe_rx_pg_order(rx_ring));
1586
1587 rx_ring->rx_stats.alloc_rx_page_failed++;
1588 return false;
1589 }
1590
1591 bi->dma = dma;
1592 bi->page = page;
1593 bi->page_offset = rx_ring->rx_offset;
1594 page_ref_add(page, USHRT_MAX - 1);
1595 bi->pagecnt_bias = USHRT_MAX;
1596 rx_ring->rx_stats.alloc_rx_page++;
1597
1598 return true;
1599 }
1600
1601 /**
1602 * ixgbe_alloc_rx_buffers - Replace used receive buffers
1603 * @rx_ring: ring to place buffers on
1604 * @cleaned_count: number of buffers to replace
1605 **/
1606 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1607 {
1608 union ixgbe_adv_rx_desc *rx_desc;
1609 struct ixgbe_rx_buffer *bi;
1610 u16 i = rx_ring->next_to_use;
1611 u16 bufsz;
1612
1613 /* nothing to do */
1614 if (!cleaned_count)
1615 return;
1616
1617 rx_desc = IXGBE_RX_DESC(rx_ring, i);
1618 bi = &rx_ring->rx_buffer_info[i];
1619 i -= rx_ring->count;
1620
1621 bufsz = ixgbe_rx_bufsz(rx_ring);
1622
1623 do {
1624 if (!ixgbe_alloc_mapped_page(rx_ring, bi))
1625 break;
1626
1627 /* sync the buffer for use by the device */
1628 dma_sync_single_range_for_device(rx_ring->dev, bi->dma,
1629 bi->page_offset, bufsz,
1630 DMA_FROM_DEVICE);
1631
1632 /*
1633 * Refresh the desc even if buffer_addrs didn't change
1634 * because each write-back erases this info.
1635 */
1636 rx_desc->read.pkt_addr = cpu_to_le64(bi->dma + bi->page_offset);
1637
1638 rx_desc++;
1639 bi++;
1640 i++;
1641 if (unlikely(!i)) {
1642 rx_desc = IXGBE_RX_DESC(rx_ring, 0);
1643 bi = rx_ring->rx_buffer_info;
1644 i -= rx_ring->count;
1645 }
1646
1647 /* clear the length for the next_to_use descriptor */
1648 rx_desc->wb.upper.length = 0;
1649
1650 cleaned_count--;
1651 } while (cleaned_count);
1652
1653 i += rx_ring->count;
1654
1655 if (rx_ring->next_to_use != i) {
1656 rx_ring->next_to_use = i;
1657
1658 /* update next to alloc since we have filled the ring */
1659 rx_ring->next_to_alloc = i;
1660
1661 /* Force memory writes to complete before letting h/w
1662 * know there are new descriptors to fetch. (Only
1663 * applicable for weak-ordered memory model archs,
1664 * such as IA-64).
1665 */
1666 wmb();
1667 writel(i, rx_ring->tail);
1668 }
1669 }
1670
1671 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
1672 struct sk_buff *skb)
1673 {
1674 u16 hdr_len = skb_headlen(skb);
1675
1676 /* set gso_size to avoid messing up TCP MSS */
1677 skb_shinfo(skb)->gso_size = DIV_ROUND_UP((skb->len - hdr_len),
1678 IXGBE_CB(skb)->append_cnt);
1679 skb_shinfo(skb)->gso_type = SKB_GSO_TCPV4;
1680 }
1681
1682 static void ixgbe_update_rsc_stats(struct ixgbe_ring *rx_ring,
1683 struct sk_buff *skb)
1684 {
1685 /* if append_cnt is 0 then frame is not RSC */
1686 if (!IXGBE_CB(skb)->append_cnt)
1687 return;
1688
1689 rx_ring->rx_stats.rsc_count += IXGBE_CB(skb)->append_cnt;
1690 rx_ring->rx_stats.rsc_flush++;
1691
1692 ixgbe_set_rsc_gso_size(rx_ring, skb);
1693
1694 /* gso_size is computed using append_cnt so always clear it last */
1695 IXGBE_CB(skb)->append_cnt = 0;
1696 }
1697
1698 /**
1699 * ixgbe_process_skb_fields - Populate skb header fields from Rx descriptor
1700 * @rx_ring: rx descriptor ring packet is being transacted on
1701 * @rx_desc: pointer to the EOP Rx descriptor
1702 * @skb: pointer to current skb being populated
1703 *
1704 * This function checks the ring, descriptor, and packet information in
1705 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
1706 * other fields within the skb.
1707 **/
1708 void ixgbe_process_skb_fields(struct ixgbe_ring *rx_ring,
1709 union ixgbe_adv_rx_desc *rx_desc,
1710 struct sk_buff *skb)
1711 {
1712 struct net_device *dev = rx_ring->netdev;
1713 u32 flags = rx_ring->q_vector->adapter->flags;
1714
1715 ixgbe_update_rsc_stats(rx_ring, skb);
1716
1717 ixgbe_rx_hash(rx_ring, rx_desc, skb);
1718
1719 ixgbe_rx_checksum(rx_ring, rx_desc, skb);
1720
1721 if (unlikely(flags & IXGBE_FLAG_RX_HWTSTAMP_ENABLED))
1722 ixgbe_ptp_rx_hwtstamp(rx_ring, rx_desc, skb);
1723
1724 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
1725 ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_VP)) {
1726 u16 vid = le16_to_cpu(rx_desc->wb.upper.vlan);
1727 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
1728 }
1729
1730 if (ixgbe_test_staterr(rx_desc, IXGBE_RXDADV_STAT_SECP))
1731 ixgbe_ipsec_rx(rx_ring, rx_desc, skb);
1732
1733 /* record Rx queue, or update MACVLAN statistics */
1734 if (netif_is_ixgbe(dev))
1735 skb_record_rx_queue(skb, rx_ring->queue_index);
1736 else
1737 macvlan_count_rx(netdev_priv(dev), skb->len + ETH_HLEN, true,
1738 false);
1739
1740 skb->protocol = eth_type_trans(skb, dev);
1741 }
1742
1743 void ixgbe_rx_skb(struct ixgbe_q_vector *q_vector,
1744 struct sk_buff *skb)
1745 {
1746 napi_gro_receive(&q_vector->napi, skb);
1747 }
1748
1749 /**
1750 * ixgbe_is_non_eop - process handling of non-EOP buffers
1751 * @rx_ring: Rx ring being processed
1752 * @rx_desc: Rx descriptor for current buffer
1753 * @skb: Current socket buffer containing buffer in progress
1754 *
1755 * This function updates next to clean. If the buffer is an EOP buffer
1756 * this function exits returning false, otherwise it will place the
1757 * sk_buff in the next buffer to be chained and return true indicating
1758 * that this is in fact a non-EOP buffer.
1759 **/
1760 static bool ixgbe_is_non_eop(struct ixgbe_ring *rx_ring,
1761 union ixgbe_adv_rx_desc *rx_desc,
1762 struct sk_buff *skb)
1763 {
1764 u32 ntc = rx_ring->next_to_clean + 1;
1765
1766 /* fetch, update, and store next to clean */
1767 ntc = (ntc < rx_ring->count) ? ntc : 0;
1768 rx_ring->next_to_clean = ntc;
1769
1770 prefetch(IXGBE_RX_DESC(rx_ring, ntc));
1771
1772 /* update RSC append count if present */
1773 if (ring_is_rsc_enabled(rx_ring)) {
1774 __le32 rsc_enabled = rx_desc->wb.lower.lo_dword.data &
1775 cpu_to_le32(IXGBE_RXDADV_RSCCNT_MASK);
1776
1777 if (unlikely(rsc_enabled)) {
1778 u32 rsc_cnt = le32_to_cpu(rsc_enabled);
1779
1780 rsc_cnt >>= IXGBE_RXDADV_RSCCNT_SHIFT;
1781 IXGBE_CB(skb)->append_cnt += rsc_cnt - 1;
1782
1783 /* update ntc based on RSC value */
1784 ntc = le32_to_cpu(rx_desc->wb.upper.status_error);
1785 ntc &= IXGBE_RXDADV_NEXTP_MASK;
1786 ntc >>= IXGBE_RXDADV_NEXTP_SHIFT;
1787 }
1788 }
1789
1790 /* if we are the last buffer then there is nothing else to do */
1791 if (likely(ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)))
1792 return false;
1793
1794 /* place skb in next buffer to be received */
1795 rx_ring->rx_buffer_info[ntc].skb = skb;
1796 rx_ring->rx_stats.non_eop_descs++;
1797
1798 return true;
1799 }
1800
1801 /**
1802 * ixgbe_pull_tail - ixgbe specific version of skb_pull_tail
1803 * @rx_ring: rx descriptor ring packet is being transacted on
1804 * @skb: pointer to current skb being adjusted
1805 *
1806 * This function is an ixgbe specific version of __pskb_pull_tail. The
1807 * main difference between this version and the original function is that
1808 * this function can make several assumptions about the state of things
1809 * that allow for significant optimizations versus the standard function.
1810 * As a result we can do things like drop a frag and maintain an accurate
1811 * truesize for the skb.
1812 */
1813 static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
1814 struct sk_buff *skb)
1815 {
1816 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1817 unsigned char *va;
1818 unsigned int pull_len;
1819
1820 /*
1821 * it is valid to use page_address instead of kmap since we are
1822 * working with pages allocated out of the lomem pool per
1823 * alloc_page(GFP_ATOMIC)
1824 */
1825 va = skb_frag_address(frag);
1826
1827 /*
1828 * we need the header to contain the greater of either ETH_HLEN or
1829 * 60 bytes if the skb->len is less than 60 for skb_pad.
1830 */
1831 pull_len = eth_get_headlen(skb->dev, va, IXGBE_RX_HDR_SIZE);
1832
1833 /* align pull length to size of long to optimize memcpy performance */
1834 skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
1835
1836 /* update all of the pointers */
1837 skb_frag_size_sub(frag, pull_len);
1838 skb_frag_off_add(frag, pull_len);
1839 skb->data_len -= pull_len;
1840 skb->tail += pull_len;
1841 }
1842
1843 /**
1844 * ixgbe_dma_sync_frag - perform DMA sync for first frag of SKB
1845 * @rx_ring: rx descriptor ring packet is being transacted on
1846 * @skb: pointer to current skb being updated
1847 *
1848 * This function provides a basic DMA sync up for the first fragment of an
1849 * skb. The reason for doing this is that the first fragment cannot be
1850 * unmapped until we have reached the end of packet descriptor for a buffer
1851 * chain.
1852 */
1853 static void ixgbe_dma_sync_frag(struct ixgbe_ring *rx_ring,
1854 struct sk_buff *skb)
1855 {
1856 if (ring_uses_build_skb(rx_ring)) {
1857 unsigned long mask = (unsigned long)ixgbe_rx_pg_size(rx_ring) - 1;
1858 unsigned long offset = (unsigned long)(skb->data) & mask;
1859
1860 dma_sync_single_range_for_cpu(rx_ring->dev,
1861 IXGBE_CB(skb)->dma,
1862 offset,
1863 skb_headlen(skb),
1864 DMA_FROM_DEVICE);
1865 } else {
1866 skb_frag_t *frag = &skb_shinfo(skb)->frags[0];
1867
1868 dma_sync_single_range_for_cpu(rx_ring->dev,
1869 IXGBE_CB(skb)->dma,
1870 skb_frag_off(frag),
1871 skb_frag_size(frag),
1872 DMA_FROM_DEVICE);
1873 }
1874
1875 /* If the page was released, just unmap it. */
1876 if (unlikely(IXGBE_CB(skb)->page_released)) {
1877 dma_unmap_page_attrs(rx_ring->dev, IXGBE_CB(skb)->dma,
1878 ixgbe_rx_pg_size(rx_ring),
1879 DMA_FROM_DEVICE,
1880 IXGBE_RX_DMA_ATTR);
1881 }
1882 }
1883
1884 /**
1885 * ixgbe_cleanup_headers - Correct corrupted or empty headers
1886 * @rx_ring: rx descriptor ring packet is being transacted on
1887 * @rx_desc: pointer to the EOP Rx descriptor
1888 * @skb: pointer to current skb being fixed
1889 *
1890 * Check if the skb is valid in the XDP case it will be an error pointer.
1891 * Return true in this case to abort processing and advance to next
1892 * descriptor.
1893 *
1894 * Check for corrupted packet headers caused by senders on the local L2
1895 * embedded NIC switch not setting up their Tx Descriptors right. These
1896 * should be very rare.
1897 *
1898 * Also address the case where we are pulling data in on pages only
1899 * and as such no data is present in the skb header.
1900 *
1901 * In addition if skb is not at least 60 bytes we need to pad it so that
1902 * it is large enough to qualify as a valid Ethernet frame.
1903 *
1904 * Returns true if an error was encountered and skb was freed.
1905 **/
1906 bool ixgbe_cleanup_headers(struct ixgbe_ring *rx_ring,
1907 union ixgbe_adv_rx_desc *rx_desc,
1908 struct sk_buff *skb)
1909 {
1910 struct net_device *netdev = rx_ring->netdev;
1911
1912 /* XDP packets use error pointer so abort at this point */
1913 if (IS_ERR(skb))
1914 return true;
1915
1916 /* Verify netdev is present, and that packet does not have any
1917 * errors that would be unacceptable to the netdev.
1918 */
1919 if (!netdev ||
1920 (unlikely(ixgbe_test_staterr(rx_desc,
1921 IXGBE_RXDADV_ERR_FRAME_ERR_MASK) &&
1922 !(netdev->features & NETIF_F_RXALL)))) {
1923 dev_kfree_skb_any(skb);
1924 return true;
1925 }
1926
1927 /* place header in linear portion of buffer */
1928 if (!skb_headlen(skb))
1929 ixgbe_pull_tail(rx_ring, skb);
1930
1931 #ifdef IXGBE_FCOE
1932 /* do not attempt to pad FCoE Frames as this will disrupt DDP */
1933 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc))
1934 return false;
1935
1936 #endif
1937 /* if eth_skb_pad returns an error the skb was freed */
1938 if (eth_skb_pad(skb))
1939 return true;
1940
1941 return false;
1942 }
1943
1944 /**
1945 * ixgbe_reuse_rx_page - page flip buffer and store it back on the ring
1946 * @rx_ring: rx descriptor ring to store buffers on
1947 * @old_buff: donor buffer to have page reused
1948 *
1949 * Synchronizes page for reuse by the adapter
1950 **/
1951 static void ixgbe_reuse_rx_page(struct ixgbe_ring *rx_ring,
1952 struct ixgbe_rx_buffer *old_buff)
1953 {
1954 struct ixgbe_rx_buffer *new_buff;
1955 u16 nta = rx_ring->next_to_alloc;
1956
1957 new_buff = &rx_ring->rx_buffer_info[nta];
1958
1959 /* update, and store next to alloc */
1960 nta++;
1961 rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;
1962
1963 /* Transfer page from old buffer to new buffer.
1964 * Move each member individually to avoid possible store
1965 * forwarding stalls and unnecessary copy of skb.
1966 */
1967 new_buff->dma = old_buff->dma;
1968 new_buff->page = old_buff->page;
1969 new_buff->page_offset = old_buff->page_offset;
1970 new_buff->pagecnt_bias = old_buff->pagecnt_bias;
1971 }
1972
1973 static bool ixgbe_can_reuse_rx_page(struct ixgbe_rx_buffer *rx_buffer,
1974 int rx_buffer_pgcnt)
1975 {
1976 unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
1977 struct page *page = rx_buffer->page;
1978
1979 /* avoid re-using remote and pfmemalloc pages */
1980 if (!dev_page_is_reusable(page))
1981 return false;
1982
1983 #if (PAGE_SIZE < 8192)
1984 /* if we are only owner of page we can reuse it */
1985 if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
1986 return false;
1987 #else
1988 /* The last offset is a bit aggressive in that we assume the
1989 * worst case of FCoE being enabled and using a 3K buffer.
1990 * However this should have minimal impact as the 1K extra is
1991 * still less than one buffer in size.
1992 */
1993 #define IXGBE_LAST_OFFSET \
1994 (SKB_WITH_OVERHEAD(PAGE_SIZE) - IXGBE_RXBUFFER_3K)
1995 if (rx_buffer->page_offset > IXGBE_LAST_OFFSET)
1996 return false;
1997 #endif
1998
1999 /* If we have drained the page fragment pool we need to update
2000 * the pagecnt_bias and page count so that we fully restock the
2001 * number of references the driver holds.
2002 */
2003 if (unlikely(pagecnt_bias == 1)) {
2004 page_ref_add(page, USHRT_MAX - 1);
2005 rx_buffer->pagecnt_bias = USHRT_MAX;
2006 }
2007
2008 return true;
2009 }
2010
2011 /**
2012 * ixgbe_add_rx_frag - Add contents of Rx buffer to sk_buff
2013 * @rx_ring: rx descriptor ring to transact packets on
2014 * @rx_buffer: buffer containing page to add
2015 * @skb: sk_buff to place the data into
2016 * @size: size of data in rx_buffer
2017 *
2018 * This function will add the data contained in rx_buffer->page to the skb.
2019 * This is done either through a direct copy if the data in the buffer is
2020 * less than the skb header size, otherwise it will just attach the page as
2021 * a frag to the skb.
2022 *
2023 * The function will then update the page offset if necessary and return
2024 * true if the buffer can be reused by the adapter.
2025 **/
2026 static void ixgbe_add_rx_frag(struct ixgbe_ring *rx_ring,
2027 struct ixgbe_rx_buffer *rx_buffer,
2028 struct sk_buff *skb,
2029 unsigned int size)
2030 {
2031 #if (PAGE_SIZE < 8192)
2032 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2033 #else
2034 unsigned int truesize = rx_ring->rx_offset ?
2035 SKB_DATA_ALIGN(rx_ring->rx_offset + size) :
2036 SKB_DATA_ALIGN(size);
2037 #endif
2038 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
2039 rx_buffer->page_offset, size, truesize);
2040 #if (PAGE_SIZE < 8192)
2041 rx_buffer->page_offset ^= truesize;
2042 #else
2043 rx_buffer->page_offset += truesize;
2044 #endif
2045 }
2046
2047 static struct ixgbe_rx_buffer *ixgbe_get_rx_buffer(struct ixgbe_ring *rx_ring,
2048 union ixgbe_adv_rx_desc *rx_desc,
2049 struct sk_buff **skb,
2050 const unsigned int size,
2051 int *rx_buffer_pgcnt)
2052 {
2053 struct ixgbe_rx_buffer *rx_buffer;
2054
2055 rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
2056 *rx_buffer_pgcnt =
2057 #if (PAGE_SIZE < 8192)
2058 page_count(rx_buffer->page);
2059 #else
2060 0;
2061 #endif
2062 prefetchw(rx_buffer->page);
2063 *skb = rx_buffer->skb;
2064
2065 /* Delay unmapping of the first packet. It carries the header
2066 * information, HW may still access the header after the writeback.
2067 * Only unmap it when EOP is reached
2068 */
2069 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP)) {
2070 if (!*skb)
2071 goto skip_sync;
2072 } else {
2073 if (*skb)
2074 ixgbe_dma_sync_frag(rx_ring, *skb);
2075 }
2076
2077 /* we are reusing so sync this buffer for CPU use */
2078 dma_sync_single_range_for_cpu(rx_ring->dev,
2079 rx_buffer->dma,
2080 rx_buffer->page_offset,
2081 size,
2082 DMA_FROM_DEVICE);
2083 skip_sync:
2084 rx_buffer->pagecnt_bias--;
2085
2086 return rx_buffer;
2087 }
2088
2089 static void ixgbe_put_rx_buffer(struct ixgbe_ring *rx_ring,
2090 struct ixgbe_rx_buffer *rx_buffer,
2091 struct sk_buff *skb,
2092 int rx_buffer_pgcnt)
2093 {
2094 if (ixgbe_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
2095 /* hand second half of page back to the ring */
2096 ixgbe_reuse_rx_page(rx_ring, rx_buffer);
2097 } else {
2098 if (!IS_ERR(skb) && IXGBE_CB(skb)->dma == rx_buffer->dma) {
2099 /* the page has been released from the ring */
2100 IXGBE_CB(skb)->page_released = true;
2101 } else {
2102 /* we are not reusing the buffer so unmap it */
2103 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
2104 ixgbe_rx_pg_size(rx_ring),
2105 DMA_FROM_DEVICE,
2106 IXGBE_RX_DMA_ATTR);
2107 }
2108 __page_frag_cache_drain(rx_buffer->page,
2109 rx_buffer->pagecnt_bias);
2110 }
2111
2112 /* clear contents of rx_buffer */
2113 rx_buffer->page = NULL;
2114 rx_buffer->skb = NULL;
2115 }
2116
2117 static struct sk_buff *ixgbe_construct_skb(struct ixgbe_ring *rx_ring,
2118 struct ixgbe_rx_buffer *rx_buffer,
2119 struct xdp_buff *xdp,
2120 union ixgbe_adv_rx_desc *rx_desc)
2121 {
2122 unsigned int size = xdp->data_end - xdp->data;
2123 #if (PAGE_SIZE < 8192)
2124 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2125 #else
2126 unsigned int truesize = SKB_DATA_ALIGN(xdp->data_end -
2127 xdp->data_hard_start);
2128 #endif
2129 struct sk_buff *skb;
2130
2131 /* prefetch first cache line of first page */
2132 net_prefetch(xdp->data);
2133
2134 /* Note, we get here by enabling legacy-rx via:
2135 *
2136 * ethtool --set-priv-flags <dev> legacy-rx on
2137 *
2138 * In this mode, we currently get 0 extra XDP headroom as
2139 * opposed to having legacy-rx off, where we process XDP
2140 * packets going to stack via ixgbe_build_skb(). The latter
2141 * provides us currently with 192 bytes of headroom.
2142 *
2143 * For ixgbe_construct_skb() mode it means that the
2144 * xdp->data_meta will always point to xdp->data, since
2145 * the helper cannot expand the head. Should this ever
2146 * change in future for legacy-rx mode on, then lets also
2147 * add xdp->data_meta handling here.
2148 */
2149
2150 /* allocate a skb to store the frags */
2151 skb = napi_alloc_skb(&rx_ring->q_vector->napi, IXGBE_RX_HDR_SIZE);
2152 if (unlikely(!skb))
2153 return NULL;
2154
2155 if (size > IXGBE_RX_HDR_SIZE) {
2156 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2157 IXGBE_CB(skb)->dma = rx_buffer->dma;
2158
2159 skb_add_rx_frag(skb, 0, rx_buffer->page,
2160 xdp->data - page_address(rx_buffer->page),
2161 size, truesize);
2162 #if (PAGE_SIZE < 8192)
2163 rx_buffer->page_offset ^= truesize;
2164 #else
2165 rx_buffer->page_offset += truesize;
2166 #endif
2167 } else {
2168 memcpy(__skb_put(skb, size),
2169 xdp->data, ALIGN(size, sizeof(long)));
2170 rx_buffer->pagecnt_bias++;
2171 }
2172
2173 return skb;
2174 }
2175
2176 static struct sk_buff *ixgbe_build_skb(struct ixgbe_ring *rx_ring,
2177 struct ixgbe_rx_buffer *rx_buffer,
2178 struct xdp_buff *xdp,
2179 union ixgbe_adv_rx_desc *rx_desc)
2180 {
2181 unsigned int metasize = xdp->data - xdp->data_meta;
2182 #if (PAGE_SIZE < 8192)
2183 unsigned int truesize = ixgbe_rx_pg_size(rx_ring) / 2;
2184 #else
2185 unsigned int truesize = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
2186 SKB_DATA_ALIGN(xdp->data_end -
2187 xdp->data_hard_start);
2188 #endif
2189 struct sk_buff *skb;
2190
2191 /* Prefetch first cache line of first page. If xdp->data_meta
2192 * is unused, this points extactly as xdp->data, otherwise we
2193 * likely have a consumer accessing first few bytes of meta
2194 * data, and then actual data.
2195 */
2196 net_prefetch(xdp->data_meta);
2197
2198 /* build an skb to around the page buffer */
2199 skb = napi_build_skb(xdp->data_hard_start, truesize);
2200 if (unlikely(!skb))
2201 return NULL;
2202
2203 /* update pointers within the skb to store the data */
2204 skb_reserve(skb, xdp->data - xdp->data_hard_start);
2205 __skb_put(skb, xdp->data_end - xdp->data);
2206 if (metasize)
2207 skb_metadata_set(skb, metasize);
2208
2209 /* record DMA address if this is the start of a chain of buffers */
2210 if (!ixgbe_test_staterr(rx_desc, IXGBE_RXD_STAT_EOP))
2211 IXGBE_CB(skb)->dma = rx_buffer->dma;
2212
2213 /* update buffer offset */
2214 #if (PAGE_SIZE < 8192)
2215 rx_buffer->page_offset ^= truesize;
2216 #else
2217 rx_buffer->page_offset += truesize;
2218 #endif
2219
2220 return skb;
2221 }
2222
2223 static struct sk_buff *ixgbe_run_xdp(struct ixgbe_adapter *adapter,
2224 struct ixgbe_ring *rx_ring,
2225 struct xdp_buff *xdp)
2226 {
2227 int err, result = IXGBE_XDP_PASS;
2228 struct bpf_prog *xdp_prog;
2229 struct ixgbe_ring *ring;
2230 struct xdp_frame *xdpf;
2231 u32 act;
2232
2233 xdp_prog = READ_ONCE(rx_ring->xdp_prog);
2234
2235 if (!xdp_prog)
2236 goto xdp_out;
2237
2238 prefetchw(xdp->data_hard_start); /* xdp_frame write */
2239
2240 act = bpf_prog_run_xdp(xdp_prog, xdp);
2241 switch (act) {
2242 case XDP_PASS:
2243 break;
2244 case XDP_TX:
2245 xdpf = xdp_convert_buff_to_frame(xdp);
2246 if (unlikely(!xdpf))
2247 goto out_failure;
2248 ring = ixgbe_determine_xdp_ring(adapter);
2249 if (static_branch_unlikely(&ixgbe_xdp_locking_key))
2250 spin_lock(&ring->tx_lock);
2251 result = ixgbe_xmit_xdp_ring(ring, xdpf);
2252 if (static_branch_unlikely(&ixgbe_xdp_locking_key))
2253 spin_unlock(&ring->tx_lock);
2254 if (result == IXGBE_XDP_CONSUMED)
2255 goto out_failure;
2256 break;
2257 case XDP_REDIRECT:
2258 err = xdp_do_redirect(adapter->netdev, xdp, xdp_prog);
2259 if (err)
2260 goto out_failure;
2261 result = IXGBE_XDP_REDIR;
2262 break;
2263 default:
2264 bpf_warn_invalid_xdp_action(rx_ring->netdev, xdp_prog, act);
2265 fallthrough;
2266 case XDP_ABORTED:
2267 out_failure:
2268 trace_xdp_exception(rx_ring->netdev, xdp_prog, act);
2269 fallthrough; /* handle aborts by dropping packet */
2270 case XDP_DROP:
2271 result = IXGBE_XDP_CONSUMED;
2272 break;
2273 }
2274 xdp_out:
2275 return ERR_PTR(-result);
2276 }
2277
2278 static unsigned int ixgbe_rx_frame_truesize(struct ixgbe_ring *rx_ring,
2279 unsigned int size)
2280 {
2281 unsigned int truesize;
2282
2283 #if (PAGE_SIZE < 8192)
2284 truesize = ixgbe_rx_pg_size(rx_ring) / 2; /* Must be power-of-2 */
2285 #else
2286 truesize = rx_ring->rx_offset ?
2287 SKB_DATA_ALIGN(rx_ring->rx_offset + size) +
2288 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) :
2289 SKB_DATA_ALIGN(size);
2290 #endif
2291 return truesize;
2292 }
2293
2294 static void ixgbe_rx_buffer_flip(struct ixgbe_ring *rx_ring,
2295 struct ixgbe_rx_buffer *rx_buffer,
2296 unsigned int size)
2297 {
2298 unsigned int truesize = ixgbe_rx_frame_truesize(rx_ring, size);
2299 #if (PAGE_SIZE < 8192)
2300 rx_buffer->page_offset ^= truesize;
2301 #else
2302 rx_buffer->page_offset += truesize;
2303 #endif
2304 }
2305
2306 /**
2307 * ixgbe_clean_rx_irq - Clean completed descriptors from Rx ring - bounce buf
2308 * @q_vector: structure containing interrupt and ring information
2309 * @rx_ring: rx descriptor ring to transact packets on
2310 * @budget: Total limit on number of packets to process
2311 *
2312 * This function provides a "bounce buffer" approach to Rx interrupt
2313 * processing. The advantage to this is that on systems that have
2314 * expensive overhead for IOMMU access this provides a means of avoiding
2315 * it by maintaining the mapping of the page to the syste.
2316 *
2317 * Returns amount of work completed
2318 **/
2319 static int ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
2320 struct ixgbe_ring *rx_ring,
2321 const int budget)
2322 {
2323 unsigned int total_rx_bytes = 0, total_rx_packets = 0, frame_sz = 0;
2324 struct ixgbe_adapter *adapter = q_vector->adapter;
2325 #ifdef IXGBE_FCOE
2326 int ddp_bytes;
2327 unsigned int mss = 0;
2328 #endif /* IXGBE_FCOE */
2329 u16 cleaned_count = ixgbe_desc_unused(rx_ring);
2330 unsigned int offset = rx_ring->rx_offset;
2331 unsigned int xdp_xmit = 0;
2332 struct xdp_buff xdp;
2333
2334 /* Frame size depend on rx_ring setup when PAGE_SIZE=4K */
2335 #if (PAGE_SIZE < 8192)
2336 frame_sz = ixgbe_rx_frame_truesize(rx_ring, 0);
2337 #endif
2338 xdp_init_buff(&xdp, frame_sz, &rx_ring->xdp_rxq);
2339
2340 while (likely(total_rx_packets < budget)) {
2341 union ixgbe_adv_rx_desc *rx_desc;
2342 struct ixgbe_rx_buffer *rx_buffer;
2343 struct sk_buff *skb;
2344 int rx_buffer_pgcnt;
2345 unsigned int size;
2346
2347 /* return some buffers to hardware, one at a time is too slow */
2348 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
2349 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
2350 cleaned_count = 0;
2351 }
2352
2353 rx_desc = IXGBE_RX_DESC(rx_ring, rx_ring->next_to_clean);
2354 size = le16_to_cpu(rx_desc->wb.upper.length);
2355 if (!size)
2356 break;
2357
2358 /* This memory barrier is needed to keep us from reading
2359 * any other fields out of the rx_desc until we know the
2360 * descriptor has been written back
2361 */
2362 dma_rmb();
2363
2364 rx_buffer = ixgbe_get_rx_buffer(rx_ring, rx_desc, &skb, size, &rx_buffer_pgcnt);
2365
2366 /* retrieve a buffer from the ring */
2367 if (!skb) {
2368 unsigned char *hard_start;
2369
2370 hard_start = page_address(rx_buffer->page) +
2371 rx_buffer->page_offset - offset;
2372 xdp_prepare_buff(&xdp, hard_start, offset, size, true);
2373 xdp_buff_clear_frags_flag(&xdp);
2374 #if (PAGE_SIZE > 4096)
2375 /* At larger PAGE_SIZE, frame_sz depend on len size */
2376 xdp.frame_sz = ixgbe_rx_frame_truesize(rx_ring, size);
2377 #endif
2378 skb = ixgbe_run_xdp(adapter, rx_ring, &xdp);
2379 }
2380
2381 if (IS_ERR(skb)) {
2382 unsigned int xdp_res = -PTR_ERR(skb);
2383
2384 if (xdp_res & (IXGBE_XDP_TX | IXGBE_XDP_REDIR)) {
2385 xdp_xmit |= xdp_res;
2386 ixgbe_rx_buffer_flip(rx_ring, rx_buffer, size);
2387 } else {
2388 rx_buffer->pagecnt_bias++;
2389 }
2390 total_rx_packets++;
2391 total_rx_bytes += size;
2392 } else if (skb) {
2393 ixgbe_add_rx_frag(rx_ring, rx_buffer, skb, size);
2394 } else if (ring_uses_build_skb(rx_ring)) {
2395 skb = ixgbe_build_skb(rx_ring, rx_buffer,
2396 &xdp, rx_desc);
2397 } else {
2398 skb = ixgbe_construct_skb(rx_ring, rx_buffer,
2399 &xdp, rx_desc);
2400 }
2401
2402 /* exit if we failed to retrieve a buffer */
2403 if (!skb) {
2404 rx_ring->rx_stats.alloc_rx_buff_failed++;
2405 rx_buffer->pagecnt_bias++;
2406 break;
2407 }
2408
2409 ixgbe_put_rx_buffer(rx_ring, rx_buffer, skb, rx_buffer_pgcnt);
2410 cleaned_count++;
2411
2412 /* place incomplete frames back on ring for completion */
2413 if (ixgbe_is_non_eop(rx_ring, rx_desc, skb))
2414 continue;
2415
2416 /* verify the packet layout is correct */
2417 if (ixgbe_cleanup_headers(rx_ring, rx_desc, skb))
2418 continue;
2419
2420 /* probably a little skewed due to removing CRC */
2421 total_rx_bytes += skb->len;
2422
2423 /* populate checksum, timestamp, VLAN, and protocol */
2424 ixgbe_process_skb_fields(rx_ring, rx_desc, skb);
2425
2426 #ifdef IXGBE_FCOE
2427 /* if ddp, not passing to ULD unless for FCP_RSP or error */
2428 if (ixgbe_rx_is_fcoe(rx_ring, rx_desc)) {
2429 ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
2430 /* include DDPed FCoE data */
2431 if (ddp_bytes > 0) {
2432 if (!mss) {
2433 mss = rx_ring->netdev->mtu -
2434 sizeof(struct fcoe_hdr) -
2435 sizeof(struct fc_frame_header) -
2436 sizeof(struct fcoe_crc_eof);
2437 if (mss > 512)
2438 mss &= ~511;
2439 }
2440 total_rx_bytes += ddp_bytes;
2441 total_rx_packets += DIV_ROUND_UP(ddp_bytes,
2442 mss);
2443 }
2444 if (!ddp_bytes) {
2445 dev_kfree_skb_any(skb);
2446 continue;
2447 }
2448 }
2449
2450 #endif /* IXGBE_FCOE */
2451 ixgbe_rx_skb(q_vector, skb);
2452
2453 /* update budget accounting */
2454 total_rx_packets++;
2455 }
2456
2457 if (xdp_xmit & IXGBE_XDP_REDIR)
2458 xdp_do_flush();
2459
2460 if (xdp_xmit & IXGBE_XDP_TX) {
2461 struct ixgbe_ring *ring = ixgbe_determine_xdp_ring(adapter);
2462
2463 ixgbe_xdp_ring_update_tail_locked(ring);
2464 }
2465
2466 ixgbe_update_rx_ring_stats(rx_ring, q_vector, total_rx_packets,
2467 total_rx_bytes);
2468
2469 return total_rx_packets;
2470 }
2471
2472 /**
2473 * ixgbe_configure_msix - Configure MSI-X hardware
2474 * @adapter: board private structure
2475 *
2476 * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
2477 * interrupts.
2478 **/
2479 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
2480 {
2481 struct ixgbe_q_vector *q_vector;
2482 int v_idx;
2483 u32 mask;
2484
2485 /* Populate MSIX to EITR Select */
2486 if (adapter->num_vfs > 32) {
2487 u32 eitrsel = BIT(adapter->num_vfs - 32) - 1;
2488 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2489 }
2490
2491 /*
2492 * Populate the IVAR table and set the ITR values to the
2493 * corresponding register.
2494 */
2495 for (v_idx = 0; v_idx < adapter->num_q_vectors; v_idx++) {
2496 struct ixgbe_ring *ring;
2497 q_vector = adapter->q_vector[v_idx];
2498
2499 ixgbe_for_each_ring(ring, q_vector->rx)
2500 ixgbe_set_ivar(adapter, 0, ring->reg_idx, v_idx);
2501
2502 ixgbe_for_each_ring(ring, q_vector->tx)
2503 ixgbe_set_ivar(adapter, 1, ring->reg_idx, v_idx);
2504
2505 ixgbe_write_eitr(q_vector);
2506 }
2507
2508 switch (adapter->hw.mac.type) {
2509 case ixgbe_mac_82598EB:
2510 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
2511 v_idx);
2512 break;
2513 case ixgbe_mac_82599EB:
2514 case ixgbe_mac_X540:
2515 case ixgbe_mac_X550:
2516 case ixgbe_mac_X550EM_x:
2517 case ixgbe_mac_x550em_a:
2518 ixgbe_set_ivar(adapter, -1, 1, v_idx);
2519 break;
2520 default:
2521 break;
2522 }
2523 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
2524
2525 /* set up to autoclear timer, and the vectors */
2526 mask = IXGBE_EIMS_ENABLE_MASK;
2527 mask &= ~(IXGBE_EIMS_OTHER |
2528 IXGBE_EIMS_MAILBOX |
2529 IXGBE_EIMS_LSC);
2530
2531 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
2532 }
2533
2534 /**
2535 * ixgbe_update_itr - update the dynamic ITR value based on statistics
2536 * @q_vector: structure containing interrupt and ring information
2537 * @ring_container: structure containing ring performance data
2538 *
2539 * Stores a new ITR value based on packets and byte
2540 * counts during the last interrupt. The advantage of per interrupt
2541 * computation is faster updates and more accurate ITR for the current
2542 * traffic pattern. Constants in this function were computed
2543 * based on theoretical maximum wire speed and thresholds were set based
2544 * on testing data as well as attempting to minimize response time
2545 * while increasing bulk throughput.
2546 **/
2547 static void ixgbe_update_itr(struct ixgbe_q_vector *q_vector,
2548 struct ixgbe_ring_container *ring_container)
2549 {
2550 unsigned int itr = IXGBE_ITR_ADAPTIVE_MIN_USECS |
2551 IXGBE_ITR_ADAPTIVE_LATENCY;
2552 unsigned int avg_wire_size, packets, bytes;
2553 unsigned long next_update = jiffies;
2554
2555 /* If we don't have any rings just leave ourselves set for maximum
2556 * possible latency so we take ourselves out of the equation.
2557 */
2558 if (!ring_container->ring)
2559 return;
2560
2561 /* If we didn't update within up to 1 - 2 jiffies we can assume
2562 * that either packets are coming in so slow there hasn't been
2563 * any work, or that there is so much work that NAPI is dealing
2564 * with interrupt moderation and we don't need to do anything.
2565 */
2566 if (time_after(next_update, ring_container->next_update))
2567 goto clear_counts;
2568
2569 packets = ring_container->total_packets;
2570
2571 /* We have no packets to actually measure against. This means
2572 * either one of the other queues on this vector is active or
2573 * we are a Tx queue doing TSO with too high of an interrupt rate.
2574 *
2575 * When this occurs just tick up our delay by the minimum value
2576 * and hope that this extra delay will prevent us from being called
2577 * without any work on our queue.
2578 */
2579 if (!packets) {
2580 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2581 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2582 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2583 itr += ring_container->itr & IXGBE_ITR_ADAPTIVE_LATENCY;
2584 goto clear_counts;
2585 }
2586
2587 bytes = ring_container->total_bytes;
2588
2589 /* If packets are less than 4 or bytes are less than 9000 assume
2590 * insufficient data to use bulk rate limiting approach. We are
2591 * likely latency driven.
2592 */
2593 if (packets < 4 && bytes < 9000) {
2594 itr = IXGBE_ITR_ADAPTIVE_LATENCY;
2595 goto adjust_by_size;
2596 }
2597
2598 /* Between 4 and 48 we can assume that our current interrupt delay
2599 * is only slightly too low. As such we should increase it by a small
2600 * fixed amount.
2601 */
2602 if (packets < 48) {
2603 itr = (q_vector->itr >> 2) + IXGBE_ITR_ADAPTIVE_MIN_INC;
2604 if (itr > IXGBE_ITR_ADAPTIVE_MAX_USECS)
2605 itr = IXGBE_ITR_ADAPTIVE_MAX_USECS;
2606 goto clear_counts;
2607 }
2608
2609 /* Between 48 and 96 is our "goldilocks" zone where we are working
2610 * out "just right". Just report that our current ITR is good for us.
2611 */
2612 if (packets < 96) {
2613 itr = q_vector->itr >> 2;
2614 goto clear_counts;
2615 }
2616
2617 /* If packet count is 96 or greater we are likely looking at a slight
2618 * overrun of the delay we want. Try halving our delay to see if that
2619 * will cut the number of packets in half per interrupt.
2620 */
2621 if (packets < 256) {
2622 itr = q_vector->itr >> 3;
2623 if (itr < IXGBE_ITR_ADAPTIVE_MIN_USECS)
2624 itr = IXGBE_ITR_ADAPTIVE_MIN_USECS;
2625 goto clear_counts;
2626 }
2627
2628 /* The paths below assume we are dealing with a bulk ITR since number
2629 * of packets is 256 or greater. We are just going to have to compute
2630 * a value and try to bring the count under control, though for smaller
2631 * packet sizes there isn't much we can do as NAPI polling will likely
2632 * be kicking in sooner rather than later.
2633 */
2634 itr = IXGBE_ITR_ADAPTIVE_BULK;
2635
2636 adjust_by_size:
2637 /* If packet counts are 256 or greater we can assume we have a gross
2638 * overestimation of what the rate should be. Instead of trying to fine
2639 * tune it just use the formula below to try and dial in an exact value
2640 * give the current packet size of the frame.
2641 */
2642 avg_wire_size = bytes / packets;
2643
2644 /* The following is a crude approximation of:
2645 * wmem_default / (size + overhead) = desired_pkts_per_int
2646 * rate / bits_per_byte / (size + ethernet overhead) = pkt_rate
2647 * (desired_pkt_rate / pkt_rate) * usecs_per_sec = ITR value
2648 *
2649 * Assuming wmem_default is 212992 and overhead is 640 bytes per
2650 * packet, (256 skb, 64 headroom, 320 shared info), we can reduce the
2651 * formula down to
2652 *
2653 * (170 * (size + 24)) / (size + 640) = ITR
2654 *
2655 * We first do some math on the packet size and then finally bitshift
2656 * by 8 after rounding up. We also have to account for PCIe link speed
2657 * difference as ITR scales based on this.
2658 */
2659 if (avg_wire_size <= 60) {
2660 /* Start at 50k ints/sec */
2661 avg_wire_size = 5120;
2662 } else if (avg_wire_size <= 316) {
2663 /* 50K ints/sec to 16K ints/sec */
2664 avg_wire_size *= 40;
2665 avg_wire_size += 2720;
2666 } else if (avg_wire_size <= 1084) {
2667 /* 16K ints/sec to 9.2K ints/sec */
2668 avg_wire_size *= 15;
2669 avg_wire_size += 11452;
2670 } else if (avg_wire_size < 1968) {
2671 /* 9.2K ints/sec to 8K ints/sec */
2672 avg_wire_size *= 5;
2673 avg_wire_size += 22420;
2674 } else {
2675 /* plateau at a limit of 8K ints/sec */
2676 avg_wire_size = 32256;
2677 }
2678
2679 /* If we are in low latency mode half our delay which doubles the rate
2680 * to somewhere between 100K to 16K ints/sec
2681 */
2682 if (itr & IXGBE_ITR_ADAPTIVE_LATENCY)
2683 avg_wire_size >>= 1;
2684
2685 /* Resultant value is 256 times larger than it needs to be. This
2686 * gives us room to adjust the value as needed to either increase
2687 * or decrease the value based on link speeds of 10G, 2.5G, 1G, etc.
2688 *
2689 * Use addition as we have already recorded the new latency flag
2690 * for the ITR value.
2691 */
2692 switch (q_vector->adapter->link_speed) {
2693 case IXGBE_LINK_SPEED_10GB_FULL:
2694 case IXGBE_LINK_SPEED_100_FULL:
2695 default:
2696 itr += DIV_ROUND_UP(avg_wire_size,
2697 IXGBE_ITR_ADAPTIVE_MIN_INC * 256) *
2698 IXGBE_ITR_ADAPTIVE_MIN_INC;
2699 break;
2700 case IXGBE_LINK_SPEED_2_5GB_FULL:
2701 case IXGBE_LINK_SPEED_1GB_FULL:
2702 case IXGBE_LINK_SPEED_10_FULL:
2703 if (avg_wire_size > 8064)
2704 avg_wire_size = 8064;
2705 itr += DIV_ROUND_UP(avg_wire_size,
2706 IXGBE_ITR_ADAPTIVE_MIN_INC * 64) *
2707 IXGBE_ITR_ADAPTIVE_MIN_INC;
2708 break;
2709 }
2710
2711 clear_counts:
2712 /* write back value */
2713 ring_container->itr = itr;
2714
2715 /* next update should occur within next jiffy */
2716 ring_container->next_update = next_update + 1;
2717
2718 ring_container->total_bytes = 0;
2719 ring_container->total_packets = 0;
2720 }
2721
2722 /**
2723 * ixgbe_write_eitr - write EITR register in hardware specific way
2724 * @q_vector: structure containing interrupt and ring information
2725 *
2726 * This function is made to be called by ethtool and by the driver
2727 * when it needs to update EITR registers at runtime. Hardware
2728 * specific quirks/differences are taken care of here.
2729 */
2730 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
2731 {
2732 struct ixgbe_adapter *adapter = q_vector->adapter;
2733 struct ixgbe_hw *hw = &adapter->hw;
2734 int v_idx = q_vector->v_idx;
2735 u32 itr_reg = q_vector->itr & IXGBE_MAX_EITR;
2736
2737 switch (adapter->hw.mac.type) {
2738 case ixgbe_mac_82598EB:
2739 /* must write high and low 16 bits to reset counter */
2740 itr_reg |= (itr_reg << 16);
2741 break;
2742 case ixgbe_mac_82599EB:
2743 case ixgbe_mac_X540:
2744 case ixgbe_mac_X550:
2745 case ixgbe_mac_X550EM_x:
2746 case ixgbe_mac_x550em_a:
2747 /*
2748 * set the WDIS bit to not clear the timer bits and cause an
2749 * immediate assertion of the interrupt
2750 */
2751 itr_reg |= IXGBE_EITR_CNT_WDIS;
2752 break;
2753 default:
2754 break;
2755 }
2756 IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
2757 }
2758
2759 static void ixgbe_set_itr(struct ixgbe_q_vector *q_vector)
2760 {
2761 u32 new_itr;
2762
2763 ixgbe_update_itr(q_vector, &q_vector->tx);
2764 ixgbe_update_itr(q_vector, &q_vector->rx);
2765
2766 /* use the smallest value of new ITR delay calculations */
2767 new_itr = min(q_vector->rx.itr, q_vector->tx.itr);
2768
2769 /* Clear latency flag if set, shift into correct position */
2770 new_itr &= ~IXGBE_ITR_ADAPTIVE_LATENCY;
2771 new_itr <<= 2;
2772
2773 if (new_itr != q_vector->itr) {
2774 /* save the algorithm value here */
2775 q_vector->itr = new_itr;
2776
2777 ixgbe_write_eitr(q_vector);
2778 }
2779 }
2780
2781 /**
2782 * ixgbe_check_overtemp_subtask - check for over temperature
2783 * @adapter: pointer to adapter
2784 **/
2785 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
2786 {
2787 struct ixgbe_hw *hw = &adapter->hw;
2788 u32 eicr = adapter->interrupt_event;
2789
2790 if (test_bit(__IXGBE_DOWN, &adapter->state))
2791 return;
2792
2793 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
2794 return;
2795
2796 adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2797
2798 switch (hw->device_id) {
2799 case IXGBE_DEV_ID_82599_T3_LOM:
2800 /*
2801 * Since the warning interrupt is for both ports
2802 * we don't have to check if:
2803 * - This interrupt wasn't for our port.
2804 * - We may have missed the interrupt so always have to
2805 * check if we got a LSC
2806 */
2807 if (!(eicr & IXGBE_EICR_GPI_SDP0_8259X) &&
2808 !(eicr & IXGBE_EICR_LSC))
2809 return;
2810
2811 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
2812 u32 speed;
2813 bool link_up = false;
2814
2815 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2816
2817 if (link_up)
2818 return;
2819 }
2820
2821 /* Check if this is not due to overtemp */
2822 if (!hw->phy.ops.check_overtemp(hw))
2823 return;
2824
2825 break;
2826 case IXGBE_DEV_ID_X550EM_A_1G_T:
2827 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
2828 if (!hw->phy.ops.check_overtemp(hw))
2829 return;
2830 break;
2831 default:
2832 if (adapter->hw.mac.type >= ixgbe_mac_X540)
2833 return;
2834 if (!(eicr & IXGBE_EICR_GPI_SDP0(hw)))
2835 return;
2836 break;
2837 }
2838 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2839
2840 adapter->interrupt_event = 0;
2841 }
2842
2843 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
2844 {
2845 struct ixgbe_hw *hw = &adapter->hw;
2846
2847 if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
2848 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2849 e_crit(probe, "Fan has stopped, replace the adapter\n");
2850 /* write to clear the interrupt */
2851 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2852 }
2853 }
2854
2855 static void ixgbe_check_overtemp_event(struct ixgbe_adapter *adapter, u32 eicr)
2856 {
2857 struct ixgbe_hw *hw = &adapter->hw;
2858
2859 if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE))
2860 return;
2861
2862 switch (adapter->hw.mac.type) {
2863 case ixgbe_mac_82599EB:
2864 /*
2865 * Need to check link state so complete overtemp check
2866 * on service task
2867 */
2868 if (((eicr & IXGBE_EICR_GPI_SDP0(hw)) ||
2869 (eicr & IXGBE_EICR_LSC)) &&
2870 (!test_bit(__IXGBE_DOWN, &adapter->state))) {
2871 adapter->interrupt_event = eicr;
2872 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2873 ixgbe_service_event_schedule(adapter);
2874 return;
2875 }
2876 return;
2877 case ixgbe_mac_x550em_a:
2878 if (eicr & IXGBE_EICR_GPI_SDP0_X550EM_a) {
2879 adapter->interrupt_event = eicr;
2880 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2881 ixgbe_service_event_schedule(adapter);
2882 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC,
2883 IXGBE_EICR_GPI_SDP0_X550EM_a);
2884 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICR,
2885 IXGBE_EICR_GPI_SDP0_X550EM_a);
2886 }
2887 return;
2888 case ixgbe_mac_X550:
2889 case ixgbe_mac_X540:
2890 if (!(eicr & IXGBE_EICR_TS))
2891 return;
2892 break;
2893 default:
2894 return;
2895 }
2896
2897 e_crit(drv, "%s\n", ixgbe_overheat_msg);
2898 }
2899
2900 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2901 {
2902 switch (hw->mac.type) {
2903 case ixgbe_mac_82598EB:
2904 if (hw->phy.type == ixgbe_phy_nl)
2905 return true;
2906 return false;
2907 case ixgbe_mac_82599EB:
2908 case ixgbe_mac_X550EM_x:
2909 case ixgbe_mac_x550em_a:
2910 switch (hw->mac.ops.get_media_type(hw)) {
2911 case ixgbe_media_type_fiber:
2912 case ixgbe_media_type_fiber_qsfp:
2913 return true;
2914 default:
2915 return false;
2916 }
2917 default:
2918 return false;
2919 }
2920 }
2921
2922 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
2923 {
2924 struct ixgbe_hw *hw = &adapter->hw;
2925 u32 eicr_mask = IXGBE_EICR_GPI_SDP2(hw);
2926
2927 if (!ixgbe_is_sfp(hw))
2928 return;
2929
2930 /* Later MAC's use different SDP */
2931 if (hw->mac.type >= ixgbe_mac_X540)
2932 eicr_mask = IXGBE_EICR_GPI_SDP0_X540;
2933
2934 if (eicr & eicr_mask) {
2935 /* Clear the interrupt */
2936 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr_mask);
2937 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2938 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
2939 adapter->sfp_poll_time = 0;
2940 ixgbe_service_event_schedule(adapter);
2941 }
2942 }
2943
2944 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
2945 (eicr & IXGBE_EICR_GPI_SDP1(hw))) {
2946 /* Clear the interrupt */
2947 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1(hw));
2948 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2949 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
2950 ixgbe_service_event_schedule(adapter);
2951 }
2952 }
2953 }
2954
2955 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
2956 {
2957 struct ixgbe_hw *hw = &adapter->hw;
2958
2959 adapter->lsc_int++;
2960 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2961 adapter->link_check_timeout = jiffies;
2962 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2963 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
2964 IXGBE_WRITE_FLUSH(hw);
2965 ixgbe_service_event_schedule(adapter);
2966 }
2967 }
2968
2969 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
2970 u64 qmask)
2971 {
2972 struct ixgbe_hw *hw = &adapter->hw;
2973 u32 mask;
2974
2975 switch (hw->mac.type) {
2976 case ixgbe_mac_82598EB:
2977 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
2978 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
2979 break;
2980 case ixgbe_mac_82599EB:
2981 case ixgbe_mac_X540:
2982 case ixgbe_mac_X550:
2983 case ixgbe_mac_X550EM_x:
2984 case ixgbe_mac_x550em_a:
2985 mask = (qmask & 0xFFFFFFFF);
2986 if (mask)
2987 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
2988 mask = (qmask >> 32);
2989 if (mask)
2990 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
2991 break;
2992 default:
2993 break;
2994 }
2995 /* skip the flush */
2996 }
2997
2998 /**
2999 * ixgbe_irq_enable - Enable default interrupt generation settings
3000 * @adapter: board private structure
3001 * @queues: enable irqs for queues
3002 * @flush: flush register write
3003 **/
3004 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
3005 bool flush)
3006 {
3007 struct ixgbe_hw *hw = &adapter->hw;
3008 u32 mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
3009
3010 /* don't reenable LSC while waiting for link */
3011 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
3012 mask &= ~IXGBE_EIMS_LSC;
3013
3014 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
3015 switch (adapter->hw.mac.type) {
3016 case ixgbe_mac_82599EB:
3017 mask |= IXGBE_EIMS_GPI_SDP0(hw);
3018 break;
3019 case ixgbe_mac_X540:
3020 case ixgbe_mac_X550:
3021 case ixgbe_mac_X550EM_x:
3022 case ixgbe_mac_x550em_a:
3023 mask |= IXGBE_EIMS_TS;
3024 break;
3025 default:
3026 break;
3027 }
3028 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3029 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3030 switch (adapter->hw.mac.type) {
3031 case ixgbe_mac_82599EB:
3032 mask |= IXGBE_EIMS_GPI_SDP1(hw);
3033 mask |= IXGBE_EIMS_GPI_SDP2(hw);
3034 fallthrough;
3035 case ixgbe_mac_X540:
3036 case ixgbe_mac_X550:
3037 case ixgbe_mac_X550EM_x:
3038 case ixgbe_mac_x550em_a:
3039 if (adapter->hw.device_id == IXGBE_DEV_ID_X550EM_X_SFP ||
3040 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP ||
3041 adapter->hw.device_id == IXGBE_DEV_ID_X550EM_A_SFP_N)
3042 mask |= IXGBE_EIMS_GPI_SDP0(&adapter->hw);
3043 if (adapter->hw.phy.type == ixgbe_phy_x550em_ext_t)
3044 mask |= IXGBE_EICR_GPI_SDP0_X540;
3045 mask |= IXGBE_EIMS_ECC;
3046 mask |= IXGBE_EIMS_MAILBOX;
3047 break;
3048 default:
3049 break;
3050 }
3051
3052 if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
3053 !(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
3054 mask |= IXGBE_EIMS_FLOW_DIR;
3055
3056 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
3057 if (queues)
3058 ixgbe_irq_enable_queues(adapter, ~0);
3059 if (flush)
3060 IXGBE_WRITE_FLUSH(&adapter->hw);
3061 }
3062
3063 static irqreturn_t ixgbe_msix_other(int irq, void *data)
3064 {
3065 struct ixgbe_adapter *adapter = data;
3066 struct ixgbe_hw *hw = &adapter->hw;
3067 u32 eicr;
3068
3069 /*
3070 * Workaround for Silicon errata. Use clear-by-write instead
3071 * of clear-by-read. Reading with EICS will return the
3072 * interrupt causes without clearing, which later be done
3073 * with the write to EICR.
3074 */
3075 eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
3076
3077 /* The lower 16bits of the EICR register are for the queue interrupts
3078 * which should be masked here in order to not accidentally clear them if
3079 * the bits are high when ixgbe_msix_other is called. There is a race
3080 * condition otherwise which results in possible performance loss
3081 * especially if the ixgbe_msix_other interrupt is triggering
3082 * consistently (as it would when PPS is turned on for the X540 device)
3083 */
3084 eicr &= 0xFFFF0000;
3085
3086 IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
3087
3088 if (eicr & IXGBE_EICR_LSC)
3089 ixgbe_check_lsc(adapter);
3090
3091 if (eicr & IXGBE_EICR_MAILBOX)
3092 ixgbe_msg_task(adapter);
3093
3094 switch (hw->mac.type) {
3095 case ixgbe_mac_82599EB:
3096 case ixgbe_mac_X540:
3097 case ixgbe_mac_X550:
3098 case ixgbe_mac_X550EM_x:
3099 case ixgbe_mac_x550em_a:
3100 if (hw->phy.type == ixgbe_phy_x550em_ext_t &&
3101 (eicr & IXGBE_EICR_GPI_SDP0_X540)) {
3102 adapter->flags2 |= IXGBE_FLAG2_PHY_INTERRUPT;
3103 ixgbe_service_event_schedule(adapter);
3104 IXGBE_WRITE_REG(hw, IXGBE_EICR,
3105 IXGBE_EICR_GPI_SDP0_X540);
3106 }
3107 if (eicr & IXGBE_EICR_ECC) {
3108 e_info(link, "Received ECC Err, initiating reset\n");
3109 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3110 ixgbe_service_event_schedule(adapter);
3111 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3112 }
3113 /* Handle Flow Director Full threshold interrupt */
3114 if (eicr & IXGBE_EICR_FLOW_DIR) {
3115 int reinit_count = 0;
3116 int i;
3117 for (i = 0; i < adapter->num_tx_queues; i++) {
3118 struct ixgbe_ring *ring = adapter->tx_ring[i];
3119 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
3120 &ring->state))
3121 reinit_count++;
3122 }
3123 if (reinit_count) {
3124 /* no more flow director interrupts until after init */
3125 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
3126 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
3127 ixgbe_service_event_schedule(adapter);
3128 }
3129 }
3130 ixgbe_check_sfp_event(adapter, eicr);
3131 ixgbe_check_overtemp_event(adapter, eicr);
3132 break;
3133 default:
3134 break;
3135 }
3136
3137 ixgbe_check_fan_failure(adapter, eicr);
3138
3139 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3140 ixgbe_ptp_check_pps_event(adapter);
3141
3142 /* re-enable the original interrupt state, no lsc, no queues */
3143 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3144 ixgbe_irq_enable(adapter, false, false);
3145
3146 return IRQ_HANDLED;
3147 }
3148
3149 static irqreturn_t ixgbe_msix_clean_rings(int irq, void *data)
3150 {
3151 struct ixgbe_q_vector *q_vector = data;
3152
3153 /* EIAM disabled interrupts (on this vector) for us */
3154
3155 if (q_vector->rx.ring || q_vector->tx.ring)
3156 napi_schedule_irqoff(&q_vector->napi);
3157
3158 return IRQ_HANDLED;
3159 }
3160
3161 /**
3162 * ixgbe_poll - NAPI Rx polling callback
3163 * @napi: structure for representing this polling device
3164 * @budget: how many packets driver is allowed to clean
3165 *
3166 * This function is used for legacy and MSI, NAPI mode
3167 **/
3168 int ixgbe_poll(struct napi_struct *napi, int budget)
3169 {
3170 struct ixgbe_q_vector *q_vector =
3171 container_of(napi, struct ixgbe_q_vector, napi);
3172 struct ixgbe_adapter *adapter = q_vector->adapter;
3173 struct ixgbe_ring *ring;
3174 int per_ring_budget, work_done = 0;
3175 bool clean_complete = true;
3176
3177 #ifdef CONFIG_IXGBE_DCA
3178 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
3179 ixgbe_update_dca(q_vector);
3180 #endif
3181
3182 ixgbe_for_each_ring(ring, q_vector->tx) {
3183 bool wd = ring->xsk_pool ?
3184 ixgbe_clean_xdp_tx_irq(q_vector, ring, budget) :
3185 ixgbe_clean_tx_irq(q_vector, ring, budget);
3186
3187 if (!wd)
3188 clean_complete = false;
3189 }
3190
3191 /* Exit if we are called by netpoll */
3192 if (budget <= 0)
3193 return budget;
3194
3195 /* attempt to distribute budget to each queue fairly, but don't allow
3196 * the budget to go below 1 because we'll exit polling */
3197 if (q_vector->rx.count > 1)
3198 per_ring_budget = max(budget/q_vector->rx.count, 1);
3199 else
3200 per_ring_budget = budget;
3201
3202 ixgbe_for_each_ring(ring, q_vector->rx) {
3203 int cleaned = ring->xsk_pool ?
3204 ixgbe_clean_rx_irq_zc(q_vector, ring,
3205 per_ring_budget) :
3206 ixgbe_clean_rx_irq(q_vector, ring,
3207 per_ring_budget);
3208
3209 work_done += cleaned;
3210 if (cleaned >= per_ring_budget)
3211 clean_complete = false;
3212 }
3213
3214 /* If all work not completed, return budget and keep polling */
3215 if (!clean_complete)
3216 return budget;
3217
3218 /* all work done, exit the polling mode */
3219 if (likely(napi_complete_done(napi, work_done))) {
3220 if (adapter->rx_itr_setting & 1)
3221 ixgbe_set_itr(q_vector);
3222 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3223 ixgbe_irq_enable_queues(adapter,
3224 BIT_ULL(q_vector->v_idx));
3225 }
3226
3227 return min(work_done, budget - 1);
3228 }
3229
3230 /**
3231 * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
3232 * @adapter: board private structure
3233 *
3234 * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
3235 * interrupts from the kernel.
3236 **/
3237 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
3238 {
3239 struct net_device *netdev = adapter->netdev;
3240 unsigned int ri = 0, ti = 0;
3241 int vector, err;
3242
3243 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3244 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3245 struct msix_entry *entry = &adapter->msix_entries[vector];
3246
3247 if (q_vector->tx.ring && q_vector->rx.ring) {
3248 snprintf(q_vector->name, sizeof(q_vector->name),
3249 "%s-TxRx-%u", netdev->name, ri++);
3250 ti++;
3251 } else if (q_vector->rx.ring) {
3252 snprintf(q_vector->name, sizeof(q_vector->name),
3253 "%s-rx-%u", netdev->name, ri++);
3254 } else if (q_vector->tx.ring) {
3255 snprintf(q_vector->name, sizeof(q_vector->name),
3256 "%s-tx-%u", netdev->name, ti++);
3257 } else {
3258 /* skip this unused q_vector */
3259 continue;
3260 }
3261 err = request_irq(entry->vector, &ixgbe_msix_clean_rings, 0,
3262 q_vector->name, q_vector);
3263 if (err) {
3264 e_err(probe, "request_irq failed for MSIX interrupt "
3265 "Error: %d\n", err);
3266 goto free_queue_irqs;
3267 }
3268 /* If Flow Director is enabled, set interrupt affinity */
3269 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3270 /* assign the mask for this irq */
3271 irq_update_affinity_hint(entry->vector,
3272 &q_vector->affinity_mask);
3273 }
3274 }
3275
3276 err = request_irq(adapter->msix_entries[vector].vector,
3277 ixgbe_msix_other, 0, netdev->name, adapter);
3278 if (err) {
3279 e_err(probe, "request_irq for msix_other failed: %d\n", err);
3280 goto free_queue_irqs;
3281 }
3282
3283 return 0;
3284
3285 free_queue_irqs:
3286 while (vector) {
3287 vector--;
3288 irq_update_affinity_hint(adapter->msix_entries[vector].vector,
3289 NULL);
3290 free_irq(adapter->msix_entries[vector].vector,
3291 adapter->q_vector[vector]);
3292 }
3293 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3294 pci_disable_msix(adapter->pdev);
3295 kfree(adapter->msix_entries);
3296 adapter->msix_entries = NULL;
3297 return err;
3298 }
3299
3300 /**
3301 * ixgbe_intr - legacy mode Interrupt Handler
3302 * @irq: interrupt number
3303 * @data: pointer to a network interface device structure
3304 **/
3305 static irqreturn_t ixgbe_intr(int irq, void *data)
3306 {
3307 struct ixgbe_adapter *adapter = data;
3308 struct ixgbe_hw *hw = &adapter->hw;
3309 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3310 u32 eicr;
3311
3312 /*
3313 * Workaround for silicon errata #26 on 82598. Mask the interrupt
3314 * before the read of EICR.
3315 */
3316 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
3317
3318 /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
3319 * therefore no explicit interrupt disable is necessary */
3320 eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
3321 if (!eicr) {
3322 /*
3323 * shared interrupt alert!
3324 * make sure interrupts are enabled because the read will
3325 * have disabled interrupts due to EIAM
3326 * finish the workaround of silicon errata on 82598. Unmask
3327 * the interrupt that we masked before the EICR read.
3328 */
3329 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3330 ixgbe_irq_enable(adapter, true, true);
3331 return IRQ_NONE; /* Not our interrupt */
3332 }
3333
3334 if (eicr & IXGBE_EICR_LSC)
3335 ixgbe_check_lsc(adapter);
3336
3337 switch (hw->mac.type) {
3338 case ixgbe_mac_82599EB:
3339 ixgbe_check_sfp_event(adapter, eicr);
3340 fallthrough;
3341 case ixgbe_mac_X540:
3342 case ixgbe_mac_X550:
3343 case ixgbe_mac_X550EM_x:
3344 case ixgbe_mac_x550em_a:
3345 if (eicr & IXGBE_EICR_ECC) {
3346 e_info(link, "Received ECC Err, initiating reset\n");
3347 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
3348 ixgbe_service_event_schedule(adapter);
3349 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_ECC);
3350 }
3351 ixgbe_check_overtemp_event(adapter, eicr);
3352 break;
3353 default:
3354 break;
3355 }
3356
3357 ixgbe_check_fan_failure(adapter, eicr);
3358 if (unlikely(eicr & IXGBE_EICR_TIMESYNC))
3359 ixgbe_ptp_check_pps_event(adapter);
3360
3361 /* would disable interrupts here but EIAM disabled it */
3362 napi_schedule_irqoff(&q_vector->napi);
3363
3364 /*
3365 * re-enable link(maybe) and non-queue interrupts, no flush.
3366 * ixgbe_poll will re-enable the queue interrupts
3367 */
3368 if (!test_bit(__IXGBE_DOWN, &adapter->state))
3369 ixgbe_irq_enable(adapter, false, false);
3370
3371 return IRQ_HANDLED;
3372 }
3373
3374 /**
3375 * ixgbe_request_irq - initialize interrupts
3376 * @adapter: board private structure
3377 *
3378 * Attempts to configure interrupts using the best available
3379 * capabilities of the hardware and kernel.
3380 **/
3381 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
3382 {
3383 struct net_device *netdev = adapter->netdev;
3384 int err;
3385
3386 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3387 err = ixgbe_request_msix_irqs(adapter);
3388 else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED)
3389 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
3390 netdev->name, adapter);
3391 else
3392 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
3393 netdev->name, adapter);
3394
3395 if (err)
3396 e_err(probe, "request_irq failed, Error %d\n", err);
3397
3398 return err;
3399 }
3400
3401 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
3402 {
3403 int vector;
3404
3405 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
3406 free_irq(adapter->pdev->irq, adapter);
3407 return;
3408 }
3409
3410 if (!adapter->msix_entries)
3411 return;
3412
3413 for (vector = 0; vector < adapter->num_q_vectors; vector++) {
3414 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
3415 struct msix_entry *entry = &adapter->msix_entries[vector];
3416
3417 /* free only the irqs that were actually requested */
3418 if (!q_vector->rx.ring && !q_vector->tx.ring)
3419 continue;
3420
3421 /* clear the affinity_mask in the IRQ descriptor */
3422 irq_update_affinity_hint(entry->vector, NULL);
3423
3424 free_irq(entry->vector, q_vector);
3425 }
3426
3427 free_irq(adapter->msix_entries[vector].vector, adapter);
3428 }
3429
3430 /**
3431 * ixgbe_irq_disable - Mask off interrupt generation on the NIC
3432 * @adapter: board private structure
3433 **/
3434 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
3435 {
3436 switch (adapter->hw.mac.type) {
3437 case ixgbe_mac_82598EB:
3438 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
3439 break;
3440 case ixgbe_mac_82599EB:
3441 case ixgbe_mac_X540:
3442 case ixgbe_mac_X550:
3443 case ixgbe_mac_X550EM_x:
3444 case ixgbe_mac_x550em_a:
3445 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
3446 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
3447 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
3448 break;
3449 default:
3450 break;
3451 }
3452 IXGBE_WRITE_FLUSH(&adapter->hw);
3453 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3454 int vector;
3455
3456 for (vector = 0; vector < adapter->num_q_vectors; vector++)
3457 synchronize_irq(adapter->msix_entries[vector].vector);
3458
3459 synchronize_irq(adapter->msix_entries[vector++].vector);
3460 } else {
3461 synchronize_irq(adapter->pdev->irq);
3462 }
3463 }
3464
3465 /**
3466 * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
3467 * @adapter: board private structure
3468 *
3469 **/
3470 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
3471 {
3472 struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
3473
3474 ixgbe_write_eitr(q_vector);
3475
3476 ixgbe_set_ivar(adapter, 0, 0, 0);
3477 ixgbe_set_ivar(adapter, 1, 0, 0);
3478
3479 e_info(hw, "Legacy interrupt IVAR setup done\n");
3480 }
3481
3482 /**
3483 * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
3484 * @adapter: board private structure
3485 * @ring: structure containing ring specific data
3486 *
3487 * Configure the Tx descriptor ring after a reset.
3488 **/
3489 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
3490 struct ixgbe_ring *ring)
3491 {
3492 struct ixgbe_hw *hw = &adapter->hw;
3493 u64 tdba = ring->dma;
3494 int wait_loop = 10;
3495 u32 txdctl = IXGBE_TXDCTL_ENABLE;
3496 u8 reg_idx = ring->reg_idx;
3497
3498 ring->xsk_pool = NULL;
3499 if (ring_is_xdp(ring))
3500 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring);
3501
3502 /* disable queue to avoid issues while updating state */
3503 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), 0);
3504 IXGBE_WRITE_FLUSH(hw);
3505
3506 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
3507 (tdba & DMA_BIT_MASK(32)));
3508 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
3509 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
3510 ring->count * sizeof(union ixgbe_adv_tx_desc));
3511 IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
3512 IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
3513 ring->tail = adapter->io_addr + IXGBE_TDT(reg_idx);
3514
3515 /*
3516 * set WTHRESH to encourage burst writeback, it should not be set
3517 * higher than 1 when:
3518 * - ITR is 0 as it could cause false TX hangs
3519 * - ITR is set to > 100k int/sec and BQL is enabled
3520 *
3521 * In order to avoid issues WTHRESH + PTHRESH should always be equal
3522 * to or less than the number of on chip descriptors, which is
3523 * currently 40.
3524 */
3525 if (!ring->q_vector || (ring->q_vector->itr < IXGBE_100K_ITR))
3526 txdctl |= 1u << 16; /* WTHRESH = 1 */
3527 else
3528 txdctl |= 8u << 16; /* WTHRESH = 8 */
3529
3530 /*
3531 * Setting PTHRESH to 32 both improves performance
3532 * and avoids a TX hang with DFP enabled
3533 */
3534 txdctl |= (1u << 8) | /* HTHRESH = 1 */
3535 32; /* PTHRESH = 32 */
3536
3537 /* reinitialize flowdirector state */
3538 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3539 ring->atr_sample_rate = adapter->atr_sample_rate;
3540 ring->atr_count = 0;
3541 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
3542 } else {
3543 ring->atr_sample_rate = 0;
3544 }
3545
3546 /* initialize XPS */
3547 if (!test_and_set_bit(__IXGBE_TX_XPS_INIT_DONE, &ring->state)) {
3548 struct ixgbe_q_vector *q_vector = ring->q_vector;
3549
3550 if (q_vector)
3551 netif_set_xps_queue(ring->netdev,
3552 &q_vector->affinity_mask,
3553 ring->queue_index);
3554 }
3555
3556 clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
3557
3558 /* reinitialize tx_buffer_info */
3559 memset(ring->tx_buffer_info, 0,
3560 sizeof(struct ixgbe_tx_buffer) * ring->count);
3561
3562 /* enable queue */
3563 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
3564
3565 /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3566 if (hw->mac.type == ixgbe_mac_82598EB &&
3567 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3568 return;
3569
3570 /* poll to verify queue is enabled */
3571 do {
3572 usleep_range(1000, 2000);
3573 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
3574 } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
3575 if (!wait_loop)
3576 hw_dbg(hw, "Could not enable Tx Queue %d\n", reg_idx);
3577 }
3578
3579 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
3580 {
3581 struct ixgbe_hw *hw = &adapter->hw;
3582 u32 rttdcs, mtqc;
3583 u8 tcs = adapter->hw_tcs;
3584
3585 if (hw->mac.type == ixgbe_mac_82598EB)
3586 return;
3587
3588 /* disable the arbiter while setting MTQC */
3589 rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
3590 rttdcs |= IXGBE_RTTDCS_ARBDIS;
3591 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3592
3593 /* set transmit pool layout */
3594 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3595 mtqc = IXGBE_MTQC_VT_ENA;
3596 if (tcs > 4)
3597 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3598 else if (tcs > 1)
3599 mtqc |= IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3600 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3601 IXGBE_82599_VMDQ_4Q_MASK)
3602 mtqc |= IXGBE_MTQC_32VF;
3603 else
3604 mtqc |= IXGBE_MTQC_64VF;
3605 } else {
3606 if (tcs > 4) {
3607 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
3608 } else if (tcs > 1) {
3609 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3610 } else {
3611 u8 max_txq = adapter->num_tx_queues +
3612 adapter->num_xdp_queues;
3613 if (max_txq > 63)
3614 mtqc = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
3615 else
3616 mtqc = IXGBE_MTQC_64Q_1PB;
3617 }
3618 }
3619
3620 IXGBE_WRITE_REG(hw, IXGBE_MTQC, mtqc);
3621
3622 /* Enable Security TX Buffer IFG for multiple pb */
3623 if (tcs) {
3624 u32 sectx = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
3625 sectx |= IXGBE_SECTX_DCB;
3626 IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, sectx);
3627 }
3628
3629 /* re-enable the arbiter */
3630 rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
3631 IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
3632 }
3633
3634 /**
3635 * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
3636 * @adapter: board private structure
3637 *
3638 * Configure the Tx unit of the MAC after a reset.
3639 **/
3640 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
3641 {
3642 struct ixgbe_hw *hw = &adapter->hw;
3643 u32 dmatxctl;
3644 u32 i;
3645
3646 ixgbe_setup_mtqc(adapter);
3647
3648 if (hw->mac.type != ixgbe_mac_82598EB) {
3649 /* DMATXCTL.EN must be before Tx queues are enabled */
3650 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
3651 dmatxctl |= IXGBE_DMATXCTL_TE;
3652 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
3653 }
3654
3655 /* Setup the HW Tx Head and Tail descriptor pointers */
3656 for (i = 0; i < adapter->num_tx_queues; i++)
3657 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
3658 for (i = 0; i < adapter->num_xdp_queues; i++)
3659 ixgbe_configure_tx_ring(adapter, adapter->xdp_ring[i]);
3660 }
3661
3662 static void ixgbe_enable_rx_drop(struct ixgbe_adapter *adapter,
3663 struct ixgbe_ring *ring)
3664 {
3665 struct ixgbe_hw *hw = &adapter->hw;
3666 u8 reg_idx = ring->reg_idx;
3667 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3668
3669 srrctl |= IXGBE_SRRCTL_DROP_EN;
3670
3671 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3672 }
3673
3674 static void ixgbe_disable_rx_drop(struct ixgbe_adapter *adapter,
3675 struct ixgbe_ring *ring)
3676 {
3677 struct ixgbe_hw *hw = &adapter->hw;
3678 u8 reg_idx = ring->reg_idx;
3679 u32 srrctl = IXGBE_READ_REG(hw, IXGBE_SRRCTL(reg_idx));
3680
3681 srrctl &= ~IXGBE_SRRCTL_DROP_EN;
3682
3683 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3684 }
3685
3686 #ifdef CONFIG_IXGBE_DCB
3687 void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3688 #else
3689 static void ixgbe_set_rx_drop_en(struct ixgbe_adapter *adapter)
3690 #endif
3691 {
3692 int i;
3693 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
3694
3695 if (adapter->ixgbe_ieee_pfc)
3696 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
3697
3698 /*
3699 * We should set the drop enable bit if:
3700 * SR-IOV is enabled
3701 * or
3702 * Number of Rx queues > 1 and flow control is disabled
3703 *
3704 * This allows us to avoid head of line blocking for security
3705 * and performance reasons.
3706 */
3707 if (adapter->num_vfs || (adapter->num_rx_queues > 1 &&
3708 !(adapter->hw.fc.current_mode & ixgbe_fc_tx_pause) && !pfc_en)) {
3709 for (i = 0; i < adapter->num_rx_queues; i++)
3710 ixgbe_enable_rx_drop(adapter, adapter->rx_ring[i]);
3711 } else {
3712 for (i = 0; i < adapter->num_rx_queues; i++)
3713 ixgbe_disable_rx_drop(adapter, adapter->rx_ring[i]);
3714 }
3715 }
3716
3717 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
3718
3719 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
3720 struct ixgbe_ring *rx_ring)
3721 {
3722 struct ixgbe_hw *hw = &adapter->hw;
3723 u32 srrctl;
3724 u8 reg_idx = rx_ring->reg_idx;
3725
3726 if (hw->mac.type == ixgbe_mac_82598EB) {
3727 u16 mask = adapter->ring_feature[RING_F_RSS].mask;
3728
3729 /*
3730 * if VMDq is not active we must program one srrctl register
3731 * per RSS queue since we have enabled RDRXCTL.MVMEN
3732 */
3733 reg_idx &= mask;
3734 }
3735
3736 /* configure header buffer length, needed for RSC */
3737 srrctl = IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT;
3738
3739 /* configure the packet buffer length */
3740 if (rx_ring->xsk_pool) {
3741 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(rx_ring->xsk_pool);
3742
3743 /* If the MAC support setting RXDCTL.RLPML, the
3744 * SRRCTL[n].BSIZEPKT is set to PAGE_SIZE and
3745 * RXDCTL.RLPML is set to the actual UMEM buffer
3746 * size. If not, then we are stuck with a 1k buffer
3747 * size resolution. In this case frames larger than
3748 * the UMEM buffer size viewed in a 1k resolution will
3749 * be dropped.
3750 */
3751 if (hw->mac.type != ixgbe_mac_82599EB)
3752 srrctl |= PAGE_SIZE >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3753 else
3754 srrctl |= xsk_buf_len >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3755 } else if (test_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state)) {
3756 srrctl |= IXGBE_RXBUFFER_3K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3757 } else {
3758 srrctl |= IXGBE_RXBUFFER_2K >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
3759 }
3760
3761 /* configure descriptor type */
3762 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
3763
3764 IXGBE_WRITE_REG(hw, IXGBE_SRRCTL(reg_idx), srrctl);
3765 }
3766
3767 /**
3768 * ixgbe_rss_indir_tbl_entries - Return RSS indirection table entries
3769 * @adapter: device handle
3770 *
3771 * - 82598/82599/X540: 128
3772 * - X550(non-SRIOV mode): 512
3773 * - X550(SRIOV mode): 64
3774 */
3775 u32 ixgbe_rss_indir_tbl_entries(struct ixgbe_adapter *adapter)
3776 {
3777 if (adapter->hw.mac.type < ixgbe_mac_X550)
3778 return 128;
3779 else if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3780 return 64;
3781 else
3782 return 512;
3783 }
3784
3785 /**
3786 * ixgbe_store_key - Write the RSS key to HW
3787 * @adapter: device handle
3788 *
3789 * Write the RSS key stored in adapter.rss_key to HW.
3790 */
3791 void ixgbe_store_key(struct ixgbe_adapter *adapter)
3792 {
3793 struct ixgbe_hw *hw = &adapter->hw;
3794 int i;
3795
3796 for (i = 0; i < 10; i++)
3797 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), adapter->rss_key[i]);
3798 }
3799
3800 /**
3801 * ixgbe_init_rss_key - Initialize adapter RSS key
3802 * @adapter: device handle
3803 *
3804 * Allocates and initializes the RSS key if it is not allocated.
3805 **/
3806 static inline int ixgbe_init_rss_key(struct ixgbe_adapter *adapter)
3807 {
3808 u32 *rss_key;
3809
3810 if (!adapter->rss_key) {
3811 rss_key = kzalloc(IXGBE_RSS_KEY_SIZE, GFP_KERNEL);
3812 if (unlikely(!rss_key))
3813 return -ENOMEM;
3814
3815 netdev_rss_key_fill(rss_key, IXGBE_RSS_KEY_SIZE);
3816 adapter->rss_key = rss_key;
3817 }
3818
3819 return 0;
3820 }
3821
3822 /**
3823 * ixgbe_store_reta - Write the RETA table to HW
3824 * @adapter: device handle
3825 *
3826 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3827 */
3828 void ixgbe_store_reta(struct ixgbe_adapter *adapter)
3829 {
3830 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3831 struct ixgbe_hw *hw = &adapter->hw;
3832 u32 reta = 0;
3833 u32 indices_multi;
3834 u8 *indir_tbl = adapter->rss_indir_tbl;
3835
3836 /* Fill out the redirection table as follows:
3837 * - 82598: 8 bit wide entries containing pair of 4 bit RSS
3838 * indices.
3839 * - 82599/X540: 8 bit wide entries containing 4 bit RSS index
3840 * - X550: 8 bit wide entries containing 6 bit RSS index
3841 */
3842 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3843 indices_multi = 0x11;
3844 else
3845 indices_multi = 0x1;
3846
3847 /* Write redirection table to HW */
3848 for (i = 0; i < reta_entries; i++) {
3849 reta |= indices_multi * indir_tbl[i] << (i & 0x3) * 8;
3850 if ((i & 3) == 3) {
3851 if (i < 128)
3852 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
3853 else
3854 IXGBE_WRITE_REG(hw, IXGBE_ERETA((i >> 2) - 32),
3855 reta);
3856 reta = 0;
3857 }
3858 }
3859 }
3860
3861 /**
3862 * ixgbe_store_vfreta - Write the RETA table to HW (x550 devices in SRIOV mode)
3863 * @adapter: device handle
3864 *
3865 * Write the RSS redirection table stored in adapter.rss_indir_tbl[] to HW.
3866 */
3867 static void ixgbe_store_vfreta(struct ixgbe_adapter *adapter)
3868 {
3869 u32 i, reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3870 struct ixgbe_hw *hw = &adapter->hw;
3871 u32 vfreta = 0;
3872
3873 /* Write redirection table to HW */
3874 for (i = 0; i < reta_entries; i++) {
3875 u16 pool = adapter->num_rx_pools;
3876
3877 vfreta |= (u32)adapter->rss_indir_tbl[i] << (i & 0x3) * 8;
3878 if ((i & 3) != 3)
3879 continue;
3880
3881 while (pool--)
3882 IXGBE_WRITE_REG(hw,
3883 IXGBE_PFVFRETA(i >> 2, VMDQ_P(pool)),
3884 vfreta);
3885 vfreta = 0;
3886 }
3887 }
3888
3889 static void ixgbe_setup_reta(struct ixgbe_adapter *adapter)
3890 {
3891 u32 i, j;
3892 u32 reta_entries = ixgbe_rss_indir_tbl_entries(adapter);
3893 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3894
3895 /* Program table for at least 4 queues w/ SR-IOV so that VFs can
3896 * make full use of any rings they may have. We will use the
3897 * PSRTYPE register to control how many rings we use within the PF.
3898 */
3899 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) && (rss_i < 4))
3900 rss_i = 4;
3901
3902 /* Fill out hash function seeds */
3903 ixgbe_store_key(adapter);
3904
3905 /* Fill out redirection table */
3906 memset(adapter->rss_indir_tbl, 0, sizeof(adapter->rss_indir_tbl));
3907
3908 for (i = 0, j = 0; i < reta_entries; i++, j++) {
3909 if (j == rss_i)
3910 j = 0;
3911
3912 adapter->rss_indir_tbl[i] = j;
3913 }
3914
3915 ixgbe_store_reta(adapter);
3916 }
3917
3918 static void ixgbe_setup_vfreta(struct ixgbe_adapter *adapter)
3919 {
3920 struct ixgbe_hw *hw = &adapter->hw;
3921 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
3922 int i, j;
3923
3924 /* Fill out hash function seeds */
3925 for (i = 0; i < 10; i++) {
3926 u16 pool = adapter->num_rx_pools;
3927
3928 while (pool--)
3929 IXGBE_WRITE_REG(hw,
3930 IXGBE_PFVFRSSRK(i, VMDQ_P(pool)),
3931 *(adapter->rss_key + i));
3932 }
3933
3934 /* Fill out the redirection table */
3935 for (i = 0, j = 0; i < 64; i++, j++) {
3936 if (j == rss_i)
3937 j = 0;
3938
3939 adapter->rss_indir_tbl[i] = j;
3940 }
3941
3942 ixgbe_store_vfreta(adapter);
3943 }
3944
3945 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
3946 {
3947 struct ixgbe_hw *hw = &adapter->hw;
3948 u32 mrqc = 0, rss_field = 0, vfmrqc = 0;
3949 u32 rxcsum;
3950
3951 /* Disable indicating checksum in descriptor, enables RSS hash */
3952 rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
3953 rxcsum |= IXGBE_RXCSUM_PCSD;
3954 IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
3955
3956 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3957 if (adapter->ring_feature[RING_F_RSS].mask)
3958 mrqc = IXGBE_MRQC_RSSEN;
3959 } else {
3960 u8 tcs = adapter->hw_tcs;
3961
3962 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3963 if (tcs > 4)
3964 mrqc = IXGBE_MRQC_VMDQRT8TCEN; /* 8 TCs */
3965 else if (tcs > 1)
3966 mrqc = IXGBE_MRQC_VMDQRT4TCEN; /* 4 TCs */
3967 else if (adapter->ring_feature[RING_F_VMDQ].mask ==
3968 IXGBE_82599_VMDQ_4Q_MASK)
3969 mrqc = IXGBE_MRQC_VMDQRSS32EN;
3970 else
3971 mrqc = IXGBE_MRQC_VMDQRSS64EN;
3972
3973 /* Enable L3/L4 for Tx Switched packets only for X550,
3974 * older devices do not support this feature
3975 */
3976 if (hw->mac.type >= ixgbe_mac_X550)
3977 mrqc |= IXGBE_MRQC_L3L4TXSWEN;
3978 } else {
3979 if (tcs > 4)
3980 mrqc = IXGBE_MRQC_RTRSS8TCEN;
3981 else if (tcs > 1)
3982 mrqc = IXGBE_MRQC_RTRSS4TCEN;
3983 else
3984 mrqc = IXGBE_MRQC_RSSEN;
3985 }
3986 }
3987
3988 /* Perform hash on these packet types */
3989 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4 |
3990 IXGBE_MRQC_RSS_FIELD_IPV4_TCP |
3991 IXGBE_MRQC_RSS_FIELD_IPV6 |
3992 IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
3993
3994 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV4_UDP)
3995 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV4_UDP;
3996 if (adapter->flags2 & IXGBE_FLAG2_RSS_FIELD_IPV6_UDP)
3997 rss_field |= IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
3998
3999 if ((hw->mac.type >= ixgbe_mac_X550) &&
4000 (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)) {
4001 u16 pool = adapter->num_rx_pools;
4002
4003 /* Enable VF RSS mode */
4004 mrqc |= IXGBE_MRQC_MULTIPLE_RSS;
4005 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4006
4007 /* Setup RSS through the VF registers */
4008 ixgbe_setup_vfreta(adapter);
4009 vfmrqc = IXGBE_MRQC_RSSEN;
4010 vfmrqc |= rss_field;
4011
4012 while (pool--)
4013 IXGBE_WRITE_REG(hw,
4014 IXGBE_PFVFMRQC(VMDQ_P(pool)),
4015 vfmrqc);
4016 } else {
4017 ixgbe_setup_reta(adapter);
4018 mrqc |= rss_field;
4019 IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
4020 }
4021 }
4022
4023 /**
4024 * ixgbe_configure_rscctl - enable RSC for the indicated ring
4025 * @adapter: address of board private structure
4026 * @ring: structure containing ring specific data
4027 **/
4028 static void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
4029 struct ixgbe_ring *ring)
4030 {
4031 struct ixgbe_hw *hw = &adapter->hw;
4032 u32 rscctrl;
4033 u8 reg_idx = ring->reg_idx;
4034
4035 if (!ring_is_rsc_enabled(ring))
4036 return;
4037
4038 rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
4039 rscctrl |= IXGBE_RSCCTL_RSCEN;
4040 /*
4041 * we must limit the number of descriptors so that the
4042 * total size of max desc * buf_len is not greater
4043 * than 65536
4044 */
4045 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
4046 IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
4047 }
4048
4049 #define IXGBE_MAX_RX_DESC_POLL 10
4050 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
4051 struct ixgbe_ring *ring)
4052 {
4053 struct ixgbe_hw *hw = &adapter->hw;
4054 int wait_loop = IXGBE_MAX_RX_DESC_POLL;
4055 u32 rxdctl;
4056 u8 reg_idx = ring->reg_idx;
4057
4058 if (ixgbe_removed(hw->hw_addr))
4059 return;
4060 /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
4061 if (hw->mac.type == ixgbe_mac_82598EB &&
4062 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
4063 return;
4064
4065 do {
4066 usleep_range(1000, 2000);
4067 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4068 } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
4069
4070 if (!wait_loop) {
4071 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
4072 "the polling period\n", reg_idx);
4073 }
4074 }
4075
4076 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
4077 struct ixgbe_ring *ring)
4078 {
4079 struct ixgbe_hw *hw = &adapter->hw;
4080 union ixgbe_adv_rx_desc *rx_desc;
4081 u64 rdba = ring->dma;
4082 u32 rxdctl;
4083 u8 reg_idx = ring->reg_idx;
4084
4085 xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
4086 ring->xsk_pool = ixgbe_xsk_pool(adapter, ring);
4087 if (ring->xsk_pool) {
4088 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4089 MEM_TYPE_XSK_BUFF_POOL,
4090 NULL));
4091 xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
4092 } else {
4093 WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
4094 MEM_TYPE_PAGE_SHARED, NULL));
4095 }
4096
4097 /* disable queue to avoid use of these values while updating state */
4098 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
4099 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
4100
4101 /* write value back with RXDCTL.ENABLE bit cleared */
4102 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4103 IXGBE_WRITE_FLUSH(hw);
4104
4105 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
4106 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
4107 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
4108 ring->count * sizeof(union ixgbe_adv_rx_desc));
4109 /* Force flushing of IXGBE_RDLEN to prevent MDD */
4110 IXGBE_WRITE_FLUSH(hw);
4111
4112 IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
4113 IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
4114 ring->tail = adapter->io_addr + IXGBE_RDT(reg_idx);
4115
4116 ixgbe_configure_srrctl(adapter, ring);
4117 ixgbe_configure_rscctl(adapter, ring);
4118
4119 if (hw->mac.type == ixgbe_mac_82598EB) {
4120 /*
4121 * enable cache line friendly hardware writes:
4122 * PTHRESH=32 descriptors (half the internal cache),
4123 * this also removes ugly rx_no_buffer_count increment
4124 * HTHRESH=4 descriptors (to minimize latency on fetch)
4125 * WTHRESH=8 burst writeback up to two cache lines
4126 */
4127 rxdctl &= ~0x3FFFFF;
4128 rxdctl |= 0x080420;
4129 #if (PAGE_SIZE < 8192)
4130 /* RXDCTL.RLPML does not work on 82599 */
4131 } else if (hw->mac.type != ixgbe_mac_82599EB) {
4132 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4133 IXGBE_RXDCTL_RLPML_EN);
4134
4135 /* Limit the maximum frame size so we don't overrun the skb.
4136 * This can happen in SRIOV mode when the MTU of the VF is
4137 * higher than the MTU of the PF.
4138 */
4139 if (ring_uses_build_skb(ring) &&
4140 !test_bit(__IXGBE_RX_3K_BUFFER, &ring->state))
4141 rxdctl |= IXGBE_MAX_2K_FRAME_BUILD_SKB |
4142 IXGBE_RXDCTL_RLPML_EN;
4143 #endif
4144 }
4145
4146 ring->rx_offset = ixgbe_rx_offset(ring);
4147
4148 if (ring->xsk_pool && hw->mac.type != ixgbe_mac_82599EB) {
4149 u32 xsk_buf_len = xsk_pool_get_rx_frame_size(ring->xsk_pool);
4150
4151 rxdctl &= ~(IXGBE_RXDCTL_RLPMLMASK |
4152 IXGBE_RXDCTL_RLPML_EN);
4153 rxdctl |= xsk_buf_len | IXGBE_RXDCTL_RLPML_EN;
4154
4155 ring->rx_buf_len = xsk_buf_len;
4156 }
4157
4158 /* initialize rx_buffer_info */
4159 memset(ring->rx_buffer_info, 0,
4160 sizeof(struct ixgbe_rx_buffer) * ring->count);
4161
4162 /* initialize Rx descriptor 0 */
4163 rx_desc = IXGBE_RX_DESC(ring, 0);
4164 rx_desc->wb.upper.length = 0;
4165
4166 /* enable receive descriptor ring */
4167 rxdctl |= IXGBE_RXDCTL_ENABLE;
4168 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
4169
4170 ixgbe_rx_desc_queue_enable(adapter, ring);
4171 if (ring->xsk_pool)
4172 ixgbe_alloc_rx_buffers_zc(ring, ixgbe_desc_unused(ring));
4173 else
4174 ixgbe_alloc_rx_buffers(ring, ixgbe_desc_unused(ring));
4175 }
4176
4177 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
4178 {
4179 struct ixgbe_hw *hw = &adapter->hw;
4180 int rss_i = adapter->ring_feature[RING_F_RSS].indices;
4181 u16 pool = adapter->num_rx_pools;
4182
4183 /* PSRTYPE must be initialized in non 82598 adapters */
4184 u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
4185 IXGBE_PSRTYPE_UDPHDR |
4186 IXGBE_PSRTYPE_IPV4HDR |
4187 IXGBE_PSRTYPE_L2HDR |
4188 IXGBE_PSRTYPE_IPV6HDR;
4189
4190 if (hw->mac.type == ixgbe_mac_82598EB)
4191 return;
4192
4193 if (rss_i > 3)
4194 psrtype |= 2u << 29;
4195 else if (rss_i > 1)
4196 psrtype |= 1u << 29;
4197
4198 while (pool--)
4199 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(VMDQ_P(pool)), psrtype);
4200 }
4201
4202 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
4203 {
4204 struct ixgbe_hw *hw = &adapter->hw;
4205 u16 pool = adapter->num_rx_pools;
4206 u32 reg_offset, vf_shift, vmolr;
4207 u32 gcr_ext, vmdctl;
4208 int i;
4209
4210 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
4211 return;
4212
4213 vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
4214 vmdctl |= IXGBE_VMD_CTL_VMDQ_EN;
4215 vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
4216 vmdctl |= VMDQ_P(0) << IXGBE_VT_CTL_POOL_SHIFT;
4217 vmdctl |= IXGBE_VT_CTL_REPLEN;
4218 IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
4219
4220 /* accept untagged packets until a vlan tag is
4221 * specifically set for the VMDQ queue/pool
4222 */
4223 vmolr = IXGBE_VMOLR_AUPE;
4224 while (pool--)
4225 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(pool)), vmolr);
4226
4227 vf_shift = VMDQ_P(0) % 32;
4228 reg_offset = (VMDQ_P(0) >= 32) ? 1 : 0;
4229
4230 /* Enable only the PF's pool for Tx/Rx */
4231 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), GENMASK(31, vf_shift));
4232 IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), reg_offset - 1);
4233 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), GENMASK(31, vf_shift));
4234 IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), reg_offset - 1);
4235 if (adapter->bridge_mode == BRIDGE_MODE_VEB)
4236 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
4237
4238 /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
4239 hw->mac.ops.set_vmdq(hw, 0, VMDQ_P(0));
4240
4241 /* clear VLAN promisc flag so VFTA will be updated if necessary */
4242 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4243
4244 /*
4245 * Set up VF register offsets for selected VT Mode,
4246 * i.e. 32 or 64 VFs for SR-IOV
4247 */
4248 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
4249 case IXGBE_82599_VMDQ_8Q_MASK:
4250 gcr_ext = IXGBE_GCR_EXT_VT_MODE_16;
4251 break;
4252 case IXGBE_82599_VMDQ_4Q_MASK:
4253 gcr_ext = IXGBE_GCR_EXT_VT_MODE_32;
4254 break;
4255 default:
4256 gcr_ext = IXGBE_GCR_EXT_VT_MODE_64;
4257 break;
4258 }
4259
4260 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4261
4262 for (i = 0; i < adapter->num_vfs; i++) {
4263 /* configure spoof checking */
4264 ixgbe_ndo_set_vf_spoofchk(adapter->netdev, i,
4265 adapter->vfinfo[i].spoofchk_enabled);
4266
4267 /* Enable/Disable RSS query feature */
4268 ixgbe_ndo_set_vf_rss_query_en(adapter->netdev, i,
4269 adapter->vfinfo[i].rss_query_enabled);
4270 }
4271 }
4272
4273 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
4274 {
4275 struct ixgbe_hw *hw = &adapter->hw;
4276 struct net_device *netdev = adapter->netdev;
4277 int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
4278 struct ixgbe_ring *rx_ring;
4279 int i;
4280 u32 mhadd, hlreg0;
4281
4282 #ifdef IXGBE_FCOE
4283 /* adjust max frame to be able to do baby jumbo for FCoE */
4284 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
4285 (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
4286 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
4287
4288 #endif /* IXGBE_FCOE */
4289
4290 /* adjust max frame to be at least the size of a standard frame */
4291 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN))
4292 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN);
4293
4294 mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
4295 if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
4296 mhadd &= ~IXGBE_MHADD_MFS_MASK;
4297 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
4298
4299 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
4300 }
4301
4302 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4303 /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
4304 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
4305 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4306
4307 /*
4308 * Setup the HW Rx Head and Tail Descriptor Pointers and
4309 * the Base and Length of the Rx Descriptor Ring
4310 */
4311 for (i = 0; i < adapter->num_rx_queues; i++) {
4312 rx_ring = adapter->rx_ring[i];
4313
4314 clear_ring_rsc_enabled(rx_ring);
4315 clear_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4316 clear_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4317
4318 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4319 set_ring_rsc_enabled(rx_ring);
4320
4321 if (test_bit(__IXGBE_RX_FCOE, &rx_ring->state))
4322 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4323
4324 if (adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
4325 continue;
4326
4327 set_bit(__IXGBE_RX_BUILD_SKB_ENABLED, &rx_ring->state);
4328
4329 #if (PAGE_SIZE < 8192)
4330 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
4331 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4332
4333 if (IXGBE_2K_TOO_SMALL_WITH_PADDING ||
4334 (max_frame > (ETH_FRAME_LEN + ETH_FCS_LEN)))
4335 set_bit(__IXGBE_RX_3K_BUFFER, &rx_ring->state);
4336 #endif
4337 }
4338 }
4339
4340 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
4341 {
4342 struct ixgbe_hw *hw = &adapter->hw;
4343 u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
4344
4345 switch (hw->mac.type) {
4346 case ixgbe_mac_82598EB:
4347 /*
4348 * For VMDq support of different descriptor types or
4349 * buffer sizes through the use of multiple SRRCTL
4350 * registers, RDRXCTL.MVMEN must be set to 1
4351 *
4352 * also, the manual doesn't mention it clearly but DCA hints
4353 * will only use queue 0's tags unless this bit is set. Side
4354 * effects of setting this bit are only that SRRCTL must be
4355 * fully programmed [0..15]
4356 */
4357 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
4358 break;
4359 case ixgbe_mac_X550:
4360 case ixgbe_mac_X550EM_x:
4361 case ixgbe_mac_x550em_a:
4362 if (adapter->num_vfs)
4363 rdrxctl |= IXGBE_RDRXCTL_PSP;
4364 fallthrough;
4365 case ixgbe_mac_82599EB:
4366 case ixgbe_mac_X540:
4367 /* Disable RSC for ACK packets */
4368 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
4369 (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
4370 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
4371 /* hardware requires some bits to be set by default */
4372 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
4373 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
4374 break;
4375 default:
4376 /* We should do nothing since we don't know this hardware */
4377 return;
4378 }
4379
4380 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
4381 }
4382
4383 /**
4384 * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
4385 * @adapter: board private structure
4386 *
4387 * Configure the Rx unit of the MAC after a reset.
4388 **/
4389 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
4390 {
4391 struct ixgbe_hw *hw = &adapter->hw;
4392 int i;
4393 u32 rxctrl, rfctl;
4394
4395 /* disable receives while setting up the descriptors */
4396 hw->mac.ops.disable_rx(hw);
4397
4398 ixgbe_setup_psrtype(adapter);
4399 ixgbe_setup_rdrxctl(adapter);
4400
4401 /* RSC Setup */
4402 rfctl = IXGBE_READ_REG(hw, IXGBE_RFCTL);
4403 rfctl &= ~IXGBE_RFCTL_RSC_DIS;
4404 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
4405 rfctl |= IXGBE_RFCTL_RSC_DIS;
4406
4407 /* disable NFS filtering */
4408 rfctl |= (IXGBE_RFCTL_NFSW_DIS | IXGBE_RFCTL_NFSR_DIS);
4409 IXGBE_WRITE_REG(hw, IXGBE_RFCTL, rfctl);
4410
4411 /* Program registers for the distribution of queues */
4412 ixgbe_setup_mrqc(adapter);
4413
4414 /* set_rx_buffer_len must be called before ring initialization */
4415 ixgbe_set_rx_buffer_len(adapter);
4416
4417 /*
4418 * Setup the HW Rx Head and Tail Descriptor Pointers and
4419 * the Base and Length of the Rx Descriptor Ring
4420 */
4421 for (i = 0; i < adapter->num_rx_queues; i++)
4422 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
4423
4424 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4425 /* disable drop enable for 82598 parts */
4426 if (hw->mac.type == ixgbe_mac_82598EB)
4427 rxctrl |= IXGBE_RXCTRL_DMBYPS;
4428
4429 /* enable all receives */
4430 rxctrl |= IXGBE_RXCTRL_RXEN;
4431 hw->mac.ops.enable_rx_dma(hw, rxctrl);
4432 }
4433
4434 static int ixgbe_vlan_rx_add_vid(struct net_device *netdev,
4435 __be16 proto, u16 vid)
4436 {
4437 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4438 struct ixgbe_hw *hw = &adapter->hw;
4439
4440 /* add VID to filter table */
4441 if (!vid || !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4442 hw->mac.ops.set_vfta(&adapter->hw, vid, VMDQ_P(0), true, !!vid);
4443
4444 set_bit(vid, adapter->active_vlans);
4445
4446 return 0;
4447 }
4448
4449 static int ixgbe_find_vlvf_entry(struct ixgbe_hw *hw, u32 vlan)
4450 {
4451 u32 vlvf;
4452 int idx;
4453
4454 /* short cut the special case */
4455 if (vlan == 0)
4456 return 0;
4457
4458 /* Search for the vlan id in the VLVF entries */
4459 for (idx = IXGBE_VLVF_ENTRIES; --idx;) {
4460 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(idx));
4461 if ((vlvf & VLAN_VID_MASK) == vlan)
4462 break;
4463 }
4464
4465 return idx;
4466 }
4467
4468 void ixgbe_update_pf_promisc_vlvf(struct ixgbe_adapter *adapter, u32 vid)
4469 {
4470 struct ixgbe_hw *hw = &adapter->hw;
4471 u32 bits, word;
4472 int idx;
4473
4474 idx = ixgbe_find_vlvf_entry(hw, vid);
4475 if (!idx)
4476 return;
4477
4478 /* See if any other pools are set for this VLAN filter
4479 * entry other than the PF.
4480 */
4481 word = idx * 2 + (VMDQ_P(0) / 32);
4482 bits = ~BIT(VMDQ_P(0) % 32);
4483 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4484
4485 /* Disable the filter so this falls into the default pool. */
4486 if (!bits && !IXGBE_READ_REG(hw, IXGBE_VLVFB(word ^ 1))) {
4487 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4488 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), 0);
4489 IXGBE_WRITE_REG(hw, IXGBE_VLVF(idx), 0);
4490 }
4491 }
4492
4493 static int ixgbe_vlan_rx_kill_vid(struct net_device *netdev,
4494 __be16 proto, u16 vid)
4495 {
4496 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4497 struct ixgbe_hw *hw = &adapter->hw;
4498
4499 /* remove VID from filter table */
4500 if (vid && !(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4501 hw->mac.ops.set_vfta(hw, vid, VMDQ_P(0), false, true);
4502
4503 clear_bit(vid, adapter->active_vlans);
4504
4505 return 0;
4506 }
4507
4508 /**
4509 * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
4510 * @adapter: driver data
4511 */
4512 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
4513 {
4514 struct ixgbe_hw *hw = &adapter->hw;
4515 u32 vlnctrl;
4516 int i, j;
4517
4518 switch (hw->mac.type) {
4519 case ixgbe_mac_82598EB:
4520 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4521 vlnctrl &= ~IXGBE_VLNCTRL_VME;
4522 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4523 break;
4524 case ixgbe_mac_82599EB:
4525 case ixgbe_mac_X540:
4526 case ixgbe_mac_X550:
4527 case ixgbe_mac_X550EM_x:
4528 case ixgbe_mac_x550em_a:
4529 for (i = 0; i < adapter->num_rx_queues; i++) {
4530 struct ixgbe_ring *ring = adapter->rx_ring[i];
4531
4532 if (!netif_is_ixgbe(ring->netdev))
4533 continue;
4534
4535 j = ring->reg_idx;
4536 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4537 vlnctrl &= ~IXGBE_RXDCTL_VME;
4538 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4539 }
4540 break;
4541 default:
4542 break;
4543 }
4544 }
4545
4546 /**
4547 * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
4548 * @adapter: driver data
4549 */
4550 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
4551 {
4552 struct ixgbe_hw *hw = &adapter->hw;
4553 u32 vlnctrl;
4554 int i, j;
4555
4556 switch (hw->mac.type) {
4557 case ixgbe_mac_82598EB:
4558 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4559 vlnctrl |= IXGBE_VLNCTRL_VME;
4560 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4561 break;
4562 case ixgbe_mac_82599EB:
4563 case ixgbe_mac_X540:
4564 case ixgbe_mac_X550:
4565 case ixgbe_mac_X550EM_x:
4566 case ixgbe_mac_x550em_a:
4567 for (i = 0; i < adapter->num_rx_queues; i++) {
4568 struct ixgbe_ring *ring = adapter->rx_ring[i];
4569
4570 if (!netif_is_ixgbe(ring->netdev))
4571 continue;
4572
4573 j = ring->reg_idx;
4574 vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
4575 vlnctrl |= IXGBE_RXDCTL_VME;
4576 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
4577 }
4578 break;
4579 default:
4580 break;
4581 }
4582 }
4583
4584 static void ixgbe_vlan_promisc_enable(struct ixgbe_adapter *adapter)
4585 {
4586 struct ixgbe_hw *hw = &adapter->hw;
4587 u32 vlnctrl, i;
4588
4589 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4590
4591 if (adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) {
4592 /* For VMDq and SR-IOV we must leave VLAN filtering enabled */
4593 vlnctrl |= IXGBE_VLNCTRL_VFE;
4594 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4595 } else {
4596 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
4597 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4598 return;
4599 }
4600
4601 /* Nothing to do for 82598 */
4602 if (hw->mac.type == ixgbe_mac_82598EB)
4603 return;
4604
4605 /* We are already in VLAN promisc, nothing to do */
4606 if (adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC)
4607 return;
4608
4609 /* Set flag so we don't redo unnecessary work */
4610 adapter->flags2 |= IXGBE_FLAG2_VLAN_PROMISC;
4611
4612 /* Add PF to all active pools */
4613 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4614 u32 reg_offset = IXGBE_VLVFB(i * 2 + VMDQ_P(0) / 32);
4615 u32 vlvfb = IXGBE_READ_REG(hw, reg_offset);
4616
4617 vlvfb |= BIT(VMDQ_P(0) % 32);
4618 IXGBE_WRITE_REG(hw, reg_offset, vlvfb);
4619 }
4620
4621 /* Set all bits in the VLAN filter table array */
4622 for (i = hw->mac.vft_size; i--;)
4623 IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), ~0U);
4624 }
4625
4626 #define VFTA_BLOCK_SIZE 8
4627 static void ixgbe_scrub_vfta(struct ixgbe_adapter *adapter, u32 vfta_offset)
4628 {
4629 struct ixgbe_hw *hw = &adapter->hw;
4630 u32 vfta[VFTA_BLOCK_SIZE] = { 0 };
4631 u32 vid_start = vfta_offset * 32;
4632 u32 vid_end = vid_start + (VFTA_BLOCK_SIZE * 32);
4633 u32 i, vid, word, bits;
4634
4635 for (i = IXGBE_VLVF_ENTRIES; --i;) {
4636 u32 vlvf = IXGBE_READ_REG(hw, IXGBE_VLVF(i));
4637
4638 /* pull VLAN ID from VLVF */
4639 vid = vlvf & VLAN_VID_MASK;
4640
4641 /* only concern outselves with a certain range */
4642 if (vid < vid_start || vid >= vid_end)
4643 continue;
4644
4645 if (vlvf) {
4646 /* record VLAN ID in VFTA */
4647 vfta[(vid - vid_start) / 32] |= BIT(vid % 32);
4648
4649 /* if PF is part of this then continue */
4650 if (test_bit(vid, adapter->active_vlans))
4651 continue;
4652 }
4653
4654 /* remove PF from the pool */
4655 word = i * 2 + VMDQ_P(0) / 32;
4656 bits = ~BIT(VMDQ_P(0) % 32);
4657 bits &= IXGBE_READ_REG(hw, IXGBE_VLVFB(word));
4658 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(word), bits);
4659 }
4660
4661 /* extract values from active_vlans and write back to VFTA */
4662 for (i = VFTA_BLOCK_SIZE; i--;) {
4663 vid = (vfta_offset + i) * 32;
4664 word = vid / BITS_PER_LONG;
4665 bits = vid % BITS_PER_LONG;
4666
4667 vfta[i] |= adapter->active_vlans[word] >> bits;
4668
4669 IXGBE_WRITE_REG(hw, IXGBE_VFTA(vfta_offset + i), vfta[i]);
4670 }
4671 }
4672
4673 static void ixgbe_vlan_promisc_disable(struct ixgbe_adapter *adapter)
4674 {
4675 struct ixgbe_hw *hw = &adapter->hw;
4676 u32 vlnctrl, i;
4677
4678 /* Set VLAN filtering to enabled */
4679 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
4680 vlnctrl |= IXGBE_VLNCTRL_VFE;
4681 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
4682
4683 if (!(adapter->flags & IXGBE_FLAG_VMDQ_ENABLED) ||
4684 hw->mac.type == ixgbe_mac_82598EB)
4685 return;
4686
4687 /* We are not in VLAN promisc, nothing to do */
4688 if (!(adapter->flags2 & IXGBE_FLAG2_VLAN_PROMISC))
4689 return;
4690
4691 /* Set flag so we don't redo unnecessary work */
4692 adapter->flags2 &= ~IXGBE_FLAG2_VLAN_PROMISC;
4693
4694 for (i = 0; i < hw->mac.vft_size; i += VFTA_BLOCK_SIZE)
4695 ixgbe_scrub_vfta(adapter, i);
4696 }
4697
4698 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
4699 {
4700 u16 vid = 1;
4701
4702 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), 0);
4703
4704 for_each_set_bit_from(vid, adapter->active_vlans, VLAN_N_VID)
4705 ixgbe_vlan_rx_add_vid(adapter->netdev, htons(ETH_P_8021Q), vid);
4706 }
4707
4708 /**
4709 * ixgbe_write_mc_addr_list - write multicast addresses to MTA
4710 * @netdev: network interface device structure
4711 *
4712 * Writes multicast address list to the MTA hash table.
4713 * Returns: -ENOMEM on failure
4714 * 0 on no addresses written
4715 * X on writing X addresses to MTA
4716 **/
4717 static int ixgbe_write_mc_addr_list(struct net_device *netdev)
4718 {
4719 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4720 struct ixgbe_hw *hw = &adapter->hw;
4721
4722 if (!netif_running(netdev))
4723 return 0;
4724
4725 if (hw->mac.ops.update_mc_addr_list)
4726 hw->mac.ops.update_mc_addr_list(hw, netdev);
4727 else
4728 return -ENOMEM;
4729
4730 #ifdef CONFIG_PCI_IOV
4731 ixgbe_restore_vf_multicasts(adapter);
4732 #endif
4733
4734 return netdev_mc_count(netdev);
4735 }
4736
4737 #ifdef CONFIG_PCI_IOV
4738 void ixgbe_full_sync_mac_table(struct ixgbe_adapter *adapter)
4739 {
4740 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4741 struct ixgbe_hw *hw = &adapter->hw;
4742 int i;
4743
4744 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4745 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4746
4747 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4748 hw->mac.ops.set_rar(hw, i,
4749 mac_table->addr,
4750 mac_table->pool,
4751 IXGBE_RAH_AV);
4752 else
4753 hw->mac.ops.clear_rar(hw, i);
4754 }
4755 }
4756
4757 #endif
4758 static void ixgbe_sync_mac_table(struct ixgbe_adapter *adapter)
4759 {
4760 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4761 struct ixgbe_hw *hw = &adapter->hw;
4762 int i;
4763
4764 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4765 if (!(mac_table->state & IXGBE_MAC_STATE_MODIFIED))
4766 continue;
4767
4768 mac_table->state &= ~IXGBE_MAC_STATE_MODIFIED;
4769
4770 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4771 hw->mac.ops.set_rar(hw, i,
4772 mac_table->addr,
4773 mac_table->pool,
4774 IXGBE_RAH_AV);
4775 else
4776 hw->mac.ops.clear_rar(hw, i);
4777 }
4778 }
4779
4780 static void ixgbe_flush_sw_mac_table(struct ixgbe_adapter *adapter)
4781 {
4782 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4783 struct ixgbe_hw *hw = &adapter->hw;
4784 int i;
4785
4786 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4787 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4788 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4789 }
4790
4791 ixgbe_sync_mac_table(adapter);
4792 }
4793
4794 static int ixgbe_available_rars(struct ixgbe_adapter *adapter, u16 pool)
4795 {
4796 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4797 struct ixgbe_hw *hw = &adapter->hw;
4798 int i, count = 0;
4799
4800 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4801 /* do not count default RAR as available */
4802 if (mac_table->state & IXGBE_MAC_STATE_DEFAULT)
4803 continue;
4804
4805 /* only count unused and addresses that belong to us */
4806 if (mac_table->state & IXGBE_MAC_STATE_IN_USE) {
4807 if (mac_table->pool != pool)
4808 continue;
4809 }
4810
4811 count++;
4812 }
4813
4814 return count;
4815 }
4816
4817 /* this function destroys the first RAR entry */
4818 static void ixgbe_mac_set_default_filter(struct ixgbe_adapter *adapter)
4819 {
4820 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4821 struct ixgbe_hw *hw = &adapter->hw;
4822
4823 memcpy(&mac_table->addr, hw->mac.addr, ETH_ALEN);
4824 mac_table->pool = VMDQ_P(0);
4825
4826 mac_table->state = IXGBE_MAC_STATE_DEFAULT | IXGBE_MAC_STATE_IN_USE;
4827
4828 hw->mac.ops.set_rar(hw, 0, mac_table->addr, mac_table->pool,
4829 IXGBE_RAH_AV);
4830 }
4831
4832 int ixgbe_add_mac_filter(struct ixgbe_adapter *adapter,
4833 const u8 *addr, u16 pool)
4834 {
4835 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4836 struct ixgbe_hw *hw = &adapter->hw;
4837 int i;
4838
4839 if (is_zero_ether_addr(addr))
4840 return -EINVAL;
4841
4842 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4843 if (mac_table->state & IXGBE_MAC_STATE_IN_USE)
4844 continue;
4845
4846 ether_addr_copy(mac_table->addr, addr);
4847 mac_table->pool = pool;
4848
4849 mac_table->state |= IXGBE_MAC_STATE_MODIFIED |
4850 IXGBE_MAC_STATE_IN_USE;
4851
4852 ixgbe_sync_mac_table(adapter);
4853
4854 return i;
4855 }
4856
4857 return -ENOMEM;
4858 }
4859
4860 int ixgbe_del_mac_filter(struct ixgbe_adapter *adapter,
4861 const u8 *addr, u16 pool)
4862 {
4863 struct ixgbe_mac_addr *mac_table = &adapter->mac_table[0];
4864 struct ixgbe_hw *hw = &adapter->hw;
4865 int i;
4866
4867 if (is_zero_ether_addr(addr))
4868 return -EINVAL;
4869
4870 /* search table for addr, if found clear IN_USE flag and sync */
4871 for (i = 0; i < hw->mac.num_rar_entries; i++, mac_table++) {
4872 /* we can only delete an entry if it is in use */
4873 if (!(mac_table->state & IXGBE_MAC_STATE_IN_USE))
4874 continue;
4875 /* we only care about entries that belong to the given pool */
4876 if (mac_table->pool != pool)
4877 continue;
4878 /* we only care about a specific MAC address */
4879 if (!ether_addr_equal(addr, mac_table->addr))
4880 continue;
4881
4882 mac_table->state |= IXGBE_MAC_STATE_MODIFIED;
4883 mac_table->state &= ~IXGBE_MAC_STATE_IN_USE;
4884
4885 ixgbe_sync_mac_table(adapter);
4886
4887 return 0;
4888 }
4889
4890 return -ENOMEM;
4891 }
4892
4893 static int ixgbe_uc_sync(struct net_device *netdev, const unsigned char *addr)
4894 {
4895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4896 int ret;
4897
4898 ret = ixgbe_add_mac_filter(adapter, addr, VMDQ_P(0));
4899
4900 return min_t(int, ret, 0);
4901 }
4902
4903 static int ixgbe_uc_unsync(struct net_device *netdev, const unsigned char *addr)
4904 {
4905 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4906
4907 ixgbe_del_mac_filter(adapter, addr, VMDQ_P(0));
4908
4909 return 0;
4910 }
4911
4912 /**
4913 * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
4914 * @netdev: network interface device structure
4915 *
4916 * The set_rx_method entry point is called whenever the unicast/multicast
4917 * address list or the network interface flags are updated. This routine is
4918 * responsible for configuring the hardware for proper unicast, multicast and
4919 * promiscuous mode.
4920 **/
4921 void ixgbe_set_rx_mode(struct net_device *netdev)
4922 {
4923 struct ixgbe_adapter *adapter = netdev_priv(netdev);
4924 struct ixgbe_hw *hw = &adapter->hw;
4925 u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
4926 netdev_features_t features = netdev->features;
4927 int count;
4928
4929 /* Check for Promiscuous and All Multicast modes */
4930 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4931
4932 /* set all bits that we expect to always be set */
4933 fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
4934 fctrl |= IXGBE_FCTRL_BAM;
4935 fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
4936 fctrl |= IXGBE_FCTRL_PMCF;
4937
4938 /* clear the bits we are changing the status of */
4939 fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4940 if (netdev->flags & IFF_PROMISC) {
4941 hw->addr_ctrl.user_set_promisc = true;
4942 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
4943 vmolr |= IXGBE_VMOLR_MPE;
4944 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER;
4945 } else {
4946 if (netdev->flags & IFF_ALLMULTI) {
4947 fctrl |= IXGBE_FCTRL_MPE;
4948 vmolr |= IXGBE_VMOLR_MPE;
4949 }
4950 hw->addr_ctrl.user_set_promisc = false;
4951 }
4952
4953 /*
4954 * Write addresses to available RAR registers, if there is not
4955 * sufficient space to store all the addresses then enable
4956 * unicast promiscuous mode
4957 */
4958 if (__dev_uc_sync(netdev, ixgbe_uc_sync, ixgbe_uc_unsync)) {
4959 fctrl |= IXGBE_FCTRL_UPE;
4960 vmolr |= IXGBE_VMOLR_ROPE;
4961 }
4962
4963 /* Write addresses to the MTA, if the attempt fails
4964 * then we should just turn on promiscuous mode so
4965 * that we can at least receive multicast traffic
4966 */
4967 count = ixgbe_write_mc_addr_list(netdev);
4968 if (count < 0) {
4969 fctrl |= IXGBE_FCTRL_MPE;
4970 vmolr |= IXGBE_VMOLR_MPE;
4971 } else if (count) {
4972 vmolr |= IXGBE_VMOLR_ROMPE;
4973 }
4974
4975 if (hw->mac.type != ixgbe_mac_82598EB) {
4976 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(VMDQ_P(0))) &
4977 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
4978 IXGBE_VMOLR_ROPE);
4979 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(VMDQ_P(0)), vmolr);
4980 }
4981
4982 /* This is useful for sniffing bad packets. */
4983 if (features & NETIF_F_RXALL) {
4984 /* UPE and MPE will be handled by normal PROMISC logic
4985 * in e1000e_set_rx_mode */
4986 fctrl |= (IXGBE_FCTRL_SBP | /* Receive bad packets */
4987 IXGBE_FCTRL_BAM | /* RX All Bcast Pkts */
4988 IXGBE_FCTRL_PMCF); /* RX All MAC Ctrl Pkts */
4989
4990 fctrl &= ~(IXGBE_FCTRL_DPF);
4991 /* NOTE: VLAN filtering is disabled by setting PROMISC */
4992 }
4993
4994 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4995
4996 if (features & NETIF_F_HW_VLAN_CTAG_RX)
4997 ixgbe_vlan_strip_enable(adapter);
4998 else
4999 ixgbe_vlan_strip_disable(adapter);
5000
5001 if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
5002 ixgbe_vlan_promisc_disable(adapter);
5003 else
5004 ixgbe_vlan_promisc_enable(adapter);
5005 }
5006
5007 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
5008 {
5009 int q_idx;
5010
5011 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
5012 napi_enable(&adapter->q_vector[q_idx]->napi);
5013 }
5014
5015 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
5016 {
5017 int q_idx;
5018
5019 for (q_idx = 0; q_idx < adapter->num_q_vectors; q_idx++)
5020 napi_disable(&adapter->q_vector[q_idx]->napi);
5021 }
5022
5023 static int ixgbe_udp_tunnel_sync(struct net_device *dev, unsigned int table)
5024 {
5025 struct ixgbe_adapter *adapter = netdev_priv(dev);
5026 struct ixgbe_hw *hw = &adapter->hw;
5027 struct udp_tunnel_info ti;
5028
5029 udp_tunnel_nic_get_port(dev, table, 0, &ti);
5030 if (ti.type == UDP_TUNNEL_TYPE_VXLAN)
5031 adapter->vxlan_port = ti.port;
5032 else
5033 adapter->geneve_port = ti.port;
5034
5035 IXGBE_WRITE_REG(hw, IXGBE_VXLANCTRL,
5036 ntohs(adapter->vxlan_port) |
5037 ntohs(adapter->geneve_port) <<
5038 IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT);
5039 return 0;
5040 }
5041
5042 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550 = {
5043 .sync_table = ixgbe_udp_tunnel_sync,
5044 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5045 .tables = {
5046 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
5047 },
5048 };
5049
5050 static const struct udp_tunnel_nic_info ixgbe_udp_tunnels_x550em_a = {
5051 .sync_table = ixgbe_udp_tunnel_sync,
5052 .flags = UDP_TUNNEL_NIC_INFO_IPV4_ONLY,
5053 .tables = {
5054 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_VXLAN, },
5055 { .n_entries = 1, .tunnel_types = UDP_TUNNEL_TYPE_GENEVE, },
5056 },
5057 };
5058
5059 #ifdef CONFIG_IXGBE_DCB
5060 /**
5061 * ixgbe_configure_dcb - Configure DCB hardware
5062 * @adapter: ixgbe adapter struct
5063 *
5064 * This is called by the driver on open to configure the DCB hardware.
5065 * This is also called by the gennetlink interface when reconfiguring
5066 * the DCB state.
5067 */
5068 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
5069 {
5070 struct ixgbe_hw *hw = &adapter->hw;
5071 int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
5072
5073 if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
5074 if (hw->mac.type == ixgbe_mac_82598EB)
5075 netif_set_tso_max_size(adapter->netdev, 65536);
5076 return;
5077 }
5078
5079 if (hw->mac.type == ixgbe_mac_82598EB)
5080 netif_set_tso_max_size(adapter->netdev, 32768);
5081
5082 #ifdef IXGBE_FCOE
5083 if (adapter->netdev->fcoe_mtu)
5084 max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
5085 #endif
5086
5087 /* reconfigure the hardware */
5088 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
5089 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5090 DCB_TX_CONFIG);
5091 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
5092 DCB_RX_CONFIG);
5093 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
5094 } else if (adapter->ixgbe_ieee_ets && adapter->ixgbe_ieee_pfc) {
5095 ixgbe_dcb_hw_ets(&adapter->hw,
5096 adapter->ixgbe_ieee_ets,
5097 max_frame);
5098 ixgbe_dcb_hw_pfc_config(&adapter->hw,
5099 adapter->ixgbe_ieee_pfc->pfc_en,
5100 adapter->ixgbe_ieee_ets->prio_tc);
5101 }
5102
5103 /* Enable RSS Hash per TC */
5104 if (hw->mac.type != ixgbe_mac_82598EB) {
5105 u32 msb = 0;
5106 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices - 1;
5107
5108 while (rss_i) {
5109 msb++;
5110 rss_i >>= 1;
5111 }
5112
5113 /* write msb to all 8 TCs in one write */
5114 IXGBE_WRITE_REG(hw, IXGBE_RQTC, msb * 0x11111111);
5115 }
5116 }
5117 #endif
5118
5119 /* Additional bittime to account for IXGBE framing */
5120 #define IXGBE_ETH_FRAMING 20
5121
5122 /**
5123 * ixgbe_hpbthresh - calculate high water mark for flow control
5124 *
5125 * @adapter: board private structure to calculate for
5126 * @pb: packet buffer to calculate
5127 */
5128 static int ixgbe_hpbthresh(struct ixgbe_adapter *adapter, int pb)
5129 {
5130 struct ixgbe_hw *hw = &adapter->hw;
5131 struct net_device *dev = adapter->netdev;
5132 int link, tc, kb, marker;
5133 u32 dv_id, rx_pba;
5134
5135 /* Calculate max LAN frame size */
5136 tc = link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + IXGBE_ETH_FRAMING;
5137
5138 #ifdef IXGBE_FCOE
5139 /* FCoE traffic class uses FCOE jumbo frames */
5140 if (dev->fcoe_mtu && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE &&
5141 (pb == ixgbe_fcoe_get_tc(adapter)))
5142 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5143 #endif
5144
5145 /* Calculate delay value for device */
5146 switch (hw->mac.type) {
5147 case ixgbe_mac_X540:
5148 case ixgbe_mac_X550:
5149 case ixgbe_mac_X550EM_x:
5150 case ixgbe_mac_x550em_a:
5151 dv_id = IXGBE_DV_X540(link, tc);
5152 break;
5153 default:
5154 dv_id = IXGBE_DV(link, tc);
5155 break;
5156 }
5157
5158 /* Loopback switch introduces additional latency */
5159 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5160 dv_id += IXGBE_B2BT(tc);
5161
5162 /* Delay value is calculated in bit times convert to KB */
5163 kb = IXGBE_BT2KB(dv_id);
5164 rx_pba = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(pb)) >> 10;
5165
5166 marker = rx_pba - kb;
5167
5168 /* It is possible that the packet buffer is not large enough
5169 * to provide required headroom. In this case throw an error
5170 * to user and a do the best we can.
5171 */
5172 if (marker < 0) {
5173 e_warn(drv, "Packet Buffer(%i) can not provide enough"
5174 "headroom to support flow control."
5175 "Decrease MTU or number of traffic classes\n", pb);
5176 marker = tc + 1;
5177 }
5178
5179 return marker;
5180 }
5181
5182 /**
5183 * ixgbe_lpbthresh - calculate low water mark for flow control
5184 *
5185 * @adapter: board private structure to calculate for
5186 * @pb: packet buffer to calculate
5187 */
5188 static int ixgbe_lpbthresh(struct ixgbe_adapter *adapter, int pb)
5189 {
5190 struct ixgbe_hw *hw = &adapter->hw;
5191 struct net_device *dev = adapter->netdev;
5192 int tc;
5193 u32 dv_id;
5194
5195 /* Calculate max LAN frame size */
5196 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5197
5198 #ifdef IXGBE_FCOE
5199 /* FCoE traffic class uses FCOE jumbo frames */
5200 if (dev->fcoe_mtu && tc < IXGBE_FCOE_JUMBO_FRAME_SIZE &&
5201 (pb == netdev_get_prio_tc_map(dev, adapter->fcoe.up)))
5202 tc = IXGBE_FCOE_JUMBO_FRAME_SIZE;
5203 #endif
5204
5205 /* Calculate delay value for device */
5206 switch (hw->mac.type) {
5207 case ixgbe_mac_X540:
5208 case ixgbe_mac_X550:
5209 case ixgbe_mac_X550EM_x:
5210 case ixgbe_mac_x550em_a:
5211 dv_id = IXGBE_LOW_DV_X540(tc);
5212 break;
5213 default:
5214 dv_id = IXGBE_LOW_DV(tc);
5215 break;
5216 }
5217
5218 /* Delay value is calculated in bit times convert to KB */
5219 return IXGBE_BT2KB(dv_id);
5220 }
5221
5222 /*
5223 * ixgbe_pbthresh_setup - calculate and setup high low water marks
5224 */
5225 static void ixgbe_pbthresh_setup(struct ixgbe_adapter *adapter)
5226 {
5227 struct ixgbe_hw *hw = &adapter->hw;
5228 int num_tc = adapter->hw_tcs;
5229 int i;
5230
5231 if (!num_tc)
5232 num_tc = 1;
5233
5234 for (i = 0; i < num_tc; i++) {
5235 hw->fc.high_water[i] = ixgbe_hpbthresh(adapter, i);
5236 hw->fc.low_water[i] = ixgbe_lpbthresh(adapter, i);
5237
5238 /* Low water marks must not be larger than high water marks */
5239 if (hw->fc.low_water[i] > hw->fc.high_water[i])
5240 hw->fc.low_water[i] = 0;
5241 }
5242
5243 for (; i < MAX_TRAFFIC_CLASS; i++)
5244 hw->fc.high_water[i] = 0;
5245 }
5246
5247 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
5248 {
5249 struct ixgbe_hw *hw = &adapter->hw;
5250 int hdrm;
5251 u8 tc = adapter->hw_tcs;
5252
5253 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5254 adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5255 hdrm = 32 << adapter->fdir_pballoc;
5256 else
5257 hdrm = 0;
5258
5259 hw->mac.ops.set_rxpba(hw, tc, hdrm, PBA_STRATEGY_EQUAL);
5260 ixgbe_pbthresh_setup(adapter);
5261 }
5262
5263 static void ixgbe_fdir_filter_restore(struct ixgbe_adapter *adapter)
5264 {
5265 struct ixgbe_hw *hw = &adapter->hw;
5266 struct hlist_node *node2;
5267 struct ixgbe_fdir_filter *filter;
5268 u8 queue;
5269
5270 spin_lock(&adapter->fdir_perfect_lock);
5271
5272 if (!hlist_empty(&adapter->fdir_filter_list))
5273 ixgbe_fdir_set_input_mask_82599(hw, &adapter->fdir_mask);
5274
5275 hlist_for_each_entry_safe(filter, node2,
5276 &adapter->fdir_filter_list, fdir_node) {
5277 if (filter->action == IXGBE_FDIR_DROP_QUEUE) {
5278 queue = IXGBE_FDIR_DROP_QUEUE;
5279 } else {
5280 u32 ring = ethtool_get_flow_spec_ring(filter->action);
5281 u8 vf = ethtool_get_flow_spec_ring_vf(filter->action);
5282
5283 if (!vf && (ring >= adapter->num_rx_queues)) {
5284 e_err(drv, "FDIR restore failed without VF, ring: %u\n",
5285 ring);
5286 continue;
5287 } else if (vf &&
5288 ((vf > adapter->num_vfs) ||
5289 ring >= adapter->num_rx_queues_per_pool)) {
5290 e_err(drv, "FDIR restore failed with VF, vf: %hhu, ring: %u\n",
5291 vf, ring);
5292 continue;
5293 }
5294
5295 /* Map the ring onto the absolute queue index */
5296 if (!vf)
5297 queue = adapter->rx_ring[ring]->reg_idx;
5298 else
5299 queue = ((vf - 1) *
5300 adapter->num_rx_queues_per_pool) + ring;
5301 }
5302
5303 ixgbe_fdir_write_perfect_filter_82599(hw,
5304 &filter->filter, filter->sw_idx, queue);
5305 }
5306
5307 spin_unlock(&adapter->fdir_perfect_lock);
5308 }
5309
5310 /**
5311 * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
5312 * @rx_ring: ring to free buffers from
5313 **/
5314 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
5315 {
5316 u16 i = rx_ring->next_to_clean;
5317 struct ixgbe_rx_buffer *rx_buffer = &rx_ring->rx_buffer_info[i];
5318
5319 if (rx_ring->xsk_pool) {
5320 ixgbe_xsk_clean_rx_ring(rx_ring);
5321 goto skip_free;
5322 }
5323
5324 /* Free all the Rx ring sk_buffs */
5325 while (i != rx_ring->next_to_alloc) {
5326 if (rx_buffer->skb) {
5327 struct sk_buff *skb = rx_buffer->skb;
5328 if (IXGBE_CB(skb)->page_released)
5329 dma_unmap_page_attrs(rx_ring->dev,
5330 IXGBE_CB(skb)->dma,
5331 ixgbe_rx_pg_size(rx_ring),
5332 DMA_FROM_DEVICE,
5333 IXGBE_RX_DMA_ATTR);
5334 dev_kfree_skb(skb);
5335 }
5336
5337 /* Invalidate cache lines that may have been written to by
5338 * device so that we avoid corrupting memory.
5339 */
5340 dma_sync_single_range_for_cpu(rx_ring->dev,
5341 rx_buffer->dma,
5342 rx_buffer->page_offset,
5343 ixgbe_rx_bufsz(rx_ring),
5344 DMA_FROM_DEVICE);
5345
5346 /* free resources associated with mapping */
5347 dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
5348 ixgbe_rx_pg_size(rx_ring),
5349 DMA_FROM_DEVICE,
5350 IXGBE_RX_DMA_ATTR);
5351 __page_frag_cache_drain(rx_buffer->page,
5352 rx_buffer->pagecnt_bias);
5353
5354 i++;
5355 rx_buffer++;
5356 if (i == rx_ring->count) {
5357 i = 0;
5358 rx_buffer = rx_ring->rx_buffer_info;
5359 }
5360 }
5361
5362 skip_free:
5363 rx_ring->next_to_alloc = 0;
5364 rx_ring->next_to_clean = 0;
5365 rx_ring->next_to_use = 0;
5366 }
5367
5368 static int ixgbe_fwd_ring_up(struct ixgbe_adapter *adapter,
5369 struct ixgbe_fwd_adapter *accel)
5370 {
5371 u16 rss_i = adapter->ring_feature[RING_F_RSS].indices;
5372 int num_tc = netdev_get_num_tc(adapter->netdev);
5373 struct net_device *vdev = accel->netdev;
5374 int i, baseq, err;
5375
5376 baseq = accel->pool * adapter->num_rx_queues_per_pool;
5377 netdev_dbg(vdev, "pool %i:%i queues %i:%i\n",
5378 accel->pool, adapter->num_rx_pools,
5379 baseq, baseq + adapter->num_rx_queues_per_pool);
5380
5381 accel->rx_base_queue = baseq;
5382 accel->tx_base_queue = baseq;
5383
5384 /* record configuration for macvlan interface in vdev */
5385 for (i = 0; i < num_tc; i++)
5386 netdev_bind_sb_channel_queue(adapter->netdev, vdev,
5387 i, rss_i, baseq + (rss_i * i));
5388
5389 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5390 adapter->rx_ring[baseq + i]->netdev = vdev;
5391
5392 /* Guarantee all rings are updated before we update the
5393 * MAC address filter.
5394 */
5395 wmb();
5396
5397 /* ixgbe_add_mac_filter will return an index if it succeeds, so we
5398 * need to only treat it as an error value if it is negative.
5399 */
5400 err = ixgbe_add_mac_filter(adapter, vdev->dev_addr,
5401 VMDQ_P(accel->pool));
5402 if (err >= 0)
5403 return 0;
5404
5405 /* if we cannot add the MAC rule then disable the offload */
5406 macvlan_release_l2fw_offload(vdev);
5407
5408 for (i = 0; i < adapter->num_rx_queues_per_pool; i++)
5409 adapter->rx_ring[baseq + i]->netdev = NULL;
5410
5411 netdev_err(vdev, "L2FW offload disabled due to L2 filter error\n");
5412
5413 /* unbind the queues and drop the subordinate channel config */
5414 netdev_unbind_sb_channel(adapter->netdev, vdev);
5415 netdev_set_sb_channel(vdev, 0);
5416
5417 clear_bit(accel->pool, adapter->fwd_bitmask);
5418 kfree(accel);
5419
5420 return err;
5421 }
5422
5423 static int ixgbe_macvlan_up(struct net_device *vdev,
5424 struct netdev_nested_priv *priv)
5425 {
5426 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
5427 struct ixgbe_fwd_adapter *accel;
5428
5429 if (!netif_is_macvlan(vdev))
5430 return 0;
5431
5432 accel = macvlan_accel_priv(vdev);
5433 if (!accel)
5434 return 0;
5435
5436 ixgbe_fwd_ring_up(adapter, accel);
5437
5438 return 0;
5439 }
5440
5441 static void ixgbe_configure_dfwd(struct ixgbe_adapter *adapter)
5442 {
5443 struct netdev_nested_priv priv = {
5444 .data = (void *)adapter,
5445 };
5446
5447 netdev_walk_all_upper_dev_rcu(adapter->netdev,
5448 ixgbe_macvlan_up, &priv);
5449 }
5450
5451 static void ixgbe_configure(struct ixgbe_adapter *adapter)
5452 {
5453 struct ixgbe_hw *hw = &adapter->hw;
5454
5455 ixgbe_configure_pb(adapter);
5456 #ifdef CONFIG_IXGBE_DCB
5457 ixgbe_configure_dcb(adapter);
5458 #endif
5459 /*
5460 * We must restore virtualization before VLANs or else
5461 * the VLVF registers will not be populated
5462 */
5463 ixgbe_configure_virtualization(adapter);
5464
5465 ixgbe_set_rx_mode(adapter->netdev);
5466 ixgbe_restore_vlan(adapter);
5467 ixgbe_ipsec_restore(adapter);
5468
5469 switch (hw->mac.type) {
5470 case ixgbe_mac_82599EB:
5471 case ixgbe_mac_X540:
5472 hw->mac.ops.disable_rx_buff(hw);
5473 break;
5474 default:
5475 break;
5476 }
5477
5478 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
5479 ixgbe_init_fdir_signature_82599(&adapter->hw,
5480 adapter->fdir_pballoc);
5481 } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
5482 ixgbe_init_fdir_perfect_82599(&adapter->hw,
5483 adapter->fdir_pballoc);
5484 ixgbe_fdir_filter_restore(adapter);
5485 }
5486
5487 switch (hw->mac.type) {
5488 case ixgbe_mac_82599EB:
5489 case ixgbe_mac_X540:
5490 hw->mac.ops.enable_rx_buff(hw);
5491 break;
5492 default:
5493 break;
5494 }
5495
5496 #ifdef CONFIG_IXGBE_DCA
5497 /* configure DCA */
5498 if (adapter->flags & IXGBE_FLAG_DCA_CAPABLE)
5499 ixgbe_setup_dca(adapter);
5500 #endif /* CONFIG_IXGBE_DCA */
5501
5502 #ifdef IXGBE_FCOE
5503 /* configure FCoE L2 filters, redirection table, and Rx control */
5504 ixgbe_configure_fcoe(adapter);
5505
5506 #endif /* IXGBE_FCOE */
5507 ixgbe_configure_tx(adapter);
5508 ixgbe_configure_rx(adapter);
5509 ixgbe_configure_dfwd(adapter);
5510 }
5511
5512 /**
5513 * ixgbe_sfp_link_config - set up SFP+ link
5514 * @adapter: pointer to private adapter struct
5515 **/
5516 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
5517 {
5518 /*
5519 * We are assuming the worst case scenario here, and that
5520 * is that an SFP was inserted/removed after the reset
5521 * but before SFP detection was enabled. As such the best
5522 * solution is to just start searching as soon as we start
5523 */
5524 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
5525 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
5526
5527 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
5528 adapter->sfp_poll_time = 0;
5529 }
5530
5531 /**
5532 * ixgbe_non_sfp_link_config - set up non-SFP+ link
5533 * @hw: pointer to private hardware struct
5534 *
5535 * Returns 0 on success, negative on failure
5536 **/
5537 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
5538 {
5539 u32 speed;
5540 bool autoneg, link_up = false;
5541 int ret = -EIO;
5542
5543 if (hw->mac.ops.check_link)
5544 ret = hw->mac.ops.check_link(hw, &speed, &link_up, false);
5545
5546 if (ret)
5547 return ret;
5548
5549 speed = hw->phy.autoneg_advertised;
5550 if (!speed && hw->mac.ops.get_link_capabilities) {
5551 ret = hw->mac.ops.get_link_capabilities(hw, &speed,
5552 &autoneg);
5553 /* remove NBASE-T speeds from default autonegotiation
5554 * to accommodate broken network switches in the field
5555 * which cannot cope with advertised NBASE-T speeds
5556 */
5557 speed &= ~(IXGBE_LINK_SPEED_5GB_FULL |
5558 IXGBE_LINK_SPEED_2_5GB_FULL);
5559 }
5560
5561 if (ret)
5562 return ret;
5563
5564 if (hw->mac.ops.setup_link)
5565 ret = hw->mac.ops.setup_link(hw, speed, link_up);
5566
5567 return ret;
5568 }
5569
5570 /**
5571 * ixgbe_clear_vf_stats_counters - Clear out VF stats after reset
5572 * @adapter: board private structure
5573 *
5574 * On a reset we need to clear out the VF stats or accounting gets
5575 * messed up because they're not clear on read.
5576 **/
5577 static void ixgbe_clear_vf_stats_counters(struct ixgbe_adapter *adapter)
5578 {
5579 struct ixgbe_hw *hw = &adapter->hw;
5580 int i;
5581
5582 for (i = 0; i < adapter->num_vfs; i++) {
5583 adapter->vfinfo[i].last_vfstats.gprc =
5584 IXGBE_READ_REG(hw, IXGBE_PVFGPRC(i));
5585 adapter->vfinfo[i].saved_rst_vfstats.gprc +=
5586 adapter->vfinfo[i].vfstats.gprc;
5587 adapter->vfinfo[i].vfstats.gprc = 0;
5588 adapter->vfinfo[i].last_vfstats.gptc =
5589 IXGBE_READ_REG(hw, IXGBE_PVFGPTC(i));
5590 adapter->vfinfo[i].saved_rst_vfstats.gptc +=
5591 adapter->vfinfo[i].vfstats.gptc;
5592 adapter->vfinfo[i].vfstats.gptc = 0;
5593 adapter->vfinfo[i].last_vfstats.gorc =
5594 IXGBE_READ_REG(hw, IXGBE_PVFGORC_LSB(i));
5595 adapter->vfinfo[i].saved_rst_vfstats.gorc +=
5596 adapter->vfinfo[i].vfstats.gorc;
5597 adapter->vfinfo[i].vfstats.gorc = 0;
5598 adapter->vfinfo[i].last_vfstats.gotc =
5599 IXGBE_READ_REG(hw, IXGBE_PVFGOTC_LSB(i));
5600 adapter->vfinfo[i].saved_rst_vfstats.gotc +=
5601 adapter->vfinfo[i].vfstats.gotc;
5602 adapter->vfinfo[i].vfstats.gotc = 0;
5603 adapter->vfinfo[i].last_vfstats.mprc =
5604 IXGBE_READ_REG(hw, IXGBE_PVFMPRC(i));
5605 adapter->vfinfo[i].saved_rst_vfstats.mprc +=
5606 adapter->vfinfo[i].vfstats.mprc;
5607 adapter->vfinfo[i].vfstats.mprc = 0;
5608 }
5609 }
5610
5611 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
5612 {
5613 struct ixgbe_hw *hw = &adapter->hw;
5614 u32 gpie = 0;
5615
5616 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5617 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
5618 IXGBE_GPIE_OCD;
5619 gpie |= IXGBE_GPIE_EIAME;
5620 /*
5621 * use EIAM to auto-mask when MSI-X interrupt is asserted
5622 * this saves a register write for every interrupt
5623 */
5624 switch (hw->mac.type) {
5625 case ixgbe_mac_82598EB:
5626 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5627 break;
5628 case ixgbe_mac_82599EB:
5629 case ixgbe_mac_X540:
5630 case ixgbe_mac_X550:
5631 case ixgbe_mac_X550EM_x:
5632 case ixgbe_mac_x550em_a:
5633 default:
5634 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
5635 IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
5636 break;
5637 }
5638 } else {
5639 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
5640 * specifically only auto mask tx and rx interrupts */
5641 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
5642 }
5643
5644 /* XXX: to interrupt immediately for EICS writes, enable this */
5645 /* gpie |= IXGBE_GPIE_EIMEN; */
5646
5647 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
5648 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
5649
5650 switch (adapter->ring_feature[RING_F_VMDQ].mask) {
5651 case IXGBE_82599_VMDQ_8Q_MASK:
5652 gpie |= IXGBE_GPIE_VTMODE_16;
5653 break;
5654 case IXGBE_82599_VMDQ_4Q_MASK:
5655 gpie |= IXGBE_GPIE_VTMODE_32;
5656 break;
5657 default:
5658 gpie |= IXGBE_GPIE_VTMODE_64;
5659 break;
5660 }
5661 }
5662
5663 /* Enable Thermal over heat sensor interrupt */
5664 if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) {
5665 switch (adapter->hw.mac.type) {
5666 case ixgbe_mac_82599EB:
5667 gpie |= IXGBE_SDP0_GPIEN_8259X;
5668 break;
5669 default:
5670 break;
5671 }
5672 }
5673
5674 /* Enable fan failure interrupt */
5675 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
5676 gpie |= IXGBE_SDP1_GPIEN(hw);
5677
5678 switch (hw->mac.type) {
5679 case ixgbe_mac_82599EB:
5680 gpie |= IXGBE_SDP1_GPIEN_8259X | IXGBE_SDP2_GPIEN_8259X;
5681 break;
5682 case ixgbe_mac_X550EM_x:
5683 case ixgbe_mac_x550em_a:
5684 gpie |= IXGBE_SDP0_GPIEN_X540;
5685 break;
5686 default:
5687 break;
5688 }
5689
5690 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
5691 }
5692
5693 static void ixgbe_up_complete(struct ixgbe_adapter *adapter)
5694 {
5695 struct ixgbe_hw *hw = &adapter->hw;
5696 int err;
5697 u32 ctrl_ext;
5698
5699 ixgbe_get_hw_control(adapter);
5700 ixgbe_setup_gpie(adapter);
5701
5702 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
5703 ixgbe_configure_msix(adapter);
5704 else
5705 ixgbe_configure_msi_and_legacy(adapter);
5706
5707 /* enable the optics for 82599 SFP+ fiber */
5708 if (hw->mac.ops.enable_tx_laser)
5709 hw->mac.ops.enable_tx_laser(hw);
5710
5711 if (hw->phy.ops.set_phy_power)
5712 hw->phy.ops.set_phy_power(hw, true);
5713
5714 smp_mb__before_atomic();
5715 clear_bit(__IXGBE_DOWN, &adapter->state);
5716 ixgbe_napi_enable_all(adapter);
5717
5718 if (ixgbe_is_sfp(hw)) {
5719 ixgbe_sfp_link_config(adapter);
5720 } else {
5721 err = ixgbe_non_sfp_link_config(hw);
5722 if (err)
5723 e_err(probe, "link_config FAILED %d\n", err);
5724 }
5725
5726 /* clear any pending interrupts, may auto mask */
5727 IXGBE_READ_REG(hw, IXGBE_EICR);
5728 ixgbe_irq_enable(adapter, true, true);
5729
5730 /*
5731 * If this adapter has a fan, check to see if we had a failure
5732 * before we enabled the interrupt.
5733 */
5734 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5735 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5736 if (esdp & IXGBE_ESDP_SDP1)
5737 e_crit(drv, "Fan has stopped, replace the adapter\n");
5738 }
5739
5740 /* bring the link up in the watchdog, this could race with our first
5741 * link up interrupt but shouldn't be a problem */
5742 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
5743 adapter->link_check_timeout = jiffies;
5744 mod_timer(&adapter->service_timer, jiffies);
5745
5746 ixgbe_clear_vf_stats_counters(adapter);
5747 /* Set PF Reset Done bit so PF/VF Mail Ops can work */
5748 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
5749 ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
5750 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
5751
5752 /* update setting rx tx for all active vfs */
5753 ixgbe_set_all_vfs(adapter);
5754 }
5755
5756 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
5757 {
5758 /* put off any impending NetWatchDogTimeout */
5759 netif_trans_update(adapter->netdev);
5760
5761 while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
5762 usleep_range(1000, 2000);
5763 if (adapter->hw.phy.type == ixgbe_phy_fw)
5764 ixgbe_watchdog_link_is_down(adapter);
5765 ixgbe_down(adapter);
5766 /*
5767 * If SR-IOV enabled then wait a bit before bringing the adapter
5768 * back up to give the VFs time to respond to the reset. The
5769 * two second wait is based upon the watchdog timer cycle in
5770 * the VF driver.
5771 */
5772 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
5773 msleep(2000);
5774 ixgbe_up(adapter);
5775 clear_bit(__IXGBE_RESETTING, &adapter->state);
5776 }
5777
5778 void ixgbe_up(struct ixgbe_adapter *adapter)
5779 {
5780 /* hardware has been reset, we need to reload some things */
5781 ixgbe_configure(adapter);
5782
5783 ixgbe_up_complete(adapter);
5784 }
5785
5786 static unsigned long ixgbe_get_completion_timeout(struct ixgbe_adapter *adapter)
5787 {
5788 u16 devctl2;
5789
5790 pcie_capability_read_word(adapter->pdev, PCI_EXP_DEVCTL2, &devctl2);
5791
5792 switch (devctl2 & IXGBE_PCIDEVCTRL2_TIMEO_MASK) {
5793 case IXGBE_PCIDEVCTRL2_17_34s:
5794 case IXGBE_PCIDEVCTRL2_4_8s:
5795 /* For now we cap the upper limit on delay to 2 seconds
5796 * as we end up going up to 34 seconds of delay in worst
5797 * case timeout value.
5798 */
5799 case IXGBE_PCIDEVCTRL2_1_2s:
5800 return 2000000ul; /* 2.0 s */
5801 case IXGBE_PCIDEVCTRL2_260_520ms:
5802 return 520000ul; /* 520 ms */
5803 case IXGBE_PCIDEVCTRL2_65_130ms:
5804 return 130000ul; /* 130 ms */
5805 case IXGBE_PCIDEVCTRL2_16_32ms:
5806 return 32000ul; /* 32 ms */
5807 case IXGBE_PCIDEVCTRL2_1_2ms:
5808 return 2000ul; /* 2 ms */
5809 case IXGBE_PCIDEVCTRL2_50_100us:
5810 return 100ul; /* 100 us */
5811 case IXGBE_PCIDEVCTRL2_16_32ms_def:
5812 return 32000ul; /* 32 ms */
5813 default:
5814 break;
5815 }
5816
5817 /* We shouldn't need to hit this path, but just in case default as
5818 * though completion timeout is not supported and support 32ms.
5819 */
5820 return 32000ul;
5821 }
5822
5823 void ixgbe_disable_rx(struct ixgbe_adapter *adapter)
5824 {
5825 unsigned long wait_delay, delay_interval;
5826 struct ixgbe_hw *hw = &adapter->hw;
5827 int i, wait_loop;
5828 u32 rxdctl;
5829
5830 /* disable receives */
5831 hw->mac.ops.disable_rx(hw);
5832
5833 if (ixgbe_removed(hw->hw_addr))
5834 return;
5835
5836 /* disable all enabled Rx queues */
5837 for (i = 0; i < adapter->num_rx_queues; i++) {
5838 struct ixgbe_ring *ring = adapter->rx_ring[i];
5839 u8 reg_idx = ring->reg_idx;
5840
5841 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5842 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
5843 rxdctl |= IXGBE_RXDCTL_SWFLSH;
5844
5845 /* write value back with RXDCTL.ENABLE bit cleared */
5846 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
5847 }
5848
5849 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
5850 if (hw->mac.type == ixgbe_mac_82598EB &&
5851 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5852 return;
5853
5854 /* Determine our minimum delay interval. We will increase this value
5855 * with each subsequent test. This way if the device returns quickly
5856 * we should spend as little time as possible waiting, however as
5857 * the time increases we will wait for larger periods of time.
5858 *
5859 * The trick here is that we increase the interval using the
5860 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5861 * of that wait is that it totals up to 100x whatever interval we
5862 * choose. Since our minimum wait is 100us we can just divide the
5863 * total timeout by 100 to get our minimum delay interval.
5864 */
5865 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5866
5867 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5868 wait_delay = delay_interval;
5869
5870 while (wait_loop--) {
5871 usleep_range(wait_delay, wait_delay + 10);
5872 wait_delay += delay_interval * 2;
5873 rxdctl = 0;
5874
5875 /* OR together the reading of all the active RXDCTL registers,
5876 * and then test the result. We need the disable to complete
5877 * before we start freeing the memory and invalidating the
5878 * DMA mappings.
5879 */
5880 for (i = 0; i < adapter->num_rx_queues; i++) {
5881 struct ixgbe_ring *ring = adapter->rx_ring[i];
5882 u8 reg_idx = ring->reg_idx;
5883
5884 rxdctl |= IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
5885 }
5886
5887 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
5888 return;
5889 }
5890
5891 e_err(drv,
5892 "RXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5893 }
5894
5895 void ixgbe_disable_tx(struct ixgbe_adapter *adapter)
5896 {
5897 unsigned long wait_delay, delay_interval;
5898 struct ixgbe_hw *hw = &adapter->hw;
5899 int i, wait_loop;
5900 u32 txdctl;
5901
5902 if (ixgbe_removed(hw->hw_addr))
5903 return;
5904
5905 /* disable all enabled Tx queues */
5906 for (i = 0; i < adapter->num_tx_queues; i++) {
5907 struct ixgbe_ring *ring = adapter->tx_ring[i];
5908 u8 reg_idx = ring->reg_idx;
5909
5910 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5911 }
5912
5913 /* disable all enabled XDP Tx queues */
5914 for (i = 0; i < adapter->num_xdp_queues; i++) {
5915 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5916 u8 reg_idx = ring->reg_idx;
5917
5918 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
5919 }
5920
5921 /* If the link is not up there shouldn't be much in the way of
5922 * pending transactions. Those that are left will be flushed out
5923 * when the reset logic goes through the flush sequence to clean out
5924 * the pending Tx transactions.
5925 */
5926 if (!(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
5927 goto dma_engine_disable;
5928
5929 /* Determine our minimum delay interval. We will increase this value
5930 * with each subsequent test. This way if the device returns quickly
5931 * we should spend as little time as possible waiting, however as
5932 * the time increases we will wait for larger periods of time.
5933 *
5934 * The trick here is that we increase the interval using the
5935 * following pattern: 1x 3x 5x 7x 9x 11x 13x 15x 17x 19x. The result
5936 * of that wait is that it totals up to 100x whatever interval we
5937 * choose. Since our minimum wait is 100us we can just divide the
5938 * total timeout by 100 to get our minimum delay interval.
5939 */
5940 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
5941
5942 wait_loop = IXGBE_MAX_RX_DESC_POLL;
5943 wait_delay = delay_interval;
5944
5945 while (wait_loop--) {
5946 usleep_range(wait_delay, wait_delay + 10);
5947 wait_delay += delay_interval * 2;
5948 txdctl = 0;
5949
5950 /* OR together the reading of all the active TXDCTL registers,
5951 * and then test the result. We need the disable to complete
5952 * before we start freeing the memory and invalidating the
5953 * DMA mappings.
5954 */
5955 for (i = 0; i < adapter->num_tx_queues; i++) {
5956 struct ixgbe_ring *ring = adapter->tx_ring[i];
5957 u8 reg_idx = ring->reg_idx;
5958
5959 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5960 }
5961 for (i = 0; i < adapter->num_xdp_queues; i++) {
5962 struct ixgbe_ring *ring = adapter->xdp_ring[i];
5963 u8 reg_idx = ring->reg_idx;
5964
5965 txdctl |= IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
5966 }
5967
5968 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
5969 goto dma_engine_disable;
5970 }
5971
5972 e_err(drv,
5973 "TXDCTL.ENABLE for one or more queues not cleared within the polling period\n");
5974
5975 dma_engine_disable:
5976 /* Disable the Tx DMA engine on 82599 and later MAC */
5977 switch (hw->mac.type) {
5978 case ixgbe_mac_82599EB:
5979 case ixgbe_mac_X540:
5980 case ixgbe_mac_X550:
5981 case ixgbe_mac_X550EM_x:
5982 case ixgbe_mac_x550em_a:
5983 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
5984 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
5985 ~IXGBE_DMATXCTL_TE));
5986 fallthrough;
5987 default:
5988 break;
5989 }
5990 }
5991
5992 void ixgbe_reset(struct ixgbe_adapter *adapter)
5993 {
5994 struct ixgbe_hw *hw = &adapter->hw;
5995 struct net_device *netdev = adapter->netdev;
5996 int err;
5997
5998 if (ixgbe_removed(hw->hw_addr))
5999 return;
6000 /* lock SFP init bit to prevent race conditions with the watchdog */
6001 while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6002 usleep_range(1000, 2000);
6003
6004 /* clear all SFP and link config related flags while holding SFP_INIT */
6005 adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
6006 IXGBE_FLAG2_SFP_NEEDS_RESET);
6007 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6008
6009 err = hw->mac.ops.init_hw(hw);
6010 switch (err) {
6011 case 0:
6012 case -ENOENT:
6013 case -EOPNOTSUPP:
6014 break;
6015 case -EALREADY:
6016 e_dev_err("primary disable timed out\n");
6017 break;
6018 case -EACCES:
6019 /* We are running on a pre-production device, log a warning */
6020 e_dev_warn("This device is a pre-production adapter/LOM. "
6021 "Please be aware there may be issues associated with "
6022 "your hardware. If you are experiencing problems "
6023 "please contact your Intel or hardware "
6024 "representative who provided you with this "
6025 "hardware.\n");
6026 break;
6027 default:
6028 e_dev_err("Hardware Error: %d\n", err);
6029 }
6030
6031 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6032
6033 /* flush entries out of MAC table */
6034 ixgbe_flush_sw_mac_table(adapter);
6035 __dev_uc_unsync(netdev, NULL);
6036
6037 /* do not flush user set addresses */
6038 ixgbe_mac_set_default_filter(adapter);
6039
6040 /* update SAN MAC vmdq pool selection */
6041 if (hw->mac.san_mac_rar_index)
6042 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
6043
6044 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
6045 ixgbe_ptp_reset(adapter);
6046
6047 if (hw->phy.ops.set_phy_power) {
6048 if (!netif_running(adapter->netdev) && !adapter->wol)
6049 hw->phy.ops.set_phy_power(hw, false);
6050 else
6051 hw->phy.ops.set_phy_power(hw, true);
6052 }
6053 }
6054
6055 /**
6056 * ixgbe_clean_tx_ring - Free Tx Buffers
6057 * @tx_ring: ring to be cleaned
6058 **/
6059 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
6060 {
6061 u16 i = tx_ring->next_to_clean;
6062 struct ixgbe_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
6063
6064 if (tx_ring->xsk_pool) {
6065 ixgbe_xsk_clean_tx_ring(tx_ring);
6066 goto out;
6067 }
6068
6069 while (i != tx_ring->next_to_use) {
6070 union ixgbe_adv_tx_desc *eop_desc, *tx_desc;
6071
6072 /* Free all the Tx ring sk_buffs */
6073 if (ring_is_xdp(tx_ring))
6074 xdp_return_frame(tx_buffer->xdpf);
6075 else
6076 dev_kfree_skb_any(tx_buffer->skb);
6077
6078 /* unmap skb header data */
6079 dma_unmap_single(tx_ring->dev,
6080 dma_unmap_addr(tx_buffer, dma),
6081 dma_unmap_len(tx_buffer, len),
6082 DMA_TO_DEVICE);
6083
6084 /* check for eop_desc to determine the end of the packet */
6085 eop_desc = tx_buffer->next_to_watch;
6086 tx_desc = IXGBE_TX_DESC(tx_ring, i);
6087
6088 /* unmap remaining buffers */
6089 while (tx_desc != eop_desc) {
6090 tx_buffer++;
6091 tx_desc++;
6092 i++;
6093 if (unlikely(i == tx_ring->count)) {
6094 i = 0;
6095 tx_buffer = tx_ring->tx_buffer_info;
6096 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
6097 }
6098
6099 /* unmap any remaining paged data */
6100 if (dma_unmap_len(tx_buffer, len))
6101 dma_unmap_page(tx_ring->dev,
6102 dma_unmap_addr(tx_buffer, dma),
6103 dma_unmap_len(tx_buffer, len),
6104 DMA_TO_DEVICE);
6105 }
6106
6107 /* move us one more past the eop_desc for start of next pkt */
6108 tx_buffer++;
6109 i++;
6110 if (unlikely(i == tx_ring->count)) {
6111 i = 0;
6112 tx_buffer = tx_ring->tx_buffer_info;
6113 }
6114 }
6115
6116 /* reset BQL for queue */
6117 if (!ring_is_xdp(tx_ring))
6118 netdev_tx_reset_queue(txring_txq(tx_ring));
6119
6120 out:
6121 /* reset next_to_use and next_to_clean */
6122 tx_ring->next_to_use = 0;
6123 tx_ring->next_to_clean = 0;
6124 }
6125
6126 /**
6127 * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
6128 * @adapter: board private structure
6129 **/
6130 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
6131 {
6132 int i;
6133
6134 for (i = 0; i < adapter->num_rx_queues; i++)
6135 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
6136 }
6137
6138 /**
6139 * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
6140 * @adapter: board private structure
6141 **/
6142 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
6143 {
6144 int i;
6145
6146 for (i = 0; i < adapter->num_tx_queues; i++)
6147 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
6148 for (i = 0; i < adapter->num_xdp_queues; i++)
6149 ixgbe_clean_tx_ring(adapter->xdp_ring[i]);
6150 }
6151
6152 static void ixgbe_fdir_filter_exit(struct ixgbe_adapter *adapter)
6153 {
6154 struct hlist_node *node2;
6155 struct ixgbe_fdir_filter *filter;
6156
6157 spin_lock(&adapter->fdir_perfect_lock);
6158
6159 hlist_for_each_entry_safe(filter, node2,
6160 &adapter->fdir_filter_list, fdir_node) {
6161 hlist_del(&filter->fdir_node);
6162 kfree(filter);
6163 }
6164 adapter->fdir_filter_count = 0;
6165
6166 spin_unlock(&adapter->fdir_perfect_lock);
6167 }
6168
6169 void ixgbe_down(struct ixgbe_adapter *adapter)
6170 {
6171 struct net_device *netdev = adapter->netdev;
6172 struct ixgbe_hw *hw = &adapter->hw;
6173 int i;
6174
6175 /* signal that we are down to the interrupt handler */
6176 if (test_and_set_bit(__IXGBE_DOWN, &adapter->state))
6177 return; /* do nothing if already down */
6178
6179 /* Shut off incoming Tx traffic */
6180 netif_tx_stop_all_queues(netdev);
6181
6182 /* call carrier off first to avoid false dev_watchdog timeouts */
6183 netif_carrier_off(netdev);
6184 netif_tx_disable(netdev);
6185
6186 /* Disable Rx */
6187 ixgbe_disable_rx(adapter);
6188
6189 /* synchronize_rcu() needed for pending XDP buffers to drain */
6190 if (adapter->xdp_ring[0])
6191 synchronize_rcu();
6192
6193 ixgbe_irq_disable(adapter);
6194
6195 ixgbe_napi_disable_all(adapter);
6196
6197 clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
6198 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
6199 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
6200
6201 del_timer_sync(&adapter->service_timer);
6202
6203 if (adapter->num_vfs) {
6204 /* Clear EITR Select mapping */
6205 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
6206
6207 /* Mark all the VFs as inactive */
6208 for (i = 0 ; i < adapter->num_vfs; i++)
6209 adapter->vfinfo[i].clear_to_send = false;
6210
6211 /* update setting rx tx for all active vfs */
6212 ixgbe_set_all_vfs(adapter);
6213 }
6214
6215 /* disable transmits in the hardware now that interrupts are off */
6216 ixgbe_disable_tx(adapter);
6217
6218 if (!pci_channel_offline(adapter->pdev))
6219 ixgbe_reset(adapter);
6220
6221 /* power down the optics for 82599 SFP+ fiber */
6222 if (hw->mac.ops.disable_tx_laser)
6223 hw->mac.ops.disable_tx_laser(hw);
6224
6225 ixgbe_clean_all_tx_rings(adapter);
6226 ixgbe_clean_all_rx_rings(adapter);
6227 }
6228
6229 /**
6230 * ixgbe_set_eee_capable - helper function to determine EEE support on X550
6231 * @adapter: board private structure
6232 */
6233 static void ixgbe_set_eee_capable(struct ixgbe_adapter *adapter)
6234 {
6235 struct ixgbe_hw *hw = &adapter->hw;
6236
6237 switch (hw->device_id) {
6238 case IXGBE_DEV_ID_X550EM_A_1G_T:
6239 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6240 if (!hw->phy.eee_speeds_supported)
6241 break;
6242 adapter->flags2 |= IXGBE_FLAG2_EEE_CAPABLE;
6243 if (!hw->phy.eee_speeds_advertised)
6244 break;
6245 adapter->flags2 |= IXGBE_FLAG2_EEE_ENABLED;
6246 break;
6247 default:
6248 adapter->flags2 &= ~IXGBE_FLAG2_EEE_CAPABLE;
6249 adapter->flags2 &= ~IXGBE_FLAG2_EEE_ENABLED;
6250 break;
6251 }
6252 }
6253
6254 /**
6255 * ixgbe_tx_timeout - Respond to a Tx Hang
6256 * @netdev: network interface device structure
6257 * @txqueue: queue number that timed out
6258 **/
6259 static void ixgbe_tx_timeout(struct net_device *netdev, unsigned int __always_unused txqueue)
6260 {
6261 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6262
6263 /* Do the reset outside of interrupt context */
6264 ixgbe_tx_timeout_reset(adapter);
6265 }
6266
6267 #ifdef CONFIG_IXGBE_DCB
6268 static void ixgbe_init_dcb(struct ixgbe_adapter *adapter)
6269 {
6270 struct ixgbe_hw *hw = &adapter->hw;
6271 struct tc_configuration *tc;
6272 int j;
6273
6274 switch (hw->mac.type) {
6275 case ixgbe_mac_82598EB:
6276 case ixgbe_mac_82599EB:
6277 adapter->dcb_cfg.num_tcs.pg_tcs = MAX_TRAFFIC_CLASS;
6278 adapter->dcb_cfg.num_tcs.pfc_tcs = MAX_TRAFFIC_CLASS;
6279 break;
6280 case ixgbe_mac_X540:
6281 case ixgbe_mac_X550:
6282 adapter->dcb_cfg.num_tcs.pg_tcs = X540_TRAFFIC_CLASS;
6283 adapter->dcb_cfg.num_tcs.pfc_tcs = X540_TRAFFIC_CLASS;
6284 break;
6285 case ixgbe_mac_X550EM_x:
6286 case ixgbe_mac_x550em_a:
6287 default:
6288 adapter->dcb_cfg.num_tcs.pg_tcs = DEF_TRAFFIC_CLASS;
6289 adapter->dcb_cfg.num_tcs.pfc_tcs = DEF_TRAFFIC_CLASS;
6290 break;
6291 }
6292
6293 /* Configure DCB traffic classes */
6294 for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
6295 tc = &adapter->dcb_cfg.tc_config[j];
6296 tc->path[DCB_TX_CONFIG].bwg_id = 0;
6297 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
6298 tc->path[DCB_RX_CONFIG].bwg_id = 0;
6299 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
6300 tc->dcb_pfc = pfc_disabled;
6301 }
6302
6303 /* Initialize default user to priority mapping, UPx->TC0 */
6304 tc = &adapter->dcb_cfg.tc_config[0];
6305 tc->path[DCB_TX_CONFIG].up_to_tc_bitmap = 0xFF;
6306 tc->path[DCB_RX_CONFIG].up_to_tc_bitmap = 0xFF;
6307
6308 adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
6309 adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
6310 adapter->dcb_cfg.pfc_mode_enable = false;
6311 adapter->dcb_set_bitmap = 0x00;
6312 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
6313 adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
6314 memcpy(&adapter->temp_dcb_cfg, &adapter->dcb_cfg,
6315 sizeof(adapter->temp_dcb_cfg));
6316 }
6317 #endif
6318
6319 /**
6320 * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
6321 * @adapter: board private structure to initialize
6322 * @ii: pointer to ixgbe_info for device
6323 *
6324 * ixgbe_sw_init initializes the Adapter private data structure.
6325 * Fields are initialized based on PCI device information and
6326 * OS network device settings (MTU size).
6327 **/
6328 static int ixgbe_sw_init(struct ixgbe_adapter *adapter,
6329 const struct ixgbe_info *ii)
6330 {
6331 struct ixgbe_hw *hw = &adapter->hw;
6332 struct pci_dev *pdev = adapter->pdev;
6333 unsigned int rss, fdir;
6334 u32 fwsm;
6335 int i;
6336
6337 /* PCI config space info */
6338
6339 hw->vendor_id = pdev->vendor;
6340 hw->device_id = pdev->device;
6341 hw->revision_id = pdev->revision;
6342 hw->subsystem_vendor_id = pdev->subsystem_vendor;
6343 hw->subsystem_device_id = pdev->subsystem_device;
6344
6345 /* get_invariants needs the device IDs */
6346 ii->get_invariants(hw);
6347
6348 /* Set common capability flags and settings */
6349 rss = min_t(int, ixgbe_max_rss_indices(adapter), num_online_cpus());
6350 adapter->ring_feature[RING_F_RSS].limit = rss;
6351 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
6352 adapter->max_q_vectors = MAX_Q_VECTORS_82599;
6353 adapter->atr_sample_rate = 20;
6354 fdir = min_t(int, IXGBE_MAX_FDIR_INDICES, num_online_cpus());
6355 adapter->ring_feature[RING_F_FDIR].limit = fdir;
6356 adapter->fdir_pballoc = IXGBE_FDIR_PBALLOC_64K;
6357 adapter->ring_feature[RING_F_VMDQ].limit = 1;
6358 #ifdef CONFIG_IXGBE_DCA
6359 adapter->flags |= IXGBE_FLAG_DCA_CAPABLE;
6360 #endif
6361 #ifdef CONFIG_IXGBE_DCB
6362 adapter->flags |= IXGBE_FLAG_DCB_CAPABLE;
6363 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
6364 #endif
6365 #ifdef IXGBE_FCOE
6366 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
6367 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6368 #ifdef CONFIG_IXGBE_DCB
6369 /* Default traffic class to use for FCoE */
6370 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
6371 #endif /* CONFIG_IXGBE_DCB */
6372 #endif /* IXGBE_FCOE */
6373
6374 /* initialize static ixgbe jump table entries */
6375 adapter->jump_tables[0] = kzalloc(sizeof(*adapter->jump_tables[0]),
6376 GFP_KERNEL);
6377 if (!adapter->jump_tables[0])
6378 return -ENOMEM;
6379 adapter->jump_tables[0]->mat = ixgbe_ipv4_fields;
6380
6381 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++)
6382 adapter->jump_tables[i] = NULL;
6383
6384 adapter->mac_table = kcalloc(hw->mac.num_rar_entries,
6385 sizeof(struct ixgbe_mac_addr),
6386 GFP_KERNEL);
6387 if (!adapter->mac_table)
6388 return -ENOMEM;
6389
6390 if (ixgbe_init_rss_key(adapter))
6391 return -ENOMEM;
6392
6393 adapter->af_xdp_zc_qps = bitmap_zalloc(IXGBE_MAX_XDP_QS, GFP_KERNEL);
6394 if (!adapter->af_xdp_zc_qps)
6395 return -ENOMEM;
6396
6397 /* Set MAC specific capability flags and exceptions */
6398 switch (hw->mac.type) {
6399 case ixgbe_mac_82598EB:
6400 adapter->flags2 &= ~IXGBE_FLAG2_RSC_CAPABLE;
6401
6402 if (hw->device_id == IXGBE_DEV_ID_82598AT)
6403 adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
6404
6405 adapter->max_q_vectors = MAX_Q_VECTORS_82598;
6406 adapter->ring_feature[RING_F_FDIR].limit = 0;
6407 adapter->atr_sample_rate = 0;
6408 adapter->fdir_pballoc = 0;
6409 #ifdef IXGBE_FCOE
6410 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6411 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
6412 #ifdef CONFIG_IXGBE_DCB
6413 adapter->fcoe.up = 0;
6414 #endif /* IXGBE_DCB */
6415 #endif /* IXGBE_FCOE */
6416 break;
6417 case ixgbe_mac_82599EB:
6418 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
6419 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6420 break;
6421 case ixgbe_mac_X540:
6422 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
6423 if (fwsm & IXGBE_FWSM_TS_ENABLED)
6424 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6425 break;
6426 case ixgbe_mac_x550em_a:
6427 switch (hw->device_id) {
6428 case IXGBE_DEV_ID_X550EM_A_1G_T:
6429 case IXGBE_DEV_ID_X550EM_A_1G_T_L:
6430 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6431 break;
6432 default:
6433 break;
6434 }
6435 fallthrough;
6436 case ixgbe_mac_X550EM_x:
6437 #ifdef CONFIG_IXGBE_DCB
6438 adapter->flags &= ~IXGBE_FLAG_DCB_CAPABLE;
6439 #endif
6440 #ifdef IXGBE_FCOE
6441 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
6442 #ifdef CONFIG_IXGBE_DCB
6443 adapter->fcoe.up = 0;
6444 #endif /* IXGBE_DCB */
6445 #endif /* IXGBE_FCOE */
6446 fallthrough;
6447 case ixgbe_mac_X550:
6448 if (hw->mac.type == ixgbe_mac_X550)
6449 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
6450 #ifdef CONFIG_IXGBE_DCA
6451 adapter->flags &= ~IXGBE_FLAG_DCA_CAPABLE;
6452 #endif
6453 break;
6454 default:
6455 break;
6456 }
6457
6458 #ifdef IXGBE_FCOE
6459 /* FCoE support exists, always init the FCoE lock */
6460 spin_lock_init(&adapter->fcoe.lock);
6461
6462 #endif
6463 /* n-tuple support exists, always init our spinlock */
6464 spin_lock_init(&adapter->fdir_perfect_lock);
6465
6466 /* init spinlock to avoid concurrency of VF resources */
6467 spin_lock_init(&adapter->vfs_lock);
6468
6469 #ifdef CONFIG_IXGBE_DCB
6470 ixgbe_init_dcb(adapter);
6471 #endif
6472 ixgbe_init_ipsec_offload(adapter);
6473
6474 /* default flow control settings */
6475 hw->fc.requested_mode = ixgbe_fc_full;
6476 hw->fc.current_mode = ixgbe_fc_full; /* init for ethtool output */
6477 ixgbe_pbthresh_setup(adapter);
6478 hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
6479 hw->fc.send_xon = true;
6480 hw->fc.disable_fc_autoneg = ixgbe_device_supports_autoneg_fc(hw);
6481
6482 #ifdef CONFIG_PCI_IOV
6483 if (max_vfs > 0)
6484 e_dev_warn("Enabling SR-IOV VFs using the max_vfs module parameter is deprecated - please use the pci sysfs interface instead.\n");
6485
6486 /* assign number of SR-IOV VFs */
6487 if (hw->mac.type != ixgbe_mac_82598EB) {
6488 if (max_vfs > IXGBE_MAX_VFS_DRV_LIMIT) {
6489 max_vfs = 0;
6490 e_dev_warn("max_vfs parameter out of range. Not assigning any SR-IOV VFs\n");
6491 }
6492 }
6493 #endif /* CONFIG_PCI_IOV */
6494
6495 /* enable itr by default in dynamic mode */
6496 adapter->rx_itr_setting = 1;
6497 adapter->tx_itr_setting = 1;
6498
6499 /* set default ring sizes */
6500 adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
6501 adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
6502
6503 /* set default work limits */
6504 adapter->tx_work_limit = IXGBE_DEFAULT_TX_WORK;
6505
6506 /* initialize eeprom parameters */
6507 if (ixgbe_init_eeprom_params_generic(hw)) {
6508 e_dev_err("EEPROM initialization failed\n");
6509 return -EIO;
6510 }
6511
6512 /* PF holds first pool slot */
6513 set_bit(0, adapter->fwd_bitmask);
6514 set_bit(__IXGBE_DOWN, &adapter->state);
6515
6516 /* enable locking for XDP_TX if we have more CPUs than queues */
6517 if (nr_cpu_ids > IXGBE_MAX_XDP_QS)
6518 static_branch_enable(&ixgbe_xdp_locking_key);
6519
6520 return 0;
6521 }
6522
6523 /**
6524 * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
6525 * @tx_ring: tx descriptor ring (for a specific queue) to setup
6526 *
6527 * Return 0 on success, negative on failure
6528 **/
6529 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
6530 {
6531 struct device *dev = tx_ring->dev;
6532 int orig_node = dev_to_node(dev);
6533 int ring_node = NUMA_NO_NODE;
6534 int size;
6535
6536 size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
6537
6538 if (tx_ring->q_vector)
6539 ring_node = tx_ring->q_vector->numa_node;
6540
6541 tx_ring->tx_buffer_info = vmalloc_node(size, ring_node);
6542 if (!tx_ring->tx_buffer_info)
6543 tx_ring->tx_buffer_info = vmalloc(size);
6544 if (!tx_ring->tx_buffer_info)
6545 goto err;
6546
6547 /* round up to nearest 4K */
6548 tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
6549 tx_ring->size = ALIGN(tx_ring->size, 4096);
6550
6551 set_dev_node(dev, ring_node);
6552 tx_ring->desc = dma_alloc_coherent(dev,
6553 tx_ring->size,
6554 &tx_ring->dma,
6555 GFP_KERNEL);
6556 set_dev_node(dev, orig_node);
6557 if (!tx_ring->desc)
6558 tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
6559 &tx_ring->dma, GFP_KERNEL);
6560 if (!tx_ring->desc)
6561 goto err;
6562
6563 tx_ring->next_to_use = 0;
6564 tx_ring->next_to_clean = 0;
6565 return 0;
6566
6567 err:
6568 vfree(tx_ring->tx_buffer_info);
6569 tx_ring->tx_buffer_info = NULL;
6570 dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
6571 return -ENOMEM;
6572 }
6573
6574 /**
6575 * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
6576 * @adapter: board private structure
6577 *
6578 * If this function returns with an error, then it's possible one or
6579 * more of the rings is populated (while the rest are not). It is the
6580 * callers duty to clean those orphaned rings.
6581 *
6582 * Return 0 on success, negative on failure
6583 **/
6584 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
6585 {
6586 int i, j = 0, err = 0;
6587
6588 for (i = 0; i < adapter->num_tx_queues; i++) {
6589 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
6590 if (!err)
6591 continue;
6592
6593 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
6594 goto err_setup_tx;
6595 }
6596 for (j = 0; j < adapter->num_xdp_queues; j++) {
6597 err = ixgbe_setup_tx_resources(adapter->xdp_ring[j]);
6598 if (!err)
6599 continue;
6600
6601 e_err(probe, "Allocation for Tx Queue %u failed\n", j);
6602 goto err_setup_tx;
6603 }
6604
6605 return 0;
6606 err_setup_tx:
6607 /* rewind the index freeing the rings as we go */
6608 while (j--)
6609 ixgbe_free_tx_resources(adapter->xdp_ring[j]);
6610 while (i--)
6611 ixgbe_free_tx_resources(adapter->tx_ring[i]);
6612 return err;
6613 }
6614
6615 static int ixgbe_rx_napi_id(struct ixgbe_ring *rx_ring)
6616 {
6617 struct ixgbe_q_vector *q_vector = rx_ring->q_vector;
6618
6619 return q_vector ? q_vector->napi.napi_id : 0;
6620 }
6621
6622 /**
6623 * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
6624 * @adapter: pointer to ixgbe_adapter
6625 * @rx_ring: rx descriptor ring (for a specific queue) to setup
6626 *
6627 * Returns 0 on success, negative on failure
6628 **/
6629 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
6630 struct ixgbe_ring *rx_ring)
6631 {
6632 struct device *dev = rx_ring->dev;
6633 int orig_node = dev_to_node(dev);
6634 int ring_node = NUMA_NO_NODE;
6635 int size;
6636
6637 size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
6638
6639 if (rx_ring->q_vector)
6640 ring_node = rx_ring->q_vector->numa_node;
6641
6642 rx_ring->rx_buffer_info = vmalloc_node(size, ring_node);
6643 if (!rx_ring->rx_buffer_info)
6644 rx_ring->rx_buffer_info = vmalloc(size);
6645 if (!rx_ring->rx_buffer_info)
6646 goto err;
6647
6648 /* Round up to nearest 4K */
6649 rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
6650 rx_ring->size = ALIGN(rx_ring->size, 4096);
6651
6652 set_dev_node(dev, ring_node);
6653 rx_ring->desc = dma_alloc_coherent(dev,
6654 rx_ring->size,
6655 &rx_ring->dma,
6656 GFP_KERNEL);
6657 set_dev_node(dev, orig_node);
6658 if (!rx_ring->desc)
6659 rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
6660 &rx_ring->dma, GFP_KERNEL);
6661 if (!rx_ring->desc)
6662 goto err;
6663
6664 rx_ring->next_to_clean = 0;
6665 rx_ring->next_to_use = 0;
6666
6667 /* XDP RX-queue info */
6668 if (xdp_rxq_info_reg(&rx_ring->xdp_rxq, adapter->netdev,
6669 rx_ring->queue_index, ixgbe_rx_napi_id(rx_ring)) < 0)
6670 goto err;
6671
6672 WRITE_ONCE(rx_ring->xdp_prog, adapter->xdp_prog);
6673
6674 return 0;
6675 err:
6676 vfree(rx_ring->rx_buffer_info);
6677 rx_ring->rx_buffer_info = NULL;
6678 dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
6679 return -ENOMEM;
6680 }
6681
6682 /**
6683 * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
6684 * @adapter: board private structure
6685 *
6686 * If this function returns with an error, then it's possible one or
6687 * more of the rings is populated (while the rest are not). It is the
6688 * callers duty to clean those orphaned rings.
6689 *
6690 * Return 0 on success, negative on failure
6691 **/
6692 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
6693 {
6694 int i, err = 0;
6695
6696 for (i = 0; i < adapter->num_rx_queues; i++) {
6697 err = ixgbe_setup_rx_resources(adapter, adapter->rx_ring[i]);
6698 if (!err)
6699 continue;
6700
6701 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
6702 goto err_setup_rx;
6703 }
6704
6705 #ifdef IXGBE_FCOE
6706 err = ixgbe_setup_fcoe_ddp_resources(adapter);
6707 if (!err)
6708 #endif
6709 return 0;
6710 err_setup_rx:
6711 /* rewind the index freeing the rings as we go */
6712 while (i--)
6713 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6714 return err;
6715 }
6716
6717 /**
6718 * ixgbe_free_tx_resources - Free Tx Resources per Queue
6719 * @tx_ring: Tx descriptor ring for a specific queue
6720 *
6721 * Free all transmit software resources
6722 **/
6723 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
6724 {
6725 ixgbe_clean_tx_ring(tx_ring);
6726
6727 vfree(tx_ring->tx_buffer_info);
6728 tx_ring->tx_buffer_info = NULL;
6729
6730 /* if not set, then don't free */
6731 if (!tx_ring->desc)
6732 return;
6733
6734 dma_free_coherent(tx_ring->dev, tx_ring->size,
6735 tx_ring->desc, tx_ring->dma);
6736
6737 tx_ring->desc = NULL;
6738 }
6739
6740 /**
6741 * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
6742 * @adapter: board private structure
6743 *
6744 * Free all transmit software resources
6745 **/
6746 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
6747 {
6748 int i;
6749
6750 for (i = 0; i < adapter->num_tx_queues; i++)
6751 if (adapter->tx_ring[i]->desc)
6752 ixgbe_free_tx_resources(adapter->tx_ring[i]);
6753 for (i = 0; i < adapter->num_xdp_queues; i++)
6754 if (adapter->xdp_ring[i]->desc)
6755 ixgbe_free_tx_resources(adapter->xdp_ring[i]);
6756 }
6757
6758 /**
6759 * ixgbe_free_rx_resources - Free Rx Resources
6760 * @rx_ring: ring to clean the resources from
6761 *
6762 * Free all receive software resources
6763 **/
6764 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
6765 {
6766 ixgbe_clean_rx_ring(rx_ring);
6767
6768 rx_ring->xdp_prog = NULL;
6769 xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
6770 vfree(rx_ring->rx_buffer_info);
6771 rx_ring->rx_buffer_info = NULL;
6772
6773 /* if not set, then don't free */
6774 if (!rx_ring->desc)
6775 return;
6776
6777 dma_free_coherent(rx_ring->dev, rx_ring->size,
6778 rx_ring->desc, rx_ring->dma);
6779
6780 rx_ring->desc = NULL;
6781 }
6782
6783 /**
6784 * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
6785 * @adapter: board private structure
6786 *
6787 * Free all receive software resources
6788 **/
6789 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
6790 {
6791 int i;
6792
6793 #ifdef IXGBE_FCOE
6794 ixgbe_free_fcoe_ddp_resources(adapter);
6795
6796 #endif
6797 for (i = 0; i < adapter->num_rx_queues; i++)
6798 if (adapter->rx_ring[i]->desc)
6799 ixgbe_free_rx_resources(adapter->rx_ring[i]);
6800 }
6801
6802 /**
6803 * ixgbe_max_xdp_frame_size - returns the maximum allowed frame size for XDP
6804 * @adapter: device handle, pointer to adapter
6805 */
6806 static int ixgbe_max_xdp_frame_size(struct ixgbe_adapter *adapter)
6807 {
6808 if (PAGE_SIZE >= 8192 || adapter->flags2 & IXGBE_FLAG2_RX_LEGACY)
6809 return IXGBE_RXBUFFER_2K;
6810 else
6811 return IXGBE_RXBUFFER_3K;
6812 }
6813
6814 /**
6815 * ixgbe_change_mtu - Change the Maximum Transfer Unit
6816 * @netdev: network interface device structure
6817 * @new_mtu: new value for maximum frame size
6818 *
6819 * Returns 0 on success, negative on failure
6820 **/
6821 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
6822 {
6823 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6824
6825 if (ixgbe_enabled_xdp_adapter(adapter)) {
6826 int new_frame_size = new_mtu + IXGBE_PKT_HDR_PAD;
6827
6828 if (new_frame_size > ixgbe_max_xdp_frame_size(adapter)) {
6829 e_warn(probe, "Requested MTU size is not supported with XDP\n");
6830 return -EINVAL;
6831 }
6832 }
6833
6834 /*
6835 * For 82599EB we cannot allow legacy VFs to enable their receive
6836 * paths when MTU greater than 1500 is configured. So display a
6837 * warning that legacy VFs will be disabled.
6838 */
6839 if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
6840 (adapter->hw.mac.type == ixgbe_mac_82599EB) &&
6841 (new_mtu > ETH_DATA_LEN))
6842 e_warn(probe, "Setting MTU > 1500 will disable legacy VFs\n");
6843
6844 netdev_dbg(netdev, "changing MTU from %d to %d\n",
6845 netdev->mtu, new_mtu);
6846
6847 /* must set new MTU before calling down or up */
6848 WRITE_ONCE(netdev->mtu, new_mtu);
6849
6850 if (netif_running(netdev))
6851 ixgbe_reinit_locked(adapter);
6852
6853 return 0;
6854 }
6855
6856 /**
6857 * ixgbe_open - Called when a network interface is made active
6858 * @netdev: network interface device structure
6859 *
6860 * Returns 0 on success, negative value on failure
6861 *
6862 * The open entry point is called when a network interface is made
6863 * active by the system (IFF_UP). At this point all resources needed
6864 * for transmit and receive operations are allocated, the interrupt
6865 * handler is registered with the OS, the watchdog timer is started,
6866 * and the stack is notified that the interface is ready.
6867 **/
6868 int ixgbe_open(struct net_device *netdev)
6869 {
6870 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6871 struct ixgbe_hw *hw = &adapter->hw;
6872 int err, queues;
6873
6874 /* disallow open during test */
6875 if (test_bit(__IXGBE_TESTING, &adapter->state))
6876 return -EBUSY;
6877
6878 netif_carrier_off(netdev);
6879
6880 /* allocate transmit descriptors */
6881 err = ixgbe_setup_all_tx_resources(adapter);
6882 if (err)
6883 goto err_setup_tx;
6884
6885 /* allocate receive descriptors */
6886 err = ixgbe_setup_all_rx_resources(adapter);
6887 if (err)
6888 goto err_setup_rx;
6889
6890 ixgbe_configure(adapter);
6891
6892 err = ixgbe_request_irq(adapter);
6893 if (err)
6894 goto err_req_irq;
6895
6896 /* Notify the stack of the actual queue counts. */
6897 queues = adapter->num_tx_queues;
6898 err = netif_set_real_num_tx_queues(netdev, queues);
6899 if (err)
6900 goto err_set_queues;
6901
6902 queues = adapter->num_rx_queues;
6903 err = netif_set_real_num_rx_queues(netdev, queues);
6904 if (err)
6905 goto err_set_queues;
6906
6907 ixgbe_ptp_init(adapter);
6908
6909 ixgbe_up_complete(adapter);
6910
6911 udp_tunnel_nic_reset_ntf(netdev);
6912
6913 return 0;
6914
6915 err_set_queues:
6916 ixgbe_free_irq(adapter);
6917 err_req_irq:
6918 ixgbe_free_all_rx_resources(adapter);
6919 if (hw->phy.ops.set_phy_power && !adapter->wol)
6920 hw->phy.ops.set_phy_power(&adapter->hw, false);
6921 err_setup_rx:
6922 ixgbe_free_all_tx_resources(adapter);
6923 err_setup_tx:
6924 ixgbe_reset(adapter);
6925
6926 return err;
6927 }
6928
6929 static void ixgbe_close_suspend(struct ixgbe_adapter *adapter)
6930 {
6931 ixgbe_ptp_suspend(adapter);
6932
6933 if (adapter->hw.phy.ops.enter_lplu) {
6934 adapter->hw.phy.reset_disable = true;
6935 ixgbe_down(adapter);
6936 adapter->hw.phy.ops.enter_lplu(&adapter->hw);
6937 adapter->hw.phy.reset_disable = false;
6938 } else {
6939 ixgbe_down(adapter);
6940 }
6941
6942 ixgbe_free_irq(adapter);
6943
6944 ixgbe_free_all_tx_resources(adapter);
6945 ixgbe_free_all_rx_resources(adapter);
6946 }
6947
6948 /**
6949 * ixgbe_close - Disables a network interface
6950 * @netdev: network interface device structure
6951 *
6952 * Returns 0, this is not allowed to fail
6953 *
6954 * The close entry point is called when an interface is de-activated
6955 * by the OS. The hardware is still under the drivers control, but
6956 * needs to be disabled. A global MAC reset is issued to stop the
6957 * hardware, and all transmit and receive resources are freed.
6958 **/
6959 int ixgbe_close(struct net_device *netdev)
6960 {
6961 struct ixgbe_adapter *adapter = netdev_priv(netdev);
6962
6963 ixgbe_ptp_stop(adapter);
6964
6965 if (netif_device_present(netdev))
6966 ixgbe_close_suspend(adapter);
6967
6968 ixgbe_fdir_filter_exit(adapter);
6969
6970 ixgbe_release_hw_control(adapter);
6971
6972 return 0;
6973 }
6974
6975 static int ixgbe_resume(struct device *dev_d)
6976 {
6977 struct pci_dev *pdev = to_pci_dev(dev_d);
6978 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
6979 struct net_device *netdev = adapter->netdev;
6980 u32 err;
6981
6982 adapter->hw.hw_addr = adapter->io_addr;
6983
6984 err = pci_enable_device_mem(pdev);
6985 if (err) {
6986 e_dev_err("Cannot enable PCI device from suspend\n");
6987 return err;
6988 }
6989 smp_mb__before_atomic();
6990 clear_bit(__IXGBE_DISABLED, &adapter->state);
6991 pci_set_master(pdev);
6992
6993 device_wakeup_disable(dev_d);
6994
6995 ixgbe_reset(adapter);
6996
6997 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
6998
6999 rtnl_lock();
7000 err = ixgbe_init_interrupt_scheme(adapter);
7001 if (!err && netif_running(netdev))
7002 err = ixgbe_open(netdev);
7003
7004
7005 if (!err)
7006 netif_device_attach(netdev);
7007 rtnl_unlock();
7008
7009 return err;
7010 }
7011
7012 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
7013 {
7014 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7015 struct net_device *netdev = adapter->netdev;
7016 struct ixgbe_hw *hw = &adapter->hw;
7017 u32 ctrl;
7018 u32 wufc = adapter->wol;
7019
7020 rtnl_lock();
7021 netif_device_detach(netdev);
7022
7023 if (netif_running(netdev))
7024 ixgbe_close_suspend(adapter);
7025
7026 ixgbe_clear_interrupt_scheme(adapter);
7027 rtnl_unlock();
7028
7029 if (hw->mac.ops.stop_link_on_d3)
7030 hw->mac.ops.stop_link_on_d3(hw);
7031
7032 if (wufc) {
7033 u32 fctrl;
7034
7035 ixgbe_set_rx_mode(netdev);
7036
7037 /* enable the optics for 82599 SFP+ fiber as we can WoL */
7038 if (hw->mac.ops.enable_tx_laser)
7039 hw->mac.ops.enable_tx_laser(hw);
7040
7041 /* enable the reception of multicast packets */
7042 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
7043 fctrl |= IXGBE_FCTRL_MPE;
7044 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
7045
7046 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
7047 ctrl |= IXGBE_CTRL_GIO_DIS;
7048 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
7049
7050 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
7051 } else {
7052 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
7053 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
7054 }
7055
7056 switch (hw->mac.type) {
7057 case ixgbe_mac_82598EB:
7058 pci_wake_from_d3(pdev, false);
7059 break;
7060 case ixgbe_mac_82599EB:
7061 case ixgbe_mac_X540:
7062 case ixgbe_mac_X550:
7063 case ixgbe_mac_X550EM_x:
7064 case ixgbe_mac_x550em_a:
7065 pci_wake_from_d3(pdev, !!wufc);
7066 break;
7067 default:
7068 break;
7069 }
7070
7071 *enable_wake = !!wufc;
7072 if (hw->phy.ops.set_phy_power && !*enable_wake)
7073 hw->phy.ops.set_phy_power(hw, false);
7074
7075 ixgbe_release_hw_control(adapter);
7076
7077 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
7078 pci_disable_device(pdev);
7079
7080 return 0;
7081 }
7082
7083 static int ixgbe_suspend(struct device *dev_d)
7084 {
7085 struct pci_dev *pdev = to_pci_dev(dev_d);
7086 int retval;
7087 bool wake;
7088
7089 retval = __ixgbe_shutdown(pdev, &wake);
7090
7091 device_set_wakeup_enable(dev_d, wake);
7092
7093 return retval;
7094 }
7095
7096 static void ixgbe_shutdown(struct pci_dev *pdev)
7097 {
7098 bool wake;
7099
7100 __ixgbe_shutdown(pdev, &wake);
7101
7102 if (system_state == SYSTEM_POWER_OFF) {
7103 pci_wake_from_d3(pdev, wake);
7104 pci_set_power_state(pdev, PCI_D3hot);
7105 }
7106 }
7107
7108 /**
7109 * ixgbe_update_stats - Update the board statistics counters.
7110 * @adapter: board private structure
7111 **/
7112 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
7113 {
7114 struct net_device *netdev = adapter->netdev;
7115 struct ixgbe_hw *hw = &adapter->hw;
7116 struct ixgbe_hw_stats *hwstats = &adapter->stats;
7117 u64 total_mpc = 0;
7118 u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
7119 u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
7120 u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
7121 u64 alloc_rx_page = 0;
7122 u64 bytes = 0, packets = 0, hw_csum_rx_error = 0;
7123
7124 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7125 test_bit(__IXGBE_RESETTING, &adapter->state))
7126 return;
7127
7128 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
7129 u64 rsc_count = 0;
7130 u64 rsc_flush = 0;
7131 for (i = 0; i < adapter->num_rx_queues; i++) {
7132 rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
7133 rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
7134 }
7135 adapter->rsc_total_count = rsc_count;
7136 adapter->rsc_total_flush = rsc_flush;
7137 }
7138
7139 for (i = 0; i < adapter->num_rx_queues; i++) {
7140 struct ixgbe_ring *rx_ring = READ_ONCE(adapter->rx_ring[i]);
7141
7142 if (!rx_ring)
7143 continue;
7144 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
7145 alloc_rx_page += rx_ring->rx_stats.alloc_rx_page;
7146 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
7147 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
7148 hw_csum_rx_error += rx_ring->rx_stats.csum_err;
7149 bytes += rx_ring->stats.bytes;
7150 packets += rx_ring->stats.packets;
7151 }
7152 adapter->non_eop_descs = non_eop_descs;
7153 adapter->alloc_rx_page = alloc_rx_page;
7154 adapter->alloc_rx_page_failed = alloc_rx_page_failed;
7155 adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
7156 adapter->hw_csum_rx_error = hw_csum_rx_error;
7157 netdev->stats.rx_bytes = bytes;
7158 netdev->stats.rx_packets = packets;
7159
7160 bytes = 0;
7161 packets = 0;
7162 /* gather some stats to the adapter struct that are per queue */
7163 for (i = 0; i < adapter->num_tx_queues; i++) {
7164 struct ixgbe_ring *tx_ring = READ_ONCE(adapter->tx_ring[i]);
7165
7166 if (!tx_ring)
7167 continue;
7168 restart_queue += tx_ring->tx_stats.restart_queue;
7169 tx_busy += tx_ring->tx_stats.tx_busy;
7170 bytes += tx_ring->stats.bytes;
7171 packets += tx_ring->stats.packets;
7172 }
7173 for (i = 0; i < adapter->num_xdp_queues; i++) {
7174 struct ixgbe_ring *xdp_ring = READ_ONCE(adapter->xdp_ring[i]);
7175
7176 if (!xdp_ring)
7177 continue;
7178 restart_queue += xdp_ring->tx_stats.restart_queue;
7179 tx_busy += xdp_ring->tx_stats.tx_busy;
7180 bytes += xdp_ring->stats.bytes;
7181 packets += xdp_ring->stats.packets;
7182 }
7183 adapter->restart_queue = restart_queue;
7184 adapter->tx_busy = tx_busy;
7185 netdev->stats.tx_bytes = bytes;
7186 netdev->stats.tx_packets = packets;
7187
7188 hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
7189
7190 /* 8 register reads */
7191 for (i = 0; i < 8; i++) {
7192 /* for packet buffers not used, the register should read 0 */
7193 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
7194 missed_rx += mpc;
7195 hwstats->mpc[i] += mpc;
7196 total_mpc += hwstats->mpc[i];
7197 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
7198 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
7199 switch (hw->mac.type) {
7200 case ixgbe_mac_82598EB:
7201 hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
7202 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
7203 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
7204 hwstats->pxonrxc[i] +=
7205 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
7206 break;
7207 case ixgbe_mac_82599EB:
7208 case ixgbe_mac_X540:
7209 case ixgbe_mac_X550:
7210 case ixgbe_mac_X550EM_x:
7211 case ixgbe_mac_x550em_a:
7212 hwstats->pxonrxc[i] +=
7213 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
7214 break;
7215 default:
7216 break;
7217 }
7218 }
7219
7220 /*16 register reads */
7221 for (i = 0; i < 16; i++) {
7222 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
7223 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
7224 if ((hw->mac.type == ixgbe_mac_82599EB) ||
7225 (hw->mac.type == ixgbe_mac_X540) ||
7226 (hw->mac.type == ixgbe_mac_X550) ||
7227 (hw->mac.type == ixgbe_mac_X550EM_x) ||
7228 (hw->mac.type == ixgbe_mac_x550em_a)) {
7229 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
7230 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i)); /* to clear */
7231 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
7232 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i)); /* to clear */
7233 }
7234 }
7235
7236 hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
7237 /* work around hardware counting issue */
7238 hwstats->gprc -= missed_rx;
7239
7240 ixgbe_update_xoff_received(adapter);
7241
7242 /* 82598 hardware only has a 32 bit counter in the high register */
7243 switch (hw->mac.type) {
7244 case ixgbe_mac_82598EB:
7245 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
7246 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
7247 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
7248 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
7249 break;
7250 case ixgbe_mac_X540:
7251 case ixgbe_mac_X550:
7252 case ixgbe_mac_X550EM_x:
7253 case ixgbe_mac_x550em_a:
7254 /* OS2BMC stats are X540 and later */
7255 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
7256 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
7257 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
7258 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
7259 fallthrough;
7260 case ixgbe_mac_82599EB:
7261 for (i = 0; i < 16; i++)
7262 adapter->hw_rx_no_dma_resources +=
7263 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
7264 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
7265 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
7266 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
7267 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
7268 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
7269 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
7270 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
7271 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
7272 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
7273 #ifdef IXGBE_FCOE
7274 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
7275 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
7276 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
7277 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
7278 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
7279 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
7280 /* Add up per cpu counters for total ddp aloc fail */
7281 if (adapter->fcoe.ddp_pool) {
7282 struct ixgbe_fcoe *fcoe = &adapter->fcoe;
7283 struct ixgbe_fcoe_ddp_pool *ddp_pool;
7284 unsigned int cpu;
7285 u64 noddp = 0, noddp_ext_buff = 0;
7286 for_each_possible_cpu(cpu) {
7287 ddp_pool = per_cpu_ptr(fcoe->ddp_pool, cpu);
7288 noddp += ddp_pool->noddp;
7289 noddp_ext_buff += ddp_pool->noddp_ext_buff;
7290 }
7291 hwstats->fcoe_noddp = noddp;
7292 hwstats->fcoe_noddp_ext_buff = noddp_ext_buff;
7293 }
7294 #endif /* IXGBE_FCOE */
7295 break;
7296 default:
7297 break;
7298 }
7299 bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
7300 hwstats->bprc += bprc;
7301 hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
7302 if (hw->mac.type == ixgbe_mac_82598EB)
7303 hwstats->mprc -= bprc;
7304 hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
7305 hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
7306 hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
7307 hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
7308 hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
7309 hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
7310 hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
7311 hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
7312 lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
7313 hwstats->lxontxc += lxon;
7314 lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
7315 hwstats->lxofftxc += lxoff;
7316 hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
7317 hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
7318 /*
7319 * 82598 errata - tx of flow control packets is included in tx counters
7320 */
7321 xon_off_tot = lxon + lxoff;
7322 hwstats->gptc -= xon_off_tot;
7323 hwstats->mptc -= xon_off_tot;
7324 hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
7325 hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
7326 hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
7327 hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
7328 hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
7329 hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
7330 hwstats->ptc64 -= xon_off_tot;
7331 hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
7332 hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
7333 hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
7334 hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
7335 hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
7336 hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
7337
7338 /* Fill out the OS statistics structure */
7339 netdev->stats.multicast = hwstats->mprc;
7340
7341 /* Rx Errors */
7342 netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
7343 netdev->stats.rx_dropped = 0;
7344 netdev->stats.rx_length_errors = hwstats->rlec;
7345 netdev->stats.rx_crc_errors = hwstats->crcerrs;
7346 netdev->stats.rx_missed_errors = total_mpc;
7347
7348 /* VF Stats Collection - skip while resetting because these
7349 * are not clear on read and otherwise you'll sometimes get
7350 * crazy values.
7351 */
7352 if (!test_bit(__IXGBE_RESETTING, &adapter->state)) {
7353 for (i = 0; i < adapter->num_vfs; i++) {
7354 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPRC(i),
7355 adapter->vfinfo[i].last_vfstats.gprc,
7356 adapter->vfinfo[i].vfstats.gprc);
7357 UPDATE_VF_COUNTER_32bit(IXGBE_PVFGPTC(i),
7358 adapter->vfinfo[i].last_vfstats.gptc,
7359 adapter->vfinfo[i].vfstats.gptc);
7360 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGORC_LSB(i),
7361 IXGBE_PVFGORC_MSB(i),
7362 adapter->vfinfo[i].last_vfstats.gorc,
7363 adapter->vfinfo[i].vfstats.gorc);
7364 UPDATE_VF_COUNTER_36bit(IXGBE_PVFGOTC_LSB(i),
7365 IXGBE_PVFGOTC_MSB(i),
7366 adapter->vfinfo[i].last_vfstats.gotc,
7367 adapter->vfinfo[i].vfstats.gotc);
7368 UPDATE_VF_COUNTER_32bit(IXGBE_PVFMPRC(i),
7369 adapter->vfinfo[i].last_vfstats.mprc,
7370 adapter->vfinfo[i].vfstats.mprc);
7371 }
7372 }
7373 }
7374
7375 /**
7376 * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
7377 * @adapter: pointer to the device adapter structure
7378 **/
7379 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
7380 {
7381 struct ixgbe_hw *hw = &adapter->hw;
7382 int i;
7383
7384 if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
7385 return;
7386
7387 adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
7388
7389 /* if interface is down do nothing */
7390 if (test_bit(__IXGBE_DOWN, &adapter->state))
7391 return;
7392
7393 /* do nothing if we are not using signature filters */
7394 if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
7395 return;
7396
7397 adapter->fdir_overflow++;
7398
7399 if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
7400 for (i = 0; i < adapter->num_tx_queues; i++)
7401 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7402 &(adapter->tx_ring[i]->state));
7403 for (i = 0; i < adapter->num_xdp_queues; i++)
7404 set_bit(__IXGBE_TX_FDIR_INIT_DONE,
7405 &adapter->xdp_ring[i]->state);
7406 /* re-enable flow director interrupts */
7407 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
7408 } else {
7409 e_err(probe, "failed to finish FDIR re-initialization, "
7410 "ignored adding FDIR ATR filters\n");
7411 }
7412 }
7413
7414 /**
7415 * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
7416 * @adapter: pointer to the device adapter structure
7417 *
7418 * This function serves two purposes. First it strobes the interrupt lines
7419 * in order to make certain interrupts are occurring. Secondly it sets the
7420 * bits needed to check for TX hangs. As a result we should immediately
7421 * determine if a hang has occurred.
7422 */
7423 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
7424 {
7425 struct ixgbe_hw *hw = &adapter->hw;
7426 u64 eics = 0;
7427 int i;
7428
7429 /* If we're down, removing or resetting, just bail */
7430 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7431 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7432 test_bit(__IXGBE_RESETTING, &adapter->state))
7433 return;
7434
7435 /* Force detection of hung controller */
7436 if (netif_carrier_ok(adapter->netdev)) {
7437 for (i = 0; i < adapter->num_tx_queues; i++)
7438 set_check_for_tx_hang(adapter->tx_ring[i]);
7439 for (i = 0; i < adapter->num_xdp_queues; i++)
7440 set_check_for_tx_hang(adapter->xdp_ring[i]);
7441 }
7442
7443 if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
7444 /*
7445 * for legacy and MSI interrupts don't set any bits
7446 * that are enabled for EIAM, because this operation
7447 * would set *both* EIMS and EICS for any bit in EIAM
7448 */
7449 IXGBE_WRITE_REG(hw, IXGBE_EICS,
7450 (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
7451 } else {
7452 /* get one bit for every active tx/rx interrupt vector */
7453 for (i = 0; i < adapter->num_q_vectors; i++) {
7454 struct ixgbe_q_vector *qv = adapter->q_vector[i];
7455 if (qv->rx.ring || qv->tx.ring)
7456 eics |= BIT_ULL(i);
7457 }
7458 }
7459
7460 /* Cause software interrupt to ensure rings are cleaned */
7461 ixgbe_irq_rearm_queues(adapter, eics);
7462 }
7463
7464 /**
7465 * ixgbe_watchdog_update_link - update the link status
7466 * @adapter: pointer to the device adapter structure
7467 **/
7468 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
7469 {
7470 struct ixgbe_hw *hw = &adapter->hw;
7471 u32 link_speed = adapter->link_speed;
7472 bool link_up = adapter->link_up;
7473 bool pfc_en = adapter->dcb_cfg.pfc_mode_enable;
7474
7475 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
7476 return;
7477
7478 if (hw->mac.ops.check_link) {
7479 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
7480 } else {
7481 /* always assume link is up, if no check link function */
7482 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
7483 link_up = true;
7484 }
7485
7486 if (adapter->ixgbe_ieee_pfc)
7487 pfc_en |= !!(adapter->ixgbe_ieee_pfc->pfc_en);
7488
7489 if (link_up && !((adapter->flags & IXGBE_FLAG_DCB_ENABLED) && pfc_en)) {
7490 hw->mac.ops.fc_enable(hw);
7491 ixgbe_set_rx_drop_en(adapter);
7492 }
7493
7494 if (link_up ||
7495 time_after(jiffies, (adapter->link_check_timeout +
7496 IXGBE_TRY_LINK_TIMEOUT))) {
7497 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
7498 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
7499 IXGBE_WRITE_FLUSH(hw);
7500 }
7501
7502 adapter->link_up = link_up;
7503 adapter->link_speed = link_speed;
7504 }
7505
7506 static void ixgbe_update_default_up(struct ixgbe_adapter *adapter)
7507 {
7508 #ifdef CONFIG_IXGBE_DCB
7509 struct net_device *netdev = adapter->netdev;
7510 struct dcb_app app = {
7511 .selector = IEEE_8021QAZ_APP_SEL_ETHERTYPE,
7512 .protocol = 0,
7513 };
7514 u8 up = 0;
7515
7516 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_IEEE)
7517 up = dcb_ieee_getapp_mask(netdev, &app);
7518
7519 adapter->default_up = (up > 1) ? (ffs(up) - 1) : 0;
7520 #endif
7521 }
7522
7523 /**
7524 * ixgbe_watchdog_link_is_up - update netif_carrier status and
7525 * print link up message
7526 * @adapter: pointer to the device adapter structure
7527 **/
7528 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
7529 {
7530 struct net_device *netdev = adapter->netdev;
7531 struct ixgbe_hw *hw = &adapter->hw;
7532 u32 link_speed = adapter->link_speed;
7533 const char *speed_str;
7534 bool flow_rx, flow_tx;
7535
7536 /* only continue if link was previously down */
7537 if (netif_carrier_ok(netdev))
7538 return;
7539
7540 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7541
7542 switch (hw->mac.type) {
7543 case ixgbe_mac_82598EB: {
7544 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
7545 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
7546 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
7547 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
7548 }
7549 break;
7550 case ixgbe_mac_X540:
7551 case ixgbe_mac_X550:
7552 case ixgbe_mac_X550EM_x:
7553 case ixgbe_mac_x550em_a:
7554 case ixgbe_mac_82599EB: {
7555 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
7556 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
7557 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
7558 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
7559 }
7560 break;
7561 default:
7562 flow_tx = false;
7563 flow_rx = false;
7564 break;
7565 }
7566
7567 adapter->last_rx_ptp_check = jiffies;
7568
7569 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7570 ixgbe_ptp_start_cyclecounter(adapter);
7571
7572 switch (link_speed) {
7573 case IXGBE_LINK_SPEED_10GB_FULL:
7574 speed_str = "10 Gbps";
7575 break;
7576 case IXGBE_LINK_SPEED_5GB_FULL:
7577 speed_str = "5 Gbps";
7578 break;
7579 case IXGBE_LINK_SPEED_2_5GB_FULL:
7580 speed_str = "2.5 Gbps";
7581 break;
7582 case IXGBE_LINK_SPEED_1GB_FULL:
7583 speed_str = "1 Gbps";
7584 break;
7585 case IXGBE_LINK_SPEED_100_FULL:
7586 speed_str = "100 Mbps";
7587 break;
7588 case IXGBE_LINK_SPEED_10_FULL:
7589 speed_str = "10 Mbps";
7590 break;
7591 default:
7592 speed_str = "unknown speed";
7593 break;
7594 }
7595 e_info(drv, "NIC Link is Up %s, Flow Control: %s\n", speed_str,
7596 ((flow_rx && flow_tx) ? "RX/TX" :
7597 (flow_rx ? "RX" :
7598 (flow_tx ? "TX" : "None"))));
7599
7600 netif_carrier_on(netdev);
7601 ixgbe_check_vf_rate_limit(adapter);
7602
7603 /* enable transmits */
7604 netif_tx_wake_all_queues(adapter->netdev);
7605
7606 /* update the default user priority for VFs */
7607 ixgbe_update_default_up(adapter);
7608
7609 /* ping all the active vfs to let them know link has changed */
7610 ixgbe_ping_all_vfs(adapter);
7611 }
7612
7613 /**
7614 * ixgbe_watchdog_link_is_down - update netif_carrier status and
7615 * print link down message
7616 * @adapter: pointer to the adapter structure
7617 **/
7618 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
7619 {
7620 struct net_device *netdev = adapter->netdev;
7621 struct ixgbe_hw *hw = &adapter->hw;
7622
7623 adapter->link_up = false;
7624 adapter->link_speed = 0;
7625
7626 /* only continue if link was up previously */
7627 if (!netif_carrier_ok(netdev))
7628 return;
7629
7630 /* poll for SFP+ cable when link is down */
7631 if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
7632 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
7633
7634 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state))
7635 ixgbe_ptp_start_cyclecounter(adapter);
7636
7637 e_info(drv, "NIC Link is Down\n");
7638 netif_carrier_off(netdev);
7639
7640 /* ping all the active vfs to let them know link has changed */
7641 ixgbe_ping_all_vfs(adapter);
7642 }
7643
7644 static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
7645 {
7646 int i;
7647
7648 for (i = 0; i < adapter->num_tx_queues; i++) {
7649 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
7650
7651 if (tx_ring->next_to_use != tx_ring->next_to_clean)
7652 return true;
7653 }
7654
7655 for (i = 0; i < adapter->num_xdp_queues; i++) {
7656 struct ixgbe_ring *ring = adapter->xdp_ring[i];
7657
7658 if (ring->next_to_use != ring->next_to_clean)
7659 return true;
7660 }
7661
7662 return false;
7663 }
7664
7665 static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
7666 {
7667 struct ixgbe_hw *hw = &adapter->hw;
7668 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
7669 u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
7670
7671 int i, j;
7672
7673 if (!adapter->num_vfs)
7674 return false;
7675
7676 /* resetting the PF is only needed for MAC before X550 */
7677 if (hw->mac.type >= ixgbe_mac_X550)
7678 return false;
7679
7680 for (i = 0; i < adapter->num_vfs; i++) {
7681 for (j = 0; j < q_per_pool; j++) {
7682 u32 h, t;
7683
7684 h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
7685 t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
7686
7687 if (h != t)
7688 return true;
7689 }
7690 }
7691
7692 return false;
7693 }
7694
7695 /**
7696 * ixgbe_watchdog_flush_tx - flush queues on link down
7697 * @adapter: pointer to the device adapter structure
7698 **/
7699 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
7700 {
7701 if (!netif_carrier_ok(adapter->netdev)) {
7702 if (ixgbe_ring_tx_pending(adapter) ||
7703 ixgbe_vf_tx_pending(adapter)) {
7704 /* We've lost link, so the controller stops DMA,
7705 * but we've got queued Tx work that's never going
7706 * to get done, so reset controller to flush Tx.
7707 * (Do the reset outside of interrupt context).
7708 */
7709 e_warn(drv, "initiating reset to clear Tx work after link loss\n");
7710 set_bit(__IXGBE_RESET_REQUESTED, &adapter->state);
7711 }
7712 }
7713 }
7714
7715 #ifdef CONFIG_PCI_IOV
7716 static void ixgbe_bad_vf_abort(struct ixgbe_adapter *adapter, u32 vf)
7717 {
7718 struct ixgbe_hw *hw = &adapter->hw;
7719
7720 if (adapter->hw.mac.type == ixgbe_mac_82599EB &&
7721 adapter->flags2 & IXGBE_FLAG2_AUTO_DISABLE_VF) {
7722 adapter->vfinfo[vf].primary_abort_count++;
7723 if (adapter->vfinfo[vf].primary_abort_count ==
7724 IXGBE_PRIMARY_ABORT_LIMIT) {
7725 ixgbe_set_vf_link_state(adapter, vf,
7726 IFLA_VF_LINK_STATE_DISABLE);
7727 adapter->vfinfo[vf].primary_abort_count = 0;
7728
7729 e_info(drv,
7730 "Malicious Driver Detection event detected on PF %d VF %d MAC: %pM mdd-disable-vf=on",
7731 hw->bus.func, vf,
7732 adapter->vfinfo[vf].vf_mac_addresses);
7733 }
7734 }
7735 }
7736
7737 static void ixgbe_check_for_bad_vf(struct ixgbe_adapter *adapter)
7738 {
7739 struct ixgbe_hw *hw = &adapter->hw;
7740 struct pci_dev *pdev = adapter->pdev;
7741 unsigned int vf;
7742 u32 gpc;
7743
7744 if (!(netif_carrier_ok(adapter->netdev)))
7745 return;
7746
7747 gpc = IXGBE_READ_REG(hw, IXGBE_TXDGPC);
7748 if (gpc) /* If incrementing then no need for the check below */
7749 return;
7750 /* Check to see if a bad DMA write target from an errant or
7751 * malicious VF has caused a PCIe error. If so then we can
7752 * issue a VFLR to the offending VF(s) and then resume without
7753 * requesting a full slot reset.
7754 */
7755
7756 if (!pdev)
7757 return;
7758
7759 /* check status reg for all VFs owned by this PF */
7760 for (vf = 0; vf < adapter->num_vfs; ++vf) {
7761 struct pci_dev *vfdev = adapter->vfinfo[vf].vfdev;
7762 u16 status_reg;
7763
7764 if (!vfdev)
7765 continue;
7766 pci_read_config_word(vfdev, PCI_STATUS, &status_reg);
7767 if (status_reg != IXGBE_FAILED_READ_CFG_WORD &&
7768 status_reg & PCI_STATUS_REC_MASTER_ABORT) {
7769 ixgbe_bad_vf_abort(adapter, vf);
7770 pcie_flr(vfdev);
7771 }
7772 }
7773 }
7774
7775 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
7776 {
7777 u32 ssvpc;
7778
7779 /* Do not perform spoof check for 82598 or if not in IOV mode */
7780 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
7781 adapter->num_vfs == 0)
7782 return;
7783
7784 ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
7785
7786 /*
7787 * ssvpc register is cleared on read, if zero then no
7788 * spoofed packets in the last interval.
7789 */
7790 if (!ssvpc)
7791 return;
7792
7793 e_warn(drv, "%u Spoofed packets detected\n", ssvpc);
7794 }
7795 #else
7796 static void ixgbe_spoof_check(struct ixgbe_adapter __always_unused *adapter)
7797 {
7798 }
7799
7800 static void
7801 ixgbe_check_for_bad_vf(struct ixgbe_adapter __always_unused *adapter)
7802 {
7803 }
7804 #endif /* CONFIG_PCI_IOV */
7805
7806
7807 /**
7808 * ixgbe_watchdog_subtask - check and bring link up
7809 * @adapter: pointer to the device adapter structure
7810 **/
7811 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
7812 {
7813 /* if interface is down, removing or resetting, do nothing */
7814 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7815 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7816 test_bit(__IXGBE_RESETTING, &adapter->state))
7817 return;
7818
7819 ixgbe_watchdog_update_link(adapter);
7820
7821 if (adapter->link_up)
7822 ixgbe_watchdog_link_is_up(adapter);
7823 else
7824 ixgbe_watchdog_link_is_down(adapter);
7825
7826 ixgbe_check_for_bad_vf(adapter);
7827 ixgbe_spoof_check(adapter);
7828 ixgbe_update_stats(adapter);
7829
7830 ixgbe_watchdog_flush_tx(adapter);
7831 }
7832
7833 /**
7834 * ixgbe_sfp_detection_subtask - poll for SFP+ cable
7835 * @adapter: the ixgbe adapter structure
7836 **/
7837 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
7838 {
7839 struct ixgbe_hw *hw = &adapter->hw;
7840 int err;
7841
7842 /* not searching for SFP so there is nothing to do here */
7843 if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
7844 !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7845 return;
7846
7847 if (adapter->sfp_poll_time &&
7848 time_after(adapter->sfp_poll_time, jiffies))
7849 return; /* If not yet time to poll for SFP */
7850
7851 /* someone else is in init, wait until next service event */
7852 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7853 return;
7854
7855 adapter->sfp_poll_time = jiffies + IXGBE_SFP_POLL_JIFFIES - 1;
7856
7857 err = hw->phy.ops.identify_sfp(hw);
7858 if (err == -EOPNOTSUPP)
7859 goto sfp_out;
7860
7861 if (err == -ENOENT) {
7862 /* If no cable is present, then we need to reset
7863 * the next time we find a good cable. */
7864 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
7865 }
7866
7867 /* exit on error */
7868 if (err)
7869 goto sfp_out;
7870
7871 /* exit if reset not needed */
7872 if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
7873 goto sfp_out;
7874
7875 adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
7876
7877 /*
7878 * A module may be identified correctly, but the EEPROM may not have
7879 * support for that module. setup_sfp() will fail in that case, so
7880 * we should not allow that module to load.
7881 */
7882 if (hw->mac.type == ixgbe_mac_82598EB)
7883 err = hw->phy.ops.reset(hw);
7884 else
7885 err = hw->mac.ops.setup_sfp(hw);
7886
7887 if (err == -EOPNOTSUPP)
7888 goto sfp_out;
7889
7890 adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
7891 e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
7892
7893 sfp_out:
7894 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7895
7896 if (err == -EOPNOTSUPP &&
7897 adapter->netdev->reg_state == NETREG_REGISTERED) {
7898 e_dev_err("failed to initialize because an unsupported "
7899 "SFP+ module type was detected.\n");
7900 e_dev_err("Reload the driver after installing a "
7901 "supported module.\n");
7902 unregister_netdev(adapter->netdev);
7903 }
7904 }
7905
7906 /**
7907 * ixgbe_sfp_link_config_subtask - set up link SFP after module install
7908 * @adapter: the ixgbe adapter structure
7909 **/
7910 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
7911 {
7912 struct ixgbe_hw *hw = &adapter->hw;
7913 u32 cap_speed;
7914 u32 speed;
7915 bool autoneg = false;
7916
7917 if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
7918 return;
7919
7920 /* someone else is in init, wait until next service event */
7921 if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
7922 return;
7923
7924 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
7925
7926 hw->mac.ops.get_link_capabilities(hw, &cap_speed, &autoneg);
7927
7928 /* advertise highest capable link speed */
7929 if (!autoneg && (cap_speed & IXGBE_LINK_SPEED_10GB_FULL))
7930 speed = IXGBE_LINK_SPEED_10GB_FULL;
7931 else
7932 speed = cap_speed & (IXGBE_LINK_SPEED_10GB_FULL |
7933 IXGBE_LINK_SPEED_1GB_FULL);
7934
7935 if (hw->mac.ops.setup_link)
7936 hw->mac.ops.setup_link(hw, speed, true);
7937
7938 adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
7939 adapter->link_check_timeout = jiffies;
7940 clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
7941 }
7942
7943 /**
7944 * ixgbe_service_timer - Timer Call-back
7945 * @t: pointer to timer_list structure
7946 **/
7947 static void ixgbe_service_timer(struct timer_list *t)
7948 {
7949 struct ixgbe_adapter *adapter = from_timer(adapter, t, service_timer);
7950 unsigned long next_event_offset;
7951
7952 /* poll faster when waiting for link */
7953 if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
7954 next_event_offset = HZ / 10;
7955 else
7956 next_event_offset = HZ * 2;
7957
7958 /* Reset the timer */
7959 mod_timer(&adapter->service_timer, next_event_offset + jiffies);
7960
7961 ixgbe_service_event_schedule(adapter);
7962 }
7963
7964 static void ixgbe_phy_interrupt_subtask(struct ixgbe_adapter *adapter)
7965 {
7966 struct ixgbe_hw *hw = &adapter->hw;
7967 bool overtemp;
7968
7969 if (!(adapter->flags2 & IXGBE_FLAG2_PHY_INTERRUPT))
7970 return;
7971
7972 adapter->flags2 &= ~IXGBE_FLAG2_PHY_INTERRUPT;
7973
7974 if (!hw->phy.ops.handle_lasi)
7975 return;
7976
7977 hw->phy.ops.handle_lasi(&adapter->hw, &overtemp);
7978 if (overtemp)
7979 e_crit(drv, "%s\n", ixgbe_overheat_msg);
7980 }
7981
7982 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
7983 {
7984 if (!test_and_clear_bit(__IXGBE_RESET_REQUESTED, &adapter->state))
7985 return;
7986
7987 rtnl_lock();
7988 /* If we're already down, removing or resetting, just bail */
7989 if (test_bit(__IXGBE_DOWN, &adapter->state) ||
7990 test_bit(__IXGBE_REMOVING, &adapter->state) ||
7991 test_bit(__IXGBE_RESETTING, &adapter->state)) {
7992 rtnl_unlock();
7993 return;
7994 }
7995
7996 ixgbe_dump(adapter);
7997 netdev_err(adapter->netdev, "Reset adapter\n");
7998 adapter->tx_timeout_count++;
7999
8000 ixgbe_reinit_locked(adapter);
8001 rtnl_unlock();
8002 }
8003
8004 /**
8005 * ixgbe_check_fw_error - Check firmware for errors
8006 * @adapter: the adapter private structure
8007 *
8008 * Check firmware errors in register FWSM
8009 */
8010 static bool ixgbe_check_fw_error(struct ixgbe_adapter *adapter)
8011 {
8012 struct ixgbe_hw *hw = &adapter->hw;
8013 u32 fwsm;
8014
8015 /* read fwsm.ext_err_ind register and log errors */
8016 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM(hw));
8017
8018 if (fwsm & IXGBE_FWSM_EXT_ERR_IND_MASK ||
8019 !(fwsm & IXGBE_FWSM_FW_VAL_BIT))
8020 e_dev_warn("Warning firmware error detected FWSM: 0x%08X\n",
8021 fwsm);
8022
8023 if (hw->mac.ops.fw_recovery_mode && hw->mac.ops.fw_recovery_mode(hw)) {
8024 e_dev_err("Firmware recovery mode detected. Limiting functionality. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for details on firmware recovery mode.\n");
8025 return true;
8026 }
8027
8028 return false;
8029 }
8030
8031 /**
8032 * ixgbe_service_task - manages and runs subtasks
8033 * @work: pointer to work_struct containing our data
8034 **/
8035 static void ixgbe_service_task(struct work_struct *work)
8036 {
8037 struct ixgbe_adapter *adapter = container_of(work,
8038 struct ixgbe_adapter,
8039 service_task);
8040 if (ixgbe_removed(adapter->hw.hw_addr)) {
8041 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
8042 rtnl_lock();
8043 ixgbe_down(adapter);
8044 rtnl_unlock();
8045 }
8046 ixgbe_service_event_complete(adapter);
8047 return;
8048 }
8049 if (ixgbe_check_fw_error(adapter)) {
8050 if (!test_bit(__IXGBE_DOWN, &adapter->state))
8051 unregister_netdev(adapter->netdev);
8052 ixgbe_service_event_complete(adapter);
8053 return;
8054 }
8055 ixgbe_reset_subtask(adapter);
8056 ixgbe_phy_interrupt_subtask(adapter);
8057 ixgbe_sfp_detection_subtask(adapter);
8058 ixgbe_sfp_link_config_subtask(adapter);
8059 ixgbe_check_overtemp_subtask(adapter);
8060 ixgbe_watchdog_subtask(adapter);
8061 ixgbe_fdir_reinit_subtask(adapter);
8062 ixgbe_check_hang_subtask(adapter);
8063
8064 if (test_bit(__IXGBE_PTP_RUNNING, &adapter->state)) {
8065 ixgbe_ptp_overflow_check(adapter);
8066 if (adapter->flags & IXGBE_FLAG_RX_HWTSTAMP_IN_REGISTER)
8067 ixgbe_ptp_rx_hang(adapter);
8068 ixgbe_ptp_tx_hang(adapter);
8069 }
8070
8071 ixgbe_service_event_complete(adapter);
8072 }
8073
8074 static int ixgbe_tso(struct ixgbe_ring *tx_ring,
8075 struct ixgbe_tx_buffer *first,
8076 u8 *hdr_len,
8077 struct ixgbe_ipsec_tx_data *itd)
8078 {
8079 u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
8080 struct sk_buff *skb = first->skb;
8081 union {
8082 struct iphdr *v4;
8083 struct ipv6hdr *v6;
8084 unsigned char *hdr;
8085 } ip;
8086 union {
8087 struct tcphdr *tcp;
8088 struct udphdr *udp;
8089 unsigned char *hdr;
8090 } l4;
8091 u32 paylen, l4_offset;
8092 u32 fceof_saidx = 0;
8093 int err;
8094
8095 if (skb->ip_summed != CHECKSUM_PARTIAL)
8096 return 0;
8097
8098 if (!skb_is_gso(skb))
8099 return 0;
8100
8101 err = skb_cow_head(skb, 0);
8102 if (err < 0)
8103 return err;
8104
8105 if (eth_p_mpls(first->protocol))
8106 ip.hdr = skb_inner_network_header(skb);
8107 else
8108 ip.hdr = skb_network_header(skb);
8109 l4.hdr = skb_checksum_start(skb);
8110
8111 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
8112 type_tucmd = (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) ?
8113 IXGBE_ADVTXD_TUCMD_L4T_UDP : IXGBE_ADVTXD_TUCMD_L4T_TCP;
8114
8115 /* initialize outer IP header fields */
8116 if (ip.v4->version == 4) {
8117 unsigned char *csum_start = skb_checksum_start(skb);
8118 unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);
8119 int len = csum_start - trans_start;
8120
8121 /* IP header will have to cancel out any data that
8122 * is not a part of the outer IP header, so set to
8123 * a reverse csum if needed, else init check to 0.
8124 */
8125 ip.v4->check = (skb_shinfo(skb)->gso_type & SKB_GSO_PARTIAL) ?
8126 csum_fold(csum_partial(trans_start,
8127 len, 0)) : 0;
8128 type_tucmd |= IXGBE_ADVTXD_TUCMD_IPV4;
8129
8130 ip.v4->tot_len = 0;
8131 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
8132 IXGBE_TX_FLAGS_CSUM |
8133 IXGBE_TX_FLAGS_IPV4;
8134 } else {
8135 ip.v6->payload_len = 0;
8136 first->tx_flags |= IXGBE_TX_FLAGS_TSO |
8137 IXGBE_TX_FLAGS_CSUM;
8138 }
8139
8140 /* determine offset of inner transport header */
8141 l4_offset = l4.hdr - skb->data;
8142
8143 /* remove payload length from inner checksum */
8144 paylen = skb->len - l4_offset;
8145
8146 if (type_tucmd & IXGBE_ADVTXD_TUCMD_L4T_TCP) {
8147 /* compute length of segmentation header */
8148 *hdr_len = (l4.tcp->doff * 4) + l4_offset;
8149 csum_replace_by_diff(&l4.tcp->check,
8150 (__force __wsum)htonl(paylen));
8151 } else {
8152 /* compute length of segmentation header */
8153 *hdr_len = sizeof(*l4.udp) + l4_offset;
8154 csum_replace_by_diff(&l4.udp->check,
8155 (__force __wsum)htonl(paylen));
8156 }
8157
8158 /* update gso size and bytecount with header size */
8159 first->gso_segs = skb_shinfo(skb)->gso_segs;
8160 first->bytecount += (first->gso_segs - 1) * *hdr_len;
8161
8162 /* mss_l4len_id: use 0 as index for TSO */
8163 mss_l4len_idx = (*hdr_len - l4_offset) << IXGBE_ADVTXD_L4LEN_SHIFT;
8164 mss_l4len_idx |= skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT;
8165
8166 fceof_saidx |= itd->sa_idx;
8167 type_tucmd |= itd->flags | itd->trailer_len;
8168
8169 /* vlan_macip_lens: HEADLEN, MACLEN, VLAN tag */
8170 vlan_macip_lens = l4.hdr - ip.hdr;
8171 vlan_macip_lens |= (ip.hdr - skb->data) << IXGBE_ADVTXD_MACLEN_SHIFT;
8172 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8173
8174 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd,
8175 mss_l4len_idx);
8176
8177 return 1;
8178 }
8179
8180 static void ixgbe_tx_csum(struct ixgbe_ring *tx_ring,
8181 struct ixgbe_tx_buffer *first,
8182 struct ixgbe_ipsec_tx_data *itd)
8183 {
8184 struct sk_buff *skb = first->skb;
8185 u32 vlan_macip_lens = 0;
8186 u32 fceof_saidx = 0;
8187 u32 type_tucmd = 0;
8188
8189 if (skb->ip_summed != CHECKSUM_PARTIAL) {
8190 csum_failed:
8191 if (!(first->tx_flags & (IXGBE_TX_FLAGS_HW_VLAN |
8192 IXGBE_TX_FLAGS_CC)))
8193 return;
8194 goto no_csum;
8195 }
8196
8197 switch (skb->csum_offset) {
8198 case offsetof(struct tcphdr, check):
8199 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_TCP;
8200 fallthrough;
8201 case offsetof(struct udphdr, check):
8202 break;
8203 case offsetof(struct sctphdr, checksum):
8204 /* validate that this is actually an SCTP request */
8205 if (skb_csum_is_sctp(skb)) {
8206 type_tucmd = IXGBE_ADVTXD_TUCMD_L4T_SCTP;
8207 break;
8208 }
8209 fallthrough;
8210 default:
8211 skb_checksum_help(skb);
8212 goto csum_failed;
8213 }
8214
8215 /* update TX checksum flag */
8216 first->tx_flags |= IXGBE_TX_FLAGS_CSUM;
8217 vlan_macip_lens = skb_checksum_start_offset(skb) -
8218 skb_network_offset(skb);
8219 no_csum:
8220 /* vlan_macip_lens: MACLEN, VLAN tag */
8221 vlan_macip_lens |= skb_network_offset(skb) << IXGBE_ADVTXD_MACLEN_SHIFT;
8222 vlan_macip_lens |= first->tx_flags & IXGBE_TX_FLAGS_VLAN_MASK;
8223
8224 fceof_saidx |= itd->sa_idx;
8225 type_tucmd |= itd->flags | itd->trailer_len;
8226
8227 ixgbe_tx_ctxtdesc(tx_ring, vlan_macip_lens, fceof_saidx, type_tucmd, 0);
8228 }
8229
8230 #define IXGBE_SET_FLAG(_input, _flag, _result) \
8231 ((_flag <= _result) ? \
8232 ((u32)(_input & _flag) * (_result / _flag)) : \
8233 ((u32)(_input & _flag) / (_flag / _result)))
8234
8235 static u32 ixgbe_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
8236 {
8237 /* set type for advanced descriptor with frame checksum insertion */
8238 u32 cmd_type = IXGBE_ADVTXD_DTYP_DATA |
8239 IXGBE_ADVTXD_DCMD_DEXT |
8240 IXGBE_ADVTXD_DCMD_IFCS;
8241
8242 /* set HW vlan bit if vlan is present */
8243 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_HW_VLAN,
8244 IXGBE_ADVTXD_DCMD_VLE);
8245
8246 /* set segmentation enable bits for TSO/FSO */
8247 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSO,
8248 IXGBE_ADVTXD_DCMD_TSE);
8249
8250 /* set timestamp bit if present */
8251 cmd_type |= IXGBE_SET_FLAG(tx_flags, IXGBE_TX_FLAGS_TSTAMP,
8252 IXGBE_ADVTXD_MAC_TSTAMP);
8253
8254 /* insert frame checksum */
8255 cmd_type ^= IXGBE_SET_FLAG(skb->no_fcs, 1, IXGBE_ADVTXD_DCMD_IFCS);
8256
8257 return cmd_type;
8258 }
8259
8260 static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
8261 u32 tx_flags, unsigned int paylen)
8262 {
8263 u32 olinfo_status = paylen << IXGBE_ADVTXD_PAYLEN_SHIFT;
8264
8265 /* enable L4 checksum for TSO and TX checksum offload */
8266 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8267 IXGBE_TX_FLAGS_CSUM,
8268 IXGBE_ADVTXD_POPTS_TXSM);
8269
8270 /* enable IPv4 checksum for TSO */
8271 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8272 IXGBE_TX_FLAGS_IPV4,
8273 IXGBE_ADVTXD_POPTS_IXSM);
8274
8275 /* enable IPsec */
8276 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8277 IXGBE_TX_FLAGS_IPSEC,
8278 IXGBE_ADVTXD_POPTS_IPSEC);
8279
8280 /*
8281 * Check Context must be set if Tx switch is enabled, which it
8282 * always is for case where virtual functions are running
8283 */
8284 olinfo_status |= IXGBE_SET_FLAG(tx_flags,
8285 IXGBE_TX_FLAGS_CC,
8286 IXGBE_ADVTXD_CC);
8287
8288 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
8289 }
8290
8291 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8292 {
8293 if (!netif_subqueue_try_stop(tx_ring->netdev, tx_ring->queue_index,
8294 ixgbe_desc_unused(tx_ring), size))
8295 return -EBUSY;
8296
8297 ++tx_ring->tx_stats.restart_queue;
8298 return 0;
8299 }
8300
8301 static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
8302 {
8303 if (likely(ixgbe_desc_unused(tx_ring) >= size))
8304 return 0;
8305
8306 return __ixgbe_maybe_stop_tx(tx_ring, size);
8307 }
8308
8309 static int ixgbe_tx_map(struct ixgbe_ring *tx_ring,
8310 struct ixgbe_tx_buffer *first,
8311 const u8 hdr_len)
8312 {
8313 struct sk_buff *skb = first->skb;
8314 struct ixgbe_tx_buffer *tx_buffer;
8315 union ixgbe_adv_tx_desc *tx_desc;
8316 skb_frag_t *frag;
8317 dma_addr_t dma;
8318 unsigned int data_len, size;
8319 u32 tx_flags = first->tx_flags;
8320 u32 cmd_type = ixgbe_tx_cmd_type(skb, tx_flags);
8321 u16 i = tx_ring->next_to_use;
8322
8323 tx_desc = IXGBE_TX_DESC(tx_ring, i);
8324
8325 ixgbe_tx_olinfo_status(tx_desc, tx_flags, skb->len - hdr_len);
8326
8327 size = skb_headlen(skb);
8328 data_len = skb->data_len;
8329
8330 #ifdef IXGBE_FCOE
8331 if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
8332 if (data_len < sizeof(struct fcoe_crc_eof)) {
8333 size -= sizeof(struct fcoe_crc_eof) - data_len;
8334 data_len = 0;
8335 } else {
8336 data_len -= sizeof(struct fcoe_crc_eof);
8337 }
8338 }
8339
8340 #endif
8341 dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);
8342
8343 tx_buffer = first;
8344
8345 for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
8346 if (dma_mapping_error(tx_ring->dev, dma))
8347 goto dma_error;
8348
8349 /* record length, and DMA address */
8350 dma_unmap_len_set(tx_buffer, len, size);
8351 dma_unmap_addr_set(tx_buffer, dma, dma);
8352
8353 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8354
8355 while (unlikely(size > IXGBE_MAX_DATA_PER_TXD)) {
8356 tx_desc->read.cmd_type_len =
8357 cpu_to_le32(cmd_type ^ IXGBE_MAX_DATA_PER_TXD);
8358
8359 i++;
8360 tx_desc++;
8361 if (i == tx_ring->count) {
8362 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8363 i = 0;
8364 }
8365 tx_desc->read.olinfo_status = 0;
8366
8367 dma += IXGBE_MAX_DATA_PER_TXD;
8368 size -= IXGBE_MAX_DATA_PER_TXD;
8369
8370 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8371 }
8372
8373 if (likely(!data_len))
8374 break;
8375
8376 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);
8377
8378 i++;
8379 tx_desc++;
8380 if (i == tx_ring->count) {
8381 tx_desc = IXGBE_TX_DESC(tx_ring, 0);
8382 i = 0;
8383 }
8384 tx_desc->read.olinfo_status = 0;
8385
8386 #ifdef IXGBE_FCOE
8387 size = min_t(unsigned int, data_len, skb_frag_size(frag));
8388 #else
8389 size = skb_frag_size(frag);
8390 #endif
8391 data_len -= size;
8392
8393 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, size,
8394 DMA_TO_DEVICE);
8395
8396 tx_buffer = &tx_ring->tx_buffer_info[i];
8397 }
8398
8399 /* write last descriptor with RS and EOP bits */
8400 cmd_type |= size | IXGBE_TXD_CMD;
8401 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8402
8403 netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);
8404
8405 /* set the timestamp */
8406 first->time_stamp = jiffies;
8407
8408 skb_tx_timestamp(skb);
8409
8410 /*
8411 * Force memory writes to complete before letting h/w know there
8412 * are new descriptors to fetch. (Only applicable for weak-ordered
8413 * memory model archs, such as IA-64).
8414 *
8415 * We also need this memory barrier to make certain all of the
8416 * status bits have been updated before next_to_watch is written.
8417 */
8418 wmb();
8419
8420 /* set next_to_watch value indicating a packet is present */
8421 first->next_to_watch = tx_desc;
8422
8423 i++;
8424 if (i == tx_ring->count)
8425 i = 0;
8426
8427 tx_ring->next_to_use = i;
8428
8429 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
8430
8431 if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
8432 writel(i, tx_ring->tail);
8433 }
8434
8435 return 0;
8436 dma_error:
8437 dev_err(tx_ring->dev, "TX DMA map failed\n");
8438
8439 /* clear dma mappings for failed tx_buffer_info map */
8440 for (;;) {
8441 tx_buffer = &tx_ring->tx_buffer_info[i];
8442 if (dma_unmap_len(tx_buffer, len))
8443 dma_unmap_page(tx_ring->dev,
8444 dma_unmap_addr(tx_buffer, dma),
8445 dma_unmap_len(tx_buffer, len),
8446 DMA_TO_DEVICE);
8447 dma_unmap_len_set(tx_buffer, len, 0);
8448 if (tx_buffer == first)
8449 break;
8450 if (i == 0)
8451 i += tx_ring->count;
8452 i--;
8453 }
8454
8455 dev_kfree_skb_any(first->skb);
8456 first->skb = NULL;
8457
8458 tx_ring->next_to_use = i;
8459
8460 return -1;
8461 }
8462
8463 static void ixgbe_atr(struct ixgbe_ring *ring,
8464 struct ixgbe_tx_buffer *first)
8465 {
8466 struct ixgbe_q_vector *q_vector = ring->q_vector;
8467 union ixgbe_atr_hash_dword input = { .dword = 0 };
8468 union ixgbe_atr_hash_dword common = { .dword = 0 };
8469 union {
8470 unsigned char *network;
8471 struct iphdr *ipv4;
8472 struct ipv6hdr *ipv6;
8473 } hdr;
8474 struct tcphdr *th;
8475 unsigned int hlen;
8476 struct sk_buff *skb;
8477 __be16 vlan_id;
8478 int l4_proto;
8479
8480 /* if ring doesn't have a interrupt vector, cannot perform ATR */
8481 if (!q_vector)
8482 return;
8483
8484 /* do nothing if sampling is disabled */
8485 if (!ring->atr_sample_rate)
8486 return;
8487
8488 ring->atr_count++;
8489
8490 /* currently only IPv4/IPv6 with TCP is supported */
8491 if ((first->protocol != htons(ETH_P_IP)) &&
8492 (first->protocol != htons(ETH_P_IPV6)))
8493 return;
8494
8495 /* snag network header to get L4 type and address */
8496 skb = first->skb;
8497 hdr.network = skb_network_header(skb);
8498 if (unlikely(hdr.network <= skb->data))
8499 return;
8500 if (skb->encapsulation &&
8501 first->protocol == htons(ETH_P_IP) &&
8502 hdr.ipv4->protocol == IPPROTO_UDP) {
8503 struct ixgbe_adapter *adapter = q_vector->adapter;
8504
8505 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8506 vxlan_headroom(0)))
8507 return;
8508
8509 /* verify the port is recognized as VXLAN */
8510 if (adapter->vxlan_port &&
8511 udp_hdr(skb)->dest == adapter->vxlan_port)
8512 hdr.network = skb_inner_network_header(skb);
8513
8514 if (adapter->geneve_port &&
8515 udp_hdr(skb)->dest == adapter->geneve_port)
8516 hdr.network = skb_inner_network_header(skb);
8517 }
8518
8519 /* Make sure we have at least [minimum IPv4 header + TCP]
8520 * or [IPv6 header] bytes
8521 */
8522 if (unlikely(skb_tail_pointer(skb) < hdr.network + 40))
8523 return;
8524
8525 /* Currently only IPv4/IPv6 with TCP is supported */
8526 switch (hdr.ipv4->version) {
8527 case IPVERSION:
8528 /* access ihl as u8 to avoid unaligned access on ia64 */
8529 hlen = (hdr.network[0] & 0x0F) << 2;
8530 l4_proto = hdr.ipv4->protocol;
8531 break;
8532 case 6:
8533 hlen = hdr.network - skb->data;
8534 l4_proto = ipv6_find_hdr(skb, &hlen, IPPROTO_TCP, NULL, NULL);
8535 hlen -= hdr.network - skb->data;
8536 break;
8537 default:
8538 return;
8539 }
8540
8541 if (l4_proto != IPPROTO_TCP)
8542 return;
8543
8544 if (unlikely(skb_tail_pointer(skb) < hdr.network +
8545 hlen + sizeof(struct tcphdr)))
8546 return;
8547
8548 th = (struct tcphdr *)(hdr.network + hlen);
8549
8550 /* skip this packet since the socket is closing */
8551 if (th->fin)
8552 return;
8553
8554 /* sample on all syn packets or once every atr sample count */
8555 if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
8556 return;
8557
8558 /* reset sample count */
8559 ring->atr_count = 0;
8560
8561 vlan_id = htons(first->tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
8562
8563 /*
8564 * src and dst are inverted, think how the receiver sees them
8565 *
8566 * The input is broken into two sections, a non-compressed section
8567 * containing vm_pool, vlan_id, and flow_type. The rest of the data
8568 * is XORed together and stored in the compressed dword.
8569 */
8570 input.formatted.vlan_id = vlan_id;
8571
8572 /*
8573 * since src port and flex bytes occupy the same word XOR them together
8574 * and write the value to source port portion of compressed dword
8575 */
8576 if (first->tx_flags & (IXGBE_TX_FLAGS_SW_VLAN | IXGBE_TX_FLAGS_HW_VLAN))
8577 common.port.src ^= th->dest ^ htons(ETH_P_8021Q);
8578 else
8579 common.port.src ^= th->dest ^ first->protocol;
8580 common.port.dst ^= th->source;
8581
8582 switch (hdr.ipv4->version) {
8583 case IPVERSION:
8584 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
8585 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
8586 break;
8587 case 6:
8588 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
8589 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
8590 hdr.ipv6->saddr.s6_addr32[1] ^
8591 hdr.ipv6->saddr.s6_addr32[2] ^
8592 hdr.ipv6->saddr.s6_addr32[3] ^
8593 hdr.ipv6->daddr.s6_addr32[0] ^
8594 hdr.ipv6->daddr.s6_addr32[1] ^
8595 hdr.ipv6->daddr.s6_addr32[2] ^
8596 hdr.ipv6->daddr.s6_addr32[3];
8597 break;
8598 default:
8599 break;
8600 }
8601
8602 if (hdr.network != skb_network_header(skb))
8603 input.formatted.flow_type |= IXGBE_ATR_L4TYPE_TUNNEL_MASK;
8604
8605 /* This assumes the Rx queue and Tx queue are bound to the same CPU */
8606 ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
8607 input, common, ring->queue_index);
8608 }
8609
8610 #ifdef IXGBE_FCOE
8611 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
8612 struct net_device *sb_dev)
8613 {
8614 struct ixgbe_adapter *adapter;
8615 struct ixgbe_ring_feature *f;
8616 int txq;
8617
8618 if (sb_dev) {
8619 u8 tc = netdev_get_prio_tc_map(dev, skb->priority);
8620 struct net_device *vdev = sb_dev;
8621
8622 txq = vdev->tc_to_txq[tc].offset;
8623 txq += reciprocal_scale(skb_get_hash(skb),
8624 vdev->tc_to_txq[tc].count);
8625
8626 return txq;
8627 }
8628
8629 /*
8630 * only execute the code below if protocol is FCoE
8631 * or FIP and we have FCoE enabled on the adapter
8632 */
8633 switch (vlan_get_protocol(skb)) {
8634 case htons(ETH_P_FCOE):
8635 case htons(ETH_P_FIP):
8636 adapter = netdev_priv(dev);
8637
8638 if (!sb_dev && (adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
8639 break;
8640 fallthrough;
8641 default:
8642 return netdev_pick_tx(dev, skb, sb_dev);
8643 }
8644
8645 f = &adapter->ring_feature[RING_F_FCOE];
8646
8647 txq = skb_rx_queue_recorded(skb) ? skb_get_rx_queue(skb) :
8648 smp_processor_id();
8649
8650 while (txq >= f->indices)
8651 txq -= f->indices;
8652
8653 return txq + f->offset;
8654 }
8655
8656 #endif
8657 int ixgbe_xmit_xdp_ring(struct ixgbe_ring *ring,
8658 struct xdp_frame *xdpf)
8659 {
8660 struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
8661 u8 nr_frags = unlikely(xdp_frame_has_frags(xdpf)) ? sinfo->nr_frags : 0;
8662 u16 i = 0, index = ring->next_to_use;
8663 struct ixgbe_tx_buffer *tx_head = &ring->tx_buffer_info[index];
8664 struct ixgbe_tx_buffer *tx_buff = tx_head;
8665 union ixgbe_adv_tx_desc *tx_desc = IXGBE_TX_DESC(ring, index);
8666 u32 cmd_type, len = xdpf->len;
8667 void *data = xdpf->data;
8668
8669 if (unlikely(ixgbe_desc_unused(ring) < 1 + nr_frags))
8670 return IXGBE_XDP_CONSUMED;
8671
8672 tx_head->bytecount = xdp_get_frame_len(xdpf);
8673 tx_head->gso_segs = 1;
8674 tx_head->xdpf = xdpf;
8675
8676 tx_desc->read.olinfo_status =
8677 cpu_to_le32(tx_head->bytecount << IXGBE_ADVTXD_PAYLEN_SHIFT);
8678
8679 for (;;) {
8680 dma_addr_t dma;
8681
8682 dma = dma_map_single(ring->dev, data, len, DMA_TO_DEVICE);
8683 if (dma_mapping_error(ring->dev, dma))
8684 goto unmap;
8685
8686 dma_unmap_len_set(tx_buff, len, len);
8687 dma_unmap_addr_set(tx_buff, dma, dma);
8688
8689 cmd_type = IXGBE_ADVTXD_DTYP_DATA | IXGBE_ADVTXD_DCMD_DEXT |
8690 IXGBE_ADVTXD_DCMD_IFCS | len;
8691 tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);
8692 tx_desc->read.buffer_addr = cpu_to_le64(dma);
8693 tx_buff->protocol = 0;
8694
8695 if (++index == ring->count)
8696 index = 0;
8697
8698 if (i == nr_frags)
8699 break;
8700
8701 tx_buff = &ring->tx_buffer_info[index];
8702 tx_desc = IXGBE_TX_DESC(ring, index);
8703 tx_desc->read.olinfo_status = 0;
8704
8705 data = skb_frag_address(&sinfo->frags[i]);
8706 len = skb_frag_size(&sinfo->frags[i]);
8707 i++;
8708 }
8709 /* put descriptor type bits */
8710 tx_desc->read.cmd_type_len |= cpu_to_le32(IXGBE_TXD_CMD);
8711
8712 /* Avoid any potential race with xdp_xmit and cleanup */
8713 smp_wmb();
8714
8715 tx_head->next_to_watch = tx_desc;
8716 ring->next_to_use = index;
8717
8718 return IXGBE_XDP_TX;
8719
8720 unmap:
8721 for (;;) {
8722 tx_buff = &ring->tx_buffer_info[index];
8723 if (dma_unmap_len(tx_buff, len))
8724 dma_unmap_page(ring->dev, dma_unmap_addr(tx_buff, dma),
8725 dma_unmap_len(tx_buff, len),
8726 DMA_TO_DEVICE);
8727 dma_unmap_len_set(tx_buff, len, 0);
8728 if (tx_buff == tx_head)
8729 break;
8730
8731 if (!index)
8732 index += ring->count;
8733 index--;
8734 }
8735
8736 return IXGBE_XDP_CONSUMED;
8737 }
8738
8739 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
8740 struct ixgbe_adapter *adapter,
8741 struct ixgbe_ring *tx_ring)
8742 {
8743 struct ixgbe_tx_buffer *first;
8744 int tso;
8745 u32 tx_flags = 0;
8746 unsigned short f;
8747 u16 count = TXD_USE_COUNT(skb_headlen(skb));
8748 struct ixgbe_ipsec_tx_data ipsec_tx = { 0 };
8749 __be16 protocol = skb->protocol;
8750 u8 hdr_len = 0;
8751
8752 /*
8753 * need: 1 descriptor per page * PAGE_SIZE/IXGBE_MAX_DATA_PER_TXD,
8754 * + 1 desc for skb_headlen/IXGBE_MAX_DATA_PER_TXD,
8755 * + 2 desc gap to keep tail from touching head,
8756 * + 1 desc for context descriptor,
8757 * otherwise try next time
8758 */
8759 for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
8760 count += TXD_USE_COUNT(skb_frag_size(
8761 &skb_shinfo(skb)->frags[f]));
8762
8763 if (ixgbe_maybe_stop_tx(tx_ring, count + 3)) {
8764 tx_ring->tx_stats.tx_busy++;
8765 return NETDEV_TX_BUSY;
8766 }
8767
8768 /* record the location of the first descriptor for this packet */
8769 first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
8770 first->skb = skb;
8771 first->bytecount = skb->len;
8772 first->gso_segs = 1;
8773
8774 /* if we have a HW VLAN tag being added default to the HW one */
8775 if (skb_vlan_tag_present(skb)) {
8776 tx_flags |= skb_vlan_tag_get(skb) << IXGBE_TX_FLAGS_VLAN_SHIFT;
8777 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8778 /* else if it is a SW VLAN check the next protocol and store the tag */
8779 } else if (protocol == htons(ETH_P_8021Q)) {
8780 struct vlan_hdr *vhdr, _vhdr;
8781 vhdr = skb_header_pointer(skb, ETH_HLEN, sizeof(_vhdr), &_vhdr);
8782 if (!vhdr)
8783 goto out_drop;
8784
8785 tx_flags |= ntohs(vhdr->h_vlan_TCI) <<
8786 IXGBE_TX_FLAGS_VLAN_SHIFT;
8787 tx_flags |= IXGBE_TX_FLAGS_SW_VLAN;
8788 }
8789 protocol = vlan_get_protocol(skb);
8790
8791 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
8792 adapter->ptp_clock) {
8793 if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
8794 !test_and_set_bit_lock(__IXGBE_PTP_TX_IN_PROGRESS,
8795 &adapter->state)) {
8796 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
8797 tx_flags |= IXGBE_TX_FLAGS_TSTAMP;
8798
8799 /* schedule check for Tx timestamp */
8800 adapter->ptp_tx_skb = skb_get(skb);
8801 adapter->ptp_tx_start = jiffies;
8802 schedule_work(&adapter->ptp_tx_work);
8803 } else {
8804 adapter->tx_hwtstamp_skipped++;
8805 }
8806 }
8807
8808 #ifdef CONFIG_PCI_IOV
8809 /*
8810 * Use the l2switch_enable flag - would be false if the DMA
8811 * Tx switch had been disabled.
8812 */
8813 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
8814 tx_flags |= IXGBE_TX_FLAGS_CC;
8815
8816 #endif
8817 /* DCB maps skb priorities 0-7 onto 3 bit PCP of VLAN tag. */
8818 if ((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
8819 ((tx_flags & (IXGBE_TX_FLAGS_HW_VLAN | IXGBE_TX_FLAGS_SW_VLAN)) ||
8820 (skb->priority != TC_PRIO_CONTROL))) {
8821 tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
8822 tx_flags |= (skb->priority & 0x7) <<
8823 IXGBE_TX_FLAGS_VLAN_PRIO_SHIFT;
8824 if (tx_flags & IXGBE_TX_FLAGS_SW_VLAN) {
8825 struct vlan_ethhdr *vhdr;
8826
8827 if (skb_cow_head(skb, 0))
8828 goto out_drop;
8829 vhdr = skb_vlan_eth_hdr(skb);
8830 vhdr->h_vlan_TCI = htons(tx_flags >>
8831 IXGBE_TX_FLAGS_VLAN_SHIFT);
8832 } else {
8833 tx_flags |= IXGBE_TX_FLAGS_HW_VLAN;
8834 }
8835 }
8836
8837 /* record initial flags and protocol */
8838 first->tx_flags = tx_flags;
8839 first->protocol = protocol;
8840
8841 #ifdef IXGBE_FCOE
8842 /* setup tx offload for FCoE */
8843 if ((protocol == htons(ETH_P_FCOE)) &&
8844 (tx_ring->netdev->features & (NETIF_F_FSO | NETIF_F_FCOE_CRC))) {
8845 tso = ixgbe_fso(tx_ring, first, &hdr_len);
8846 if (tso < 0)
8847 goto out_drop;
8848
8849 goto xmit_fcoe;
8850 }
8851
8852 #endif /* IXGBE_FCOE */
8853
8854 #ifdef CONFIG_IXGBE_IPSEC
8855 if (xfrm_offload(skb) &&
8856 !ixgbe_ipsec_tx(tx_ring, first, &ipsec_tx))
8857 goto out_drop;
8858 #endif
8859 tso = ixgbe_tso(tx_ring, first, &hdr_len, &ipsec_tx);
8860 if (tso < 0)
8861 goto out_drop;
8862 else if (!tso)
8863 ixgbe_tx_csum(tx_ring, first, &ipsec_tx);
8864
8865 /* add the ATR filter if ATR is on */
8866 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
8867 ixgbe_atr(tx_ring, first);
8868
8869 #ifdef IXGBE_FCOE
8870 xmit_fcoe:
8871 #endif /* IXGBE_FCOE */
8872 if (ixgbe_tx_map(tx_ring, first, hdr_len))
8873 goto cleanup_tx_timestamp;
8874
8875 return NETDEV_TX_OK;
8876
8877 out_drop:
8878 dev_kfree_skb_any(first->skb);
8879 first->skb = NULL;
8880 cleanup_tx_timestamp:
8881 if (unlikely(tx_flags & IXGBE_TX_FLAGS_TSTAMP)) {
8882 dev_kfree_skb_any(adapter->ptp_tx_skb);
8883 adapter->ptp_tx_skb = NULL;
8884 cancel_work_sync(&adapter->ptp_tx_work);
8885 clear_bit_unlock(__IXGBE_PTP_TX_IN_PROGRESS, &adapter->state);
8886 }
8887
8888 return NETDEV_TX_OK;
8889 }
8890
8891 static netdev_tx_t __ixgbe_xmit_frame(struct sk_buff *skb,
8892 struct net_device *netdev,
8893 struct ixgbe_ring *ring)
8894 {
8895 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8896 struct ixgbe_ring *tx_ring;
8897
8898 /*
8899 * The minimum packet size for olinfo paylen is 17 so pad the skb
8900 * in order to meet this minimum size requirement.
8901 */
8902 if (skb_put_padto(skb, 17))
8903 return NETDEV_TX_OK;
8904
8905 tx_ring = ring ? ring : adapter->tx_ring[skb_get_queue_mapping(skb)];
8906 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &tx_ring->state)))
8907 return NETDEV_TX_BUSY;
8908
8909 return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
8910 }
8911
8912 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
8913 struct net_device *netdev)
8914 {
8915 return __ixgbe_xmit_frame(skb, netdev, NULL);
8916 }
8917
8918 /**
8919 * ixgbe_set_mac - Change the Ethernet Address of the NIC
8920 * @netdev: network interface device structure
8921 * @p: pointer to an address structure
8922 *
8923 * Returns 0 on success, negative on failure
8924 **/
8925 static int ixgbe_set_mac(struct net_device *netdev, void *p)
8926 {
8927 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8928 struct ixgbe_hw *hw = &adapter->hw;
8929 struct sockaddr *addr = p;
8930
8931 if (!is_valid_ether_addr(addr->sa_data))
8932 return -EADDRNOTAVAIL;
8933
8934 eth_hw_addr_set(netdev, addr->sa_data);
8935 memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
8936
8937 ixgbe_mac_set_default_filter(adapter);
8938
8939 return 0;
8940 }
8941
8942 static int
8943 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
8944 {
8945 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8946 struct ixgbe_hw *hw = &adapter->hw;
8947 u16 value;
8948 int rc;
8949
8950 if (adapter->mii_bus) {
8951 int regnum = addr;
8952
8953 if (devad != MDIO_DEVAD_NONE)
8954 return mdiobus_c45_read(adapter->mii_bus, prtad,
8955 devad, regnum);
8956
8957 return mdiobus_read(adapter->mii_bus, prtad, regnum);
8958 }
8959
8960 if (prtad != hw->phy.mdio.prtad)
8961 return -EINVAL;
8962 rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
8963 if (!rc)
8964 rc = value;
8965 return rc;
8966 }
8967
8968 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
8969 u16 addr, u16 value)
8970 {
8971 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8972 struct ixgbe_hw *hw = &adapter->hw;
8973
8974 if (adapter->mii_bus) {
8975 int regnum = addr;
8976
8977 if (devad != MDIO_DEVAD_NONE)
8978 return mdiobus_c45_write(adapter->mii_bus, prtad, devad,
8979 regnum, value);
8980
8981 return mdiobus_write(adapter->mii_bus, prtad, regnum, value);
8982 }
8983
8984 if (prtad != hw->phy.mdio.prtad)
8985 return -EINVAL;
8986 return hw->phy.ops.write_reg(hw, addr, devad, value);
8987 }
8988
8989 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
8990 {
8991 struct ixgbe_adapter *adapter = netdev_priv(netdev);
8992
8993 switch (cmd) {
8994 case SIOCSHWTSTAMP:
8995 return ixgbe_ptp_set_ts_config(adapter, req);
8996 case SIOCGHWTSTAMP:
8997 return ixgbe_ptp_get_ts_config(adapter, req);
8998 case SIOCGMIIPHY:
8999 if (!adapter->hw.phy.ops.read_reg)
9000 return -EOPNOTSUPP;
9001 fallthrough;
9002 default:
9003 return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
9004 }
9005 }
9006
9007 /**
9008 * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
9009 * netdev->dev_addrs
9010 * @dev: network interface device structure
9011 *
9012 * Returns non-zero on failure
9013 **/
9014 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
9015 {
9016 int err = 0;
9017 struct ixgbe_adapter *adapter = netdev_priv(dev);
9018 struct ixgbe_hw *hw = &adapter->hw;
9019
9020 if (is_valid_ether_addr(hw->mac.san_addr)) {
9021 rtnl_lock();
9022 err = dev_addr_add(dev, hw->mac.san_addr, NETDEV_HW_ADDR_T_SAN);
9023 rtnl_unlock();
9024
9025 /* update SAN MAC vmdq pool selection */
9026 hw->mac.ops.set_vmdq_san_mac(hw, VMDQ_P(0));
9027 }
9028 return err;
9029 }
9030
9031 /**
9032 * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
9033 * netdev->dev_addrs
9034 * @dev: network interface device structure
9035 *
9036 * Returns non-zero on failure
9037 **/
9038 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
9039 {
9040 int err = 0;
9041 struct ixgbe_adapter *adapter = netdev_priv(dev);
9042 struct ixgbe_mac_info *mac = &adapter->hw.mac;
9043
9044 if (is_valid_ether_addr(mac->san_addr)) {
9045 rtnl_lock();
9046 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
9047 rtnl_unlock();
9048 }
9049 return err;
9050 }
9051
9052 static void ixgbe_get_ring_stats64(struct rtnl_link_stats64 *stats,
9053 struct ixgbe_ring *ring)
9054 {
9055 u64 bytes, packets;
9056 unsigned int start;
9057
9058 if (ring) {
9059 do {
9060 start = u64_stats_fetch_begin(&ring->syncp);
9061 packets = ring->stats.packets;
9062 bytes = ring->stats.bytes;
9063 } while (u64_stats_fetch_retry(&ring->syncp, start));
9064 stats->tx_packets += packets;
9065 stats->tx_bytes += bytes;
9066 }
9067 }
9068
9069 static void ixgbe_get_stats64(struct net_device *netdev,
9070 struct rtnl_link_stats64 *stats)
9071 {
9072 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9073 int i;
9074
9075 rcu_read_lock();
9076 for (i = 0; i < adapter->num_rx_queues; i++) {
9077 struct ixgbe_ring *ring = READ_ONCE(adapter->rx_ring[i]);
9078 u64 bytes, packets;
9079 unsigned int start;
9080
9081 if (ring) {
9082 do {
9083 start = u64_stats_fetch_begin(&ring->syncp);
9084 packets = ring->stats.packets;
9085 bytes = ring->stats.bytes;
9086 } while (u64_stats_fetch_retry(&ring->syncp, start));
9087 stats->rx_packets += packets;
9088 stats->rx_bytes += bytes;
9089 }
9090 }
9091
9092 for (i = 0; i < adapter->num_tx_queues; i++) {
9093 struct ixgbe_ring *ring = READ_ONCE(adapter->tx_ring[i]);
9094
9095 ixgbe_get_ring_stats64(stats, ring);
9096 }
9097 for (i = 0; i < adapter->num_xdp_queues; i++) {
9098 struct ixgbe_ring *ring = READ_ONCE(adapter->xdp_ring[i]);
9099
9100 ixgbe_get_ring_stats64(stats, ring);
9101 }
9102 rcu_read_unlock();
9103
9104 /* following stats updated by ixgbe_watchdog_task() */
9105 stats->multicast = netdev->stats.multicast;
9106 stats->rx_errors = netdev->stats.rx_errors;
9107 stats->rx_length_errors = netdev->stats.rx_length_errors;
9108 stats->rx_crc_errors = netdev->stats.rx_crc_errors;
9109 stats->rx_missed_errors = netdev->stats.rx_missed_errors;
9110 }
9111
9112 static int ixgbe_ndo_get_vf_stats(struct net_device *netdev, int vf,
9113 struct ifla_vf_stats *vf_stats)
9114 {
9115 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9116
9117 if (vf < 0 || vf >= adapter->num_vfs)
9118 return -EINVAL;
9119
9120 vf_stats->rx_packets = adapter->vfinfo[vf].vfstats.gprc;
9121 vf_stats->rx_bytes = adapter->vfinfo[vf].vfstats.gorc;
9122 vf_stats->tx_packets = adapter->vfinfo[vf].vfstats.gptc;
9123 vf_stats->tx_bytes = adapter->vfinfo[vf].vfstats.gotc;
9124 vf_stats->multicast = adapter->vfinfo[vf].vfstats.mprc;
9125
9126 return 0;
9127 }
9128
9129 #ifdef CONFIG_IXGBE_DCB
9130 /**
9131 * ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
9132 * @adapter: pointer to ixgbe_adapter
9133 * @tc: number of traffic classes currently enabled
9134 *
9135 * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
9136 * 802.1Q priority maps to a packet buffer that exists.
9137 */
9138 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
9139 {
9140 struct ixgbe_hw *hw = &adapter->hw;
9141 u32 reg, rsave;
9142 int i;
9143
9144 /* 82598 have a static priority to TC mapping that can not
9145 * be changed so no validation is needed.
9146 */
9147 if (hw->mac.type == ixgbe_mac_82598EB)
9148 return;
9149
9150 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
9151 rsave = reg;
9152
9153 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
9154 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
9155
9156 /* If up2tc is out of bounds default to zero */
9157 if (up2tc > tc)
9158 reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
9159 }
9160
9161 if (reg != rsave)
9162 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
9163
9164 return;
9165 }
9166
9167 /**
9168 * ixgbe_set_prio_tc_map - Configure netdev prio tc map
9169 * @adapter: Pointer to adapter struct
9170 *
9171 * Populate the netdev user priority to tc map
9172 */
9173 static void ixgbe_set_prio_tc_map(struct ixgbe_adapter *adapter)
9174 {
9175 struct net_device *dev = adapter->netdev;
9176 struct ixgbe_dcb_config *dcb_cfg = &adapter->dcb_cfg;
9177 struct ieee_ets *ets = adapter->ixgbe_ieee_ets;
9178 u8 prio;
9179
9180 for (prio = 0; prio < MAX_USER_PRIORITY; prio++) {
9181 u8 tc = 0;
9182
9183 if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE)
9184 tc = ixgbe_dcb_get_tc_from_up(dcb_cfg, 0, prio);
9185 else if (ets)
9186 tc = ets->prio_tc[prio];
9187
9188 netdev_set_prio_tc_map(dev, prio, tc);
9189 }
9190 }
9191
9192 #endif /* CONFIG_IXGBE_DCB */
9193 static int ixgbe_reassign_macvlan_pool(struct net_device *vdev,
9194 struct netdev_nested_priv *priv)
9195 {
9196 struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)priv->data;
9197 struct ixgbe_fwd_adapter *accel;
9198 int pool;
9199
9200 /* we only care about macvlans... */
9201 if (!netif_is_macvlan(vdev))
9202 return 0;
9203
9204 /* that have hardware offload enabled... */
9205 accel = macvlan_accel_priv(vdev);
9206 if (!accel)
9207 return 0;
9208
9209 /* If we can relocate to a different bit do so */
9210 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
9211 if (pool < adapter->num_rx_pools) {
9212 set_bit(pool, adapter->fwd_bitmask);
9213 accel->pool = pool;
9214 return 0;
9215 }
9216
9217 /* if we cannot find a free pool then disable the offload */
9218 netdev_err(vdev, "L2FW offload disabled due to lack of queue resources\n");
9219 macvlan_release_l2fw_offload(vdev);
9220
9221 /* unbind the queues and drop the subordinate channel config */
9222 netdev_unbind_sb_channel(adapter->netdev, vdev);
9223 netdev_set_sb_channel(vdev, 0);
9224
9225 kfree(accel);
9226
9227 return 0;
9228 }
9229
9230 static void ixgbe_defrag_macvlan_pools(struct net_device *dev)
9231 {
9232 struct ixgbe_adapter *adapter = netdev_priv(dev);
9233 struct netdev_nested_priv priv = {
9234 .data = (void *)adapter,
9235 };
9236
9237 /* flush any stale bits out of the fwd bitmask */
9238 bitmap_clear(adapter->fwd_bitmask, 1, 63);
9239
9240 /* walk through upper devices reassigning pools */
9241 netdev_walk_all_upper_dev_rcu(dev, ixgbe_reassign_macvlan_pool,
9242 &priv);
9243 }
9244
9245 /**
9246 * ixgbe_setup_tc - configure net_device for multiple traffic classes
9247 *
9248 * @dev: net device to configure
9249 * @tc: number of traffic classes to enable
9250 */
9251 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
9252 {
9253 struct ixgbe_adapter *adapter = netdev_priv(dev);
9254 struct ixgbe_hw *hw = &adapter->hw;
9255
9256 /* Hardware supports up to 8 traffic classes */
9257 if (tc > adapter->dcb_cfg.num_tcs.pg_tcs)
9258 return -EINVAL;
9259
9260 if (hw->mac.type == ixgbe_mac_82598EB && tc && tc < MAX_TRAFFIC_CLASS)
9261 return -EINVAL;
9262
9263 /* Hardware has to reinitialize queues and interrupts to
9264 * match packet buffer alignment. Unfortunately, the
9265 * hardware is not flexible enough to do this dynamically.
9266 */
9267 if (netif_running(dev))
9268 ixgbe_close(dev);
9269 else
9270 ixgbe_reset(adapter);
9271
9272 ixgbe_clear_interrupt_scheme(adapter);
9273
9274 #ifdef CONFIG_IXGBE_DCB
9275 if (tc) {
9276 if (adapter->xdp_prog) {
9277 e_warn(probe, "DCB is not supported with XDP\n");
9278
9279 ixgbe_init_interrupt_scheme(adapter);
9280 if (netif_running(dev))
9281 ixgbe_open(dev);
9282 return -EINVAL;
9283 }
9284
9285 netdev_set_num_tc(dev, tc);
9286 ixgbe_set_prio_tc_map(adapter);
9287
9288 adapter->hw_tcs = tc;
9289 adapter->flags |= IXGBE_FLAG_DCB_ENABLED;
9290
9291 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
9292 adapter->last_lfc_mode = adapter->hw.fc.requested_mode;
9293 adapter->hw.fc.requested_mode = ixgbe_fc_none;
9294 }
9295 } else {
9296 netdev_reset_tc(dev);
9297
9298 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
9299 adapter->hw.fc.requested_mode = adapter->last_lfc_mode;
9300
9301 adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
9302 adapter->hw_tcs = tc;
9303
9304 adapter->temp_dcb_cfg.pfc_mode_enable = false;
9305 adapter->dcb_cfg.pfc_mode_enable = false;
9306 }
9307
9308 ixgbe_validate_rtr(adapter, tc);
9309
9310 #endif /* CONFIG_IXGBE_DCB */
9311 ixgbe_init_interrupt_scheme(adapter);
9312
9313 ixgbe_defrag_macvlan_pools(dev);
9314
9315 if (netif_running(dev))
9316 return ixgbe_open(dev);
9317
9318 return 0;
9319 }
9320
9321 static int ixgbe_delete_clsu32(struct ixgbe_adapter *adapter,
9322 struct tc_cls_u32_offload *cls)
9323 {
9324 u32 hdl = cls->knode.handle;
9325 u32 uhtid = TC_U32_USERHTID(cls->knode.handle);
9326 u32 loc = cls->knode.handle & 0xfffff;
9327 int err = 0, i, j;
9328 struct ixgbe_jump_table *jump = NULL;
9329
9330 if (loc > IXGBE_MAX_HW_ENTRIES)
9331 return -EINVAL;
9332
9333 if ((uhtid != 0x800) && (uhtid >= IXGBE_MAX_LINK_HANDLE))
9334 return -EINVAL;
9335
9336 /* Clear this filter in the link data it is associated with */
9337 if (uhtid != 0x800) {
9338 jump = adapter->jump_tables[uhtid];
9339 if (!jump)
9340 return -EINVAL;
9341 if (!test_bit(loc - 1, jump->child_loc_map))
9342 return -EINVAL;
9343 clear_bit(loc - 1, jump->child_loc_map);
9344 }
9345
9346 /* Check if the filter being deleted is a link */
9347 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9348 jump = adapter->jump_tables[i];
9349 if (jump && jump->link_hdl == hdl) {
9350 /* Delete filters in the hardware in the child hash
9351 * table associated with this link
9352 */
9353 for (j = 0; j < IXGBE_MAX_HW_ENTRIES; j++) {
9354 if (!test_bit(j, jump->child_loc_map))
9355 continue;
9356 spin_lock(&adapter->fdir_perfect_lock);
9357 err = ixgbe_update_ethtool_fdir_entry(adapter,
9358 NULL,
9359 j + 1);
9360 spin_unlock(&adapter->fdir_perfect_lock);
9361 clear_bit(j, jump->child_loc_map);
9362 }
9363 /* Remove resources for this link */
9364 kfree(jump->input);
9365 kfree(jump->mask);
9366 kfree(jump);
9367 adapter->jump_tables[i] = NULL;
9368 return err;
9369 }
9370 }
9371
9372 spin_lock(&adapter->fdir_perfect_lock);
9373 err = ixgbe_update_ethtool_fdir_entry(adapter, NULL, loc);
9374 spin_unlock(&adapter->fdir_perfect_lock);
9375 return err;
9376 }
9377
9378 static int ixgbe_configure_clsu32_add_hnode(struct ixgbe_adapter *adapter,
9379 struct tc_cls_u32_offload *cls)
9380 {
9381 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9382
9383 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9384 return -EINVAL;
9385
9386 /* This ixgbe devices do not support hash tables at the moment
9387 * so abort when given hash tables.
9388 */
9389 if (cls->hnode.divisor > 0)
9390 return -EINVAL;
9391
9392 set_bit(uhtid - 1, &adapter->tables);
9393 return 0;
9394 }
9395
9396 static int ixgbe_configure_clsu32_del_hnode(struct ixgbe_adapter *adapter,
9397 struct tc_cls_u32_offload *cls)
9398 {
9399 u32 uhtid = TC_U32_USERHTID(cls->hnode.handle);
9400
9401 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9402 return -EINVAL;
9403
9404 clear_bit(uhtid - 1, &adapter->tables);
9405 return 0;
9406 }
9407
9408 #ifdef CONFIG_NET_CLS_ACT
9409 struct upper_walk_data {
9410 struct ixgbe_adapter *adapter;
9411 u64 action;
9412 int ifindex;
9413 u8 queue;
9414 };
9415
9416 static int get_macvlan_queue(struct net_device *upper,
9417 struct netdev_nested_priv *priv)
9418 {
9419 if (netif_is_macvlan(upper)) {
9420 struct ixgbe_fwd_adapter *vadapter = macvlan_accel_priv(upper);
9421 struct ixgbe_adapter *adapter;
9422 struct upper_walk_data *data;
9423 int ifindex;
9424
9425 data = (struct upper_walk_data *)priv->data;
9426 ifindex = data->ifindex;
9427 adapter = data->adapter;
9428 if (vadapter && upper->ifindex == ifindex) {
9429 data->queue = adapter->rx_ring[vadapter->rx_base_queue]->reg_idx;
9430 data->action = data->queue;
9431 return 1;
9432 }
9433 }
9434
9435 return 0;
9436 }
9437
9438 static int handle_redirect_action(struct ixgbe_adapter *adapter, int ifindex,
9439 u8 *queue, u64 *action)
9440 {
9441 struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
9442 unsigned int num_vfs = adapter->num_vfs, vf;
9443 struct netdev_nested_priv priv;
9444 struct upper_walk_data data;
9445 struct net_device *upper;
9446
9447 /* redirect to a SRIOV VF */
9448 for (vf = 0; vf < num_vfs; ++vf) {
9449 upper = pci_get_drvdata(adapter->vfinfo[vf].vfdev);
9450 if (upper->ifindex == ifindex) {
9451 *queue = vf * __ALIGN_MASK(1, ~vmdq->mask);
9452 *action = vf + 1;
9453 *action <<= ETHTOOL_RX_FLOW_SPEC_RING_VF_OFF;
9454 return 0;
9455 }
9456 }
9457
9458 /* redirect to a offloaded macvlan netdev */
9459 data.adapter = adapter;
9460 data.ifindex = ifindex;
9461 data.action = 0;
9462 data.queue = 0;
9463 priv.data = (void *)&data;
9464 if (netdev_walk_all_upper_dev_rcu(adapter->netdev,
9465 get_macvlan_queue, &priv)) {
9466 *action = data.action;
9467 *queue = data.queue;
9468
9469 return 0;
9470 }
9471
9472 return -EINVAL;
9473 }
9474
9475 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9476 struct tcf_exts *exts, u64 *action, u8 *queue)
9477 {
9478 const struct tc_action *a;
9479 int i;
9480
9481 if (!tcf_exts_has_actions(exts))
9482 return -EINVAL;
9483
9484 tcf_exts_for_each_action(i, a, exts) {
9485 /* Drop action */
9486 if (is_tcf_gact_shot(a)) {
9487 *action = IXGBE_FDIR_DROP_QUEUE;
9488 *queue = IXGBE_FDIR_DROP_QUEUE;
9489 return 0;
9490 }
9491
9492 /* Redirect to a VF or a offloaded macvlan */
9493 if (is_tcf_mirred_egress_redirect(a)) {
9494 struct net_device *dev = tcf_mirred_dev(a);
9495
9496 if (!dev)
9497 return -EINVAL;
9498 return handle_redirect_action(adapter, dev->ifindex,
9499 queue, action);
9500 }
9501
9502 return -EINVAL;
9503 }
9504
9505 return -EINVAL;
9506 }
9507 #else
9508 static int parse_tc_actions(struct ixgbe_adapter *adapter,
9509 struct tcf_exts *exts, u64 *action, u8 *queue)
9510 {
9511 return -EINVAL;
9512 }
9513 #endif /* CONFIG_NET_CLS_ACT */
9514
9515 static int ixgbe_clsu32_build_input(struct ixgbe_fdir_filter *input,
9516 union ixgbe_atr_input *mask,
9517 struct tc_cls_u32_offload *cls,
9518 struct ixgbe_mat_field *field_ptr,
9519 struct ixgbe_nexthdr *nexthdr)
9520 {
9521 int i, j, off;
9522 __be32 val, m;
9523 bool found_entry = false, found_jump_field = false;
9524
9525 for (i = 0; i < cls->knode.sel->nkeys; i++) {
9526 off = cls->knode.sel->keys[i].off;
9527 val = cls->knode.sel->keys[i].val;
9528 m = cls->knode.sel->keys[i].mask;
9529
9530 for (j = 0; field_ptr[j].val; j++) {
9531 if (field_ptr[j].off == off) {
9532 field_ptr[j].val(input, mask, (__force u32)val,
9533 (__force u32)m);
9534 input->filter.formatted.flow_type |=
9535 field_ptr[j].type;
9536 found_entry = true;
9537 break;
9538 }
9539 }
9540 if (nexthdr) {
9541 if (nexthdr->off == cls->knode.sel->keys[i].off &&
9542 nexthdr->val ==
9543 (__force u32)cls->knode.sel->keys[i].val &&
9544 nexthdr->mask ==
9545 (__force u32)cls->knode.sel->keys[i].mask)
9546 found_jump_field = true;
9547 else
9548 continue;
9549 }
9550 }
9551
9552 if (nexthdr && !found_jump_field)
9553 return -EINVAL;
9554
9555 if (!found_entry)
9556 return 0;
9557
9558 mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
9559 IXGBE_ATR_L4TYPE_MASK;
9560
9561 if (input->filter.formatted.flow_type == IXGBE_ATR_FLOW_TYPE_IPV4)
9562 mask->formatted.flow_type &= IXGBE_ATR_L4TYPE_IPV6_MASK;
9563
9564 return 0;
9565 }
9566
9567 static int ixgbe_configure_clsu32(struct ixgbe_adapter *adapter,
9568 struct tc_cls_u32_offload *cls)
9569 {
9570 __be16 protocol = cls->common.protocol;
9571 u32 loc = cls->knode.handle & 0xfffff;
9572 struct ixgbe_hw *hw = &adapter->hw;
9573 struct ixgbe_mat_field *field_ptr;
9574 struct ixgbe_fdir_filter *input = NULL;
9575 union ixgbe_atr_input *mask = NULL;
9576 struct ixgbe_jump_table *jump = NULL;
9577 int i, err = -EINVAL;
9578 u8 queue;
9579 u32 uhtid, link_uhtid;
9580
9581 uhtid = TC_U32_USERHTID(cls->knode.handle);
9582 link_uhtid = TC_U32_USERHTID(cls->knode.link_handle);
9583
9584 /* At the moment cls_u32 jumps to network layer and skips past
9585 * L2 headers. The canonical method to match L2 frames is to use
9586 * negative values. However this is error prone at best but really
9587 * just broken because there is no way to "know" what sort of hdr
9588 * is in front of the network layer. Fix cls_u32 to support L2
9589 * headers when needed.
9590 */
9591 if (protocol != htons(ETH_P_IP))
9592 return err;
9593
9594 if (loc >= ((1024 << adapter->fdir_pballoc) - 2)) {
9595 e_err(drv, "Location out of range\n");
9596 return err;
9597 }
9598
9599 /* cls u32 is a graph starting at root node 0x800. The driver tracks
9600 * links and also the fields used to advance the parser across each
9601 * link (e.g. nexthdr/eat parameters from 'tc'). This way we can map
9602 * the u32 graph onto the hardware parse graph denoted in ixgbe_model.h
9603 * To add support for new nodes update ixgbe_model.h parse structures
9604 * this function _should_ be generic try not to hardcode values here.
9605 */
9606 if (uhtid == 0x800) {
9607 field_ptr = (adapter->jump_tables[0])->mat;
9608 } else {
9609 if (uhtid >= IXGBE_MAX_LINK_HANDLE)
9610 return err;
9611 if (!adapter->jump_tables[uhtid])
9612 return err;
9613 field_ptr = (adapter->jump_tables[uhtid])->mat;
9614 }
9615
9616 if (!field_ptr)
9617 return err;
9618
9619 /* At this point we know the field_ptr is valid and need to either
9620 * build cls_u32 link or attach filter. Because adding a link to
9621 * a handle that does not exist is invalid and the same for adding
9622 * rules to handles that don't exist.
9623 */
9624
9625 if (link_uhtid) {
9626 struct ixgbe_nexthdr *nexthdr = ixgbe_ipv4_jumps;
9627
9628 if (link_uhtid >= IXGBE_MAX_LINK_HANDLE)
9629 return err;
9630
9631 if (!test_bit(link_uhtid - 1, &adapter->tables))
9632 return err;
9633
9634 /* Multiple filters as links to the same hash table are not
9635 * supported. To add a new filter with the same next header
9636 * but different match/jump conditions, create a new hash table
9637 * and link to it.
9638 */
9639 if (adapter->jump_tables[link_uhtid] &&
9640 (adapter->jump_tables[link_uhtid])->link_hdl) {
9641 e_err(drv, "Link filter exists for link: %x\n",
9642 link_uhtid);
9643 return err;
9644 }
9645
9646 for (i = 0; nexthdr[i].jump; i++) {
9647 if (nexthdr[i].o != cls->knode.sel->offoff ||
9648 nexthdr[i].s != cls->knode.sel->offshift ||
9649 nexthdr[i].m !=
9650 (__force u32)cls->knode.sel->offmask)
9651 return err;
9652
9653 jump = kzalloc(sizeof(*jump), GFP_KERNEL);
9654 if (!jump)
9655 return -ENOMEM;
9656 input = kzalloc(sizeof(*input), GFP_KERNEL);
9657 if (!input) {
9658 err = -ENOMEM;
9659 goto free_jump;
9660 }
9661 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9662 if (!mask) {
9663 err = -ENOMEM;
9664 goto free_input;
9665 }
9666 jump->input = input;
9667 jump->mask = mask;
9668 jump->link_hdl = cls->knode.handle;
9669
9670 err = ixgbe_clsu32_build_input(input, mask, cls,
9671 field_ptr, &nexthdr[i]);
9672 if (!err) {
9673 jump->mat = nexthdr[i].jump;
9674 adapter->jump_tables[link_uhtid] = jump;
9675 break;
9676 } else {
9677 kfree(mask);
9678 kfree(input);
9679 kfree(jump);
9680 }
9681 }
9682 return 0;
9683 }
9684
9685 input = kzalloc(sizeof(*input), GFP_KERNEL);
9686 if (!input)
9687 return -ENOMEM;
9688 mask = kzalloc(sizeof(*mask), GFP_KERNEL);
9689 if (!mask) {
9690 err = -ENOMEM;
9691 goto free_input;
9692 }
9693
9694 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid])) {
9695 if ((adapter->jump_tables[uhtid])->input)
9696 memcpy(input, (adapter->jump_tables[uhtid])->input,
9697 sizeof(*input));
9698 if ((adapter->jump_tables[uhtid])->mask)
9699 memcpy(mask, (adapter->jump_tables[uhtid])->mask,
9700 sizeof(*mask));
9701
9702 /* Lookup in all child hash tables if this location is already
9703 * filled with a filter
9704 */
9705 for (i = 1; i < IXGBE_MAX_LINK_HANDLE; i++) {
9706 struct ixgbe_jump_table *link = adapter->jump_tables[i];
9707
9708 if (link && (test_bit(loc - 1, link->child_loc_map))) {
9709 e_err(drv, "Filter exists in location: %x\n",
9710 loc);
9711 err = -EINVAL;
9712 goto err_out;
9713 }
9714 }
9715 }
9716 err = ixgbe_clsu32_build_input(input, mask, cls, field_ptr, NULL);
9717 if (err)
9718 goto err_out;
9719
9720 err = parse_tc_actions(adapter, cls->knode.exts, &input->action,
9721 &queue);
9722 if (err < 0)
9723 goto err_out;
9724
9725 input->sw_idx = loc;
9726
9727 spin_lock(&adapter->fdir_perfect_lock);
9728
9729 if (hlist_empty(&adapter->fdir_filter_list)) {
9730 memcpy(&adapter->fdir_mask, mask, sizeof(*mask));
9731 err = ixgbe_fdir_set_input_mask_82599(hw, mask);
9732 if (err)
9733 goto err_out_w_lock;
9734 } else if (memcmp(&adapter->fdir_mask, mask, sizeof(*mask))) {
9735 err = -EINVAL;
9736 goto err_out_w_lock;
9737 }
9738
9739 ixgbe_atr_compute_perfect_hash_82599(&input->filter, mask);
9740 err = ixgbe_fdir_write_perfect_filter_82599(hw, &input->filter,
9741 input->sw_idx, queue);
9742 if (err)
9743 goto err_out_w_lock;
9744
9745 ixgbe_update_ethtool_fdir_entry(adapter, input, input->sw_idx);
9746 spin_unlock(&adapter->fdir_perfect_lock);
9747
9748 if ((uhtid != 0x800) && (adapter->jump_tables[uhtid]))
9749 set_bit(loc - 1, (adapter->jump_tables[uhtid])->child_loc_map);
9750
9751 kfree(mask);
9752 return err;
9753 err_out_w_lock:
9754 spin_unlock(&adapter->fdir_perfect_lock);
9755 err_out:
9756 kfree(mask);
9757 free_input:
9758 kfree(input);
9759 free_jump:
9760 kfree(jump);
9761 return err;
9762 }
9763
9764 static int ixgbe_setup_tc_cls_u32(struct ixgbe_adapter *adapter,
9765 struct tc_cls_u32_offload *cls_u32)
9766 {
9767 switch (cls_u32->command) {
9768 case TC_CLSU32_NEW_KNODE:
9769 case TC_CLSU32_REPLACE_KNODE:
9770 return ixgbe_configure_clsu32(adapter, cls_u32);
9771 case TC_CLSU32_DELETE_KNODE:
9772 return ixgbe_delete_clsu32(adapter, cls_u32);
9773 case TC_CLSU32_NEW_HNODE:
9774 case TC_CLSU32_REPLACE_HNODE:
9775 return ixgbe_configure_clsu32_add_hnode(adapter, cls_u32);
9776 case TC_CLSU32_DELETE_HNODE:
9777 return ixgbe_configure_clsu32_del_hnode(adapter, cls_u32);
9778 default:
9779 return -EOPNOTSUPP;
9780 }
9781 }
9782
9783 static int ixgbe_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
9784 void *cb_priv)
9785 {
9786 struct ixgbe_adapter *adapter = cb_priv;
9787
9788 if (!tc_cls_can_offload_and_chain0(adapter->netdev, type_data))
9789 return -EOPNOTSUPP;
9790
9791 switch (type) {
9792 case TC_SETUP_CLSU32:
9793 return ixgbe_setup_tc_cls_u32(adapter, type_data);
9794 default:
9795 return -EOPNOTSUPP;
9796 }
9797 }
9798
9799 static int ixgbe_setup_tc_mqprio(struct net_device *dev,
9800 struct tc_mqprio_qopt *mqprio)
9801 {
9802 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
9803 return ixgbe_setup_tc(dev, mqprio->num_tc);
9804 }
9805
9806 static LIST_HEAD(ixgbe_block_cb_list);
9807
9808 static int __ixgbe_setup_tc(struct net_device *dev, enum tc_setup_type type,
9809 void *type_data)
9810 {
9811 struct ixgbe_adapter *adapter = netdev_priv(dev);
9812
9813 switch (type) {
9814 case TC_SETUP_BLOCK:
9815 return flow_block_cb_setup_simple(type_data,
9816 &ixgbe_block_cb_list,
9817 ixgbe_setup_tc_block_cb,
9818 adapter, adapter, true);
9819 case TC_SETUP_QDISC_MQPRIO:
9820 return ixgbe_setup_tc_mqprio(dev, type_data);
9821 default:
9822 return -EOPNOTSUPP;
9823 }
9824 }
9825
9826 #ifdef CONFIG_PCI_IOV
9827 void ixgbe_sriov_reinit(struct ixgbe_adapter *adapter)
9828 {
9829 struct net_device *netdev = adapter->netdev;
9830
9831 rtnl_lock();
9832 ixgbe_setup_tc(netdev, adapter->hw_tcs);
9833 rtnl_unlock();
9834 }
9835
9836 #endif
9837 void ixgbe_do_reset(struct net_device *netdev)
9838 {
9839 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9840
9841 if (netif_running(netdev))
9842 ixgbe_reinit_locked(adapter);
9843 else
9844 ixgbe_reset(adapter);
9845 }
9846
9847 static netdev_features_t ixgbe_fix_features(struct net_device *netdev,
9848 netdev_features_t features)
9849 {
9850 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9851
9852 /* If Rx checksum is disabled, then RSC/LRO should also be disabled */
9853 if (!(features & NETIF_F_RXCSUM))
9854 features &= ~NETIF_F_LRO;
9855
9856 /* Turn off LRO if not RSC capable */
9857 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE))
9858 features &= ~NETIF_F_LRO;
9859
9860 if (adapter->xdp_prog && (features & NETIF_F_LRO)) {
9861 e_dev_err("LRO is not supported with XDP\n");
9862 features &= ~NETIF_F_LRO;
9863 }
9864
9865 return features;
9866 }
9867
9868 static void ixgbe_reset_l2fw_offload(struct ixgbe_adapter *adapter)
9869 {
9870 int rss = min_t(int, ixgbe_max_rss_indices(adapter),
9871 num_online_cpus());
9872
9873 /* go back to full RSS if we're not running SR-IOV */
9874 if (!adapter->ring_feature[RING_F_VMDQ].offset)
9875 adapter->flags &= ~(IXGBE_FLAG_VMDQ_ENABLED |
9876 IXGBE_FLAG_SRIOV_ENABLED);
9877
9878 adapter->ring_feature[RING_F_RSS].limit = rss;
9879 adapter->ring_feature[RING_F_VMDQ].limit = 1;
9880
9881 ixgbe_setup_tc(adapter->netdev, adapter->hw_tcs);
9882 }
9883
9884 static int ixgbe_set_features(struct net_device *netdev,
9885 netdev_features_t features)
9886 {
9887 struct ixgbe_adapter *adapter = netdev_priv(netdev);
9888 netdev_features_t changed = netdev->features ^ features;
9889 bool need_reset = false;
9890
9891 /* Make sure RSC matches LRO, reset if change */
9892 if (!(features & NETIF_F_LRO)) {
9893 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
9894 need_reset = true;
9895 adapter->flags2 &= ~IXGBE_FLAG2_RSC_ENABLED;
9896 } else if ((adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE) &&
9897 !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)) {
9898 if (adapter->rx_itr_setting == 1 ||
9899 adapter->rx_itr_setting > IXGBE_MIN_RSC_ITR) {
9900 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
9901 need_reset = true;
9902 } else if ((changed ^ features) & NETIF_F_LRO) {
9903 e_info(probe, "rx-usecs set too low, "
9904 "disabling RSC\n");
9905 }
9906 }
9907
9908 /*
9909 * Check if Flow Director n-tuple support or hw_tc support was
9910 * enabled or disabled. If the state changed, we need to reset.
9911 */
9912 if ((features & NETIF_F_NTUPLE) || (features & NETIF_F_HW_TC)) {
9913 /* turn off ATR, enable perfect filters and reset */
9914 if (!(adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
9915 need_reset = true;
9916
9917 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
9918 adapter->flags |= IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9919 } else {
9920 /* turn off perfect filters, enable ATR and reset */
9921 if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
9922 need_reset = true;
9923
9924 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
9925
9926 /* We cannot enable ATR if SR-IOV is enabled */
9927 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED ||
9928 /* We cannot enable ATR if we have 2 or more tcs */
9929 (adapter->hw_tcs > 1) ||
9930 /* We cannot enable ATR if RSS is disabled */
9931 (adapter->ring_feature[RING_F_RSS].limit <= 1) ||
9932 /* A sample rate of 0 indicates ATR disabled */
9933 (!adapter->atr_sample_rate))
9934 ; /* do nothing not supported */
9935 else /* otherwise supported and set the flag */
9936 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
9937 }
9938
9939 if (changed & NETIF_F_RXALL)
9940 need_reset = true;
9941
9942 netdev->features = features;
9943
9944 if ((changed & NETIF_F_HW_L2FW_DOFFLOAD) && adapter->num_rx_pools > 1)
9945 ixgbe_reset_l2fw_offload(adapter);
9946 else if (need_reset)
9947 ixgbe_do_reset(netdev);
9948 else if (changed & (NETIF_F_HW_VLAN_CTAG_RX |
9949 NETIF_F_HW_VLAN_CTAG_FILTER))
9950 ixgbe_set_rx_mode(netdev);
9951
9952 return 1;
9953 }
9954
9955 static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
9956 struct net_device *dev,
9957 const unsigned char *addr, u16 vid,
9958 u16 flags, bool *notified,
9959 struct netlink_ext_ack *extack)
9960 {
9961 /* guarantee we can provide a unique filter for the unicast address */
9962 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
9963 struct ixgbe_adapter *adapter = netdev_priv(dev);
9964 u16 pool = VMDQ_P(0);
9965
9966 if (netdev_uc_count(dev) >= ixgbe_available_rars(adapter, pool))
9967 return -ENOMEM;
9968 }
9969
9970 return ndo_dflt_fdb_add(ndm, tb, dev, addr, vid, flags);
9971 }
9972
9973 /**
9974 * ixgbe_configure_bridge_mode - set various bridge modes
9975 * @adapter: the private structure
9976 * @mode: requested bridge mode
9977 *
9978 * Configure some settings require for various bridge modes.
9979 **/
9980 static int ixgbe_configure_bridge_mode(struct ixgbe_adapter *adapter,
9981 __u16 mode)
9982 {
9983 struct ixgbe_hw *hw = &adapter->hw;
9984 unsigned int p, num_pools;
9985 u32 vmdctl;
9986
9987 switch (mode) {
9988 case BRIDGE_MODE_VEPA:
9989 /* disable Tx loopback, rely on switch hairpin mode */
9990 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC, 0);
9991
9992 /* must enable Rx switching replication to allow multicast
9993 * packet reception on all VFs, and to enable source address
9994 * pruning.
9995 */
9996 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
9997 vmdctl |= IXGBE_VT_CTL_REPLEN;
9998 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
9999
10000 /* enable Rx source address pruning. Note, this requires
10001 * replication to be enabled or else it does nothing.
10002 */
10003 num_pools = adapter->num_vfs + adapter->num_rx_pools;
10004 for (p = 0; p < num_pools; p++) {
10005 if (hw->mac.ops.set_source_address_pruning)
10006 hw->mac.ops.set_source_address_pruning(hw,
10007 true,
10008 p);
10009 }
10010 break;
10011 case BRIDGE_MODE_VEB:
10012 /* enable Tx loopback for internal VF/PF communication */
10013 IXGBE_WRITE_REG(&adapter->hw, IXGBE_PFDTXGSWC,
10014 IXGBE_PFDTXGSWC_VT_LBEN);
10015
10016 /* disable Rx switching replication unless we have SR-IOV
10017 * virtual functions
10018 */
10019 vmdctl = IXGBE_READ_REG(hw, IXGBE_VMD_CTL);
10020 if (!adapter->num_vfs)
10021 vmdctl &= ~IXGBE_VT_CTL_REPLEN;
10022 IXGBE_WRITE_REG(hw, IXGBE_VMD_CTL, vmdctl);
10023
10024 /* disable Rx source address pruning, since we don't expect to
10025 * be receiving external loopback of our transmitted frames.
10026 */
10027 num_pools = adapter->num_vfs + adapter->num_rx_pools;
10028 for (p = 0; p < num_pools; p++) {
10029 if (hw->mac.ops.set_source_address_pruning)
10030 hw->mac.ops.set_source_address_pruning(hw,
10031 false,
10032 p);
10033 }
10034 break;
10035 default:
10036 return -EINVAL;
10037 }
10038
10039 adapter->bridge_mode = mode;
10040
10041 e_info(drv, "enabling bridge mode: %s\n",
10042 mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
10043
10044 return 0;
10045 }
10046
10047 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
10048 struct nlmsghdr *nlh, u16 flags,
10049 struct netlink_ext_ack *extack)
10050 {
10051 struct ixgbe_adapter *adapter = netdev_priv(dev);
10052 struct nlattr *attr, *br_spec;
10053 int rem;
10054
10055 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
10056 return -EOPNOTSUPP;
10057
10058 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
10059 if (!br_spec)
10060 return -EINVAL;
10061
10062 nla_for_each_nested_type(attr, IFLA_BRIDGE_MODE, br_spec, rem) {
10063 __u16 mode = nla_get_u16(attr);
10064 int status = ixgbe_configure_bridge_mode(adapter, mode);
10065
10066 if (status)
10067 return status;
10068
10069 break;
10070 }
10071
10072 return 0;
10073 }
10074
10075 static int ixgbe_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
10076 struct net_device *dev,
10077 u32 filter_mask, int nlflags)
10078 {
10079 struct ixgbe_adapter *adapter = netdev_priv(dev);
10080
10081 if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
10082 return 0;
10083
10084 return ndo_dflt_bridge_getlink(skb, pid, seq, dev,
10085 adapter->bridge_mode, 0, 0, nlflags,
10086 filter_mask, NULL);
10087 }
10088
10089 static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
10090 {
10091 struct ixgbe_adapter *adapter = netdev_priv(pdev);
10092 struct ixgbe_fwd_adapter *accel;
10093 int tcs = adapter->hw_tcs ? : 1;
10094 int pool, err;
10095
10096 if (adapter->xdp_prog) {
10097 e_warn(probe, "L2FW offload is not supported with XDP\n");
10098 return ERR_PTR(-EINVAL);
10099 }
10100
10101 /* The hardware supported by ixgbe only filters on the destination MAC
10102 * address. In order to avoid issues we only support offloading modes
10103 * where the hardware can actually provide the functionality.
10104 */
10105 if (!macvlan_supports_dest_filter(vdev))
10106 return ERR_PTR(-EMEDIUMTYPE);
10107
10108 /* We need to lock down the macvlan to be a single queue device so that
10109 * we can reuse the tc_to_txq field in the macvlan netdev to represent
10110 * the queue mapping to our netdev.
10111 */
10112 if (netif_is_multiqueue(vdev))
10113 return ERR_PTR(-ERANGE);
10114
10115 pool = find_first_zero_bit(adapter->fwd_bitmask, adapter->num_rx_pools);
10116 if (pool == adapter->num_rx_pools) {
10117 u16 used_pools = adapter->num_vfs + adapter->num_rx_pools;
10118 u16 reserved_pools;
10119
10120 if (((adapter->flags & IXGBE_FLAG_DCB_ENABLED) &&
10121 adapter->num_rx_pools >= (MAX_TX_QUEUES / tcs)) ||
10122 adapter->num_rx_pools > IXGBE_MAX_MACVLANS)
10123 return ERR_PTR(-EBUSY);
10124
10125 /* Hardware has a limited number of available pools. Each VF,
10126 * and the PF require a pool. Check to ensure we don't
10127 * attempt to use more then the available number of pools.
10128 */
10129 if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
10130 return ERR_PTR(-EBUSY);
10131
10132 /* Enable VMDq flag so device will be set in VM mode */
10133 adapter->flags |= IXGBE_FLAG_VMDQ_ENABLED |
10134 IXGBE_FLAG_SRIOV_ENABLED;
10135
10136 /* Try to reserve as many queues per pool as possible,
10137 * we start with the configurations that support 4 queues
10138 * per pools, followed by 2, and then by just 1 per pool.
10139 */
10140 if (used_pools < 32 && adapter->num_rx_pools < 16)
10141 reserved_pools = min_t(u16,
10142 32 - used_pools,
10143 16 - adapter->num_rx_pools);
10144 else if (adapter->num_rx_pools < 32)
10145 reserved_pools = min_t(u16,
10146 64 - used_pools,
10147 32 - adapter->num_rx_pools);
10148 else
10149 reserved_pools = 64 - used_pools;
10150
10151
10152 if (!reserved_pools)
10153 return ERR_PTR(-EBUSY);
10154
10155 adapter->ring_feature[RING_F_VMDQ].limit += reserved_pools;
10156
10157 /* Force reinit of ring allocation with VMDQ enabled */
10158 err = ixgbe_setup_tc(pdev, adapter->hw_tcs);
10159 if (err)
10160 return ERR_PTR(err);
10161
10162 if (pool >= adapter->num_rx_pools)
10163 return ERR_PTR(-ENOMEM);
10164 }
10165
10166 accel = kzalloc(sizeof(*accel), GFP_KERNEL);
10167 if (!accel)
10168 return ERR_PTR(-ENOMEM);
10169
10170 set_bit(pool, adapter->fwd_bitmask);
10171 netdev_set_sb_channel(vdev, pool);
10172 accel->pool = pool;
10173 accel->netdev = vdev;
10174
10175 if (!netif_running(pdev))
10176 return accel;
10177
10178 err = ixgbe_fwd_ring_up(adapter, accel);
10179 if (err)
10180 return ERR_PTR(err);
10181
10182 return accel;
10183 }
10184
10185 static void ixgbe_fwd_del(struct net_device *pdev, void *priv)
10186 {
10187 struct ixgbe_fwd_adapter *accel = priv;
10188 struct ixgbe_adapter *adapter = netdev_priv(pdev);
10189 unsigned int rxbase = accel->rx_base_queue;
10190 unsigned int i;
10191
10192 /* delete unicast filter associated with offloaded interface */
10193 ixgbe_del_mac_filter(adapter, accel->netdev->dev_addr,
10194 VMDQ_P(accel->pool));
10195
10196 /* Allow remaining Rx packets to get flushed out of the
10197 * Rx FIFO before we drop the netdev for the ring.
10198 */
10199 usleep_range(10000, 20000);
10200
10201 for (i = 0; i < adapter->num_rx_queues_per_pool; i++) {
10202 struct ixgbe_ring *ring = adapter->rx_ring[rxbase + i];
10203 struct ixgbe_q_vector *qv = ring->q_vector;
10204
10205 /* Make sure we aren't processing any packets and clear
10206 * netdev to shut down the ring.
10207 */
10208 if (netif_running(adapter->netdev))
10209 napi_synchronize(&qv->napi);
10210 ring->netdev = NULL;
10211 }
10212
10213 /* unbind the queues and drop the subordinate channel config */
10214 netdev_unbind_sb_channel(pdev, accel->netdev);
10215 netdev_set_sb_channel(accel->netdev, 0);
10216
10217 clear_bit(accel->pool, adapter->fwd_bitmask);
10218 kfree(accel);
10219 }
10220
10221 #define IXGBE_MAX_MAC_HDR_LEN 127
10222 #define IXGBE_MAX_NETWORK_HDR_LEN 511
10223
10224 static netdev_features_t
10225 ixgbe_features_check(struct sk_buff *skb, struct net_device *dev,
10226 netdev_features_t features)
10227 {
10228 unsigned int network_hdr_len, mac_hdr_len;
10229
10230 /* Make certain the headers can be described by a context descriptor */
10231 mac_hdr_len = skb_network_offset(skb);
10232 if (unlikely(mac_hdr_len > IXGBE_MAX_MAC_HDR_LEN))
10233 return features & ~(NETIF_F_HW_CSUM |
10234 NETIF_F_SCTP_CRC |
10235 NETIF_F_GSO_UDP_L4 |
10236 NETIF_F_HW_VLAN_CTAG_TX |
10237 NETIF_F_TSO |
10238 NETIF_F_TSO6);
10239
10240 network_hdr_len = skb_checksum_start(skb) - skb_network_header(skb);
10241 if (unlikely(network_hdr_len > IXGBE_MAX_NETWORK_HDR_LEN))
10242 return features & ~(NETIF_F_HW_CSUM |
10243 NETIF_F_SCTP_CRC |
10244 NETIF_F_GSO_UDP_L4 |
10245 NETIF_F_TSO |
10246 NETIF_F_TSO6);
10247
10248 /* We can only support IPV4 TSO in tunnels if we can mangle the
10249 * inner IP ID field, so strip TSO if MANGLEID is not supported.
10250 * IPsec offoad sets skb->encapsulation but still can handle
10251 * the TSO, so it's the exception.
10252 */
10253 if (skb->encapsulation && !(features & NETIF_F_TSO_MANGLEID)) {
10254 #ifdef CONFIG_IXGBE_IPSEC
10255 if (!secpath_exists(skb))
10256 #endif
10257 features &= ~NETIF_F_TSO;
10258 }
10259
10260 return features;
10261 }
10262
10263 static int ixgbe_xdp_setup(struct net_device *dev, struct bpf_prog *prog)
10264 {
10265 int i, frame_size = dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
10266 struct ixgbe_adapter *adapter = netdev_priv(dev);
10267 struct bpf_prog *old_prog;
10268 bool need_reset;
10269 int num_queues;
10270
10271 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
10272 return -EINVAL;
10273
10274 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
10275 return -EINVAL;
10276
10277 /* verify ixgbe ring attributes are sufficient for XDP */
10278 for (i = 0; i < adapter->num_rx_queues; i++) {
10279 struct ixgbe_ring *ring = adapter->rx_ring[i];
10280
10281 if (ring_is_rsc_enabled(ring))
10282 return -EINVAL;
10283
10284 if (frame_size > ixgbe_rx_bufsz(ring))
10285 return -EINVAL;
10286 }
10287
10288 /* if the number of cpus is much larger than the maximum of queues,
10289 * we should stop it and then return with ENOMEM like before.
10290 */
10291 if (nr_cpu_ids > IXGBE_MAX_XDP_QS * 2)
10292 return -ENOMEM;
10293
10294 old_prog = xchg(&adapter->xdp_prog, prog);
10295 need_reset = (!!prog != !!old_prog);
10296
10297 /* If transitioning XDP modes reconfigure rings */
10298 if (need_reset) {
10299 int err;
10300
10301 if (!prog)
10302 /* Wait until ndo_xsk_wakeup completes. */
10303 synchronize_rcu();
10304 err = ixgbe_setup_tc(dev, adapter->hw_tcs);
10305
10306 if (err)
10307 return -EINVAL;
10308 if (!prog)
10309 xdp_features_clear_redirect_target(dev);
10310 } else {
10311 for (i = 0; i < adapter->num_rx_queues; i++) {
10312 WRITE_ONCE(adapter->rx_ring[i]->xdp_prog,
10313 adapter->xdp_prog);
10314 }
10315 }
10316
10317 if (old_prog)
10318 bpf_prog_put(old_prog);
10319
10320 /* Kick start the NAPI context if there is an AF_XDP socket open
10321 * on that queue id. This so that receiving will start.
10322 */
10323 if (need_reset && prog) {
10324 num_queues = min_t(int, adapter->num_rx_queues,
10325 adapter->num_xdp_queues);
10326 for (i = 0; i < num_queues; i++)
10327 if (adapter->xdp_ring[i]->xsk_pool)
10328 (void)ixgbe_xsk_wakeup(adapter->netdev, i,
10329 XDP_WAKEUP_RX);
10330 xdp_features_set_redirect_target(dev, true);
10331 }
10332
10333 return 0;
10334 }
10335
10336 static int ixgbe_xdp(struct net_device *dev, struct netdev_bpf *xdp)
10337 {
10338 struct ixgbe_adapter *adapter = netdev_priv(dev);
10339
10340 switch (xdp->command) {
10341 case XDP_SETUP_PROG:
10342 return ixgbe_xdp_setup(dev, xdp->prog);
10343 case XDP_SETUP_XSK_POOL:
10344 return ixgbe_xsk_pool_setup(adapter, xdp->xsk.pool,
10345 xdp->xsk.queue_id);
10346
10347 default:
10348 return -EINVAL;
10349 }
10350 }
10351
10352 void ixgbe_xdp_ring_update_tail(struct ixgbe_ring *ring)
10353 {
10354 /* Force memory writes to complete before letting h/w know there
10355 * are new descriptors to fetch.
10356 */
10357 wmb();
10358 writel(ring->next_to_use, ring->tail);
10359 }
10360
10361 void ixgbe_xdp_ring_update_tail_locked(struct ixgbe_ring *ring)
10362 {
10363 if (static_branch_unlikely(&ixgbe_xdp_locking_key))
10364 spin_lock(&ring->tx_lock);
10365 ixgbe_xdp_ring_update_tail(ring);
10366 if (static_branch_unlikely(&ixgbe_xdp_locking_key))
10367 spin_unlock(&ring->tx_lock);
10368 }
10369
10370 static int ixgbe_xdp_xmit(struct net_device *dev, int n,
10371 struct xdp_frame **frames, u32 flags)
10372 {
10373 struct ixgbe_adapter *adapter = netdev_priv(dev);
10374 struct ixgbe_ring *ring;
10375 int nxmit = 0;
10376 int i;
10377
10378 if (unlikely(test_bit(__IXGBE_DOWN, &adapter->state)))
10379 return -ENETDOWN;
10380
10381 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK))
10382 return -EINVAL;
10383
10384 /* During program transitions its possible adapter->xdp_prog is assigned
10385 * but ring has not been configured yet. In this case simply abort xmit.
10386 */
10387 ring = adapter->xdp_prog ? ixgbe_determine_xdp_ring(adapter) : NULL;
10388 if (unlikely(!ring))
10389 return -ENXIO;
10390
10391 if (unlikely(test_bit(__IXGBE_TX_DISABLED, &ring->state)))
10392 return -ENXIO;
10393
10394 if (static_branch_unlikely(&ixgbe_xdp_locking_key))
10395 spin_lock(&ring->tx_lock);
10396
10397 for (i = 0; i < n; i++) {
10398 struct xdp_frame *xdpf = frames[i];
10399 int err;
10400
10401 err = ixgbe_xmit_xdp_ring(ring, xdpf);
10402 if (err != IXGBE_XDP_TX)
10403 break;
10404 nxmit++;
10405 }
10406
10407 if (unlikely(flags & XDP_XMIT_FLUSH))
10408 ixgbe_xdp_ring_update_tail(ring);
10409
10410 if (static_branch_unlikely(&ixgbe_xdp_locking_key))
10411 spin_unlock(&ring->tx_lock);
10412
10413 return nxmit;
10414 }
10415
10416 static const struct net_device_ops ixgbe_netdev_ops = {
10417 .ndo_open = ixgbe_open,
10418 .ndo_stop = ixgbe_close,
10419 .ndo_start_xmit = ixgbe_xmit_frame,
10420 .ndo_set_rx_mode = ixgbe_set_rx_mode,
10421 .ndo_validate_addr = eth_validate_addr,
10422 .ndo_set_mac_address = ixgbe_set_mac,
10423 .ndo_change_mtu = ixgbe_change_mtu,
10424 .ndo_tx_timeout = ixgbe_tx_timeout,
10425 .ndo_set_tx_maxrate = ixgbe_tx_maxrate,
10426 .ndo_vlan_rx_add_vid = ixgbe_vlan_rx_add_vid,
10427 .ndo_vlan_rx_kill_vid = ixgbe_vlan_rx_kill_vid,
10428 .ndo_eth_ioctl = ixgbe_ioctl,
10429 .ndo_set_vf_mac = ixgbe_ndo_set_vf_mac,
10430 .ndo_set_vf_vlan = ixgbe_ndo_set_vf_vlan,
10431 .ndo_set_vf_rate = ixgbe_ndo_set_vf_bw,
10432 .ndo_set_vf_spoofchk = ixgbe_ndo_set_vf_spoofchk,
10433 .ndo_set_vf_link_state = ixgbe_ndo_set_vf_link_state,
10434 .ndo_set_vf_rss_query_en = ixgbe_ndo_set_vf_rss_query_en,
10435 .ndo_set_vf_trust = ixgbe_ndo_set_vf_trust,
10436 .ndo_get_vf_config = ixgbe_ndo_get_vf_config,
10437 .ndo_get_vf_stats = ixgbe_ndo_get_vf_stats,
10438 .ndo_get_stats64 = ixgbe_get_stats64,
10439 .ndo_setup_tc = __ixgbe_setup_tc,
10440 #ifdef IXGBE_FCOE
10441 .ndo_select_queue = ixgbe_select_queue,
10442 .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
10443 .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
10444 .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
10445 .ndo_fcoe_enable = ixgbe_fcoe_enable,
10446 .ndo_fcoe_disable = ixgbe_fcoe_disable,
10447 .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
10448 .ndo_fcoe_get_hbainfo = ixgbe_fcoe_get_hbainfo,
10449 #endif /* IXGBE_FCOE */
10450 .ndo_set_features = ixgbe_set_features,
10451 .ndo_fix_features = ixgbe_fix_features,
10452 .ndo_fdb_add = ixgbe_ndo_fdb_add,
10453 .ndo_bridge_setlink = ixgbe_ndo_bridge_setlink,
10454 .ndo_bridge_getlink = ixgbe_ndo_bridge_getlink,
10455 .ndo_dfwd_add_station = ixgbe_fwd_add,
10456 .ndo_dfwd_del_station = ixgbe_fwd_del,
10457 .ndo_features_check = ixgbe_features_check,
10458 .ndo_bpf = ixgbe_xdp,
10459 .ndo_xdp_xmit = ixgbe_xdp_xmit,
10460 .ndo_xsk_wakeup = ixgbe_xsk_wakeup,
10461 };
10462
10463 static void ixgbe_disable_txr_hw(struct ixgbe_adapter *adapter,
10464 struct ixgbe_ring *tx_ring)
10465 {
10466 unsigned long wait_delay, delay_interval;
10467 struct ixgbe_hw *hw = &adapter->hw;
10468 u8 reg_idx = tx_ring->reg_idx;
10469 int wait_loop;
10470 u32 txdctl;
10471
10472 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
10473
10474 /* delay mechanism from ixgbe_disable_tx */
10475 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10476
10477 wait_loop = IXGBE_MAX_RX_DESC_POLL;
10478 wait_delay = delay_interval;
10479
10480 while (wait_loop--) {
10481 usleep_range(wait_delay, wait_delay + 10);
10482 wait_delay += delay_interval * 2;
10483 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
10484
10485 if (!(txdctl & IXGBE_TXDCTL_ENABLE))
10486 return;
10487 }
10488
10489 e_err(drv, "TXDCTL.ENABLE not cleared within the polling period\n");
10490 }
10491
10492 static void ixgbe_disable_txr(struct ixgbe_adapter *adapter,
10493 struct ixgbe_ring *tx_ring)
10494 {
10495 set_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10496 ixgbe_disable_txr_hw(adapter, tx_ring);
10497 }
10498
10499 static void ixgbe_disable_rxr_hw(struct ixgbe_adapter *adapter,
10500 struct ixgbe_ring *rx_ring)
10501 {
10502 unsigned long wait_delay, delay_interval;
10503 struct ixgbe_hw *hw = &adapter->hw;
10504 u8 reg_idx = rx_ring->reg_idx;
10505 int wait_loop;
10506 u32 rxdctl;
10507
10508 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10509 rxdctl &= ~IXGBE_RXDCTL_ENABLE;
10510 rxdctl |= IXGBE_RXDCTL_SWFLSH;
10511
10512 /* write value back with RXDCTL.ENABLE bit cleared */
10513 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
10514
10515 /* RXDCTL.EN may not change on 82598 if link is down, so skip it */
10516 if (hw->mac.type == ixgbe_mac_82598EB &&
10517 !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
10518 return;
10519
10520 /* delay mechanism from ixgbe_disable_rx */
10521 delay_interval = ixgbe_get_completion_timeout(adapter) / 100;
10522
10523 wait_loop = IXGBE_MAX_RX_DESC_POLL;
10524 wait_delay = delay_interval;
10525
10526 while (wait_loop--) {
10527 usleep_range(wait_delay, wait_delay + 10);
10528 wait_delay += delay_interval * 2;
10529 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
10530
10531 if (!(rxdctl & IXGBE_RXDCTL_ENABLE))
10532 return;
10533 }
10534
10535 e_err(drv, "RXDCTL.ENABLE not cleared within the polling period\n");
10536 }
10537
10538 static void ixgbe_reset_txr_stats(struct ixgbe_ring *tx_ring)
10539 {
10540 memset(&tx_ring->stats, 0, sizeof(tx_ring->stats));
10541 memset(&tx_ring->tx_stats, 0, sizeof(tx_ring->tx_stats));
10542 }
10543
10544 static void ixgbe_reset_rxr_stats(struct ixgbe_ring *rx_ring)
10545 {
10546 memset(&rx_ring->stats, 0, sizeof(rx_ring->stats));
10547 memset(&rx_ring->rx_stats, 0, sizeof(rx_ring->rx_stats));
10548 }
10549
10550 /**
10551 * ixgbe_irq_disable_single - Disable single IRQ vector
10552 * @adapter: adapter structure
10553 * @ring: ring index
10554 **/
10555 static void ixgbe_irq_disable_single(struct ixgbe_adapter *adapter, u32 ring)
10556 {
10557 struct ixgbe_hw *hw = &adapter->hw;
10558 u64 qmask = BIT_ULL(ring);
10559 u32 mask;
10560
10561 switch (adapter->hw.mac.type) {
10562 case ixgbe_mac_82598EB:
10563 mask = qmask & IXGBE_EIMC_RTX_QUEUE;
10564 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
10565 break;
10566 case ixgbe_mac_82599EB:
10567 case ixgbe_mac_X540:
10568 case ixgbe_mac_X550:
10569 case ixgbe_mac_X550EM_x:
10570 case ixgbe_mac_x550em_a:
10571 mask = (qmask & 0xFFFFFFFF);
10572 if (mask)
10573 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
10574 mask = (qmask >> 32);
10575 if (mask)
10576 IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
10577 break;
10578 default:
10579 break;
10580 }
10581 IXGBE_WRITE_FLUSH(&adapter->hw);
10582 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
10583 synchronize_irq(adapter->msix_entries[ring].vector);
10584 else
10585 synchronize_irq(adapter->pdev->irq);
10586 }
10587
10588 /**
10589 * ixgbe_txrx_ring_disable - Disable Rx/Tx/XDP Tx rings
10590 * @adapter: adapter structure
10591 * @ring: ring index
10592 *
10593 * This function disables a certain Rx/Tx/XDP Tx ring. The function
10594 * assumes that the netdev is running.
10595 **/
10596 void ixgbe_txrx_ring_disable(struct ixgbe_adapter *adapter, int ring)
10597 {
10598 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10599
10600 rx_ring = adapter->rx_ring[ring];
10601 tx_ring = adapter->tx_ring[ring];
10602 xdp_ring = adapter->xdp_ring[ring];
10603
10604 ixgbe_irq_disable_single(adapter, ring);
10605
10606 /* Rx/Tx/XDP Tx share the same napi context. */
10607 napi_disable(&rx_ring->q_vector->napi);
10608
10609 ixgbe_disable_txr(adapter, tx_ring);
10610 if (xdp_ring)
10611 ixgbe_disable_txr(adapter, xdp_ring);
10612 ixgbe_disable_rxr_hw(adapter, rx_ring);
10613
10614 if (xdp_ring)
10615 synchronize_rcu();
10616
10617 ixgbe_clean_tx_ring(tx_ring);
10618 if (xdp_ring)
10619 ixgbe_clean_tx_ring(xdp_ring);
10620 ixgbe_clean_rx_ring(rx_ring);
10621
10622 ixgbe_reset_txr_stats(tx_ring);
10623 if (xdp_ring)
10624 ixgbe_reset_txr_stats(xdp_ring);
10625 ixgbe_reset_rxr_stats(rx_ring);
10626 }
10627
10628 /**
10629 * ixgbe_txrx_ring_enable - Enable Rx/Tx/XDP Tx rings
10630 * @adapter: adapter structure
10631 * @ring: ring index
10632 *
10633 * This function enables a certain Rx/Tx/XDP Tx ring. The function
10634 * assumes that the netdev is running.
10635 **/
10636 void ixgbe_txrx_ring_enable(struct ixgbe_adapter *adapter, int ring)
10637 {
10638 struct ixgbe_ring *rx_ring, *tx_ring, *xdp_ring;
10639
10640 rx_ring = adapter->rx_ring[ring];
10641 tx_ring = adapter->tx_ring[ring];
10642 xdp_ring = adapter->xdp_ring[ring];
10643
10644 ixgbe_configure_tx_ring(adapter, tx_ring);
10645 if (xdp_ring)
10646 ixgbe_configure_tx_ring(adapter, xdp_ring);
10647 ixgbe_configure_rx_ring(adapter, rx_ring);
10648
10649 clear_bit(__IXGBE_TX_DISABLED, &tx_ring->state);
10650 if (xdp_ring)
10651 clear_bit(__IXGBE_TX_DISABLED, &xdp_ring->state);
10652
10653 /* Rx/Tx/XDP Tx share the same napi context. */
10654 napi_enable(&rx_ring->q_vector->napi);
10655 ixgbe_irq_enable_queues(adapter, BIT_ULL(ring));
10656 IXGBE_WRITE_FLUSH(&adapter->hw);
10657 }
10658
10659 /**
10660 * ixgbe_enumerate_functions - Get the number of ports this device has
10661 * @adapter: adapter structure
10662 *
10663 * This function enumerates the phsyical functions co-located on a single slot,
10664 * in order to determine how many ports a device has. This is most useful in
10665 * determining the required GT/s of PCIe bandwidth necessary for optimal
10666 * performance.
10667 **/
10668 static inline int ixgbe_enumerate_functions(struct ixgbe_adapter *adapter)
10669 {
10670 struct pci_dev *entry, *pdev = adapter->pdev;
10671 int physfns = 0;
10672
10673 /* Some cards can not use the generic count PCIe functions method,
10674 * because they are behind a parent switch, so we hardcode these with
10675 * the correct number of functions.
10676 */
10677 if (ixgbe_pcie_from_parent(&adapter->hw))
10678 physfns = 4;
10679
10680 list_for_each_entry(entry, &adapter->pdev->bus->devices, bus_list) {
10681 /* don't count virtual functions */
10682 if (entry->is_virtfn)
10683 continue;
10684
10685 /* When the devices on the bus don't all match our device ID,
10686 * we can't reliably determine the correct number of
10687 * functions. This can occur if a function has been direct
10688 * attached to a virtual machine using VT-d, for example. In
10689 * this case, simply return -1 to indicate this.
10690 */
10691 if ((entry->vendor != pdev->vendor) ||
10692 (entry->device != pdev->device))
10693 return -1;
10694
10695 physfns++;
10696 }
10697
10698 return physfns;
10699 }
10700
10701 /**
10702 * ixgbe_wol_supported - Check whether device supports WoL
10703 * @adapter: the adapter private structure
10704 * @device_id: the device ID
10705 * @subdevice_id: the subsystem device ID
10706 *
10707 * This function is used by probe and ethtool to determine
10708 * which devices have WoL support
10709 *
10710 **/
10711 bool ixgbe_wol_supported(struct ixgbe_adapter *adapter, u16 device_id,
10712 u16 subdevice_id)
10713 {
10714 struct ixgbe_hw *hw = &adapter->hw;
10715 u16 wol_cap = adapter->eeprom_cap & IXGBE_DEVICE_CAPS_WOL_MASK;
10716
10717 /* WOL not supported on 82598 */
10718 if (hw->mac.type == ixgbe_mac_82598EB)
10719 return false;
10720
10721 /* check eeprom to see if WOL is enabled for X540 and newer */
10722 if (hw->mac.type >= ixgbe_mac_X540) {
10723 if ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0_1) ||
10724 ((wol_cap == IXGBE_DEVICE_CAPS_WOL_PORT0) &&
10725 (hw->bus.func == 0)))
10726 return true;
10727 }
10728
10729 /* WOL is determined based on device IDs for 82599 MACs */
10730 switch (device_id) {
10731 case IXGBE_DEV_ID_82599_SFP:
10732 /* Only these subdevices could supports WOL */
10733 switch (subdevice_id) {
10734 case IXGBE_SUBDEV_ID_82599_560FLR:
10735 case IXGBE_SUBDEV_ID_82599_LOM_SNAP6:
10736 case IXGBE_SUBDEV_ID_82599_SFP_WOL0:
10737 case IXGBE_SUBDEV_ID_82599_SFP_2OCP:
10738 /* only support first port */
10739 if (hw->bus.func != 0)
10740 break;
10741 fallthrough;
10742 case IXGBE_SUBDEV_ID_82599_SP_560FLR:
10743 case IXGBE_SUBDEV_ID_82599_SFP:
10744 case IXGBE_SUBDEV_ID_82599_RNDC:
10745 case IXGBE_SUBDEV_ID_82599_ECNA_DP:
10746 case IXGBE_SUBDEV_ID_82599_SFP_1OCP:
10747 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1:
10748 case IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2:
10749 return true;
10750 }
10751 break;
10752 case IXGBE_DEV_ID_82599EN_SFP:
10753 /* Only these subdevices support WOL */
10754 switch (subdevice_id) {
10755 case IXGBE_SUBDEV_ID_82599EN_SFP_OCP1:
10756 return true;
10757 }
10758 break;
10759 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
10760 /* All except this subdevice support WOL */
10761 if (subdevice_id != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
10762 return true;
10763 break;
10764 case IXGBE_DEV_ID_82599_KX4:
10765 return true;
10766 default:
10767 break;
10768 }
10769
10770 return false;
10771 }
10772
10773 /**
10774 * ixgbe_set_fw_version - Set FW version
10775 * @adapter: the adapter private structure
10776 *
10777 * This function is used by probe and ethtool to determine the FW version to
10778 * format to display. The FW version is taken from the EEPROM/NVM.
10779 */
10780 static void ixgbe_set_fw_version(struct ixgbe_adapter *adapter)
10781 {
10782 struct ixgbe_hw *hw = &adapter->hw;
10783 struct ixgbe_nvm_version nvm_ver;
10784
10785 ixgbe_get_oem_prod_version(hw, &nvm_ver);
10786 if (nvm_ver.oem_valid) {
10787 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10788 "%x.%x.%x", nvm_ver.oem_major, nvm_ver.oem_minor,
10789 nvm_ver.oem_release);
10790 return;
10791 }
10792
10793 ixgbe_get_etk_id(hw, &nvm_ver);
10794 ixgbe_get_orom_version(hw, &nvm_ver);
10795
10796 if (nvm_ver.or_valid) {
10797 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10798 "0x%08x, %d.%d.%d", nvm_ver.etk_id, nvm_ver.or_major,
10799 nvm_ver.or_build, nvm_ver.or_patch);
10800 return;
10801 }
10802
10803 /* Set ETrack ID format */
10804 snprintf(adapter->eeprom_id, sizeof(adapter->eeprom_id),
10805 "0x%08x", nvm_ver.etk_id);
10806 }
10807
10808 /**
10809 * ixgbe_probe - Device Initialization Routine
10810 * @pdev: PCI device information struct
10811 * @ent: entry in ixgbe_pci_tbl
10812 *
10813 * Returns 0 on success, negative on failure
10814 *
10815 * ixgbe_probe initializes an adapter identified by a pci_dev structure.
10816 * The OS initialization, configuring of the adapter private structure,
10817 * and a hardware reset occur.
10818 **/
10819 static int ixgbe_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
10820 {
10821 struct net_device *netdev;
10822 struct ixgbe_adapter *adapter = NULL;
10823 struct ixgbe_hw *hw;
10824 const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
10825 unsigned int indices = MAX_TX_QUEUES;
10826 u8 part_str[IXGBE_PBANUM_LENGTH];
10827 int i, err, expected_gts;
10828 bool disable_dev = false;
10829 #ifdef IXGBE_FCOE
10830 u16 device_caps;
10831 #endif
10832 u32 eec;
10833
10834 /* Catch broken hardware that put the wrong VF device ID in
10835 * the PCIe SR-IOV capability.
10836 */
10837 if (pdev->is_virtfn) {
10838 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
10839 pci_name(pdev), pdev->vendor, pdev->device);
10840 return -EINVAL;
10841 }
10842
10843 err = pci_enable_device_mem(pdev);
10844 if (err)
10845 return err;
10846
10847 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10848 if (err) {
10849 dev_err(&pdev->dev,
10850 "No usable DMA configuration, aborting\n");
10851 goto err_dma;
10852 }
10853
10854 err = pci_request_mem_regions(pdev, ixgbe_driver_name);
10855 if (err) {
10856 dev_err(&pdev->dev,
10857 "pci_request_selected_regions failed 0x%x\n", err);
10858 goto err_pci_reg;
10859 }
10860
10861 pci_set_master(pdev);
10862 pci_save_state(pdev);
10863
10864 if (ii->mac == ixgbe_mac_82598EB) {
10865 #ifdef CONFIG_IXGBE_DCB
10866 /* 8 TC w/ 4 queues per TC */
10867 indices = 4 * MAX_TRAFFIC_CLASS;
10868 #else
10869 indices = IXGBE_MAX_RSS_INDICES;
10870 #endif
10871 }
10872
10873 netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
10874 if (!netdev) {
10875 err = -ENOMEM;
10876 goto err_alloc_etherdev;
10877 }
10878
10879 SET_NETDEV_DEV(netdev, &pdev->dev);
10880
10881 adapter = netdev_priv(netdev);
10882
10883 adapter->netdev = netdev;
10884 adapter->pdev = pdev;
10885 hw = &adapter->hw;
10886 hw->back = adapter;
10887 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
10888
10889 hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
10890 pci_resource_len(pdev, 0));
10891 adapter->io_addr = hw->hw_addr;
10892 if (!hw->hw_addr) {
10893 err = -EIO;
10894 goto err_ioremap;
10895 }
10896
10897 netdev->netdev_ops = &ixgbe_netdev_ops;
10898 ixgbe_set_ethtool_ops(netdev);
10899 netdev->watchdog_timeo = 5 * HZ;
10900 strscpy(netdev->name, pci_name(pdev), sizeof(netdev->name));
10901
10902 /* Setup hw api */
10903 hw->mac.ops = *ii->mac_ops;
10904 hw->mac.type = ii->mac;
10905 hw->mvals = ii->mvals;
10906 if (ii->link_ops)
10907 hw->link.ops = *ii->link_ops;
10908
10909 /* EEPROM */
10910 hw->eeprom.ops = *ii->eeprom_ops;
10911 eec = IXGBE_READ_REG(hw, IXGBE_EEC(hw));
10912 if (ixgbe_removed(hw->hw_addr)) {
10913 err = -EIO;
10914 goto err_ioremap;
10915 }
10916 /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
10917 if (!(eec & BIT(8)))
10918 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
10919
10920 /* PHY */
10921 hw->phy.ops = *ii->phy_ops;
10922 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
10923 /* ixgbe_identify_phy_generic will set prtad and mmds properly */
10924 hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
10925 hw->phy.mdio.mmds = 0;
10926 hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
10927 hw->phy.mdio.dev = netdev;
10928 hw->phy.mdio.mdio_read = ixgbe_mdio_read;
10929 hw->phy.mdio.mdio_write = ixgbe_mdio_write;
10930
10931 /* setup the private structure */
10932 err = ixgbe_sw_init(adapter, ii);
10933 if (err)
10934 goto err_sw_init;
10935
10936 if (adapter->hw.mac.type == ixgbe_mac_82599EB)
10937 adapter->flags2 |= IXGBE_FLAG2_AUTO_DISABLE_VF;
10938
10939 switch (adapter->hw.mac.type) {
10940 case ixgbe_mac_X550:
10941 case ixgbe_mac_X550EM_x:
10942 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550;
10943 break;
10944 case ixgbe_mac_x550em_a:
10945 netdev->udp_tunnel_nic_info = &ixgbe_udp_tunnels_x550em_a;
10946 break;
10947 default:
10948 break;
10949 }
10950
10951 /* Make sure the SWFW semaphore is in a valid state */
10952 if (hw->mac.ops.init_swfw_sync)
10953 hw->mac.ops.init_swfw_sync(hw);
10954
10955 /* Make it possible the adapter to be woken up via WOL */
10956 switch (adapter->hw.mac.type) {
10957 case ixgbe_mac_82599EB:
10958 case ixgbe_mac_X540:
10959 case ixgbe_mac_X550:
10960 case ixgbe_mac_X550EM_x:
10961 case ixgbe_mac_x550em_a:
10962 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
10963 break;
10964 default:
10965 break;
10966 }
10967
10968 /*
10969 * If there is a fan on this device and it has failed log the
10970 * failure.
10971 */
10972 if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
10973 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
10974 if (esdp & IXGBE_ESDP_SDP1)
10975 e_crit(probe, "Fan has stopped, replace the adapter\n");
10976 }
10977
10978 if (allow_unsupported_sfp)
10979 hw->allow_unsupported_sfp = allow_unsupported_sfp;
10980
10981 /* reset_hw fills in the perm_addr as well */
10982 hw->phy.reset_if_overtemp = true;
10983 err = hw->mac.ops.reset_hw(hw);
10984 hw->phy.reset_if_overtemp = false;
10985 ixgbe_set_eee_capable(adapter);
10986 if (err == -ENOENT) {
10987 err = 0;
10988 } else if (err == -EOPNOTSUPP) {
10989 e_dev_err("failed to load because an unsupported SFP+ or QSFP module type was detected.\n");
10990 e_dev_err("Reload the driver after installing a supported module.\n");
10991 goto err_sw_init;
10992 } else if (err) {
10993 e_dev_err("HW Init failed: %d\n", err);
10994 goto err_sw_init;
10995 }
10996
10997 #ifdef CONFIG_PCI_IOV
10998 /* SR-IOV not supported on the 82598 */
10999 if (adapter->hw.mac.type == ixgbe_mac_82598EB)
11000 goto skip_sriov;
11001 /* Mailbox */
11002 ixgbe_init_mbx_params_pf(hw);
11003 hw->mbx.ops = ii->mbx_ops;
11004 pci_sriov_set_totalvfs(pdev, IXGBE_MAX_VFS_DRV_LIMIT);
11005 ixgbe_enable_sriov(adapter, max_vfs);
11006 skip_sriov:
11007
11008 #endif
11009 netdev->features = NETIF_F_SG |
11010 NETIF_F_TSO |
11011 NETIF_F_TSO6 |
11012 NETIF_F_RXHASH |
11013 NETIF_F_RXCSUM |
11014 NETIF_F_HW_CSUM;
11015
11016 #define IXGBE_GSO_PARTIAL_FEATURES (NETIF_F_GSO_GRE | \
11017 NETIF_F_GSO_GRE_CSUM | \
11018 NETIF_F_GSO_IPXIP4 | \
11019 NETIF_F_GSO_IPXIP6 | \
11020 NETIF_F_GSO_UDP_TUNNEL | \
11021 NETIF_F_GSO_UDP_TUNNEL_CSUM)
11022
11023 netdev->gso_partial_features = IXGBE_GSO_PARTIAL_FEATURES;
11024 netdev->features |= NETIF_F_GSO_PARTIAL |
11025 IXGBE_GSO_PARTIAL_FEATURES;
11026
11027 if (hw->mac.type >= ixgbe_mac_82599EB)
11028 netdev->features |= NETIF_F_SCTP_CRC | NETIF_F_GSO_UDP_L4;
11029
11030 #ifdef CONFIG_IXGBE_IPSEC
11031 #define IXGBE_ESP_FEATURES (NETIF_F_HW_ESP | \
11032 NETIF_F_HW_ESP_TX_CSUM | \
11033 NETIF_F_GSO_ESP)
11034
11035 if (adapter->ipsec)
11036 netdev->features |= IXGBE_ESP_FEATURES;
11037 #endif
11038 /* copy netdev features into list of user selectable features */
11039 netdev->hw_features |= netdev->features |
11040 NETIF_F_HW_VLAN_CTAG_FILTER |
11041 NETIF_F_HW_VLAN_CTAG_RX |
11042 NETIF_F_HW_VLAN_CTAG_TX |
11043 NETIF_F_RXALL |
11044 NETIF_F_HW_L2FW_DOFFLOAD;
11045
11046 if (hw->mac.type >= ixgbe_mac_82599EB)
11047 netdev->hw_features |= NETIF_F_NTUPLE |
11048 NETIF_F_HW_TC;
11049
11050 netdev->features |= NETIF_F_HIGHDMA;
11051
11052 netdev->vlan_features |= netdev->features | NETIF_F_TSO_MANGLEID;
11053 netdev->hw_enc_features |= netdev->vlan_features;
11054 netdev->mpls_features |= NETIF_F_SG |
11055 NETIF_F_TSO |
11056 NETIF_F_TSO6 |
11057 NETIF_F_HW_CSUM;
11058 netdev->mpls_features |= IXGBE_GSO_PARTIAL_FEATURES;
11059
11060 /* set this bit last since it cannot be part of vlan_features */
11061 netdev->features |= NETIF_F_HW_VLAN_CTAG_FILTER |
11062 NETIF_F_HW_VLAN_CTAG_RX |
11063 NETIF_F_HW_VLAN_CTAG_TX;
11064
11065 netdev->priv_flags |= IFF_UNICAST_FLT;
11066 netdev->priv_flags |= IFF_SUPP_NOFCS;
11067
11068 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT |
11069 NETDEV_XDP_ACT_XSK_ZEROCOPY;
11070
11071 /* MTU range: 68 - 9710 */
11072 netdev->min_mtu = ETH_MIN_MTU;
11073 netdev->max_mtu = IXGBE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN);
11074
11075 #ifdef CONFIG_IXGBE_DCB
11076 if (adapter->flags & IXGBE_FLAG_DCB_CAPABLE)
11077 netdev->dcbnl_ops = &ixgbe_dcbnl_ops;
11078 #endif
11079
11080 #ifdef IXGBE_FCOE
11081 if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
11082 unsigned int fcoe_l;
11083
11084 if (hw->mac.ops.get_device_caps) {
11085 hw->mac.ops.get_device_caps(hw, &device_caps);
11086 if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
11087 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
11088 }
11089
11090
11091 fcoe_l = min_t(int, IXGBE_FCRETA_SIZE, num_online_cpus());
11092 adapter->ring_feature[RING_F_FCOE].limit = fcoe_l;
11093
11094 netdev->features |= NETIF_F_FSO |
11095 NETIF_F_FCOE_CRC;
11096
11097 netdev->vlan_features |= NETIF_F_FSO |
11098 NETIF_F_FCOE_CRC;
11099 }
11100 #endif /* IXGBE_FCOE */
11101 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
11102 netdev->hw_features |= NETIF_F_LRO;
11103 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
11104 netdev->features |= NETIF_F_LRO;
11105
11106 if (ixgbe_check_fw_error(adapter)) {
11107 err = -EIO;
11108 goto err_sw_init;
11109 }
11110
11111 /* make sure the EEPROM is good */
11112 if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
11113 e_dev_err("The EEPROM Checksum Is Not Valid\n");
11114 err = -EIO;
11115 goto err_sw_init;
11116 }
11117
11118 eth_platform_get_mac_address(&adapter->pdev->dev,
11119 adapter->hw.mac.perm_addr);
11120
11121 eth_hw_addr_set(netdev, hw->mac.perm_addr);
11122
11123 if (!is_valid_ether_addr(netdev->dev_addr)) {
11124 e_dev_err("invalid MAC address\n");
11125 err = -EIO;
11126 goto err_sw_init;
11127 }
11128
11129 /* Set hw->mac.addr to permanent MAC address */
11130 ether_addr_copy(hw->mac.addr, hw->mac.perm_addr);
11131 ixgbe_mac_set_default_filter(adapter);
11132
11133 timer_setup(&adapter->service_timer, ixgbe_service_timer, 0);
11134
11135 if (ixgbe_removed(hw->hw_addr)) {
11136 err = -EIO;
11137 goto err_sw_init;
11138 }
11139 INIT_WORK(&adapter->service_task, ixgbe_service_task);
11140 set_bit(__IXGBE_SERVICE_INITED, &adapter->state);
11141 clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
11142
11143 err = ixgbe_init_interrupt_scheme(adapter);
11144 if (err)
11145 goto err_sw_init;
11146
11147 for (i = 0; i < adapter->num_rx_queues; i++)
11148 u64_stats_init(&adapter->rx_ring[i]->syncp);
11149 for (i = 0; i < adapter->num_tx_queues; i++)
11150 u64_stats_init(&adapter->tx_ring[i]->syncp);
11151 for (i = 0; i < adapter->num_xdp_queues; i++)
11152 u64_stats_init(&adapter->xdp_ring[i]->syncp);
11153
11154 /* WOL not supported for all devices */
11155 adapter->wol = 0;
11156 hw->eeprom.ops.read(hw, 0x2c, &adapter->eeprom_cap);
11157 hw->wol_enabled = ixgbe_wol_supported(adapter, pdev->device,
11158 pdev->subsystem_device);
11159 if (hw->wol_enabled)
11160 adapter->wol = IXGBE_WUFC_MAG;
11161
11162 device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
11163
11164 /* save off EEPROM version number */
11165 ixgbe_set_fw_version(adapter);
11166
11167 /* pick up the PCI bus settings for reporting later */
11168 if (ixgbe_pcie_from_parent(hw))
11169 ixgbe_get_parent_bus_info(adapter);
11170 else
11171 hw->mac.ops.get_bus_info(hw);
11172
11173 /* calculate the expected PCIe bandwidth required for optimal
11174 * performance. Note that some older parts will never have enough
11175 * bandwidth due to being older generation PCIe parts. We clamp these
11176 * parts to ensure no warning is displayed if it can't be fixed.
11177 */
11178 switch (hw->mac.type) {
11179 case ixgbe_mac_82598EB:
11180 expected_gts = min(ixgbe_enumerate_functions(adapter) * 10, 16);
11181 break;
11182 default:
11183 expected_gts = ixgbe_enumerate_functions(adapter) * 10;
11184 break;
11185 }
11186
11187 /* don't check link if we failed to enumerate functions */
11188 if (expected_gts > 0)
11189 ixgbe_check_minimum_link(adapter, expected_gts);
11190
11191 err = ixgbe_read_pba_string_generic(hw, part_str, sizeof(part_str));
11192 if (err)
11193 strscpy(part_str, "Unknown", sizeof(part_str));
11194 if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
11195 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
11196 hw->mac.type, hw->phy.type, hw->phy.sfp_type,
11197 part_str);
11198 else
11199 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
11200 hw->mac.type, hw->phy.type, part_str);
11201
11202 e_dev_info("%pM\n", netdev->dev_addr);
11203
11204 /* reset the hardware with the new settings */
11205 err = hw->mac.ops.start_hw(hw);
11206 if (err == -EACCES) {
11207 /* We are running on a pre-production device, log a warning */
11208 e_dev_warn("This device is a pre-production adapter/LOM. "
11209 "Please be aware there may be issues associated "
11210 "with your hardware. If you are experiencing "
11211 "problems please contact your Intel or hardware "
11212 "representative who provided you with this "
11213 "hardware.\n");
11214 }
11215 strcpy(netdev->name, "eth%d");
11216 pci_set_drvdata(pdev, adapter);
11217 err = register_netdev(netdev);
11218 if (err)
11219 goto err_register;
11220
11221
11222 /* power down the optics for 82599 SFP+ fiber */
11223 if (hw->mac.ops.disable_tx_laser)
11224 hw->mac.ops.disable_tx_laser(hw);
11225
11226 /* carrier off reporting is important to ethtool even BEFORE open */
11227 netif_carrier_off(netdev);
11228
11229 #ifdef CONFIG_IXGBE_DCA
11230 if (dca_add_requester(&pdev->dev) == 0) {
11231 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
11232 ixgbe_setup_dca(adapter);
11233 }
11234 #endif
11235 if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
11236 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
11237 for (i = 0; i < adapter->num_vfs; i++)
11238 ixgbe_vf_configuration(pdev, (i | 0x10000000));
11239 }
11240
11241 /* firmware requires driver version to be 0xFFFFFFFF
11242 * since os does not support feature
11243 */
11244 if (hw->mac.ops.set_fw_drv_ver)
11245 hw->mac.ops.set_fw_drv_ver(hw, 0xFF, 0xFF, 0xFF, 0xFF,
11246 sizeof(UTS_RELEASE) - 1,
11247 UTS_RELEASE);
11248
11249 /* add san mac addr to netdev */
11250 ixgbe_add_sanmac_netdev(netdev);
11251
11252 e_dev_info("%s\n", ixgbe_default_device_descr);
11253
11254 #ifdef CONFIG_IXGBE_HWMON
11255 if (ixgbe_sysfs_init(adapter))
11256 e_err(probe, "failed to allocate sysfs resources\n");
11257 #endif /* CONFIG_IXGBE_HWMON */
11258
11259 ixgbe_dbg_adapter_init(adapter);
11260
11261 /* setup link for SFP devices with MNG FW, else wait for IXGBE_UP */
11262 if (ixgbe_mng_enabled(hw) && ixgbe_is_sfp(hw) && hw->mac.ops.setup_link)
11263 hw->mac.ops.setup_link(hw,
11264 IXGBE_LINK_SPEED_10GB_FULL | IXGBE_LINK_SPEED_1GB_FULL,
11265 true);
11266
11267 err = ixgbe_mii_bus_init(hw);
11268 if (err)
11269 goto err_netdev;
11270
11271 return 0;
11272
11273 err_netdev:
11274 unregister_netdev(netdev);
11275 err_register:
11276 ixgbe_release_hw_control(adapter);
11277 ixgbe_clear_interrupt_scheme(adapter);
11278 err_sw_init:
11279 ixgbe_disable_sriov(adapter);
11280 adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
11281 iounmap(adapter->io_addr);
11282 kfree(adapter->jump_tables[0]);
11283 kfree(adapter->mac_table);
11284 kfree(adapter->rss_key);
11285 bitmap_free(adapter->af_xdp_zc_qps);
11286 err_ioremap:
11287 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
11288 free_netdev(netdev);
11289 err_alloc_etherdev:
11290 pci_release_mem_regions(pdev);
11291 err_pci_reg:
11292 err_dma:
11293 if (!adapter || disable_dev)
11294 pci_disable_device(pdev);
11295 return err;
11296 }
11297
11298 /**
11299 * ixgbe_remove - Device Removal Routine
11300 * @pdev: PCI device information struct
11301 *
11302 * ixgbe_remove is called by the PCI subsystem to alert the driver
11303 * that it should release a PCI device. The could be caused by a
11304 * Hot-Plug event, or because the driver is going to be removed from
11305 * memory.
11306 **/
11307 static void ixgbe_remove(struct pci_dev *pdev)
11308 {
11309 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11310 struct net_device *netdev;
11311 bool disable_dev;
11312 int i;
11313
11314 /* if !adapter then we already cleaned up in probe */
11315 if (!adapter)
11316 return;
11317
11318 netdev = adapter->netdev;
11319 ixgbe_dbg_adapter_exit(adapter);
11320
11321 set_bit(__IXGBE_REMOVING, &adapter->state);
11322 cancel_work_sync(&adapter->service_task);
11323
11324 if (adapter->mii_bus)
11325 mdiobus_unregister(adapter->mii_bus);
11326
11327 #ifdef CONFIG_IXGBE_DCA
11328 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
11329 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
11330 dca_remove_requester(&pdev->dev);
11331 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL,
11332 IXGBE_DCA_CTRL_DCA_DISABLE);
11333 }
11334
11335 #endif
11336 #ifdef CONFIG_IXGBE_HWMON
11337 ixgbe_sysfs_exit(adapter);
11338 #endif /* CONFIG_IXGBE_HWMON */
11339
11340 /* remove the added san mac */
11341 ixgbe_del_sanmac_netdev(netdev);
11342
11343 #ifdef CONFIG_PCI_IOV
11344 ixgbe_disable_sriov(adapter);
11345 #endif
11346 if (netdev->reg_state == NETREG_REGISTERED)
11347 unregister_netdev(netdev);
11348
11349 ixgbe_stop_ipsec_offload(adapter);
11350 ixgbe_clear_interrupt_scheme(adapter);
11351
11352 ixgbe_release_hw_control(adapter);
11353
11354 #ifdef CONFIG_DCB
11355 kfree(adapter->ixgbe_ieee_pfc);
11356 kfree(adapter->ixgbe_ieee_ets);
11357
11358 #endif
11359 iounmap(adapter->io_addr);
11360 pci_release_mem_regions(pdev);
11361
11362 e_dev_info("complete\n");
11363
11364 for (i = 0; i < IXGBE_MAX_LINK_HANDLE; i++) {
11365 if (adapter->jump_tables[i]) {
11366 kfree(adapter->jump_tables[i]->input);
11367 kfree(adapter->jump_tables[i]->mask);
11368 }
11369 kfree(adapter->jump_tables[i]);
11370 }
11371
11372 kfree(adapter->mac_table);
11373 kfree(adapter->rss_key);
11374 bitmap_free(adapter->af_xdp_zc_qps);
11375 disable_dev = !test_and_set_bit(__IXGBE_DISABLED, &adapter->state);
11376 free_netdev(netdev);
11377
11378 if (disable_dev)
11379 pci_disable_device(pdev);
11380 }
11381
11382 /**
11383 * ixgbe_io_error_detected - called when PCI error is detected
11384 * @pdev: Pointer to PCI device
11385 * @state: The current pci connection state
11386 *
11387 * This function is called after a PCI bus error affecting
11388 * this device has been detected.
11389 */
11390 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
11391 pci_channel_state_t state)
11392 {
11393 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11394 struct net_device *netdev = adapter->netdev;
11395
11396 #ifdef CONFIG_PCI_IOV
11397 struct ixgbe_hw *hw = &adapter->hw;
11398 struct pci_dev *bdev, *vfdev;
11399 u32 dw0, dw1, dw2, dw3;
11400 int vf, pos;
11401 u16 req_id, pf_func;
11402
11403 if (adapter->hw.mac.type == ixgbe_mac_82598EB ||
11404 adapter->num_vfs == 0)
11405 goto skip_bad_vf_detection;
11406
11407 bdev = pdev->bus->self;
11408 while (bdev && (pci_pcie_type(bdev) != PCI_EXP_TYPE_ROOT_PORT))
11409 bdev = bdev->bus->self;
11410
11411 if (!bdev)
11412 goto skip_bad_vf_detection;
11413
11414 pos = pci_find_ext_capability(bdev, PCI_EXT_CAP_ID_ERR);
11415 if (!pos)
11416 goto skip_bad_vf_detection;
11417
11418 dw0 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG);
11419 dw1 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 4);
11420 dw2 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 8);
11421 dw3 = ixgbe_read_pci_cfg_dword(hw, pos + PCI_ERR_HEADER_LOG + 12);
11422 if (ixgbe_removed(hw->hw_addr))
11423 goto skip_bad_vf_detection;
11424
11425 req_id = dw1 >> 16;
11426 /* On the 82599 if bit 7 of the requestor ID is set then it's a VF */
11427 if (!(req_id & 0x0080))
11428 goto skip_bad_vf_detection;
11429
11430 pf_func = req_id & 0x01;
11431 if ((pf_func & 1) == (pdev->devfn & 1)) {
11432 unsigned int device_id;
11433
11434 vf = FIELD_GET(0x7F, req_id);
11435 e_dev_err("VF %d has caused a PCIe error\n", vf);
11436 e_dev_err("TLP: dw0: %8.8x\tdw1: %8.8x\tdw2: "
11437 "%8.8x\tdw3: %8.8x\n",
11438 dw0, dw1, dw2, dw3);
11439 switch (adapter->hw.mac.type) {
11440 case ixgbe_mac_82599EB:
11441 device_id = IXGBE_82599_VF_DEVICE_ID;
11442 break;
11443 case ixgbe_mac_X540:
11444 device_id = IXGBE_X540_VF_DEVICE_ID;
11445 break;
11446 case ixgbe_mac_X550:
11447 device_id = IXGBE_DEV_ID_X550_VF;
11448 break;
11449 case ixgbe_mac_X550EM_x:
11450 device_id = IXGBE_DEV_ID_X550EM_X_VF;
11451 break;
11452 case ixgbe_mac_x550em_a:
11453 device_id = IXGBE_DEV_ID_X550EM_A_VF;
11454 break;
11455 default:
11456 device_id = 0;
11457 break;
11458 }
11459
11460 /* Find the pci device of the offending VF */
11461 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, device_id, NULL);
11462 while (vfdev) {
11463 if (vfdev->devfn == (req_id & 0xFF))
11464 break;
11465 vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
11466 device_id, vfdev);
11467 }
11468 /*
11469 * There's a slim chance the VF could have been hot plugged,
11470 * so if it is no longer present we don't need to issue the
11471 * VFLR. Just clean up the AER in that case.
11472 */
11473 if (vfdev) {
11474 pcie_flr(vfdev);
11475 /* Free device reference count */
11476 pci_dev_put(vfdev);
11477 }
11478 }
11479
11480 /*
11481 * Even though the error may have occurred on the other port
11482 * we still need to increment the vf error reference count for
11483 * both ports because the I/O resume function will be called
11484 * for both of them.
11485 */
11486 adapter->vferr_refcount++;
11487
11488 return PCI_ERS_RESULT_RECOVERED;
11489
11490 skip_bad_vf_detection:
11491 #endif /* CONFIG_PCI_IOV */
11492 if (!test_bit(__IXGBE_SERVICE_INITED, &adapter->state))
11493 return PCI_ERS_RESULT_DISCONNECT;
11494
11495 if (!netif_device_present(netdev))
11496 return PCI_ERS_RESULT_DISCONNECT;
11497
11498 rtnl_lock();
11499 netif_device_detach(netdev);
11500
11501 if (netif_running(netdev))
11502 ixgbe_close_suspend(adapter);
11503
11504 if (state == pci_channel_io_perm_failure) {
11505 rtnl_unlock();
11506 return PCI_ERS_RESULT_DISCONNECT;
11507 }
11508
11509 if (!test_and_set_bit(__IXGBE_DISABLED, &adapter->state))
11510 pci_disable_device(pdev);
11511 rtnl_unlock();
11512
11513 /* Request a slot reset. */
11514 return PCI_ERS_RESULT_NEED_RESET;
11515 }
11516
11517 /**
11518 * ixgbe_io_slot_reset - called after the pci bus has been reset.
11519 * @pdev: Pointer to PCI device
11520 *
11521 * Restart the card from scratch, as if from a cold-boot.
11522 */
11523 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
11524 {
11525 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11526 pci_ers_result_t result;
11527
11528 if (pci_enable_device_mem(pdev)) {
11529 e_err(probe, "Cannot re-enable PCI device after reset.\n");
11530 result = PCI_ERS_RESULT_DISCONNECT;
11531 } else {
11532 smp_mb__before_atomic();
11533 clear_bit(__IXGBE_DISABLED, &adapter->state);
11534 adapter->hw.hw_addr = adapter->io_addr;
11535 pci_set_master(pdev);
11536 pci_restore_state(pdev);
11537 pci_save_state(pdev);
11538
11539 pci_wake_from_d3(pdev, false);
11540
11541 ixgbe_reset(adapter);
11542 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
11543 result = PCI_ERS_RESULT_RECOVERED;
11544 }
11545
11546 return result;
11547 }
11548
11549 /**
11550 * ixgbe_io_resume - called when traffic can start flowing again.
11551 * @pdev: Pointer to PCI device
11552 *
11553 * This callback is called when the error recovery driver tells us that
11554 * its OK to resume normal operation.
11555 */
11556 static void ixgbe_io_resume(struct pci_dev *pdev)
11557 {
11558 struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
11559 struct net_device *netdev = adapter->netdev;
11560
11561 #ifdef CONFIG_PCI_IOV
11562 if (adapter->vferr_refcount) {
11563 e_info(drv, "Resuming after VF err\n");
11564 adapter->vferr_refcount--;
11565 return;
11566 }
11567
11568 #endif
11569 rtnl_lock();
11570 if (netif_running(netdev))
11571 ixgbe_open(netdev);
11572
11573 netif_device_attach(netdev);
11574 rtnl_unlock();
11575 }
11576
11577 static const struct pci_error_handlers ixgbe_err_handler = {
11578 .error_detected = ixgbe_io_error_detected,
11579 .slot_reset = ixgbe_io_slot_reset,
11580 .resume = ixgbe_io_resume,
11581 };
11582
11583 static DEFINE_SIMPLE_DEV_PM_OPS(ixgbe_pm_ops, ixgbe_suspend, ixgbe_resume);
11584
11585 static struct pci_driver ixgbe_driver = {
11586 .name = ixgbe_driver_name,
11587 .id_table = ixgbe_pci_tbl,
11588 .probe = ixgbe_probe,
11589 .remove = ixgbe_remove,
11590 .driver.pm = pm_sleep_ptr(&ixgbe_pm_ops),
11591 .shutdown = ixgbe_shutdown,
11592 .sriov_configure = ixgbe_pci_sriov_configure,
11593 .err_handler = &ixgbe_err_handler
11594 };
11595
11596 /**
11597 * ixgbe_init_module - Driver Registration Routine
11598 *
11599 * ixgbe_init_module is the first routine called when the driver is
11600 * loaded. All it does is register with the PCI subsystem.
11601 **/
11602 static int __init ixgbe_init_module(void)
11603 {
11604 int ret;
11605 pr_info("%s\n", ixgbe_driver_string);
11606 pr_info("%s\n", ixgbe_copyright);
11607
11608 ixgbe_wq = create_singlethread_workqueue(ixgbe_driver_name);
11609 if (!ixgbe_wq) {
11610 pr_err("%s: Failed to create workqueue\n", ixgbe_driver_name);
11611 return -ENOMEM;
11612 }
11613
11614 ixgbe_dbg_init();
11615
11616 ret = pci_register_driver(&ixgbe_driver);
11617 if (ret) {
11618 destroy_workqueue(ixgbe_wq);
11619 ixgbe_dbg_exit();
11620 return ret;
11621 }
11622
11623 #ifdef CONFIG_IXGBE_DCA
11624 dca_register_notify(&dca_notifier);
11625 #endif
11626
11627 return 0;
11628 }
11629
11630 module_init(ixgbe_init_module);
11631
11632 /**
11633 * ixgbe_exit_module - Driver Exit Cleanup Routine
11634 *
11635 * ixgbe_exit_module is called just before the driver is removed
11636 * from memory.
11637 **/
11638 static void __exit ixgbe_exit_module(void)
11639 {
11640 #ifdef CONFIG_IXGBE_DCA
11641 dca_unregister_notify(&dca_notifier);
11642 #endif
11643 pci_unregister_driver(&ixgbe_driver);
11644
11645 ixgbe_dbg_exit();
11646 if (ixgbe_wq) {
11647 destroy_workqueue(ixgbe_wq);
11648 ixgbe_wq = NULL;
11649 }
11650 }
11651
11652 #ifdef CONFIG_IXGBE_DCA
11653 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
11654 void *p)
11655 {
11656 int ret_val;
11657
11658 ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
11659 __ixgbe_notify_dca);
11660
11661 return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
11662 }
11663
11664 #endif /* CONFIG_IXGBE_DCA */
11665
11666 module_exit(ixgbe_exit_module);
11667
11668 /* ixgbe_main.c */
Kernel DRM miscellaneous fixes and cross-tree changes