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drm: bridge: adv7511: remove s32 format from i2s capabilities
[drm/drm-misc.git] / drivers / net / ethernet / microchip / sparx5 / sparx5_main.c
blob2f1013f870fbf2b84db07cd3565b0c35261b7caa
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
3 *
4 * Copyright (c) 2021 Microchip Technology Inc. and its subsidiaries.
5 *
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
8 */
9 #include <linux/module.h>
10 #include <linux/device.h>
11 #include <linux/netdevice.h>
12 #include <linux/platform_device.h>
13 #include <linux/interrupt.h>
14 #include <linux/of.h>
15 #include <linux/of_net.h>
16 #include <linux/of_mdio.h>
17 #include <net/switchdev.h>
18 #include <linux/etherdevice.h>
19 #include <linux/io.h>
20 #include <linux/printk.h>
21 #include <linux/iopoll.h>
22 #include <linux/mfd/syscon.h>
23 #include <linux/regmap.h>
24 #include <linux/types.h>
25 #include <linux/reset.h>
26
27 #include "../lan969x/lan969x.h" /* for lan969x match data */
28
29 #include "sparx5_main_regs.h"
30 #include "sparx5_main.h"
31 #include "sparx5_port.h"
32 #include "sparx5_qos.h"
33 #include "sparx5_vcap_ag_api.h"
34 #include "sparx5_vcap_impl.h"
35
36 const struct sparx5_regs *regs;
37
38 #define IO_RANGES 3
39
40 struct initial_port_config {
41 u32 portno;
42 struct device_node *node;
43 struct sparx5_port_config conf;
44 struct phy *serdes;
45 };
46
47 struct sparx5_ram_config {
48 void __iomem *init_reg;
49 u32 init_val;
50 };
51
52 static const struct sparx5_main_io_resource sparx5_main_iomap[] = {
53 { TARGET_CPU, 0, 0 }, /* 0x600000000 */
54 { TARGET_FDMA, 0x80000, 0 }, /* 0x600080000 */
55 { TARGET_PCEP, 0x400000, 0 }, /* 0x600400000 */
56 { TARGET_DEV2G5, 0x10004000, 1 }, /* 0x610004000 */
57 { TARGET_DEV5G, 0x10008000, 1 }, /* 0x610008000 */
58 { TARGET_PCS5G_BR, 0x1000c000, 1 }, /* 0x61000c000 */
59 { TARGET_DEV2G5 + 1, 0x10010000, 1 }, /* 0x610010000 */
60 { TARGET_DEV5G + 1, 0x10014000, 1 }, /* 0x610014000 */
61 { TARGET_PCS5G_BR + 1, 0x10018000, 1 }, /* 0x610018000 */
62 { TARGET_DEV2G5 + 2, 0x1001c000, 1 }, /* 0x61001c000 */
63 { TARGET_DEV5G + 2, 0x10020000, 1 }, /* 0x610020000 */
64 { TARGET_PCS5G_BR + 2, 0x10024000, 1 }, /* 0x610024000 */
65 { TARGET_DEV2G5 + 6, 0x10028000, 1 }, /* 0x610028000 */
66 { TARGET_DEV5G + 6, 0x1002c000, 1 }, /* 0x61002c000 */
67 { TARGET_PCS5G_BR + 6, 0x10030000, 1 }, /* 0x610030000 */
68 { TARGET_DEV2G5 + 7, 0x10034000, 1 }, /* 0x610034000 */
69 { TARGET_DEV5G + 7, 0x10038000, 1 }, /* 0x610038000 */
70 { TARGET_PCS5G_BR + 7, 0x1003c000, 1 }, /* 0x61003c000 */
71 { TARGET_DEV2G5 + 8, 0x10040000, 1 }, /* 0x610040000 */
72 { TARGET_DEV5G + 8, 0x10044000, 1 }, /* 0x610044000 */
73 { TARGET_PCS5G_BR + 8, 0x10048000, 1 }, /* 0x610048000 */
74 { TARGET_DEV2G5 + 9, 0x1004c000, 1 }, /* 0x61004c000 */
75 { TARGET_DEV5G + 9, 0x10050000, 1 }, /* 0x610050000 */
76 { TARGET_PCS5G_BR + 9, 0x10054000, 1 }, /* 0x610054000 */
77 { TARGET_DEV2G5 + 10, 0x10058000, 1 }, /* 0x610058000 */
78 { TARGET_DEV5G + 10, 0x1005c000, 1 }, /* 0x61005c000 */
79 { TARGET_PCS5G_BR + 10, 0x10060000, 1 }, /* 0x610060000 */
80 { TARGET_DEV2G5 + 11, 0x10064000, 1 }, /* 0x610064000 */
81 { TARGET_DEV5G + 11, 0x10068000, 1 }, /* 0x610068000 */
82 { TARGET_PCS5G_BR + 11, 0x1006c000, 1 }, /* 0x61006c000 */
83 { TARGET_DEV2G5 + 12, 0x10070000, 1 }, /* 0x610070000 */
84 { TARGET_DEV10G, 0x10074000, 1 }, /* 0x610074000 */
85 { TARGET_PCS10G_BR, 0x10078000, 1 }, /* 0x610078000 */
86 { TARGET_DEV2G5 + 14, 0x1007c000, 1 }, /* 0x61007c000 */
87 { TARGET_DEV10G + 2, 0x10080000, 1 }, /* 0x610080000 */
88 { TARGET_PCS10G_BR + 2, 0x10084000, 1 }, /* 0x610084000 */
89 { TARGET_DEV2G5 + 15, 0x10088000, 1 }, /* 0x610088000 */
90 { TARGET_DEV10G + 3, 0x1008c000, 1 }, /* 0x61008c000 */
91 { TARGET_PCS10G_BR + 3, 0x10090000, 1 }, /* 0x610090000 */
92 { TARGET_DEV2G5 + 16, 0x10094000, 1 }, /* 0x610094000 */
93 { TARGET_DEV2G5 + 17, 0x10098000, 1 }, /* 0x610098000 */
94 { TARGET_DEV2G5 + 18, 0x1009c000, 1 }, /* 0x61009c000 */
95 { TARGET_DEV2G5 + 19, 0x100a0000, 1 }, /* 0x6100a0000 */
96 { TARGET_DEV2G5 + 20, 0x100a4000, 1 }, /* 0x6100a4000 */
97 { TARGET_DEV2G5 + 21, 0x100a8000, 1 }, /* 0x6100a8000 */
98 { TARGET_DEV2G5 + 22, 0x100ac000, 1 }, /* 0x6100ac000 */
99 { TARGET_DEV2G5 + 23, 0x100b0000, 1 }, /* 0x6100b0000 */
100 { TARGET_DEV2G5 + 32, 0x100b4000, 1 }, /* 0x6100b4000 */
101 { TARGET_DEV2G5 + 33, 0x100b8000, 1 }, /* 0x6100b8000 */
102 { TARGET_DEV2G5 + 34, 0x100bc000, 1 }, /* 0x6100bc000 */
103 { TARGET_DEV2G5 + 35, 0x100c0000, 1 }, /* 0x6100c0000 */
104 { TARGET_DEV2G5 + 36, 0x100c4000, 1 }, /* 0x6100c4000 */
105 { TARGET_DEV2G5 + 37, 0x100c8000, 1 }, /* 0x6100c8000 */
106 { TARGET_DEV2G5 + 38, 0x100cc000, 1 }, /* 0x6100cc000 */
107 { TARGET_DEV2G5 + 39, 0x100d0000, 1 }, /* 0x6100d0000 */
108 { TARGET_DEV2G5 + 40, 0x100d4000, 1 }, /* 0x6100d4000 */
109 { TARGET_DEV2G5 + 41, 0x100d8000, 1 }, /* 0x6100d8000 */
110 { TARGET_DEV2G5 + 42, 0x100dc000, 1 }, /* 0x6100dc000 */
111 { TARGET_DEV2G5 + 43, 0x100e0000, 1 }, /* 0x6100e0000 */
112 { TARGET_DEV2G5 + 44, 0x100e4000, 1 }, /* 0x6100e4000 */
113 { TARGET_DEV2G5 + 45, 0x100e8000, 1 }, /* 0x6100e8000 */
114 { TARGET_DEV2G5 + 46, 0x100ec000, 1 }, /* 0x6100ec000 */
115 { TARGET_DEV2G5 + 47, 0x100f0000, 1 }, /* 0x6100f0000 */
116 { TARGET_DEV2G5 + 57, 0x100f4000, 1 }, /* 0x6100f4000 */
117 { TARGET_DEV25G + 1, 0x100f8000, 1 }, /* 0x6100f8000 */
118 { TARGET_PCS25G_BR + 1, 0x100fc000, 1 }, /* 0x6100fc000 */
119 { TARGET_DEV2G5 + 59, 0x10104000, 1 }, /* 0x610104000 */
120 { TARGET_DEV25G + 3, 0x10108000, 1 }, /* 0x610108000 */
121 { TARGET_PCS25G_BR + 3, 0x1010c000, 1 }, /* 0x61010c000 */
122 { TARGET_DEV2G5 + 60, 0x10114000, 1 }, /* 0x610114000 */
123 { TARGET_DEV25G + 4, 0x10118000, 1 }, /* 0x610118000 */
124 { TARGET_PCS25G_BR + 4, 0x1011c000, 1 }, /* 0x61011c000 */
125 { TARGET_DEV2G5 + 64, 0x10124000, 1 }, /* 0x610124000 */
126 { TARGET_DEV5G + 12, 0x10128000, 1 }, /* 0x610128000 */
127 { TARGET_PCS5G_BR + 12, 0x1012c000, 1 }, /* 0x61012c000 */
128 { TARGET_PORT_CONF, 0x10130000, 1 }, /* 0x610130000 */
129 { TARGET_DEV2G5 + 3, 0x10404000, 1 }, /* 0x610404000 */
130 { TARGET_DEV5G + 3, 0x10408000, 1 }, /* 0x610408000 */
131 { TARGET_PCS5G_BR + 3, 0x1040c000, 1 }, /* 0x61040c000 */
132 { TARGET_DEV2G5 + 4, 0x10410000, 1 }, /* 0x610410000 */
133 { TARGET_DEV5G + 4, 0x10414000, 1 }, /* 0x610414000 */
134 { TARGET_PCS5G_BR + 4, 0x10418000, 1 }, /* 0x610418000 */
135 { TARGET_DEV2G5 + 5, 0x1041c000, 1 }, /* 0x61041c000 */
136 { TARGET_DEV5G + 5, 0x10420000, 1 }, /* 0x610420000 */
137 { TARGET_PCS5G_BR + 5, 0x10424000, 1 }, /* 0x610424000 */
138 { TARGET_DEV2G5 + 13, 0x10428000, 1 }, /* 0x610428000 */
139 { TARGET_DEV10G + 1, 0x1042c000, 1 }, /* 0x61042c000 */
140 { TARGET_PCS10G_BR + 1, 0x10430000, 1 }, /* 0x610430000 */
141 { TARGET_DEV2G5 + 24, 0x10434000, 1 }, /* 0x610434000 */
142 { TARGET_DEV2G5 + 25, 0x10438000, 1 }, /* 0x610438000 */
143 { TARGET_DEV2G5 + 26, 0x1043c000, 1 }, /* 0x61043c000 */
144 { TARGET_DEV2G5 + 27, 0x10440000, 1 }, /* 0x610440000 */
145 { TARGET_DEV2G5 + 28, 0x10444000, 1 }, /* 0x610444000 */
146 { TARGET_DEV2G5 + 29, 0x10448000, 1 }, /* 0x610448000 */
147 { TARGET_DEV2G5 + 30, 0x1044c000, 1 }, /* 0x61044c000 */
148 { TARGET_DEV2G5 + 31, 0x10450000, 1 }, /* 0x610450000 */
149 { TARGET_DEV2G5 + 48, 0x10454000, 1 }, /* 0x610454000 */
150 { TARGET_DEV10G + 4, 0x10458000, 1 }, /* 0x610458000 */
151 { TARGET_PCS10G_BR + 4, 0x1045c000, 1 }, /* 0x61045c000 */
152 { TARGET_DEV2G5 + 49, 0x10460000, 1 }, /* 0x610460000 */
153 { TARGET_DEV10G + 5, 0x10464000, 1 }, /* 0x610464000 */
154 { TARGET_PCS10G_BR + 5, 0x10468000, 1 }, /* 0x610468000 */
155 { TARGET_DEV2G5 + 50, 0x1046c000, 1 }, /* 0x61046c000 */
156 { TARGET_DEV10G + 6, 0x10470000, 1 }, /* 0x610470000 */
157 { TARGET_PCS10G_BR + 6, 0x10474000, 1 }, /* 0x610474000 */
158 { TARGET_DEV2G5 + 51, 0x10478000, 1 }, /* 0x610478000 */
159 { TARGET_DEV10G + 7, 0x1047c000, 1 }, /* 0x61047c000 */
160 { TARGET_PCS10G_BR + 7, 0x10480000, 1 }, /* 0x610480000 */
161 { TARGET_DEV2G5 + 52, 0x10484000, 1 }, /* 0x610484000 */
162 { TARGET_DEV10G + 8, 0x10488000, 1 }, /* 0x610488000 */
163 { TARGET_PCS10G_BR + 8, 0x1048c000, 1 }, /* 0x61048c000 */
164 { TARGET_DEV2G5 + 53, 0x10490000, 1 }, /* 0x610490000 */
165 { TARGET_DEV10G + 9, 0x10494000, 1 }, /* 0x610494000 */
166 { TARGET_PCS10G_BR + 9, 0x10498000, 1 }, /* 0x610498000 */
167 { TARGET_DEV2G5 + 54, 0x1049c000, 1 }, /* 0x61049c000 */
168 { TARGET_DEV10G + 10, 0x104a0000, 1 }, /* 0x6104a0000 */
169 { TARGET_PCS10G_BR + 10, 0x104a4000, 1 }, /* 0x6104a4000 */
170 { TARGET_DEV2G5 + 55, 0x104a8000, 1 }, /* 0x6104a8000 */
171 { TARGET_DEV10G + 11, 0x104ac000, 1 }, /* 0x6104ac000 */
172 { TARGET_PCS10G_BR + 11, 0x104b0000, 1 }, /* 0x6104b0000 */
173 { TARGET_DEV2G5 + 56, 0x104b4000, 1 }, /* 0x6104b4000 */
174 { TARGET_DEV25G, 0x104b8000, 1 }, /* 0x6104b8000 */
175 { TARGET_PCS25G_BR, 0x104bc000, 1 }, /* 0x6104bc000 */
176 { TARGET_DEV2G5 + 58, 0x104c4000, 1 }, /* 0x6104c4000 */
177 { TARGET_DEV25G + 2, 0x104c8000, 1 }, /* 0x6104c8000 */
178 { TARGET_PCS25G_BR + 2, 0x104cc000, 1 }, /* 0x6104cc000 */
179 { TARGET_DEV2G5 + 61, 0x104d4000, 1 }, /* 0x6104d4000 */
180 { TARGET_DEV25G + 5, 0x104d8000, 1 }, /* 0x6104d8000 */
181 { TARGET_PCS25G_BR + 5, 0x104dc000, 1 }, /* 0x6104dc000 */
182 { TARGET_DEV2G5 + 62, 0x104e4000, 1 }, /* 0x6104e4000 */
183 { TARGET_DEV25G + 6, 0x104e8000, 1 }, /* 0x6104e8000 */
184 { TARGET_PCS25G_BR + 6, 0x104ec000, 1 }, /* 0x6104ec000 */
185 { TARGET_DEV2G5 + 63, 0x104f4000, 1 }, /* 0x6104f4000 */
186 { TARGET_DEV25G + 7, 0x104f8000, 1 }, /* 0x6104f8000 */
187 { TARGET_PCS25G_BR + 7, 0x104fc000, 1 }, /* 0x6104fc000 */
188 { TARGET_DSM, 0x10504000, 1 }, /* 0x610504000 */
189 { TARGET_ASM, 0x10600000, 1 }, /* 0x610600000 */
190 { TARGET_GCB, 0x11010000, 2 }, /* 0x611010000 */
191 { TARGET_QS, 0x11030000, 2 }, /* 0x611030000 */
192 { TARGET_PTP, 0x11040000, 2 }, /* 0x611040000 */
193 { TARGET_ANA_ACL, 0x11050000, 2 }, /* 0x611050000 */
194 { TARGET_LRN, 0x11060000, 2 }, /* 0x611060000 */
195 { TARGET_VCAP_SUPER, 0x11080000, 2 }, /* 0x611080000 */
196 { TARGET_QSYS, 0x110a0000, 2 }, /* 0x6110a0000 */
197 { TARGET_QFWD, 0x110b0000, 2 }, /* 0x6110b0000 */
198 { TARGET_XQS, 0x110c0000, 2 }, /* 0x6110c0000 */
199 { TARGET_VCAP_ES2, 0x110d0000, 2 }, /* 0x6110d0000 */
200 { TARGET_VCAP_ES0, 0x110e0000, 2 }, /* 0x6110e0000 */
201 { TARGET_CLKGEN, 0x11100000, 2 }, /* 0x611100000 */
202 { TARGET_ANA_AC_POL, 0x11200000, 2 }, /* 0x611200000 */
203 { TARGET_QRES, 0x11280000, 2 }, /* 0x611280000 */
204 { TARGET_EACL, 0x112c0000, 2 }, /* 0x6112c0000 */
205 { TARGET_ANA_CL, 0x11400000, 2 }, /* 0x611400000 */
206 { TARGET_ANA_L3, 0x11480000, 2 }, /* 0x611480000 */
207 { TARGET_ANA_AC_SDLB, 0x11500000, 2 }, /* 0x611500000 */
208 { TARGET_HSCH, 0x11580000, 2 }, /* 0x611580000 */
209 { TARGET_REW, 0x11600000, 2 }, /* 0x611600000 */
210 { TARGET_ANA_L2, 0x11800000, 2 }, /* 0x611800000 */
211 { TARGET_ANA_AC, 0x11900000, 2 }, /* 0x611900000 */
212 { TARGET_VOP, 0x11a00000, 2 }, /* 0x611a00000 */
213 };
214
215 bool is_sparx5(struct sparx5 *sparx5)
216 {
217 switch (sparx5->target_ct) {
218 case SPX5_TARGET_CT_7546:
219 case SPX5_TARGET_CT_7549:
220 case SPX5_TARGET_CT_7552:
221 case SPX5_TARGET_CT_7556:
222 case SPX5_TARGET_CT_7558:
223 case SPX5_TARGET_CT_7546TSN:
224 case SPX5_TARGET_CT_7549TSN:
225 case SPX5_TARGET_CT_7552TSN:
226 case SPX5_TARGET_CT_7556TSN:
227 case SPX5_TARGET_CT_7558TSN:
228 return true;
229 default:
230 return false;
231 }
232 }
233
234 static void sparx5_init_features(struct sparx5 *sparx5)
235 {
236 switch (sparx5->target_ct) {
237 case SPX5_TARGET_CT_7546:
238 case SPX5_TARGET_CT_7549:
239 case SPX5_TARGET_CT_7552:
240 case SPX5_TARGET_CT_7556:
241 case SPX5_TARGET_CT_7558:
242 case SPX5_TARGET_CT_7546TSN:
243 case SPX5_TARGET_CT_7549TSN:
244 case SPX5_TARGET_CT_7552TSN:
245 case SPX5_TARGET_CT_7556TSN:
246 case SPX5_TARGET_CT_7558TSN:
247 case SPX5_TARGET_CT_LAN9691VAO:
248 case SPX5_TARGET_CT_LAN9694TSN:
249 case SPX5_TARGET_CT_LAN9694RED:
250 case SPX5_TARGET_CT_LAN9692VAO:
251 case SPX5_TARGET_CT_LAN9696TSN:
252 case SPX5_TARGET_CT_LAN9696RED:
253 case SPX5_TARGET_CT_LAN9693VAO:
254 case SPX5_TARGET_CT_LAN9698TSN:
255 case SPX5_TARGET_CT_LAN9698RED:
256 sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP);
257 break;
258 default:
259 break;
260 }
261 }
262
263 bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature)
264 {
265 return sparx5->features & feature;
266 }
267
268 static int sparx5_create_targets(struct sparx5 *sparx5)
269 {
270 const struct sparx5_main_io_resource *iomap = sparx5->data->iomap;
271 int iomap_size = sparx5->data->iomap_size;
272 int ioranges = sparx5->data->ioranges;
273 struct resource *iores[IO_RANGES];
274 void __iomem *iomem[IO_RANGES];
275 void __iomem *begin[IO_RANGES];
276 int range_id[IO_RANGES];
277 int idx, jdx;
278
279 for (idx = 0, jdx = 0; jdx < iomap_size; jdx++) {
280 const struct sparx5_main_io_resource *io = &iomap[jdx];
281
282 if (idx == io->range) {
283 range_id[idx] = jdx;
284 idx++;
285 }
286 }
287 for (idx = 0; idx < ioranges; idx++) {
288 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM,
289 idx);
290 if (!iores[idx]) {
291 dev_err(sparx5->dev, "Invalid resource\n");
292 return -EINVAL;
293 }
294 iomem[idx] = devm_ioremap(sparx5->dev,
295 iores[idx]->start,
296 resource_size(iores[idx]));
297 if (!iomem[idx]) {
298 dev_err(sparx5->dev, "Unable to get switch registers: %s\n",
299 iores[idx]->name);
300 return -ENOMEM;
301 }
302 begin[idx] = iomem[idx] - iomap[range_id[idx]].offset;
303 }
304 for (jdx = 0; jdx < iomap_size; jdx++) {
305 const struct sparx5_main_io_resource *io = &iomap[jdx];
306
307 sparx5->regs[io->id] = begin[io->range] + io->offset;
308 }
309 return 0;
310 }
311
312 static int sparx5_create_port(struct sparx5 *sparx5,
313 struct initial_port_config *config)
314 {
315 struct sparx5_port *spx5_port;
316 struct net_device *ndev;
317 struct phylink *phylink;
318 int err;
319
320 ndev = sparx5_create_netdev(sparx5, config->portno);
321 if (IS_ERR(ndev)) {
322 dev_err(sparx5->dev, "Could not create net device: %02u\n",
323 config->portno);
324 return PTR_ERR(ndev);
325 }
326 spx5_port = netdev_priv(ndev);
327 spx5_port->of_node = config->node;
328 spx5_port->serdes = config->serdes;
329 spx5_port->pvid = NULL_VID;
330 spx5_port->signd_internal = true;
331 spx5_port->signd_active_high = true;
332 spx5_port->signd_enable = true;
333 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE;
334 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE;
335 spx5_port->custom_etype = 0x8880; /* Vitesse */
336 spx5_port->phylink_pcs.poll = true;
337 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops;
338 spx5_port->phylink_pcs.neg_mode = true;
339 spx5_port->is_mrouter = false;
340 INIT_LIST_HEAD(&spx5_port->tc_templates);
341 sparx5->ports[config->portno] = spx5_port;
342
343 err = sparx5_port_init(sparx5, spx5_port, &config->conf);
344 if (err) {
345 dev_err(sparx5->dev, "port init failed\n");
346 return err;
347 }
348 spx5_port->conf = config->conf;
349
350 /* Setup VLAN */
351 sparx5_vlan_port_setup(sparx5, spx5_port->portno);
352
353 /* Create a phylink for PHY management. Also handles SFPs */
354 spx5_port->phylink_config.dev = &spx5_port->ndev->dev;
355 spx5_port->phylink_config.type = PHYLINK_NETDEV;
356 spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
357 MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD |
358 MAC_2500FD | MAC_5000FD | MAC_10000FD | MAC_25000FD;
359
360 __set_bit(PHY_INTERFACE_MODE_SGMII,
361 spx5_port->phylink_config.supported_interfaces);
362 __set_bit(PHY_INTERFACE_MODE_QSGMII,
363 spx5_port->phylink_config.supported_interfaces);
364 __set_bit(PHY_INTERFACE_MODE_1000BASEX,
365 spx5_port->phylink_config.supported_interfaces);
366 __set_bit(PHY_INTERFACE_MODE_2500BASEX,
367 spx5_port->phylink_config.supported_interfaces);
368
369 if (spx5_port->conf.bandwidth == SPEED_5000 ||
370 spx5_port->conf.bandwidth == SPEED_10000 ||
371 spx5_port->conf.bandwidth == SPEED_25000)
372 __set_bit(PHY_INTERFACE_MODE_5GBASER,
373 spx5_port->phylink_config.supported_interfaces);
374
375 if (spx5_port->conf.bandwidth == SPEED_10000 ||
376 spx5_port->conf.bandwidth == SPEED_25000)
377 __set_bit(PHY_INTERFACE_MODE_10GBASER,
378 spx5_port->phylink_config.supported_interfaces);
379
380 if (spx5_port->conf.bandwidth == SPEED_25000)
381 __set_bit(PHY_INTERFACE_MODE_25GBASER,
382 spx5_port->phylink_config.supported_interfaces);
383
384 phylink = phylink_create(&spx5_port->phylink_config,
385 of_fwnode_handle(config->node),
386 config->conf.phy_mode,
387 &sparx5_phylink_mac_ops);
388 if (IS_ERR(phylink))
389 return PTR_ERR(phylink);
390
391 spx5_port->phylink = phylink;
392
393 return 0;
394 }
395
396 static int sparx5_init_ram(struct sparx5 *s5)
397 {
398 const struct sparx5_ram_config spx5_ram_cfg[] = {
399 {spx5_reg_get(s5, ANA_AC_STAT_RESET), ANA_AC_STAT_RESET_RESET},
400 {spx5_reg_get(s5, ASM_STAT_CFG), ASM_STAT_CFG_STAT_CNT_CLR_SHOT},
401 {spx5_reg_get(s5, QSYS_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
402 {spx5_reg_get(s5, REW_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
403 {spx5_reg_get(s5, VOP_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
404 {spx5_reg_get(s5, ANA_AC_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
405 {spx5_reg_get(s5, ASM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
406 {spx5_reg_get(s5, EACL_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
407 {spx5_reg_get(s5, VCAP_SUPER_RAM_INIT), QSYS_RAM_INIT_RAM_INIT},
408 {spx5_reg_get(s5, DSM_RAM_INIT), QSYS_RAM_INIT_RAM_INIT}
409 };
410 const struct sparx5_ram_config *cfg;
411 u32 value, pending, jdx, idx;
412
413 for (jdx = 0; jdx < 10; jdx++) {
414 pending = ARRAY_SIZE(spx5_ram_cfg);
415 for (idx = 0; idx < ARRAY_SIZE(spx5_ram_cfg); idx++) {
416 cfg = &spx5_ram_cfg[idx];
417 if (jdx == 0) {
418 writel(cfg->init_val, cfg->init_reg);
419 } else {
420 value = readl(cfg->init_reg);
421 if ((value & cfg->init_val) != cfg->init_val)
422 pending--;
423 }
424 }
425 if (!pending)
426 break;
427 usleep_range(USEC_PER_MSEC, 2 * USEC_PER_MSEC);
428 }
429
430 if (pending > 0) {
431 /* Still initializing, should be complete in
432 * less than 1ms
433 */
434 dev_err(s5->dev, "Memory initialization error\n");
435 return -EINVAL;
436 }
437 return 0;
438 }
439
440 static int sparx5_init_switchcore(struct sparx5 *sparx5)
441 {
442 u32 value;
443 int err = 0;
444
445 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(1),
446 EACL_POL_EACL_CFG_EACL_FORCE_INIT,
447 sparx5,
448 EACL_POL_EACL_CFG);
449
450 spx5_rmw(EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(0),
451 EACL_POL_EACL_CFG_EACL_FORCE_INIT,
452 sparx5,
453 EACL_POL_EACL_CFG);
454
455 /* Initialize memories, if not done already */
456 value = spx5_rd(sparx5, HSCH_RESET_CFG);
457 if (!(value & HSCH_RESET_CFG_CORE_ENA)) {
458 err = sparx5_init_ram(sparx5);
459 if (err)
460 return err;
461 }
462
463 /* Reset counters */
464 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET);
465 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG);
466
467 /* Enable switch-core and queue system */
468 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG);
469
470 return 0;
471 }
472
473 static int sparx5_init_coreclock(struct sparx5 *sparx5)
474 {
475 enum sparx5_core_clockfreq freq = sparx5->coreclock;
476 u32 clk_div, clk_period, pol_upd_int, idx;
477
478 /* Verify if core clock frequency is supported on target.
479 * If 'VTSS_CORE_CLOCK_DEFAULT' then the highest supported
480 * freq. is used
481 */
482 switch (sparx5->target_ct) {
483 case SPX5_TARGET_CT_7546:
484 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
485 freq = SPX5_CORE_CLOCK_250MHZ;
486 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ)
487 freq = 0; /* Not supported */
488 break;
489 case SPX5_TARGET_CT_7549:
490 case SPX5_TARGET_CT_7552:
491 case SPX5_TARGET_CT_7556:
492 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
493 freq = SPX5_CORE_CLOCK_500MHZ;
494 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ)
495 freq = 0; /* Not supported */
496 break;
497 case SPX5_TARGET_CT_7558:
498 case SPX5_TARGET_CT_7558TSN:
499 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
500 freq = SPX5_CORE_CLOCK_625MHZ;
501 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ)
502 freq = 0; /* Not supported */
503 break;
504 case SPX5_TARGET_CT_7546TSN:
505 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
506 freq = SPX5_CORE_CLOCK_625MHZ;
507 break;
508 case SPX5_TARGET_CT_7549TSN:
509 case SPX5_TARGET_CT_7552TSN:
510 case SPX5_TARGET_CT_7556TSN:
511 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT)
512 freq = SPX5_CORE_CLOCK_625MHZ;
513 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ)
514 freq = 0; /* Not supported */
515 break;
516 case SPX5_TARGET_CT_LAN9694:
517 case SPX5_TARGET_CT_LAN9691VAO:
518 case SPX5_TARGET_CT_LAN9694TSN:
519 case SPX5_TARGET_CT_LAN9694RED:
520 case SPX5_TARGET_CT_LAN9696:
521 case SPX5_TARGET_CT_LAN9692VAO:
522 case SPX5_TARGET_CT_LAN9696TSN:
523 case SPX5_TARGET_CT_LAN9696RED:
524 case SPX5_TARGET_CT_LAN9698:
525 case SPX5_TARGET_CT_LAN9693VAO:
526 case SPX5_TARGET_CT_LAN9698TSN:
527 case SPX5_TARGET_CT_LAN9698RED:
528 freq = SPX5_CORE_CLOCK_328MHZ;
529 break;
530 default:
531 dev_err(sparx5->dev, "Target (%#04x) not supported\n",
532 sparx5->target_ct);
533 return -ENODEV;
534 }
535
536 if (is_sparx5(sparx5)) {
537 switch (freq) {
538 case SPX5_CORE_CLOCK_250MHZ:
539 clk_div = 10;
540 pol_upd_int = 312;
541 break;
542 case SPX5_CORE_CLOCK_500MHZ:
543 clk_div = 5;
544 pol_upd_int = 624;
545 break;
546 case SPX5_CORE_CLOCK_625MHZ:
547 clk_div = 4;
548 pol_upd_int = 780;
549 break;
550 default:
551 dev_err(sparx5->dev,
552 "%d coreclock not supported on (%#04x)\n",
553 sparx5->coreclock, sparx5->target_ct);
554 return -EINVAL;
555 }
556
557 /* Configure the LCPLL */
558 spx5_rmw(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(clk_div) |
559 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(0) |
560 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(0) |
561 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(0) |
562 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(0) |
563 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(1),
564 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV |
565 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV |
566 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR |
567 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL |
568 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA |
569 CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA,
570 sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG);
571 } else {
572 pol_upd_int = 820; // SPX5_CORE_CLOCK_328MHZ
573 }
574
575 /* Update state with chosen frequency */
576 sparx5->coreclock = freq;
577 clk_period = sparx5_clk_period(freq);
578
579 if (is_sparx5(sparx5))
580 spx5_rmw(HSCH_SYS_CLK_PER_100PS_SET(clk_period / 100),
581 HSCH_SYS_CLK_PER_100PS,
582 sparx5,
583 HSCH_SYS_CLK_PER);
584
585 spx5_rmw(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
586 ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS,
587 sparx5,
588 ANA_AC_POL_BDLB_DLB_CTRL);
589
590 spx5_rmw(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(clk_period / 100),
591 ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS,
592 sparx5,
593 ANA_AC_POL_SLB_DLB_CTRL);
594
595 spx5_rmw(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(clk_period / 100),
596 LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS,
597 sparx5,
598 LRN_AUTOAGE_CFG_1);
599
600 for (idx = 0; idx < sparx5->data->consts->n_sio_clks; idx++)
601 spx5_rmw(GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(clk_period / 100),
602 GCB_SIO_CLOCK_SYS_CLK_PERIOD,
603 sparx5,
604 GCB_SIO_CLOCK(idx));
605
606 spx5_rmw(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET
607 ((256 * 1000) / clk_period),
608 HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY,
609 sparx5,
610 HSCH_TAS_STATEMACHINE_CFG);
611
612 spx5_rmw(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(pol_upd_int),
613 ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT,
614 sparx5,
615 ANA_AC_POL_POL_UPD_INT_CFG);
616
617 return 0;
618 }
619
620 static u32 qlim_wm(struct sparx5 *sparx5, int fraction)
621 {
622 return (sparx5->data->consts->buf_size / SPX5_BUFFER_CELL_SZ - 100) *
623 fraction / 100;
624 }
625
626 static int sparx5_qlim_set(struct sparx5 *sparx5)
627 {
628 const struct sparx5_consts *consts = sparx5->data->consts;
629 u32 res, dp, prio;
630
631 for (res = 0; res < 2; res++) {
632 for (prio = 0; prio < 8; prio++)
633 spx5_wr(0xFFF, sparx5,
634 QRES_RES_CFG(prio +
635 consts->qres_max_prio_idx +
636 res * 1024));
637
638 for (dp = 0; dp < 4; dp++)
639 spx5_wr(0xFFF, sparx5,
640 QRES_RES_CFG(dp +
641 consts->qres_max_colour_idx +
642 res * 1024));
643 }
644
645 /* Set 80,90,95,100% of memory size for top watermarks */
646 spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0));
647 spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0));
648 spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0));
649 spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0));
650
651 return 0;
652 }
653
654 /* Some boards needs to map the SGPIO for signal detect explicitly to the
655 * port module
656 */
657 static void sparx5_board_init(struct sparx5 *sparx5)
658 {
659 int idx;
660
661 if (!sparx5->sd_sgpio_remapping)
662 return;
663
664 /* Enable SGPIO Signal Detect remapping */
665 spx5_rmw(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
666 GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL,
667 sparx5,
668 GCB_HW_SGPIO_SD_CFG);
669
670 /* Refer to LOS SGPIO */
671 for (idx = 0; idx < sparx5->data->consts->n_ports; idx++)
672 if (sparx5->ports[idx])
673 if (sparx5->ports[idx]->conf.sd_sgpio != ~0)
674 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio,
675 sparx5,
676 GCB_HW_SGPIO_TO_SD_MAP_CFG(idx));
677 }
678
679 static int sparx5_start(struct sparx5 *sparx5)
680 {
681 u8 broadcast[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
682 const struct sparx5_consts *consts = sparx5->data->consts;
683 const struct sparx5_ops *ops = sparx5->data->ops;
684 char queue_name[32];
685 u32 idx;
686 int err;
687
688 /* Setup own UPSIDs */
689 for (idx = 0; idx < consts->n_own_upsids; idx++) {
690 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx));
691 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx));
692 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx));
693 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx));
694 }
695
696 /* Enable CPU ports */
697 for (idx = consts->n_ports; idx < consts->n_ports_all; idx++)
698 spx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1),
699 QFWD_SWITCH_PORT_MODE_PORT_ENA,
700 sparx5,
701 QFWD_SWITCH_PORT_MODE(idx));
702
703 /* Init masks */
704 sparx5_update_fwd(sparx5);
705
706 /* CPU copy CPU pgids */
707 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5,
708 ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU)));
709 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5,
710 ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_BCAST)));
711
712 /* Recalc injected frame FCS */
713 for (idx = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0);
714 idx <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); idx++)
715 spx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1),
716 ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA,
717 sparx5, ANA_CL_FILTER_CTRL(idx));
718
719 /* Init MAC table, ageing */
720 sparx5_mact_init(sparx5);
721
722 /* Init PGID table arbitrator */
723 sparx5_pgid_init(sparx5);
724
725 /* Setup VLANs */
726 sparx5_vlan_init(sparx5);
727
728 /* Add host mode BC address (points only to CPU) */
729 sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), broadcast,
730 NULL_VID);
731
732 /* Enable queue limitation watermarks */
733 sparx5_qlim_set(sparx5);
734
735 err = sparx5_config_auto_calendar(sparx5);
736 if (err)
737 return err;
738
739 err = sparx5_config_dsm_calendar(sparx5);
740 if (err)
741 return err;
742
743 /* Init stats */
744 err = sparx_stats_init(sparx5);
745 if (err)
746 return err;
747
748 /* Init mact_sw struct */
749 mutex_init(&sparx5->mact_lock);
750 INIT_LIST_HEAD(&sparx5->mact_entries);
751 snprintf(queue_name, sizeof(queue_name), "%s-mact",
752 dev_name(sparx5->dev));
753 sparx5->mact_queue = create_singlethread_workqueue(queue_name);
754 if (!sparx5->mact_queue)
755 return -ENOMEM;
756
757 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work);
758 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work,
759 SPX5_MACT_PULL_DELAY);
760
761 mutex_init(&sparx5->mdb_lock);
762 INIT_LIST_HEAD(&sparx5->mdb_entries);
763
764 err = sparx5_register_netdevs(sparx5);
765 if (err)
766 return err;
767
768 sparx5_board_init(sparx5);
769 err = sparx5_register_notifier_blocks(sparx5);
770 if (err)
771 return err;
772
773 err = sparx5_vcap_init(sparx5);
774 if (err) {
775 sparx5_unregister_notifier_blocks(sparx5);
776 return err;
777 }
778
779 /* Start Frame DMA with fallback to register based INJ/XTR */
780 err = -ENXIO;
781 if (sparx5->fdma_irq >= 0 && is_sparx5(sparx5)) {
782 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0)
783 err = devm_request_threaded_irq(sparx5->dev,
784 sparx5->fdma_irq,
785 NULL,
786 sparx5_fdma_handler,
787 IRQF_ONESHOT,
788 "sparx5-fdma", sparx5);
789 if (!err)
790 err = sparx5_fdma_start(sparx5);
791 if (err)
792 sparx5->fdma_irq = -ENXIO;
793 } else {
794 sparx5->fdma_irq = -ENXIO;
795 }
796 if (err && sparx5->xtr_irq >= 0) {
797 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq,
798 sparx5_xtr_handler, IRQF_SHARED,
799 "sparx5-xtr", sparx5);
800 if (!err)
801 err = sparx5_manual_injection_mode(sparx5);
802 if (err)
803 sparx5->xtr_irq = -ENXIO;
804 } else {
805 sparx5->xtr_irq = -ENXIO;
806 }
807
808 if (sparx5->ptp_irq >= 0 &&
809 sparx5_has_feature(sparx5, SPX5_FEATURE_PTP)) {
810 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq,
811 NULL, ops->ptp_irq_handler,
812 IRQF_ONESHOT, "sparx5-ptp",
813 sparx5);
814 if (err)
815 sparx5->ptp_irq = -ENXIO;
816
817 sparx5->ptp = 1;
818 }
819
820 return err;
821 }
822
823 static void sparx5_cleanup_ports(struct sparx5 *sparx5)
824 {
825 sparx5_unregister_netdevs(sparx5);
826 sparx5_destroy_netdevs(sparx5);
827 }
828
829 static int mchp_sparx5_probe(struct platform_device *pdev)
830 {
831 struct initial_port_config *configs, *config;
832 struct device_node *np = pdev->dev.of_node;
833 struct device_node *ports, *portnp;
834 struct reset_control *reset;
835 struct sparx5 *sparx5;
836 int idx = 0, err = 0;
837
838 if (!np && !pdev->dev.platform_data)
839 return -ENODEV;
840
841 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL);
842 if (!sparx5)
843 return -ENOMEM;
844
845 platform_set_drvdata(pdev, sparx5);
846 sparx5->pdev = pdev;
847 sparx5->dev = &pdev->dev;
848 spin_lock_init(&sparx5->tx_lock);
849
850 sparx5->data = device_get_match_data(sparx5->dev);
851 if (!sparx5->data)
852 return -EINVAL;
853
854 regs = sparx5->data->regs;
855
856 /* Do switch core reset if available */
857 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch");
858 if (IS_ERR(reset))
859 return dev_err_probe(&pdev->dev, PTR_ERR(reset),
860 "Failed to get switch reset controller.\n");
861 reset_control_reset(reset);
862
863 /* Default values, some from DT */
864 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT;
865
866 sparx5->debugfs_root = debugfs_create_dir("sparx5", NULL);
867
868 ports = of_get_child_by_name(np, "ethernet-ports");
869 if (!ports) {
870 dev_err(sparx5->dev, "no ethernet-ports child node found\n");
871 return -ENODEV;
872 }
873 sparx5->port_count = of_get_child_count(ports);
874
875 configs = kcalloc(sparx5->port_count,
876 sizeof(struct initial_port_config), GFP_KERNEL);
877 if (!configs) {
878 err = -ENOMEM;
879 goto cleanup_pnode;
880 }
881
882 for_each_available_child_of_node(ports, portnp) {
883 struct sparx5_port_config *conf;
884 struct phy *serdes;
885 u32 portno;
886
887 err = of_property_read_u32(portnp, "reg", &portno);
888 if (err) {
889 dev_err(sparx5->dev, "port reg property error\n");
890 continue;
891 }
892 config = &configs[idx];
893 conf = &config->conf;
894 conf->speed = SPEED_UNKNOWN;
895 conf->bandwidth = SPEED_UNKNOWN;
896 err = of_get_phy_mode(portnp, &conf->phy_mode);
897 if (err) {
898 dev_err(sparx5->dev, "port %u: missing phy-mode\n",
899 portno);
900 continue;
901 }
902 err = of_property_read_u32(portnp, "microchip,bandwidth",
903 &conf->bandwidth);
904 if (err) {
905 dev_err(sparx5->dev, "port %u: missing bandwidth\n",
906 portno);
907 continue;
908 }
909 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio);
910 if (err)
911 conf->sd_sgpio = ~0;
912 else
913 sparx5->sd_sgpio_remapping = true;
914 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL);
915 if (IS_ERR(serdes)) {
916 err = dev_err_probe(sparx5->dev, PTR_ERR(serdes),
917 "port %u: missing serdes\n",
918 portno);
919 of_node_put(portnp);
920 goto cleanup_config;
921 }
922 config->portno = portno;
923 config->node = portnp;
924 config->serdes = serdes;
925
926 conf->media = PHY_MEDIA_DAC;
927 conf->serdes_reset = true;
928 conf->portmode = conf->phy_mode;
929 conf->power_down = true;
930 idx++;
931 }
932
933 err = sparx5_create_targets(sparx5);
934 if (err)
935 goto cleanup_config;
936
937 if (of_get_mac_address(np, sparx5->base_mac)) {
938 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n");
939 eth_random_addr(sparx5->base_mac);
940 sparx5->base_mac[5] = 0;
941 }
942
943 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma");
944 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr");
945 sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp");
946
947 /* Read chip ID to check CPU interface */
948 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID);
949
950 sparx5->target_ct = (enum spx5_target_chiptype)
951 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id);
952
953 /* Initialize the features based on the target */
954 sparx5_init_features(sparx5);
955
956 /* Initialize Switchcore and internal RAMs */
957 err = sparx5_init_switchcore(sparx5);
958 if (err) {
959 dev_err(sparx5->dev, "Switchcore initialization error\n");
960 goto cleanup_config;
961 }
962
963 /* Initialize the LC-PLL (core clock) and set affected registers */
964 err = sparx5_init_coreclock(sparx5);
965 if (err) {
966 dev_err(sparx5->dev, "LC-PLL initialization error\n");
967 goto cleanup_config;
968 }
969
970 for (idx = 0; idx < sparx5->port_count; ++idx) {
971 config = &configs[idx];
972 if (!config->node)
973 continue;
974
975 err = sparx5_create_port(sparx5, config);
976 if (err) {
977 dev_err(sparx5->dev, "port create error\n");
978 goto cleanup_ports;
979 }
980 }
981
982 err = sparx5_start(sparx5);
983 if (err) {
984 dev_err(sparx5->dev, "Start failed\n");
985 goto cleanup_ports;
986 }
987
988 err = sparx5_qos_init(sparx5);
989 if (err) {
990 dev_err(sparx5->dev, "Failed to initialize QoS\n");
991 goto cleanup_ports;
992 }
993
994 err = sparx5_ptp_init(sparx5);
995 if (err) {
996 dev_err(sparx5->dev, "PTP failed\n");
997 goto cleanup_ports;
998 }
999
1000 INIT_LIST_HEAD(&sparx5->mall_entries);
1001
1002 goto cleanup_config;
1003
1004 cleanup_ports:
1005 sparx5_cleanup_ports(sparx5);
1006 if (sparx5->mact_queue)
1007 destroy_workqueue(sparx5->mact_queue);
1008 cleanup_config:
1009 kfree(configs);
1010 cleanup_pnode:
1011 of_node_put(ports);
1012 return err;
1013 }
1014
1015 static void mchp_sparx5_remove(struct platform_device *pdev)
1016 {
1017 struct sparx5 *sparx5 = platform_get_drvdata(pdev);
1018
1019 debugfs_remove_recursive(sparx5->debugfs_root);
1020 if (sparx5->xtr_irq) {
1021 disable_irq(sparx5->xtr_irq);
1022 sparx5->xtr_irq = -ENXIO;
1023 }
1024 if (sparx5->fdma_irq) {
1025 disable_irq(sparx5->fdma_irq);
1026 sparx5->fdma_irq = -ENXIO;
1027 }
1028 sparx5_ptp_deinit(sparx5);
1029 sparx5_fdma_stop(sparx5);
1030 sparx5_cleanup_ports(sparx5);
1031 sparx5_vcap_destroy(sparx5);
1032 /* Unregister netdevs */
1033 sparx5_unregister_notifier_blocks(sparx5);
1034 destroy_workqueue(sparx5->mact_queue);
1035 }
1036
1037 static const struct sparx5_regs sparx5_regs = {
1038 .tsize = sparx5_tsize,
1039 .gaddr = sparx5_gaddr,
1040 .gcnt = sparx5_gcnt,
1041 .gsize = sparx5_gsize,
1042 .raddr = sparx5_raddr,
1043 .rcnt = sparx5_rcnt,
1044 .fpos = sparx5_fpos,
1045 .fsize = sparx5_fsize,
1046 };
1047
1048 static const struct sparx5_consts sparx5_consts = {
1049 .n_ports = 65,
1050 .n_ports_all = 70,
1051 .n_hsch_l1_elems = 64,
1052 .n_hsch_queues = 8,
1053 .n_lb_groups = 10,
1054 .n_pgids = 2113, /* (2048 + n_ports) */
1055 .n_sio_clks = 3,
1056 .n_own_upsids = 3,
1057 .n_auto_cals = 7,
1058 .n_filters = 1024,
1059 .n_gates = 1024,
1060 .n_sdlbs = 4096,
1061 .n_dsm_cal_taxis = 8,
1062 .buf_size = 4194280,
1063 .qres_max_prio_idx = 630,
1064 .qres_max_colour_idx = 638,
1065 .tod_pin = 4,
1066 .vcaps = sparx5_vcaps,
1067 .vcaps_cfg = sparx5_vcap_inst_cfg,
1068 .vcap_stats = &sparx5_vcap_stats,
1069 };
1070
1071 static const struct sparx5_ops sparx5_ops = {
1072 .is_port_2g5 = &sparx5_port_is_2g5,
1073 .is_port_5g = &sparx5_port_is_5g,
1074 .is_port_10g = &sparx5_port_is_10g,
1075 .is_port_25g = &sparx5_port_is_25g,
1076 .get_port_dev_index = &sparx5_port_dev_mapping,
1077 .get_port_dev_bit = &sparx5_port_dev_mapping,
1078 .get_hsch_max_group_rate = &sparx5_get_hsch_max_group_rate,
1079 .get_sdlb_group = &sparx5_get_sdlb_group,
1080 .set_port_mux = &sparx5_port_mux_set,
1081 .ptp_irq_handler = &sparx5_ptp_irq_handler,
1082 .dsm_calendar_calc = &sparx5_dsm_calendar_calc,
1083 };
1084
1085 static const struct sparx5_match_data sparx5_desc = {
1086 .iomap = sparx5_main_iomap,
1087 .iomap_size = ARRAY_SIZE(sparx5_main_iomap),
1088 .ioranges = 3,
1089 .regs = &sparx5_regs,
1090 .consts = &sparx5_consts,
1091 .ops = &sparx5_ops,
1092 };
1093
1094 static const struct of_device_id mchp_sparx5_match[] = {
1095 { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc },
1096 #if IS_ENABLED(CONFIG_LAN969X_SWITCH)
1097 { .compatible = "microchip,lan9691-switch", .data = &lan969x_desc },
1098 #endif
1099 { }
1100 };
1101 MODULE_DEVICE_TABLE(of, mchp_sparx5_match);
1102
1103 static struct platform_driver mchp_sparx5_driver = {
1104 .probe = mchp_sparx5_probe,
1105 .remove = mchp_sparx5_remove,
1106 .driver = {
1107 .name = "sparx5-switch",
1108 .of_match_table = mchp_sparx5_match,
1109 },
1110 };
1111
1112 module_platform_driver(mchp_sparx5_driver);
1113
1114 MODULE_DESCRIPTION("Microchip Sparx5 switch driver");
1115 MODULE_AUTHOR("Steen Hegelund <steen.hegelund@microchip.com>");
1116 MODULE_LICENSE("Dual MIT/GPL");
Kernel DRM miscellaneous fixes and cross-tree changes