drivers/net/ethernet/microchip/sparx5/sparx5_main_regs.h

   1 /* SPDX-License-Identifier: GPL-2.0+
   2  * Microchip Sparx5 Switch driver
   3  *
   4  * Copyright (c) 2024 Microchip Technology Inc.
   5  */
   6
   7 /* This file is autogenerated by cml-utils 2024-10-04 10:40:40 +0200.
   8  * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b
   9  */
  10
  11 #ifndef _SPARX5_MAIN_REGS_H_
  12 #define _SPARX5_MAIN_REGS_H_
  13
  14 #include <linux/bitfield.h>
  15 #include <linux/types.h>
  16 #include <linux/bug.h>
  17
  18 #include "sparx5_regs.h"
  19
  20 enum sparx5_target {
  21         TARGET_ANA_AC = 1,
  22         TARGET_ANA_ACL = 2,
  23         TARGET_ANA_AC_POL = 4,
  24         TARGET_ANA_AC_SDLB = 5,
  25         TARGET_ANA_CL = 6,
  26         TARGET_ANA_L2 = 7,
  27         TARGET_ANA_L3 = 8,
  28         TARGET_ASM = 9,
  29         TARGET_CLKGEN = 11,
  30         TARGET_CPU = 12,
  31         TARGET_DEV10G = 17,
  32         TARGET_DEV25G = 29,
  33         TARGET_DEV2G5 = 37,
  34         TARGET_DEV5G = 102,
  35         TARGET_DSM = 115,
  36         TARGET_EACL = 116,
  37         TARGET_FDMA = 117,
  38         TARGET_GCB = 118,
  39         TARGET_HSCH = 119,
  40         TARGET_LRN = 122,
  41         TARGET_PCEP = 129,
  42         TARGET_PCS10G_BR = 132,
  43         TARGET_PCS25G_BR = 144,
  44         TARGET_PCS5G_BR = 160,
  45         TARGET_PORT_CONF = 173,
  46         TARGET_PTP = 174,
  47         TARGET_QFWD = 175,
  48         TARGET_QRES = 176,
  49         TARGET_QS = 177,
  50         TARGET_QSYS = 178,
  51         TARGET_REW = 179,
  52         TARGET_VCAP_ES0 = 323,
  53         TARGET_VCAP_ES2 = 324,
  54         TARGET_VCAP_SUPER = 326,
  55         TARGET_VOP = 327,
  56         TARGET_XQS = 331,
  57         NUM_TARGETS = 517
  58 };
  59
  60 /* sparx5_main.c
  61  *
  62  * This is used by the register macros to access chip differences (if any) in:
  63  * target size, register address, register count, group address, group count,
  64  * group size, field position and field size.
  65  */
  66 extern const struct sparx5_regs *regs;
  67
  68 /* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */
  69 #define spx5_field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))
  70 #define spx5_field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (_mask))
  71
  72 #define __REG(...)    __VA_ARGS__
  73
  74 /* ANA_AC:RAM_CTRL:RAM_INIT */
  75 #define ANA_AC_RAM_INIT                                                        \
  76         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_RAM_CTRL], 0, 1, 4, 0,\
  77               0, 1, 4)
  78
  79 #define ANA_AC_RAM_INIT_RAM_INIT                 BIT(1)
  80 #define ANA_AC_RAM_INIT_RAM_INIT_SET(x)\
  81         FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x)
  82 #define ANA_AC_RAM_INIT_RAM_INIT_GET(x)\
  83         FIELD_GET(ANA_AC_RAM_INIT_RAM_INIT, x)
  84
  85 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK             BIT(0)
  86 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_SET(x)\
  87         FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
  88 #define ANA_AC_RAM_INIT_RAM_CFG_HOOK_GET(x)\
  89         FIELD_GET(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x)
  90
  91 /* ANA_AC:PS_COMMON:OWN_UPSID */
  92 #define ANA_AC_OWN_UPSID(r)                                                    \
  93         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PS_COMMON], 0, 1, 352,\
  94               52, r, regs->rcnt[RC_ANA_AC_OWN_UPSID], 4)
  95
  96 #define ANA_AC_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
  97 #define ANA_AC_OWN_UPSID_OWN_UPSID_SET(x)\
  98         FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x)
  99 #define ANA_AC_OWN_UPSID_OWN_UPSID_GET(x)\
 100         FIELD_GET(ANA_AC_OWN_UPSID_OWN_UPSID, x)
 101
 102 /* ANA_AC:MIRROR_PROBE:PROBE_CFG */
 103 #define ANA_AC_PROBE_CFG(g)                                                    \
 104         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3,  \
 105               32, 0, 0, 1, 4)
 106
 107 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD     GENMASK(31, 27)
 108 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_SET(x)\
 109         FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)
 110 #define ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD_GET(x)\
 111         FIELD_GET(ANA_AC_PROBE_CFG_PROBE_RX_CPU_AND_VD, x)
 112
 113 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET           GENMASK(26, 19)
 114 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_SET(x)\
 115         FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)
 116 #define ANA_AC_PROBE_CFG_PROBE_CPU_SET_GET(x)\
 117         FIELD_GET(ANA_AC_PROBE_CFG_PROBE_CPU_SET, x)
 118
 119 #define ANA_AC_PROBE_CFG_PROBE_VID               GENMASK(18, 6)
 120 #define ANA_AC_PROBE_CFG_PROBE_VID_SET(x)\
 121         FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VID, x)
 122 #define ANA_AC_PROBE_CFG_PROBE_VID_GET(x)\
 123         FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VID, x)
 124
 125 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE         GENMASK(5, 4)
 126 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_SET(x)\
 127         FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)
 128 #define ANA_AC_PROBE_CFG_PROBE_VLAN_MODE_GET(x)\
 129         FIELD_GET(ANA_AC_PROBE_CFG_PROBE_VLAN_MODE, x)
 130
 131 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE          GENMASK(3, 2)
 132 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_SET(x)\
 133         FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)
 134 #define ANA_AC_PROBE_CFG_PROBE_MAC_MODE_GET(x)\
 135         FIELD_GET(ANA_AC_PROBE_CFG_PROBE_MAC_MODE, x)
 136
 137 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION         GENMASK(1, 0)
 138 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_SET(x)\
 139         FIELD_PREP(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)
 140 #define ANA_AC_PROBE_CFG_PROBE_DIRECTION_GET(x)\
 141         FIELD_GET(ANA_AC_PROBE_CFG_PROBE_DIRECTION, x)
 142
 143 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG */
 144 #define ANA_AC_PROBE_PORT_CFG(g)                                               \
 145         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3,  \
 146               32, 8, 0, 1, 4)
 147
 148 /* SPARX5 ONLY */
 149 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG1 */
 150 #define ANA_AC_PROBE_PORT_CFG1(g)                                              \
 151         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3,  \
 152               32, 12, 0, 1, 4)
 153
 154 /* SPARX5 ONLY */
 155 /* ANA_AC:MIRROR_PROBE:PROBE_PORT_CFG2 */
 156 #define ANA_AC_PROBE_PORT_CFG2(g)                                              \
 157         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_MIRROR_PROBE], g, 3,  \
 158               32, 16, 0, 1, 4)
 159
 160 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2  BIT(0)
 161 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_SET(x)\
 162         FIELD_PREP(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)
 163 #define ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2_GET(x)\
 164         FIELD_GET(ANA_AC_PROBE_PORT_CFG2_PROBE_PORT_MASK2, x)
 165
 166 /* ANA_AC:SRC:SRC_CFG */
 167 #define ANA_AC_SRC_CFG(g)                                                      \
 168         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g,              \
 169               regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 0, 0, 1, 4)
 170
 171 /* SPARX5 ONLY */
 172 /* ANA_AC:SRC:SRC_CFG1 */
 173 #define ANA_AC_SRC_CFG1(g)                                                     \
 174         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g,              \
 175               regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 4, 0, 1, 4)
 176
 177 /* SPARX5 ONLY */
 178 /* ANA_AC:SRC:SRC_CFG2 */
 179 #define ANA_AC_SRC_CFG2(g)                                                     \
 180         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SRC], g,              \
 181               regs->gcnt[GC_ANA_AC_SRC], regs->gsize[GW_ANA_AC_SRC], 8, 0, 1, 4)
 182
 183 #define ANA_AC_SRC_CFG2_PORT_MASK2               BIT(0)
 184 #define ANA_AC_SRC_CFG2_PORT_MASK2_SET(x)\
 185         FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x)
 186 #define ANA_AC_SRC_CFG2_PORT_MASK2_GET(x)\
 187         FIELD_GET(ANA_AC_SRC_CFG2_PORT_MASK2, x)
 188
 189 /* ANA_AC:PGID:PGID_CFG */
 190 #define ANA_AC_PGID_CFG(g)                                                     \
 191         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g,             \
 192               regs->gcnt[GC_ANA_AC_PGID], 16, 0, 0, 1, 4)
 193
 194 /* SPARX5 ONLY */
 195 /* ANA_AC:PGID:PGID_CFG1 */
 196 #define ANA_AC_PGID_CFG1(g)                                                    \
 197         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g,             \
 198               regs->gcnt[GC_ANA_AC_PGID], 16, 4, 0, 1, 4)
 199
 200 /* SPARX5 ONLY */
 201 /* ANA_AC:PGID:PGID_CFG2 */
 202 #define ANA_AC_PGID_CFG2(g)                                                    \
 203         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g,             \
 204               regs->gcnt[GC_ANA_AC_PGID], 16, 8, 0, 1, 4)
 205
 206 #define ANA_AC_PGID_CFG2_PORT_MASK2              BIT(0)
 207 #define ANA_AC_PGID_CFG2_PORT_MASK2_SET(x)\
 208         FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x)
 209 #define ANA_AC_PGID_CFG2_PORT_MASK2_GET(x)\
 210         FIELD_GET(ANA_AC_PGID_CFG2_PORT_MASK2, x)
 211
 212 /* ANA_AC:PGID:PGID_MISC_CFG */
 213 #define ANA_AC_PGID_MISC_CFG(g)                                                \
 214         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_PGID], g,             \
 215               regs->gcnt[GC_ANA_AC_PGID], 16, 12, 0, 1, 4)
 216
 217 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU         GENMASK(6, 4)
 218 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_SET(x)\
 219         FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
 220 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_QU_GET(x)\
 221         FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x)
 222
 223 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA      BIT(1)
 224 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_SET(x)\
 225         FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
 226 #define ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA_GET(x)\
 227         FIELD_GET(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x)
 228
 229 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA   BIT(0)
 230 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(x)\
 231         FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
 232 #define ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_GET(x)\
 233         FIELD_GET(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x)
 234
 235 /* ANA_AC:TSN_SF:TSN_SF */
 236 #define ANA_AC_TSN_SF                                                          \
 237         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF], 0, 1, 4, 0,  \
 238               0, 1, 4)
 239
 240 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY BIT(9)
 241 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_SET(x)\
 242         FIELD_PREP(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x)
 243 #define ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY_GET(x)\
 244         FIELD_GET(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x)
 245
 246 #define ANA_AC_TSN_SF_PORT_NUM\
 247         GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_PORT_NUM] + 0 - 1, 0)
 248 #define ANA_AC_TSN_SF_PORT_NUM_SET(x)\
 249         spx5_field_prep(ANA_AC_TSN_SF_PORT_NUM, x)
 250 #define ANA_AC_TSN_SF_PORT_NUM_GET(x)\
 251         spx5_field_get(ANA_AC_TSN_SF_PORT_NUM, x)
 252
 253 /* ANA_AC:TSN_SF_CFG:TSN_SF_CFG */
 254 #define ANA_AC_TSN_SF_CFG(g)                                                   \
 255         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_CFG], g,       \
 256               regs->gcnt[GC_ANA_AC_TSN_SF_CFG], 4, 0, 0, 1, 4)
 257
 258 #define ANA_AC_TSN_SF_CFG_TSN_SGID\
 259         GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] + 16 - 1, 16)
 260 #define ANA_AC_TSN_SF_CFG_TSN_SGID_SET(x)\
 261         spx5_field_prep(ANA_AC_TSN_SF_CFG_TSN_SGID, x)
 262 #define ANA_AC_TSN_SF_CFG_TSN_SGID_GET(x)\
 263         spx5_field_get(ANA_AC_TSN_SF_CFG_TSN_SGID, x)
 264
 265 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU            GENMASK(15, 2)
 266 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_SET(x)\
 267         FIELD_PREP(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x)
 268 #define ANA_AC_TSN_SF_CFG_TSN_MAX_SDU_GET(x)\
 269         FIELD_GET(ANA_AC_TSN_SF_CFG_TSN_MAX_SDU, x)
 270
 271 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA     BIT(1)
 272 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_SET(x)\
 273         FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x)
 274 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA_GET(x)\
 275         FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_ENA, x)
 276
 277 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE   BIT(0)
 278 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_SET(x)\
 279         FIELD_PREP(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x)
 280 #define ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE_GET(x)\
 281         FIELD_GET(ANA_AC_TSN_SF_CFG_BLOCK_OVERSIZE_STATE, x)
 282
 283 /* ANA_AC:TSN_SF_STATUS:TSN_SF_STATUS */
 284 #define ANA_AC_TSN_SF_STATUS                                                   \
 285         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_TSN_SF_STATUS], 0, 1, \
 286               16, 0, 0, 1, 4)
 287
 288 #define ANA_AC_TSN_SF_STATUS_FRM_LEN             GENMASK(25, 12)
 289 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_SET(x)\
 290         FIELD_PREP(ANA_AC_TSN_SF_STATUS_FRM_LEN, x)
 291 #define ANA_AC_TSN_SF_STATUS_FRM_LEN_GET(x)\
 292         FIELD_GET(ANA_AC_TSN_SF_STATUS_FRM_LEN, x)
 293
 294 #define ANA_AC_TSN_SF_STATUS_DLB_DROP            BIT(11)
 295 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_SET(x)\
 296         FIELD_PREP(ANA_AC_TSN_SF_STATUS_DLB_DROP, x)
 297 #define ANA_AC_TSN_SF_STATUS_DLB_DROP_GET(x)\
 298         FIELD_GET(ANA_AC_TSN_SF_STATUS_DLB_DROP, x)
 299
 300 #define ANA_AC_TSN_SF_STATUS_TSN_SFID\
 301         GENMASK(regs->fsize[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] + 1 - 1, 1)
 302 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_SET(x)\
 303         spx5_field_prep(ANA_AC_TSN_SF_STATUS_TSN_SFID, x)
 304 #define ANA_AC_TSN_SF_STATUS_TSN_SFID_GET(x)\
 305         spx5_field_get(ANA_AC_TSN_SF_STATUS_TSN_SFID, x)
 306
 307 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD          BIT(0)
 308 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_SET(x)\
 309         FIELD_PREP(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x)
 310 #define ANA_AC_TSN_SF_STATUS_TSTAMP_VLD_GET(x)\
 311         FIELD_GET(ANA_AC_TSN_SF_STATUS_TSTAMP_VLD, x)
 312
 313 /* ANA_AC:SG_ACCESS:SG_ACCESS_CTRL */
 314 #define ANA_AC_SG_ACCESS_CTRL                                                  \
 315         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \
 316               0, 0, 1, 4)
 317
 318 #define ANA_AC_SG_ACCESS_CTRL_SGID\
 319         GENMASK(regs->fsize[FW_ANA_AC_SG_ACCESS_CTRL_SGID] + 0 - 1, 0)
 320 #define ANA_AC_SG_ACCESS_CTRL_SGID_SET(x)\
 321         spx5_field_prep(ANA_AC_SG_ACCESS_CTRL_SGID, x)
 322 #define ANA_AC_SG_ACCESS_CTRL_SGID_GET(x)\
 323         spx5_field_get(ANA_AC_SG_ACCESS_CTRL_SGID, x)
 324
 325 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE      BIT(28)
 326 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_SET(x)\
 327         FIELD_PREP(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x)
 328 #define ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE_GET(x)\
 329         FIELD_GET(ANA_AC_SG_ACCESS_CTRL_CONFIG_CHANGE, x)
 330
 331 /* ANA_AC:SG_ACCESS:SG_CYCLETIME_UPDATE_PERIOD */
 332 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD                                      \
 333         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_ACCESS], 0, 1, 12, \
 334               8, 0, 1, 4)
 335
 336 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS GENMASK(15, 0)
 337 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_SET(x)\
 338         FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x)
 339 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS_GET(x)\
 340         FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_CLKS, x)
 341
 342 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA BIT(31)
 343 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_SET(x)\
 344         FIELD_PREP(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x)
 345 #define ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA_GET(x)\
 346         FIELD_GET(ANA_AC_SG_CYCLETIME_UPDATE_PERIOD_SG_CT_UPDATE_ENA, x)
 347
 348 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_1 */
 349 #define ANA_AC_SG_CONFIG_REG_1                                                 \
 350         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
 351               48, 0, 1, 4)
 352
 353 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_2 */
 354 #define ANA_AC_SG_CONFIG_REG_2                                                 \
 355         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
 356               52, 0, 1, 4)
 357
 358 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_3 */
 359 #define ANA_AC_SG_CONFIG_REG_3                                                 \
 360         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
 361               56, 0, 1, 4)
 362
 363 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB GENMASK(15, 0)
 364 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_SET(x)\
 365         FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x)
 366 #define ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB_GET(x)\
 367         FIELD_GET(ANA_AC_SG_CONFIG_REG_3_BASE_TIME_SEC_MSB, x)
 368
 369 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH       GENMASK(18, 16)
 370 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_SET(x)\
 371         FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x)
 372 #define ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH_GET(x)\
 373         FIELD_GET(ANA_AC_SG_CONFIG_REG_3_LIST_LENGTH, x)
 374
 375 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE       BIT(20)
 376 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_SET(x)\
 377         FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x)
 378 #define ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE_GET(x)\
 379         FIELD_GET(ANA_AC_SG_CONFIG_REG_3_GATE_ENABLE, x)
 380
 381 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS          GENMASK(24, 21)
 382 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_SET(x)\
 383         FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x)
 384 #define ANA_AC_SG_CONFIG_REG_3_INIT_IPS_GET(x)\
 385         FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_IPS, x)
 386
 387 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE   BIT(25)
 388 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_SET(x)\
 389         FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x)
 390 #define ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE_GET(x)\
 391         FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INIT_GATE_STATE, x)
 392
 393 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA    BIT(26)
 394 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_SET(x)\
 395         FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x)
 396 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA_GET(x)\
 397         FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX_ENA, x)
 398
 399 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX        BIT(27)
 400 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_SET(x)\
 401         FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x)
 402 #define ANA_AC_SG_CONFIG_REG_3_INVALID_RX_GET(x)\
 403         FIELD_GET(ANA_AC_SG_CONFIG_REG_3_INVALID_RX, x)
 404
 405 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA BIT(28)
 406 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_SET(x)\
 407         FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x)
 408 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA_GET(x)\
 409         FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_ENA, x)
 410
 411 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED   BIT(29)
 412 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_SET(x)\
 413         FIELD_PREP(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x)
 414 #define ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED_GET(x)\
 415         FIELD_GET(ANA_AC_SG_CONFIG_REG_3_OCTETS_EXCEEDED, x)
 416
 417 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_4 */
 418 #define ANA_AC_SG_CONFIG_REG_4                                                 \
 419         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
 420               60, 0, 1, 4)
 421
 422 /* ANA_AC:SG_CONFIG:SG_CONFIG_REG_5 */
 423 #define ANA_AC_SG_CONFIG_REG_5                                                 \
 424         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
 425               64, 0, 1, 4)
 426
 427 /* ANA_AC:SG_CONFIG:SG_GCL_GS_CONFIG */
 428 #define ANA_AC_SG_GCL_GS_CONFIG(r)                                             \
 429         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
 430               0, r, 4, 4)
 431
 432 #define ANA_AC_SG_GCL_GS_CONFIG_IPS              GENMASK(3, 0)
 433 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_SET(x)\
 434         FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_IPS, x)
 435 #define ANA_AC_SG_GCL_GS_CONFIG_IPS_GET(x)\
 436         FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_IPS, x)
 437
 438 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE       BIT(4)
 439 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_SET(x)\
 440         FIELD_PREP(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x)
 441 #define ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE_GET(x)\
 442         FIELD_GET(ANA_AC_SG_GCL_GS_CONFIG_GATE_STATE, x)
 443
 444 /* ANA_AC:SG_CONFIG:SG_GCL_TI_CONFIG */
 445 #define ANA_AC_SG_GCL_TI_CONFIG(r)                                             \
 446         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
 447               16, r, 4, 4)
 448
 449 /* ANA_AC:SG_CONFIG:SG_GCL_OCT_CONFIG */
 450 #define ANA_AC_SG_GCL_OCT_CONFIG(r)                                            \
 451         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_CONFIG], 0, 1, 128,\
 452               32, r, 4, 4)
 453
 454 /* ANA_AC:SG_STATUS:SG_STATUS_REG_1 */
 455 #define ANA_AC_SG_STATUS_REG_1                                                 \
 456         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
 457               0, 0, 1, 4)
 458
 459 /* ANA_AC:SG_STATUS:SG_STATUS_REG_2 */
 460 #define ANA_AC_SG_STATUS_REG_2                                                 \
 461         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
 462               4, 0, 1, 4)
 463
 464 /* ANA_AC:SG_STATUS:SG_STATUS_REG_3 */
 465 #define ANA_AC_SG_STATUS_REG_3                                                 \
 466         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
 467               8, 0, 1, 4)
 468
 469 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB GENMASK(15, 0)
 470 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_SET(x)\
 471         FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x)
 472 #define ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB_GET(x)\
 473         FIELD_GET(ANA_AC_SG_STATUS_REG_3_CFG_CHG_TIME_SEC_MSB, x)
 474
 475 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE        BIT(16)
 476 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_SET(x)\
 477         FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x)
 478 #define ANA_AC_SG_STATUS_REG_3_GATE_STATE_GET(x)\
 479         FIELD_GET(ANA_AC_SG_STATUS_REG_3_GATE_STATE, x)
 480
 481 #define ANA_AC_SG_STATUS_REG_3_IPS               GENMASK(23, 20)
 482 #define ANA_AC_SG_STATUS_REG_3_IPS_SET(x)\
 483         FIELD_PREP(ANA_AC_SG_STATUS_REG_3_IPS, x)
 484 #define ANA_AC_SG_STATUS_REG_3_IPS_GET(x)\
 485         FIELD_GET(ANA_AC_SG_STATUS_REG_3_IPS, x)
 486
 487 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING    BIT(24)
 488 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_SET(x)\
 489         FIELD_PREP(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x)
 490 #define ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING_GET(x)\
 491         FIELD_GET(ANA_AC_SG_STATUS_REG_3_CONFIG_PENDING, x)
 492
 493 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX   GENMASK(27, 25)
 494 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_SET(x)\
 495         FIELD_PREP(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x)
 496 #define ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX_GET(x)\
 497         FIELD_GET(ANA_AC_SG_STATUS_REG_3_GCL_OCTET_INDEX, x)
 498
 499 /* ANA_AC:SG_STATUS:SG_STATUS_REG_4 */
 500 #define ANA_AC_SG_STATUS_REG_4                                                 \
 501         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_SG_STATUS], 0, 1, 16, \
 502               12, 0, 1, 4)
 503
 504 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_GLOBAL_EVENT_MASK */
 505 #define ANA_AC_PORT_SGE_CFG(r)                                                 \
 506         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\
 507               0, 1, 20, 0, r, 4, 4)
 508
 509 #define ANA_AC_PORT_SGE_CFG_MASK\
 510         GENMASK(regs->fsize[FW_ANA_AC_PORT_SGE_CFG_MASK] + 0 - 1, 0)
 511 #define ANA_AC_PORT_SGE_CFG_MASK_SET(x)\
 512         spx5_field_prep(ANA_AC_PORT_SGE_CFG_MASK, x)
 513 #define ANA_AC_PORT_SGE_CFG_MASK_GET(x)\
 514         spx5_field_get(ANA_AC_PORT_SGE_CFG_MASK, x)
 515
 516 /* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */
 517 #define ANA_AC_STAT_RESET                                                      \
 518         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_PORT],\
 519               0, 1, 20, 16, 0, 1, 4)
 520
 521 #define ANA_AC_STAT_RESET_RESET                  BIT(0)
 522 #define ANA_AC_STAT_RESET_RESET_SET(x)\
 523         FIELD_PREP(ANA_AC_STAT_RESET_RESET, x)
 524 #define ANA_AC_STAT_RESET_RESET_GET(x)\
 525         FIELD_GET(ANA_AC_STAT_RESET_RESET, x)
 526
 527 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_CFG */
 528 #define ANA_AC_PORT_STAT_CFG(g, r)                                             \
 529         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\
 530               regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 4, r, 4, 4)
 531
 532 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK       GENMASK(11, 4)
 533 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_SET(x)\
 534         FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
 535 #define ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK_GET(x)\
 536         FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_PRIO_MASK, x)
 537
 538 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE    GENMASK(3, 1)
 539 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_SET(x)\
 540         FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
 541 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE_GET(x)\
 542         FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_FRM_TYPE, x)
 543
 544 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE        BIT(0)
 545 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_SET(x)\
 546         FIELD_PREP(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
 547 #define ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE_GET(x)\
 548         FIELD_GET(ANA_AC_PORT_STAT_CFG_CFG_CNT_BYTE, x)
 549
 550 /* ANA_AC:STAT_CNT_CFG_PORT:STAT_LSB_CNT */
 551 #define ANA_AC_PORT_STAT_LSB_CNT(g, r)                                         \
 552         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_CNT_CFG_PORT], g,\
 553               regs->gcnt[GC_ANA_AC_STAT_CNT_CFG_PORT], 64, 20, r, 4, 4)
 554
 555 /* ANA_AC:STAT_GLOBAL_CFG_ACL:GLOBAL_CNT_FRM_TYPE_CFG */
 556 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG(r)                                  \
 557         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \
 558               0, 1, 24, 0, r, 2, 4)
 559
 560 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE GENMASK(2, 0)
 561 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_SET(x)\
 562         FIELD_PREP(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x)
 563 #define ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE_GET(x)\
 564         FIELD_GET(ANA_AC_ACL_GLOBAL_CNT_FRM_TYPE_CFG_GLOBAL_CFG_CNT_FRM_TYPE, x)
 565
 566 /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_CFG */
 567 #define ANA_AC_ACL_STAT_GLOBAL_CFG(r)                                          \
 568         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \
 569               0, 1, 24, 8, r, 2, 4)
 570
 571 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE BIT(0)
 572 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_SET(x)\
 573         FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x)
 574 #define ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE_GET(x)\
 575         FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_CFG_GLOBAL_CFG_CNT_BYTE, x)
 576
 577 /* ANA_AC:STAT_GLOBAL_CFG_ACL:STAT_GLOBAL_EVENT_MASK */
 578 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK(r)                                   \
 579         __REG(TARGET_ANA_AC, 0, 1, regs->gaddr[GA_ANA_AC_STAT_GLOBAL_CFG_ACL], \
 580               0, 1, 24, 16, r, 2, 4)
 581
 582 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK GENMASK(3, 0)
 583 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_SET(x)\
 584         FIELD_PREP(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x)
 585 #define ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK_GET(x)\
 586         FIELD_GET(ANA_AC_ACL_STAT_GLOBAL_EVENT_MASK_GLOBAL_EVENT_MASK, x)
 587
 588 /* ANA_ACL:COMMON:VCAP_S2_CFG */
 589 #define ANA_ACL_VCAP_S2_CFG(r)                                                 \
 590         __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
 591               0, r, regs->rcnt[RC_ANA_ACL_VCAP_S2_CFG], 4)
 592
 593 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA BIT(28)
 594 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_SET(x)\
 595         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x)
 596 #define ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA_GET(x)\
 597         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ROUTE_HANDLING_ENA, x)
 598
 599 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA     GENMASK(27, 26)
 600 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_SET(x)\
 601         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x)
 602 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA_GET(x)\
 603         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_OAM_ENA, x)
 604
 605 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA GENMASK(25, 24)
 606 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_SET(x)\
 607         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x)
 608 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA_GET(x)\
 609         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_OTHER_ENA, x)
 610
 611 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA GENMASK(23, 22)
 612 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_SET(x)\
 613         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x)
 614 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA_GET(x)\
 615         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_VID_ENA, x)
 616
 617 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA GENMASK(21, 20)
 618 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_SET(x)\
 619         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x)
 620 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA_GET(x)\
 621         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_STD_ENA, x)
 622
 623 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA GENMASK(19, 18)
 624 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_SET(x)\
 625         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x)
 626 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA_GET(x)\
 627         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP6_TCPUDP_ENA, x)
 628
 629 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA GENMASK(17, 16)
 630 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_SET(x)\
 631         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x)
 632 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA_GET(x)\
 633         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP_7TUPLE_ENA, x)
 634
 635 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA GENMASK(15, 14)
 636 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_SET(x)\
 637         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x)
 638 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA_GET(x)\
 639         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_VID_ENA, x)
 640
 641 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA GENMASK(13, 12)
 642 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_SET(x)\
 643         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x)
 644 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA_GET(x)\
 645         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_TCPUDP_ENA, x)
 646
 647 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA GENMASK(11, 10)
 648 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_SET(x)\
 649         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x)
 650 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA_GET(x)\
 651         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_IP4_OTHER_ENA, x)
 652
 653 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA     GENMASK(9, 8)
 654 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_SET(x)\
 655         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x)
 656 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA_GET(x)\
 657         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_ARP_ENA, x)
 658
 659 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA GENMASK(7, 6)
 660 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_SET(x)\
 661         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x)
 662 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA_GET(x)\
 663         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_SNAP_ENA, x)
 664
 665 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA GENMASK(5, 4)
 666 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_SET(x)\
 667         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x)
 668 #define ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA_GET(x)\
 669         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_TYPE_MAC_LLC_ENA, x)
 670
 671 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA              GENMASK(3, 0)
 672 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_SET(x)\
 673         FIELD_PREP(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x)
 674 #define ANA_ACL_VCAP_S2_CFG_SEC_ENA_GET(x)\
 675         FIELD_GET(ANA_ACL_VCAP_S2_CFG_SEC_ENA, x)
 676
 677 /* ANA_ACL:COMMON:SWAP_IP_CTRL */
 678 #define ANA_ACL_SWAP_IP_CTRL                                                   \
 679         __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
 680               412, 0, 1, 4)
 681
 682 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL GENMASK(23, 18)
 683 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_SET(x)\
 684         FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x)
 685 #define ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL_GET(x)\
 686         FIELD_GET(ANA_ACL_SWAP_IP_CTRL_DMAC_REPL_OFFSET_VAL, x)
 687
 688 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL GENMASK(17, 10)
 689 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_SET(x)\
 690         FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x)
 691 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL_GET(x)\
 692         FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_VAL, x)
 693
 694 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL GENMASK(9, 2)
 695 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_SET(x)\
 696         FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x)
 697 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL_GET(x)\
 698         FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_VAL, x)
 699
 700 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA BIT(1)
 701 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_SET(x)\
 702         FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x)
 703 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA_GET(x)\
 704         FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP6_HOPC_ENA, x)
 705
 706 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA BIT(0)
 707 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_SET(x)\
 708         FIELD_PREP(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x)
 709 #define ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA_GET(x)\
 710         FIELD_GET(ANA_ACL_SWAP_IP_CTRL_IP_SWAP_IP4_TTL_ENA, x)
 711
 712 /* ANA_ACL:COMMON:VCAP_S2_RLEG_STAT */
 713 #define ANA_ACL_VCAP_S2_RLEG_STAT(r)                                           \
 714         __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
 715               424, r, 4, 4)
 716
 717 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK GENMASK(12, 6)
 718 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_SET(x)\
 719         FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x)
 720 #define ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK_GET(x)\
 721         FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_IRLEG_STAT_MASK, x)
 722
 723 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK GENMASK(5, 0)
 724 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_SET(x)\
 725         FIELD_PREP(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x)
 726 #define ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK_GET(x)\
 727         FIELD_GET(ANA_ACL_VCAP_S2_RLEG_STAT_ERLEG_STAT_MASK, x)
 728
 729 /* ANA_ACL:COMMON:VCAP_S2_FRAGMENT_CFG */
 730 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG                                           \
 731         __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
 732               440, 0, 1, 4)
 733
 734 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN  GENMASK(9, 5)
 735 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_SET(x)\
 736         FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x)
 737 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN_GET(x)\
 738         FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_L4_MIN_LEN, x)
 739
 740 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS BIT(4)
 741 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_SET(x)\
 742         FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x)
 743 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS_GET(x)\
 744         FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_DIS, x)
 745
 746 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES GENMASK(3, 0)
 747 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_SET(x)\
 748         FIELD_PREP(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x)
 749 #define ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES_GET(x)\
 750         FIELD_GET(ANA_ACL_VCAP_S2_FRAGMENT_CFG_FRAGMENT_OFFSET_THRES, x)
 751
 752 /* ANA_ACL:COMMON:OWN_UPSID */
 753 #define ANA_ACL_OWN_UPSID(r)                                                   \
 754         __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_COMMON], 0, 1, 592, \
 755               580, r, regs->rcnt[RC_ANA_ACL_OWN_UPSID], 4)
 756
 757 #define ANA_ACL_OWN_UPSID_OWN_UPSID              GENMASK(4, 0)
 758 #define ANA_ACL_OWN_UPSID_OWN_UPSID_SET(x)\
 759         FIELD_PREP(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
 760 #define ANA_ACL_OWN_UPSID_OWN_UPSID_GET(x)\
 761         FIELD_GET(ANA_ACL_OWN_UPSID_OWN_UPSID, x)
 762
 763 /* ANA_ACL:KEY_SEL:VCAP_S2_KEY_SEL */
 764 #define ANA_ACL_VCAP_S2_KEY_SEL(g, r)                                          \
 765         __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_KEY_SEL], g,        \
 766               regs->gcnt[GC_ANA_ACL_KEY_SEL], 16, 0, r, 4, 4)
 767
 768 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA      BIT(13)
 769 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_SET(x)\
 770         FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x)
 771 #define ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA_GET(x)\
 772         FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_KEY_SEL_ENA, x)
 773
 774 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL BIT(12)
 775 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_SET(x)\
 776         FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x)
 777 #define ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL_GET(x)\
 778         FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IGR_PORT_MASK_SEL, x)
 779
 780 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL  GENMASK(11, 10)
 781 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_SET(x)\
 782         FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x)
 783 #define ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL_GET(x)\
 784         FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_NON_ETH_KEY_SEL, x)
 785
 786 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL   GENMASK(9, 8)
 787 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_SET(x)\
 788         FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x)
 789 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL_GET(x)\
 790         FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_MC_KEY_SEL, x)
 791
 792 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL   GENMASK(7, 6)
 793 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_SET(x)\
 794         FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x)
 795 #define ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL_GET(x)\
 796         FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP4_UC_KEY_SEL, x)
 797
 798 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL   GENMASK(5, 3)
 799 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_SET(x)\
 800         FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x)
 801 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL_GET(x)\
 802         FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_MC_KEY_SEL, x)
 803
 804 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL   GENMASK(2, 1)
 805 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_SET(x)\
 806         FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x)
 807 #define ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL_GET(x)\
 808         FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_IP6_UC_KEY_SEL, x)
 809
 810 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL      BIT(0)
 811 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_SET(x)\
 812         FIELD_PREP(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x)
 813 #define ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL_GET(x)\
 814         FIELD_GET(ANA_ACL_VCAP_S2_KEY_SEL_ARP_KEY_SEL, x)
 815
 816 /* ANA_ACL:CNT_A:CNT_A */
 817 #define ANA_ACL_CNT_A(g)                                                       \
 818         __REG(TARGET_ANA_ACL, 0, 1, 0, g, regs->gcnt[GC_ANA_ACL_CNT_A], 4, 0,  \
 819               0, 1, 4)
 820
 821 /* ANA_ACL:CNT_B:CNT_B */
 822 #define ANA_ACL_CNT_B(g)                                                       \
 823         __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_CNT_B], g,          \
 824               regs->gcnt[GC_ANA_ACL_CNT_B], 4, 0, 0, 1, 4)
 825
 826 /* ANA_ACL:STICKY:SEC_LOOKUP_STICKY */
 827 #define ANA_ACL_SEC_LOOKUP_STICKY(r)                                           \
 828         __REG(TARGET_ANA_ACL, 0, 1, regs->gaddr[GA_ANA_ACL_STICKY], 0, 1, 16,  \
 829               0, r, 4, 4)
 830
 831 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY BIT(17)
 832 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_SET(x)\
 833         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x)
 834 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY_GET(x)\
 835         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_CLM_STICKY, x)
 836
 837 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY BIT(16)
 838 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_SET(x)\
 839         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x)
 840 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY_GET(x)\
 841         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_IRLEG_STICKY, x)
 842
 843 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY BIT(15)
 844 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_SET(x)\
 845         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x)
 846 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY_GET(x)\
 847         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_ERLEG_STICKY, x)
 848
 849 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY BIT(14)
 850 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_SET(x)\
 851         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x)
 852 #define ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY_GET(x)\
 853         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_KEY_SEL_PORT_STICKY, x)
 854
 855 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY BIT(13)
 856 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_SET(x)\
 857         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x)
 858 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY_GET(x)\
 859         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM2_STICKY, x)
 860
 861 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY BIT(12)
 862 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_SET(x)\
 863         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x)
 864 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY_GET(x)\
 865         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_CUSTOM1_STICKY, x)
 866
 867 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY BIT(11)
 868 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_SET(x)\
 869         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x)
 870 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY_GET(x)\
 871         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_OAM_STICKY, x)
 872
 873 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(10)
 874 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\
 875         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
 876 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\
 877         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
 878
 879 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(9)
 880 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\
 881         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
 882 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\
 883         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
 884
 885 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY BIT(8)
 886 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_SET(x)\
 887         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x)
 888 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY_GET(x)\
 889         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_TCPUDP_STICKY, x)
 890
 891 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7)
 892 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\
 893         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
 894 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\
 895         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
 896
 897 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(6)
 898 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\
 899         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
 900 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\
 901         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
 902
 903 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(5)
 904 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\
 905         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
 906 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\
 907         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
 908
 909 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(4)
 910 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\
 911         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
 912 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\
 913         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
 914
 915 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(3)
 916 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\
 917         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
 918 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\
 919         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
 920
 921 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY BIT(2)
 922 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_SET(x)\
 923         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x)
 924 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY_GET(x)\
 925         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_SNAP_STICKY, x)
 926
 927 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY BIT(1)
 928 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_SET(x)\
 929         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x)
 930 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY_GET(x)\
 931         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_LLC_STICKY, x)
 932
 933 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0)
 934 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\
 935         FIELD_PREP(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
 936 #define ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\
 937         FIELD_GET(ANA_ACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
 938
 939 /* ANA_AC_POL:POL_ALL_CFG:POL_UPD_INT_CFG */
 940 #define ANA_AC_POL_POL_UPD_INT_CFG                                             \
 941         __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_POL_ALL_CFG], \
 942               0, 1, 1160, 1148, 0, 1, 4)
 943
 944 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT   GENMASK(9, 0)
 945 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_SET(x)\
 946         FIELD_PREP(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
 947 #define ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT_GET(x)\
 948         FIELD_GET(ANA_AC_POL_POL_UPD_INT_CFG_POL_UPD_INT, x)
 949
 950 /* ANA_AC_POL:COMMON_BDLB:DLB_CTRL */
 951 #define ANA_AC_POL_BDLB_DLB_CTRL                                               \
 952         __REG(TARGET_ANA_AC_POL, 0, 1, regs->gaddr[GA_ANA_AC_POL_COMMON_BDLB], \
 953               0, 1, 8, 0, 0, 1, 4)
 954
 955 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS GENMASK(26, 19)
 956 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
 957         FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
 958 #define ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
 959         FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_CLK_PERIOD_01NS, x)
 960
 961 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT   GENMASK(18, 4)
 962 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
 963         FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
 964 #define ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
 965         FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_BASE_TICK_CNT, x)
 966
 967 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA        BIT(1)
 968 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_SET(x)\
 969         FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
 970 #define ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA_GET(x)\
 971         FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_LEAK_ENA, x)
 972
 973 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA     BIT(0)
 974 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
 975         FIELD_PREP(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
 976 #define ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
 977         FIELD_GET(ANA_AC_POL_BDLB_DLB_CTRL_DLB_ADD_ENA, x)
 978
 979 /* ANA_AC_POL:COMMON_BUM_SLB:DLB_CTRL */
 980 #define ANA_AC_POL_SLB_DLB_CTRL                                                \
 981         __REG(TARGET_ANA_AC_POL, 0, 1,                                         \
 982               regs->gaddr[GA_ANA_AC_POL_COMMON_BUM_SLB], 0, 1, 20, 0, 0, 1, 4)
 983
 984 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS  GENMASK(26, 19)
 985 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_SET(x)\
 986         FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
 987 #define ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS_GET(x)\
 988         FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_CLK_PERIOD_01NS, x)
 989
 990 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT    GENMASK(18, 4)
 991 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_SET(x)\
 992         FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
 993 #define ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT_GET(x)\
 994         FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_BASE_TICK_CNT, x)
 995
 996 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA         BIT(1)
 997 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_SET(x)\
 998         FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
 999 #define ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA_GET(x)\
1000         FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_LEAK_ENA, x)
1001
1002 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA      BIT(0)
1003 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_SET(x)\
1004         FIELD_PREP(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
1005 #define ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA_GET(x)\
1006         FIELD_GET(ANA_AC_POL_SLB_DLB_CTRL_DLB_ADD_ENA, x)
1007
1008 /* ANA_AC_SDLB:LBGRP_TBL:XLB_START */
1009 #define ANA_AC_SDLB_XLB_START(g)                                               \
1010         __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1011               g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 0, 0, 1, 4)
1012
1013 #define ANA_AC_SDLB_XLB_START_LBSET_START\
1014         GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_START_LBSET_START] + 0 - 1, 0)
1015 #define ANA_AC_SDLB_XLB_START_LBSET_START_SET(x)\
1016         spx5_field_prep(ANA_AC_SDLB_XLB_START_LBSET_START, x)
1017 #define ANA_AC_SDLB_XLB_START_LBSET_START_GET(x)\
1018         spx5_field_get(ANA_AC_SDLB_XLB_START_LBSET_START, x)
1019
1020 /* ANA_AC_SDLB:LBGRP_TBL:PUP_INTERVAL */
1021 #define ANA_AC_SDLB_PUP_INTERVAL(g)                                            \
1022         __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1023               g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 4, 0, 1, 4)
1024
1025 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL    GENMASK(19, 0)
1026 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_SET(x)\
1027         FIELD_PREP(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x)
1028 #define ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL_GET(x)\
1029         FIELD_GET(ANA_AC_SDLB_PUP_INTERVAL_PUP_INTERVAL, x)
1030
1031 /* ANA_AC_SDLB:LBGRP_TBL:PUP_CTRL */
1032 #define ANA_AC_SDLB_PUP_CTRL(g)                                                \
1033         __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1034               g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 8, 0, 1, 4)
1035
1036 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT           GENMASK(18, 0)
1037 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_SET(x)\
1038         FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x)
1039 #define ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT_GET(x)\
1040         FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_LB_DT, x)
1041
1042 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA             BIT(24)
1043 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_SET(x)\
1044         FIELD_PREP(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x)
1045 #define ANA_AC_SDLB_PUP_CTRL_PUP_ENA_GET(x)\
1046         FIELD_GET(ANA_AC_SDLB_PUP_CTRL_PUP_ENA, x)
1047
1048 /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_MISC */
1049 #define ANA_AC_SDLB_LBGRP_MISC(g)                                              \
1050         __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1051               g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 12, 0, 1, 4)
1052
1053 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT\
1054         GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] + 8 - 1, 8)
1055 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_SET(x)\
1056         spx5_field_prep(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x)
1057 #define ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT_GET(x)\
1058         spx5_field_get(ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT, x)
1059
1060 /* ANA_AC_SDLB:LBGRP_TBL:FRM_RATE_TOKENS */
1061 #define ANA_AC_SDLB_FRM_RATE_TOKENS(g)                                         \
1062         __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1063               g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 16, 0, 1, 4)
1064
1065 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS GENMASK(12, 0)
1066 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_SET(x)\
1067         FIELD_PREP(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x)
1068 #define ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS_GET(x)\
1069         FIELD_GET(ANA_AC_SDLB_FRM_RATE_TOKENS_FRM_RATE_TOKENS, x)
1070
1071 /* ANA_AC_SDLB:LBGRP_TBL:LBGRP_STATE_TBL */
1072 #define ANA_AC_SDLB_LBGRP_STATE_TBL(g)                                         \
1073         __REG(TARGET_ANA_AC_SDLB, 0, 1, regs->gaddr[GA_ANA_AC_SDLB_LBGRP_TBL], \
1074               g, regs->gcnt[GC_ANA_AC_SDLB_LBGRP_TBL], 24, 20, 0, 1, 4)
1075
1076 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING  BIT(0)
1077 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_SET(x)\
1078         FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x)
1079 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING_GET(x)\
1080         FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_ONGOING, x)
1081
1082 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK BIT(1)
1083 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_SET(x)\
1084         FIELD_PREP(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x)
1085 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK_GET(x)\
1086         FIELD_GET(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_WAIT_ACK, x)
1087
1088 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT\
1089         GENMASK(regs->fsize[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] + 16 - 1, 16)
1090 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_SET(x)\
1091         spx5_field_prep(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x)
1092 #define ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT_GET(x)\
1093         spx5_field_get(ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT, x)
1094
1095 /* ANA_AC_SDLB:LBSET_TBL:PUP_TOKENS */
1096 #define ANA_AC_SDLB_PUP_TOKENS(g, r)                                           \
1097         __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
1098               regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 0, r, 2, 4)
1099
1100 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS        GENMASK(12, 0)
1101 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_SET(x)\
1102         FIELD_PREP(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x)
1103 #define ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS_GET(x)\
1104         FIELD_GET(ANA_AC_SDLB_PUP_TOKENS_PUP_TOKENS, x)
1105
1106 /* ANA_AC_SDLB:LBSET_TBL:THRES */
1107 #define ANA_AC_SDLB_THRES(g, r)                                                \
1108         __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
1109               regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 8, r, 2, 4)
1110
1111 #define ANA_AC_SDLB_THRES_THRES                  GENMASK(9, 0)
1112 #define ANA_AC_SDLB_THRES_THRES_SET(x)\
1113         FIELD_PREP(ANA_AC_SDLB_THRES_THRES, x)
1114 #define ANA_AC_SDLB_THRES_THRES_GET(x)\
1115         FIELD_GET(ANA_AC_SDLB_THRES_THRES, x)
1116
1117 #define ANA_AC_SDLB_THRES_THRES_HYS              GENMASK(25, 16)
1118 #define ANA_AC_SDLB_THRES_THRES_HYS_SET(x)\
1119         FIELD_PREP(ANA_AC_SDLB_THRES_THRES_HYS, x)
1120 #define ANA_AC_SDLB_THRES_THRES_HYS_GET(x)\
1121         FIELD_GET(ANA_AC_SDLB_THRES_THRES_HYS, x)
1122
1123 /* ANA_AC_SDLB:LBSET_TBL:XLB_NEXT */
1124 #define ANA_AC_SDLB_XLB_NEXT(g)                                                \
1125         __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
1126               regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 16, 0, 1, 4)
1127
1128 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT\
1129         GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] + 0 - 1, 0)
1130 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_SET(x)\
1131         spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x)
1132 #define ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT_GET(x)\
1133         spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT, x)
1134
1135 #define ANA_AC_SDLB_XLB_NEXT_LBGRP\
1136         GENMASK(regs->fsize[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] + 24 - 1, 24)
1137 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_SET(x)\
1138         spx5_field_prep(ANA_AC_SDLB_XLB_NEXT_LBGRP, x)
1139 #define ANA_AC_SDLB_XLB_NEXT_LBGRP_GET(x)\
1140         spx5_field_get(ANA_AC_SDLB_XLB_NEXT_LBGRP, x)
1141
1142 /* ANA_AC_SDLB:LBSET_TBL:INH_CTRL */
1143 #define ANA_AC_SDLB_INH_CTRL(g, r)                                             \
1144         __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
1145               regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 20, r, 2, 4)
1146
1147 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX      GENMASK(12, 0)
1148 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_SET(x)\
1149         FIELD_PREP(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x)
1150 #define ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX_GET(x)\
1151         FIELD_GET(ANA_AC_SDLB_INH_CTRL_PUP_TOKENS_MAX, x)
1152
1153 #define ANA_AC_SDLB_INH_CTRL_INH_MODE            GENMASK(21, 20)
1154 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_SET(x)\
1155         FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_MODE, x)
1156 #define ANA_AC_SDLB_INH_CTRL_INH_MODE_GET(x)\
1157         FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_MODE, x)
1158
1159 #define ANA_AC_SDLB_INH_CTRL_INH_LB              BIT(24)
1160 #define ANA_AC_SDLB_INH_CTRL_INH_LB_SET(x)\
1161         FIELD_PREP(ANA_AC_SDLB_INH_CTRL_INH_LB, x)
1162 #define ANA_AC_SDLB_INH_CTRL_INH_LB_GET(x)\
1163         FIELD_GET(ANA_AC_SDLB_INH_CTRL_INH_LB, x)
1164
1165 /* ANA_AC_SDLB:LBSET_TBL:INH_LBSET_ADDR */
1166 #define ANA_AC_SDLB_INH_LBSET_ADDR(g)                                          \
1167         __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
1168               regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 28, 0, 1, 4)
1169
1170 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR\
1171         GENMASK(regs->fsize[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] + 0 - 1, 0)
1172 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_SET(x)\
1173         spx5_field_prep(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x)
1174 #define ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR_GET(x)\
1175         spx5_field_get(ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR, x)
1176
1177 /* ANA_AC_SDLB:LBSET_TBL:DLB_MISC */
1178 #define ANA_AC_SDLB_DLB_MISC(g)                                                \
1179         __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
1180               regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 32, 0, 1, 4)
1181
1182 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA    BIT(0)
1183 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_SET(x)\
1184         FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x)
1185 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA_GET(x)\
1186         FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_RATE_ENA, x)
1187
1188 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA BIT(6)
1189 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_SET(x)\
1190         FIELD_PREP(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x)
1191 #define ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA_GET(x)\
1192         FIELD_GET(ANA_AC_SDLB_DLB_MISC_MARK_ALL_FRMS_RED_ENA, x)
1193
1194 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ         GENMASK(14, 8)
1195 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_SET(x)\
1196         FIELD_PREP(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x)
1197 #define ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ_GET(x)\
1198         FIELD_GET(ANA_AC_SDLB_DLB_MISC_DLB_FRM_ADJ, x)
1199
1200 /* ANA_AC_SDLB:LBSET_TBL:DLB_CFG */
1201 #define ANA_AC_SDLB_DLB_CFG(g)                                                 \
1202         __REG(TARGET_ANA_AC_SDLB, 0, 1, 0, g,                                  \
1203               regs->gcnt[GC_ANA_AC_SDLB_LBSET_TBL], 64, 36, 0, 1, 4)
1204
1205 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA   BIT(11)
1206 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_SET(x)\
1207         FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x)
1208 #define ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA_GET(x)\
1209         FIELD_GET(ANA_AC_SDLB_DLB_CFG_DROP_ON_YELLOW_ENA, x)
1210
1211 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL        GENMASK(10, 9)
1212 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_SET(x)\
1213         FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x)
1214 #define ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL_GET(x)\
1215         FIELD_GET(ANA_AC_SDLB_DLB_CFG_DP_BYPASS_LVL, x)
1216
1217 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS         BIT(8)
1218 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_SET(x)\
1219         FIELD_PREP(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x)
1220 #define ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS_GET(x)\
1221         FIELD_GET(ANA_AC_SDLB_DLB_CFG_HIER_DLB_DIS, x)
1222
1223 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS       BIT(7)
1224 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_SET(x)\
1225         FIELD_PREP(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x)
1226 #define ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS_GET(x)\
1227         FIELD_GET(ANA_AC_SDLB_DLB_CFG_ENCAP_DATA_DIS, x)
1228
1229 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL      GENMASK(6, 5)
1230 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_SET(x)\
1231         FIELD_PREP(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x)
1232 #define ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL_GET(x)\
1233         FIELD_GET(ANA_AC_SDLB_DLB_CFG_COLOR_AWARE_LVL, x)
1234
1235 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL       GENMASK(4, 3)
1236 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_SET(x)\
1237         FIELD_PREP(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x)
1238 #define ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL_GET(x)\
1239         FIELD_GET(ANA_AC_SDLB_DLB_CFG_CIR_INC_DP_VAL, x)
1240
1241 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE             BIT(2)
1242 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_SET(x)\
1243         FIELD_PREP(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x)
1244 #define ANA_AC_SDLB_DLB_CFG_DLB_MODE_GET(x)\
1245         FIELD_GET(ANA_AC_SDLB_DLB_CFG_DLB_MODE, x)
1246
1247 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK    GENMASK(1, 0)
1248 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_SET(x)\
1249         FIELD_PREP(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x)
1250 #define ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK_GET(x)\
1251         FIELD_GET(ANA_AC_SDLB_DLB_CFG_TRAFFIC_TYPE_MASK, x)
1252
1253 /* ANA_CL:PORT:FILTER_CTRL */
1254 #define ANA_CL_FILTER_CTRL(g)                                                  \
1255         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
1256               regs->gcnt[GC_ANA_CL_PORT], 512, 4, 0, 1, 4)
1257
1258 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS    BIT(2)
1259 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_SET(x)\
1260         FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
1261 #define ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS_GET(x)\
1262         FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_SMAC_MC_DIS, x)
1263
1264 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS   BIT(1)
1265 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_SET(x)\
1266         FIELD_PREP(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
1267 #define ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS_GET(x)\
1268         FIELD_GET(ANA_CL_FILTER_CTRL_FILTER_NULL_MAC_DIS, x)
1269
1270 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA  BIT(0)
1271 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x)\
1272         FIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
1273 #define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x)\
1274         FIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)
1275
1276 /* ANA_CL:PORT:VLAN_FILTER_CTRL */
1277 #define ANA_CL_VLAN_FILTER_CTRL(g, r)                                          \
1278         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
1279               regs->gcnt[GC_ANA_CL_PORT], 512, 8, r, 3, 4)
1280
1281 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA BIT(10)
1282 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_SET(x)\
1283         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
1284 #define ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA_GET(x)\
1285         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_TAG_REQUIRED_ENA, x)
1286
1287 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS    BIT(9)
1288 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_SET(x)\
1289         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
1290 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS_GET(x)\
1291         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CTAG_DIS, x)
1292
1293 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS         BIT(8)
1294 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_SET(x)\
1295         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
1296 #define ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS_GET(x)\
1297         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CTAG_DIS, x)
1298
1299 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS    BIT(7)
1300 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_SET(x)\
1301         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
1302 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS_GET(x)\
1303         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_STAG_DIS, x)
1304
1305 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS BIT(6)
1306 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_SET(x)\
1307         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
1308 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS_GET(x)\
1309         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST1_STAG_DIS, x)
1310
1311 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS BIT(5)
1312 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_SET(x)\
1313         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
1314 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS_GET(x)\
1315         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST2_STAG_DIS, x)
1316
1317 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS BIT(4)
1318 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_SET(x)\
1319         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
1320 #define ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS_GET(x)\
1321         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_PRIO_CUST3_STAG_DIS, x)
1322
1323 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS         BIT(3)
1324 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_SET(x)\
1325         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
1326 #define ANA_CL_VLAN_FILTER_CTRL_STAG_DIS_GET(x)\
1327         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_STAG_DIS, x)
1328
1329 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS   BIT(2)
1330 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_SET(x)\
1331         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
1332 #define ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS_GET(x)\
1333         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST1_STAG_DIS, x)
1334
1335 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS   BIT(1)
1336 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_SET(x)\
1337         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
1338 #define ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS_GET(x)\
1339         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST2_STAG_DIS, x)
1340
1341 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS   BIT(0)
1342 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_SET(x)\
1343         FIELD_PREP(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
1344 #define ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS_GET(x)\
1345         FIELD_GET(ANA_CL_VLAN_FILTER_CTRL_CUST3_STAG_DIS, x)
1346
1347 /* ANA_CL:PORT:ETAG_FILTER_CTRL */
1348 #define ANA_CL_ETAG_FILTER_CTRL(g)                                             \
1349         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
1350               regs->gcnt[GC_ANA_CL_PORT], 512, 20, 0, 1, 4)
1351
1352 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA BIT(1)
1353 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_SET(x)\
1354         FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
1355 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA_GET(x)\
1356         FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_REQUIRED_ENA, x)
1357
1358 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS         BIT(0)
1359 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_SET(x)\
1360         FIELD_PREP(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
1361 #define ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS_GET(x)\
1362         FIELD_GET(ANA_CL_ETAG_FILTER_CTRL_ETAG_DIS, x)
1363
1364 /* ANA_CL:PORT:VLAN_CTRL */
1365 #define ANA_CL_VLAN_CTRL(g)                                                    \
1366         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
1367               regs->gcnt[GC_ANA_CL_PORT], 512, 32, 0, 1, 4)
1368
1369 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS GENMASK(30, 26)
1370 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_SET(x)\
1371         FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
1372 #define ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS_GET(x)\
1373         FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_TPID_AWARE_DIS, x)
1374
1375 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP    GENMASK(25, 23)
1376 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_SET(x)\
1377         FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
1378 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP_GET(x)\
1379         FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_PCP, x)
1380
1381 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI    BIT(22)
1382 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_SET(x)\
1383         FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
1384 #define ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI_GET(x)\
1385         FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VOE_DEFAULT_DEI, x)
1386
1387 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA  BIT(21)
1388 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_SET(x)\
1389         FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
1390 #define ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA_GET(x)\
1391         FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_PCP_DEI_TRANS_ENA, x)
1392
1393 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL            BIT(20)
1394 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_SET(x)\
1395         FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
1396 #define ANA_CL_VLAN_CTRL_VLAN_TAG_SEL_GET(x)\
1397         FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_TAG_SEL, x)
1398
1399 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA          BIT(19)
1400 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x)\
1401         FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
1402 #define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x)\
1403         FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)
1404
1405 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT            GENMASK(18, 17)
1406 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x)\
1407         FIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
1408 #define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x)\
1409         FIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)
1410
1411 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE           BIT(16)
1412 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_SET(x)\
1413         FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
1414 #define ANA_CL_VLAN_CTRL_PORT_TAG_TYPE_GET(x)\
1415         FIELD_GET(ANA_CL_VLAN_CTRL_PORT_TAG_TYPE, x)
1416
1417 #define ANA_CL_VLAN_CTRL_PORT_PCP                GENMASK(15, 13)
1418 #define ANA_CL_VLAN_CTRL_PORT_PCP_SET(x)\
1419         FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_PCP, x)
1420 #define ANA_CL_VLAN_CTRL_PORT_PCP_GET(x)\
1421         FIELD_GET(ANA_CL_VLAN_CTRL_PORT_PCP, x)
1422
1423 #define ANA_CL_VLAN_CTRL_PORT_DEI                BIT(12)
1424 #define ANA_CL_VLAN_CTRL_PORT_DEI_SET(x)\
1425         FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_DEI, x)
1426 #define ANA_CL_VLAN_CTRL_PORT_DEI_GET(x)\
1427         FIELD_GET(ANA_CL_VLAN_CTRL_PORT_DEI, x)
1428
1429 #define ANA_CL_VLAN_CTRL_PORT_VID                GENMASK(11, 0)
1430 #define ANA_CL_VLAN_CTRL_PORT_VID_SET(x)\
1431         FIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)
1432 #define ANA_CL_VLAN_CTRL_PORT_VID_GET(x)\
1433         FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)
1434
1435 /* ANA_CL:PORT:VLAN_CTRL_2 */
1436 #define ANA_CL_VLAN_CTRL_2(g)                                                  \
1437         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
1438               regs->gcnt[GC_ANA_CL_PORT], 512, 36, 0, 1, 4)
1439
1440 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT         GENMASK(1, 0)
1441 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_SET(x)\
1442         FIELD_PREP(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
1443 #define ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT_GET(x)\
1444         FIELD_GET(ANA_CL_VLAN_CTRL_2_VLAN_PUSH_CNT, x)
1445
1446 /* ANA_CL:PORT:PCP_DEI_MAP_CFG */
1447 #define ANA_CL_PCP_DEI_MAP_CFG(g, r)                                           \
1448         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
1449               regs->gcnt[GC_ANA_CL_PORT], 512, 108, r, 16, 4)
1450
1451 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL    GENMASK(4, 3)
1452 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_SET(x)\
1453         FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x)
1454 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL_GET(x)\
1455         FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_DP_VAL, x)
1456
1457 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL   GENMASK(2, 0)
1458 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_SET(x)\
1459         FIELD_PREP(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x)
1460 #define ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL_GET(x)\
1461         FIELD_GET(ANA_CL_PCP_DEI_MAP_CFG_PCP_DEI_QOS_VAL, x)
1462
1463 /* ANA_CL:PORT:QOS_CFG */
1464 #define ANA_CL_QOS_CFG(g)                                                      \
1465         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
1466               regs->gcnt[GC_ANA_CL_PORT], 512, 172, 0, 1, 4)
1467
1468 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA         BIT(17)
1469 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_SET(x)\
1470         FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x)
1471 #define ANA_CL_QOS_CFG_DEFAULT_COSID_ENA_GET(x)\
1472         FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_ENA, x)
1473
1474 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL         GENMASK(16, 14)
1475 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_SET(x)\
1476         FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x)
1477 #define ANA_CL_QOS_CFG_DEFAULT_COSID_VAL_GET(x)\
1478         FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_COSID_VAL, x)
1479
1480 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL        GENMASK(13, 12)
1481 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_SET(x)\
1482         FIELD_PREP(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x)
1483 #define ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL_GET(x)\
1484         FIELD_GET(ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, x)
1485
1486 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA        BIT(11)
1487 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_SET(x)\
1488         FIELD_PREP(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x)
1489 #define ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA_GET(x)\
1490         FIELD_GET(ANA_CL_QOS_CFG_DSCP_TRANSLATE_ENA, x)
1491
1492 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA             BIT(10)
1493 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_SET(x)\
1494         FIELD_PREP(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x)
1495 #define ANA_CL_QOS_CFG_DSCP_KEEP_ENA_GET(x)\
1496         FIELD_GET(ANA_CL_QOS_CFG_DSCP_KEEP_ENA, x)
1497
1498 #define ANA_CL_QOS_CFG_KEEP_ENA                  BIT(9)
1499 #define ANA_CL_QOS_CFG_KEEP_ENA_SET(x)\
1500         FIELD_PREP(ANA_CL_QOS_CFG_KEEP_ENA, x)
1501 #define ANA_CL_QOS_CFG_KEEP_ENA_GET(x)\
1502         FIELD_GET(ANA_CL_QOS_CFG_KEEP_ENA, x)
1503
1504 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA            BIT(8)
1505 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(x)\
1506         FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x)
1507 #define ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_GET(x)\
1508         FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_DP_ENA, x)
1509
1510 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA           BIT(7)
1511 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(x)\
1512         FIELD_PREP(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x)
1513 #define ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_GET(x)\
1514         FIELD_GET(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA, x)
1515
1516 #define ANA_CL_QOS_CFG_DSCP_DP_ENA               BIT(6)
1517 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(x)\
1518         FIELD_PREP(ANA_CL_QOS_CFG_DSCP_DP_ENA, x)
1519 #define ANA_CL_QOS_CFG_DSCP_DP_ENA_GET(x)\
1520         FIELD_GET(ANA_CL_QOS_CFG_DSCP_DP_ENA, x)
1521
1522 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA              BIT(5)
1523 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(x)\
1524         FIELD_PREP(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x)
1525 #define ANA_CL_QOS_CFG_DSCP_QOS_ENA_GET(x)\
1526         FIELD_GET(ANA_CL_QOS_CFG_DSCP_QOS_ENA, x)
1527
1528 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL            GENMASK(4, 3)
1529 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_SET(x)\
1530         FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x)
1531 #define ANA_CL_QOS_CFG_DEFAULT_DP_VAL_GET(x)\
1532         FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_DP_VAL, x)
1533
1534 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL           GENMASK(2, 0)
1535 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(x)\
1536         FIELD_PREP(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x)
1537 #define ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_GET(x)\
1538         FIELD_GET(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL, x)
1539
1540 /* ANA_CL:PORT:CAPTURE_BPDU_CFG */
1541 #define ANA_CL_CAPTURE_BPDU_CFG(g)                                             \
1542         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
1543               regs->gcnt[GC_ANA_CL_PORT], 512, 196, 0, 1, 4)
1544
1545 /* ANA_CL:PORT:ADV_CL_CFG_2 */
1546 #define ANA_CL_ADV_CL_CFG_2(g, r)                                              \
1547         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
1548               regs->gcnt[GC_ANA_CL_PORT], 512, 200, r, 6, 4)
1549
1550 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA      BIT(1)
1551 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_SET(x)\
1552         FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x)
1553 #define ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA_GET(x)\
1554         FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_TCI0_ENA, x)
1555
1556 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA      BIT(0)
1557 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_SET(x)\
1558         FIELD_PREP(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x)
1559 #define ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA_GET(x)\
1560         FIELD_GET(ANA_CL_ADV_CL_CFG_2_USE_CL_DSCP_ENA, x)
1561
1562 /* ANA_CL:PORT:ADV_CL_CFG */
1563 #define ANA_CL_ADV_CL_CFG(g, r)                                                \
1564         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_PORT], g,             \
1565               regs->gcnt[GC_ANA_CL_PORT], 512, 224, r, 6, 4)
1566
1567 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL        GENMASK(30, 26)
1568 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_SET(x)\
1569         FIELD_PREP(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x)
1570 #define ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL_GET(x)\
1571         FIELD_GET(ANA_CL_ADV_CL_CFG_IP4_CLM_KEY_SEL, x)
1572
1573 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL        GENMASK(25, 21)
1574 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_SET(x)\
1575         FIELD_PREP(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x)
1576 #define ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL_GET(x)\
1577         FIELD_GET(ANA_CL_ADV_CL_CFG_IP6_CLM_KEY_SEL, x)
1578
1579 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL    GENMASK(20, 16)
1580 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_SET(x)\
1581         FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x)
1582 #define ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL_GET(x)\
1583         FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_UC_CLM_KEY_SEL, x)
1584
1585 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL    GENMASK(15, 11)
1586 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_SET(x)\
1587         FIELD_PREP(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x)
1588 #define ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL_GET(x)\
1589         FIELD_GET(ANA_CL_ADV_CL_CFG_MPLS_MC_CLM_KEY_SEL, x)
1590
1591 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL       GENMASK(10, 6)
1592 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_SET(x)\
1593         FIELD_PREP(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x)
1594 #define ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL_GET(x)\
1595         FIELD_GET(ANA_CL_ADV_CL_CFG_MLBS_CLM_KEY_SEL, x)
1596
1597 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL      GENMASK(5, 1)
1598 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_SET(x)\
1599         FIELD_PREP(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x)
1600 #define ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL_GET(x)\
1601         FIELD_GET(ANA_CL_ADV_CL_CFG_ETYPE_CLM_KEY_SEL, x)
1602
1603 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA             BIT(0)
1604 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_SET(x)\
1605         FIELD_PREP(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x)
1606 #define ANA_CL_ADV_CL_CFG_LOOKUP_ENA_GET(x)\
1607         FIELD_GET(ANA_CL_ADV_CL_CFG_LOOKUP_ENA, x)
1608
1609 /* ANA_CL:COMMON:OWN_UPSID */
1610 #define ANA_CL_OWN_UPSID(r)                                                    \
1611         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756, 0,\
1612               r, regs->rcnt[RC_ANA_CL_OWN_UPSID], 4)
1613
1614 #define ANA_CL_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
1615 #define ANA_CL_OWN_UPSID_OWN_UPSID_SET(x)\
1616         FIELD_PREP(ANA_CL_OWN_UPSID_OWN_UPSID, x)
1617 #define ANA_CL_OWN_UPSID_OWN_UPSID_GET(x)\
1618         FIELD_GET(ANA_CL_OWN_UPSID_OWN_UPSID, x)
1619
1620 /* ANA_CL:COMMON:DSCP_CFG */
1621 #define ANA_CL_DSCP_CFG(r)                                                     \
1622         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756,   \
1623               256, r, 64, 4)
1624
1625 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL       GENMASK(12, 7)
1626 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_SET(x)\
1627         FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x)
1628 #define ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL_GET(x)\
1629         FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRANSLATE_VAL, x)
1630
1631 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL             GENMASK(6, 4)
1632 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_SET(x)\
1633         FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x)
1634 #define ANA_CL_DSCP_CFG_DSCP_QOS_VAL_GET(x)\
1635         FIELD_GET(ANA_CL_DSCP_CFG_DSCP_QOS_VAL, x)
1636
1637 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL              GENMASK(3, 2)
1638 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_SET(x)\
1639         FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x)
1640 #define ANA_CL_DSCP_CFG_DSCP_DP_VAL_GET(x)\
1641         FIELD_GET(ANA_CL_DSCP_CFG_DSCP_DP_VAL, x)
1642
1643 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA            BIT(1)
1644 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_SET(x)\
1645         FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x)
1646 #define ANA_CL_DSCP_CFG_DSCP_REWR_ENA_GET(x)\
1647         FIELD_GET(ANA_CL_DSCP_CFG_DSCP_REWR_ENA, x)
1648
1649 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA           BIT(0)
1650 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_SET(x)\
1651         FIELD_PREP(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x)
1652 #define ANA_CL_DSCP_CFG_DSCP_TRUST_ENA_GET(x)\
1653         FIELD_GET(ANA_CL_DSCP_CFG_DSCP_TRUST_ENA, x)
1654
1655 /* ANA_CL:COMMON:QOS_MAP_CFG */
1656 #define ANA_CL_QOS_MAP_CFG(r)                                                  \
1657         __REG(TARGET_ANA_CL, 0, 1, regs->gaddr[GA_ANA_CL_COMMON], 0, 1, 756,   \
1658               512, r, 32, 4)
1659
1660 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL         GENMASK(9, 4)
1661 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_SET(x)\
1662         FIELD_PREP(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x)
1663 #define ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL_GET(x)\
1664         FIELD_GET(ANA_CL_QOS_MAP_CFG_DSCP_REWR_VAL, x)
1665
1666 /* ANA_L2:COMMON:FWD_CFG */
1667 #define ANA_L2_FWD_CFG                                                         \
1668         __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1,        \
1669               regs->gsize[GW_ANA_L2_COMMON], 0, 0, 1, 4)
1670
1671 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL         GENMASK(21, 20)
1672 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_SET(x)\
1673         FIELD_PREP(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x)
1674 #define ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL_GET(x)\
1675         FIELD_GET(ANA_L2_FWD_CFG_MAC_TBL_SPLIT_SEL, x)
1676
1677 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA     BIT(18)
1678 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_SET(x)\
1679         FIELD_PREP(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x)
1680 #define ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA_GET(x)\
1681         FIELD_GET(ANA_L2_FWD_CFG_PORT_DEFAULT_BDLB_ENA, x)
1682
1683 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA    BIT(17)
1684 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_SET(x)\
1685         FIELD_PREP(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x)
1686 #define ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA_GET(x)\
1687         FIELD_GET(ANA_L2_FWD_CFG_QUEUE_DEFAULT_SDLB_ENA, x)
1688
1689 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA           BIT(16)
1690 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_SET(x)\
1691         FIELD_PREP(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x)
1692 #define ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA_GET(x)\
1693         FIELD_GET(ANA_L2_FWD_CFG_ISDX_LOOKUP_ENA, x)
1694
1695 #define ANA_L2_FWD_CFG_CPU_DMAC_QU               GENMASK(10, 8)
1696 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_SET(x)\
1697         FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_QU, x)
1698 #define ANA_L2_FWD_CFG_CPU_DMAC_QU_GET(x)\
1699         FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_QU, x)
1700
1701 #define ANA_L2_FWD_CFG_LOOPBACK_ENA              BIT(7)
1702 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_SET(x)\
1703         FIELD_PREP(ANA_L2_FWD_CFG_LOOPBACK_ENA, x)
1704 #define ANA_L2_FWD_CFG_LOOPBACK_ENA_GET(x)\
1705         FIELD_GET(ANA_L2_FWD_CFG_LOOPBACK_ENA, x)
1706
1707 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA         BIT(6)
1708 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x)\
1709         FIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)
1710 #define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x)\
1711         FIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)
1712
1713 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL           BIT(4)
1714 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_SET(x)\
1715         FIELD_PREP(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x)
1716 #define ANA_L2_FWD_CFG_FILTER_MODE_SEL_GET(x)\
1717         FIELD_GET(ANA_L2_FWD_CFG_FILTER_MODE_SEL, x)
1718
1719 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA          BIT(3)
1720 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_SET(x)\
1721         FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x)
1722 #define ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA_GET(x)\
1723         FIELD_GET(ANA_L2_FWD_CFG_FLOOD_MIRROR_ENA, x)
1724
1725 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA     BIT(2)
1726 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_SET(x)\
1727         FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x)
1728 #define ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA_GET(x)\
1729         FIELD_GET(ANA_L2_FWD_CFG_FLOOD_IGNORE_VLAN_ENA, x)
1730
1731 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA        BIT(1)
1732 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_SET(x)\
1733         FIELD_PREP(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x)
1734 #define ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA_GET(x)\
1735         FIELD_GET(ANA_L2_FWD_CFG_FLOOD_CPU_COPY_ENA, x)
1736
1737 #define ANA_L2_FWD_CFG_FWD_ENA                   BIT(0)
1738 #define ANA_L2_FWD_CFG_FWD_ENA_SET(x)\
1739         FIELD_PREP(ANA_L2_FWD_CFG_FWD_ENA, x)
1740 #define ANA_L2_FWD_CFG_FWD_ENA_GET(x)\
1741         FIELD_GET(ANA_L2_FWD_CFG_FWD_ENA, x)
1742
1743 /* ANA_L2:COMMON:AUTO_LRN_CFG */
1744 #define ANA_L2_AUTO_LRN_CFG                                                    \
1745         __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1,        \
1746               regs->gsize[GW_ANA_L2_COMMON], 24, 0, 1, 4)
1747
1748 /* SPARX5 ONLY */
1749 /* ANA_L2:COMMON:AUTO_LRN_CFG1 */
1750 #define ANA_L2_AUTO_LRN_CFG1                                                   \
1751         __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1,        \
1752               regs->gsize[GW_ANA_L2_COMMON], 28, 0, 1, 4)
1753
1754 /* SPARX5 ONLY */
1755 /* ANA_L2:COMMON:AUTO_LRN_CFG2 */
1756 #define ANA_L2_AUTO_LRN_CFG2                                                   \
1757         __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1,        \
1758               regs->gsize[GW_ANA_L2_COMMON], 32, 0, 1, 4)
1759
1760 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2       BIT(0)
1761 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_SET(x)\
1762         FIELD_PREP(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
1763 #define ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2_GET(x)\
1764         FIELD_GET(ANA_L2_AUTO_LRN_CFG2_AUTO_LRN_ENA2, x)
1765
1766 /* ANA_L2:COMMON:OWN_UPSID */
1767 #define ANA_L2_OWN_UPSID(r)                                                    \
1768         __REG(TARGET_ANA_L2, 0, 1, regs->gaddr[GA_ANA_L2_COMMON], 0, 1,        \
1769               regs->gsize[GW_ANA_L2_COMMON], 672, r,                           \
1770               regs->rcnt[RC_ANA_L2_OWN_UPSID], 4)
1771
1772 #define ANA_L2_OWN_UPSID_OWN_UPSID               GENMASK(4, 0)
1773 #define ANA_L2_OWN_UPSID_OWN_UPSID_SET(x)\
1774         FIELD_PREP(ANA_L2_OWN_UPSID_OWN_UPSID, x)
1775 #define ANA_L2_OWN_UPSID_OWN_UPSID_GET(x)\
1776         FIELD_GET(ANA_L2_OWN_UPSID_OWN_UPSID, x)
1777
1778 /* ANA_L2:ISDX:DLB_CFG */
1779 #define ANA_L2_DLB_CFG(g)                                                      \
1780         __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 56,  \
1781               0, 1, 4)
1782
1783 #define ANA_L2_DLB_CFG_DLB_IDX\
1784         GENMASK(regs->fsize[FW_ANA_L2_DLB_CFG_DLB_IDX] + 0 - 1, 0)
1785 #define ANA_L2_DLB_CFG_DLB_IDX_SET(x)\
1786         spx5_field_prep(ANA_L2_DLB_CFG_DLB_IDX, x)
1787 #define ANA_L2_DLB_CFG_DLB_IDX_GET(x)\
1788         spx5_field_get(ANA_L2_DLB_CFG_DLB_IDX, x)
1789
1790 /* ANA_L2:ISDX:TSN_CFG */
1791 #define ANA_L2_TSN_CFG(g)                                                      \
1792         __REG(TARGET_ANA_L2, 0, 1, 0, g, regs->gcnt[GC_ANA_L2_ISDX], 128, 100, \
1793               0, 1, 4)
1794
1795 #define ANA_L2_TSN_CFG_TSN_SFID\
1796         GENMASK(regs->fsize[FW_ANA_L2_TSN_CFG_TSN_SFID] + 0 - 1, 0)
1797 #define ANA_L2_TSN_CFG_TSN_SFID_SET(x)\
1798         spx5_field_prep(ANA_L2_TSN_CFG_TSN_SFID, x)
1799 #define ANA_L2_TSN_CFG_TSN_SFID_GET(x)\
1800         spx5_field_get(ANA_L2_TSN_CFG_TSN_SFID, x)
1801
1802 /* ANA_L3:COMMON:VLAN_CTRL */
1803 #define ANA_L3_VLAN_CTRL                                                       \
1804         __REG(TARGET_ANA_L3, 0, 1, regs->gaddr[GA_ANA_L3_COMMON], 0, 1, 184, 4,\
1805               0, 1, 4)
1806
1807 #define ANA_L3_VLAN_CTRL_VLAN_ENA                BIT(0)
1808 #define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x)\
1809         FIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
1810 #define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x)\
1811         FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x)
1812
1813 /* ANA_L3:VLAN:VLAN_CFG */
1814 #define ANA_L3_VLAN_CFG(g)                                                     \
1815         __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 8, 0, \
1816               1, 4)
1817
1818 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR            GENMASK(30, 24)
1819 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_SET(x)\
1820         FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
1821 #define ANA_L3_VLAN_CFG_VLAN_MSTP_PTR_GET(x)\
1822         FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MSTP_PTR, x)
1823
1824 #define ANA_L3_VLAN_CFG_VLAN_FID                 GENMASK(20, 8)
1825 #define ANA_L3_VLAN_CFG_VLAN_FID_SET(x)\
1826         FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x)
1827 #define ANA_L3_VLAN_CFG_VLAN_FID_GET(x)\
1828         FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x)
1829
1830 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA      BIT(6)
1831 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_SET(x)\
1832         FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
1833 #define ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA_GET(x)\
1834         FIELD_GET(ANA_L3_VLAN_CFG_VLAN_IGR_FILTER_ENA, x)
1835
1836 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA         BIT(5)
1837 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_SET(x)\
1838         FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
1839 #define ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA_GET(x)\
1840         FIELD_GET(ANA_L3_VLAN_CFG_VLAN_SEC_FWD_ENA, x)
1841
1842 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS           BIT(4)
1843 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_SET(x)\
1844         FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
1845 #define ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS_GET(x)\
1846         FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FLOOD_DIS, x)
1847
1848 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS             BIT(3)
1849 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x)\
1850         FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
1851 #define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x)\
1852         FIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)
1853
1854 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA            BIT(2)
1855 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_SET(x)\
1856         FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
1857 #define ANA_L3_VLAN_CFG_VLAN_RLEG_ENA_GET(x)\
1858         FIELD_GET(ANA_L3_VLAN_CFG_VLAN_RLEG_ENA, x)
1859
1860 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA         BIT(1)
1861 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_SET(x)\
1862         FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
1863 #define ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA_GET(x)\
1864         FIELD_GET(ANA_L3_VLAN_CFG_VLAN_PRIVATE_ENA, x)
1865
1866 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA          BIT(0)
1867 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_SET(x)\
1868         FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
1869 #define ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA_GET(x)\
1870         FIELD_GET(ANA_L3_VLAN_CFG_VLAN_MIRROR_ENA, x)
1871
1872 /* ANA_L3:VLAN:VLAN_MASK_CFG */
1873 #define ANA_L3_VLAN_MASK_CFG(g)                                                \
1874         __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 16, 0,\
1875               1, 4)
1876
1877 /* SPARX5 ONLY */
1878 /* ANA_L3:VLAN:VLAN_MASK_CFG1 */
1879 #define ANA_L3_VLAN_MASK_CFG1(g)                                               \
1880         __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 20, 0,\
1881               1, 4)
1882
1883 /* SPARX5 ONLY */
1884 /* ANA_L3:VLAN:VLAN_MASK_CFG2 */
1885 #define ANA_L3_VLAN_MASK_CFG2(g)                                               \
1886         __REG(TARGET_ANA_L3, 0, 1, 0, g, regs->gcnt[GC_ANA_L3_VLAN], 64, 24, 0,\
1887               1, 4)
1888
1889 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2    BIT(0)
1890 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_SET(x)\
1891         FIELD_PREP(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
1892 #define ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2_GET(x)\
1893         FIELD_GET(ANA_L3_VLAN_MASK_CFG2_VLAN_PORT_MASK2, x)
1894
1895 /* ASM:DEV_STATISTICS:RX_IN_BYTES_CNT */
1896 #define ASM_RX_IN_BYTES_CNT(g)                                                 \
1897         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1898               0, 0, 1, 4)
1899
1900 /* ASM:DEV_STATISTICS:RX_SYMBOL_ERR_CNT */
1901 #define ASM_RX_SYMBOL_ERR_CNT(g)                                               \
1902         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1903               4, 0, 1, 4)
1904
1905 /* ASM:DEV_STATISTICS:RX_PAUSE_CNT */
1906 #define ASM_RX_PAUSE_CNT(g)                                                    \
1907         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1908               8, 0, 1, 4)
1909
1910 /* ASM:DEV_STATISTICS:RX_UNSUP_OPCODE_CNT */
1911 #define ASM_RX_UNSUP_OPCODE_CNT(g)                                             \
1912         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1913               12, 0, 1, 4)
1914
1915 /* ASM:DEV_STATISTICS:RX_OK_BYTES_CNT */
1916 #define ASM_RX_OK_BYTES_CNT(g)                                                 \
1917         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1918               16, 0, 1, 4)
1919
1920 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_CNT */
1921 #define ASM_RX_BAD_BYTES_CNT(g)                                                \
1922         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1923               20, 0, 1, 4)
1924
1925 /* ASM:DEV_STATISTICS:RX_UC_CNT */
1926 #define ASM_RX_UC_CNT(g)                                                       \
1927         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1928               24, 0, 1, 4)
1929
1930 /* ASM:DEV_STATISTICS:RX_MC_CNT */
1931 #define ASM_RX_MC_CNT(g)                                                       \
1932         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1933               28, 0, 1, 4)
1934
1935 /* ASM:DEV_STATISTICS:RX_BC_CNT */
1936 #define ASM_RX_BC_CNT(g)                                                       \
1937         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1938               32, 0, 1, 4)
1939
1940 /* ASM:DEV_STATISTICS:RX_CRC_ERR_CNT */
1941 #define ASM_RX_CRC_ERR_CNT(g)                                                  \
1942         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1943               36, 0, 1, 4)
1944
1945 /* ASM:DEV_STATISTICS:RX_UNDERSIZE_CNT */
1946 #define ASM_RX_UNDERSIZE_CNT(g)                                                \
1947         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1948               40, 0, 1, 4)
1949
1950 /* ASM:DEV_STATISTICS:RX_FRAGMENTS_CNT */
1951 #define ASM_RX_FRAGMENTS_CNT(g)                                                \
1952         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1953               44, 0, 1, 4)
1954
1955 /* ASM:DEV_STATISTICS:RX_IN_RANGE_LEN_ERR_CNT */
1956 #define ASM_RX_IN_RANGE_LEN_ERR_CNT(g)                                         \
1957         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1958               48, 0, 1, 4)
1959
1960 /* ASM:DEV_STATISTICS:RX_OUT_OF_RANGE_LEN_ERR_CNT */
1961 #define ASM_RX_OUT_OF_RANGE_LEN_ERR_CNT(g)                                     \
1962         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1963               52, 0, 1, 4)
1964
1965 /* ASM:DEV_STATISTICS:RX_OVERSIZE_CNT */
1966 #define ASM_RX_OVERSIZE_CNT(g)                                                 \
1967         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1968               56, 0, 1, 4)
1969
1970 /* ASM:DEV_STATISTICS:RX_JABBERS_CNT */
1971 #define ASM_RX_JABBERS_CNT(g)                                                  \
1972         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1973               60, 0, 1, 4)
1974
1975 /* ASM:DEV_STATISTICS:RX_SIZE64_CNT */
1976 #define ASM_RX_SIZE64_CNT(g)                                                   \
1977         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1978               64, 0, 1, 4)
1979
1980 /* ASM:DEV_STATISTICS:RX_SIZE65TO127_CNT */
1981 #define ASM_RX_SIZE65TO127_CNT(g)                                              \
1982         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1983               68, 0, 1, 4)
1984
1985 /* ASM:DEV_STATISTICS:RX_SIZE128TO255_CNT */
1986 #define ASM_RX_SIZE128TO255_CNT(g)                                             \
1987         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1988               72, 0, 1, 4)
1989
1990 /* ASM:DEV_STATISTICS:RX_SIZE256TO511_CNT */
1991 #define ASM_RX_SIZE256TO511_CNT(g)                                             \
1992         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1993               76, 0, 1, 4)
1994
1995 /* ASM:DEV_STATISTICS:RX_SIZE512TO1023_CNT */
1996 #define ASM_RX_SIZE512TO1023_CNT(g)                                            \
1997         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
1998               80, 0, 1, 4)
1999
2000 /* ASM:DEV_STATISTICS:RX_SIZE1024TO1518_CNT */
2001 #define ASM_RX_SIZE1024TO1518_CNT(g)                                           \
2002         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2003               84, 0, 1, 4)
2004
2005 /* ASM:DEV_STATISTICS:RX_SIZE1519TOMAX_CNT */
2006 #define ASM_RX_SIZE1519TOMAX_CNT(g)                                            \
2007         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2008               88, 0, 1, 4)
2009
2010 /* ASM:DEV_STATISTICS:RX_IPG_SHRINK_CNT */
2011 #define ASM_RX_IPG_SHRINK_CNT(g)                                               \
2012         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2013               92, 0, 1, 4)
2014
2015 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_CNT */
2016 #define ASM_TX_OUT_BYTES_CNT(g)                                                \
2017         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2018               96, 0, 1, 4)
2019
2020 /* ASM:DEV_STATISTICS:TX_PAUSE_CNT */
2021 #define ASM_TX_PAUSE_CNT(g)                                                    \
2022         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2023               100, 0, 1, 4)
2024
2025 /* ASM:DEV_STATISTICS:TX_OK_BYTES_CNT */
2026 #define ASM_TX_OK_BYTES_CNT(g)                                                 \
2027         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2028               104, 0, 1, 4)
2029
2030 /* ASM:DEV_STATISTICS:TX_UC_CNT */
2031 #define ASM_TX_UC_CNT(g)                                                       \
2032         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2033               108, 0, 1, 4)
2034
2035 /* ASM:DEV_STATISTICS:TX_MC_CNT */
2036 #define ASM_TX_MC_CNT(g)                                                       \
2037         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2038               112, 0, 1, 4)
2039
2040 /* ASM:DEV_STATISTICS:TX_BC_CNT */
2041 #define ASM_TX_BC_CNT(g)                                                       \
2042         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2043               116, 0, 1, 4)
2044
2045 /* ASM:DEV_STATISTICS:TX_SIZE64_CNT */
2046 #define ASM_TX_SIZE64_CNT(g)                                                   \
2047         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2048               120, 0, 1, 4)
2049
2050 /* ASM:DEV_STATISTICS:TX_SIZE65TO127_CNT */
2051 #define ASM_TX_SIZE65TO127_CNT(g)                                              \
2052         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2053               124, 0, 1, 4)
2054
2055 /* ASM:DEV_STATISTICS:TX_SIZE128TO255_CNT */
2056 #define ASM_TX_SIZE128TO255_CNT(g)                                             \
2057         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2058               128, 0, 1, 4)
2059
2060 /* ASM:DEV_STATISTICS:TX_SIZE256TO511_CNT */
2061 #define ASM_TX_SIZE256TO511_CNT(g)                                             \
2062         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2063               132, 0, 1, 4)
2064
2065 /* ASM:DEV_STATISTICS:TX_SIZE512TO1023_CNT */
2066 #define ASM_TX_SIZE512TO1023_CNT(g)                                            \
2067         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2068               136, 0, 1, 4)
2069
2070 /* ASM:DEV_STATISTICS:TX_SIZE1024TO1518_CNT */
2071 #define ASM_TX_SIZE1024TO1518_CNT(g)                                           \
2072         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2073               140, 0, 1, 4)
2074
2075 /* ASM:DEV_STATISTICS:TX_SIZE1519TOMAX_CNT */
2076 #define ASM_TX_SIZE1519TOMAX_CNT(g)                                            \
2077         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2078               144, 0, 1, 4)
2079
2080 /* ASM:DEV_STATISTICS:RX_ALIGNMENT_LOST_CNT */
2081 #define ASM_RX_ALIGNMENT_LOST_CNT(g)                                           \
2082         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2083               148, 0, 1, 4)
2084
2085 /* ASM:DEV_STATISTICS:RX_TAGGED_FRMS_CNT */
2086 #define ASM_RX_TAGGED_FRMS_CNT(g)                                              \
2087         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2088               152, 0, 1, 4)
2089
2090 /* ASM:DEV_STATISTICS:RX_UNTAGGED_FRMS_CNT */
2091 #define ASM_RX_UNTAGGED_FRMS_CNT(g)                                            \
2092         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2093               156, 0, 1, 4)
2094
2095 /* ASM:DEV_STATISTICS:TX_TAGGED_FRMS_CNT */
2096 #define ASM_TX_TAGGED_FRMS_CNT(g)                                              \
2097         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2098               160, 0, 1, 4)
2099
2100 /* ASM:DEV_STATISTICS:TX_UNTAGGED_FRMS_CNT */
2101 #define ASM_TX_UNTAGGED_FRMS_CNT(g)                                            \
2102         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2103               164, 0, 1, 4)
2104
2105 /* ASM:DEV_STATISTICS:PMAC_RX_SYMBOL_ERR_CNT */
2106 #define ASM_PMAC_RX_SYMBOL_ERR_CNT(g)                                          \
2107         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2108               168, 0, 1, 4)
2109
2110 /* ASM:DEV_STATISTICS:PMAC_RX_PAUSE_CNT */
2111 #define ASM_PMAC_RX_PAUSE_CNT(g)                                               \
2112         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2113               172, 0, 1, 4)
2114
2115 /* ASM:DEV_STATISTICS:PMAC_RX_UNSUP_OPCODE_CNT */
2116 #define ASM_PMAC_RX_UNSUP_OPCODE_CNT(g)                                        \
2117         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2118               176, 0, 1, 4)
2119
2120 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_CNT */
2121 #define ASM_PMAC_RX_OK_BYTES_CNT(g)                                            \
2122         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2123               180, 0, 1, 4)
2124
2125 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_CNT */
2126 #define ASM_PMAC_RX_BAD_BYTES_CNT(g)                                           \
2127         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2128               184, 0, 1, 4)
2129
2130 /* ASM:DEV_STATISTICS:PMAC_RX_UC_CNT */
2131 #define ASM_PMAC_RX_UC_CNT(g)                                                  \
2132         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2133               188, 0, 1, 4)
2134
2135 /* ASM:DEV_STATISTICS:PMAC_RX_MC_CNT */
2136 #define ASM_PMAC_RX_MC_CNT(g)                                                  \
2137         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2138               192, 0, 1, 4)
2139
2140 /* ASM:DEV_STATISTICS:PMAC_RX_BC_CNT */
2141 #define ASM_PMAC_RX_BC_CNT(g)                                                  \
2142         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2143               196, 0, 1, 4)
2144
2145 /* ASM:DEV_STATISTICS:PMAC_RX_CRC_ERR_CNT */
2146 #define ASM_PMAC_RX_CRC_ERR_CNT(g)                                             \
2147         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2148               200, 0, 1, 4)
2149
2150 /* ASM:DEV_STATISTICS:PMAC_RX_UNDERSIZE_CNT */
2151 #define ASM_PMAC_RX_UNDERSIZE_CNT(g)                                           \
2152         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2153               204, 0, 1, 4)
2154
2155 /* ASM:DEV_STATISTICS:PMAC_RX_FRAGMENTS_CNT */
2156 #define ASM_PMAC_RX_FRAGMENTS_CNT(g)                                           \
2157         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2158               208, 0, 1, 4)
2159
2160 /* ASM:DEV_STATISTICS:PMAC_RX_IN_RANGE_LEN_ERR_CNT */
2161 #define ASM_PMAC_RX_IN_RANGE_LEN_ERR_CNT(g)                                    \
2162         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2163               212, 0, 1, 4)
2164
2165 /* ASM:DEV_STATISTICS:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */
2166 #define ASM_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(g)                                \
2167         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2168               216, 0, 1, 4)
2169
2170 /* ASM:DEV_STATISTICS:PMAC_RX_OVERSIZE_CNT */
2171 #define ASM_PMAC_RX_OVERSIZE_CNT(g)                                            \
2172         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2173               220, 0, 1, 4)
2174
2175 /* ASM:DEV_STATISTICS:PMAC_RX_JABBERS_CNT */
2176 #define ASM_PMAC_RX_JABBERS_CNT(g)                                             \
2177         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2178               224, 0, 1, 4)
2179
2180 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE64_CNT */
2181 #define ASM_PMAC_RX_SIZE64_CNT(g)                                              \
2182         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2183               228, 0, 1, 4)
2184
2185 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE65TO127_CNT */
2186 #define ASM_PMAC_RX_SIZE65TO127_CNT(g)                                         \
2187         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2188               232, 0, 1, 4)
2189
2190 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE128TO255_CNT */
2191 #define ASM_PMAC_RX_SIZE128TO255_CNT(g)                                        \
2192         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2193               236, 0, 1, 4)
2194
2195 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE256TO511_CNT */
2196 #define ASM_PMAC_RX_SIZE256TO511_CNT(g)                                        \
2197         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2198               240, 0, 1, 4)
2199
2200 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE512TO1023_CNT */
2201 #define ASM_PMAC_RX_SIZE512TO1023_CNT(g)                                       \
2202         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2203               244, 0, 1, 4)
2204
2205 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1024TO1518_CNT */
2206 #define ASM_PMAC_RX_SIZE1024TO1518_CNT(g)                                      \
2207         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2208               248, 0, 1, 4)
2209
2210 /* ASM:DEV_STATISTICS:PMAC_RX_SIZE1519TOMAX_CNT */
2211 #define ASM_PMAC_RX_SIZE1519TOMAX_CNT(g)                                       \
2212         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2213               252, 0, 1, 4)
2214
2215 /* ASM:DEV_STATISTICS:PMAC_TX_PAUSE_CNT */
2216 #define ASM_PMAC_TX_PAUSE_CNT(g)                                               \
2217         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2218               256, 0, 1, 4)
2219
2220 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_CNT */
2221 #define ASM_PMAC_TX_OK_BYTES_CNT(g)                                            \
2222         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2223               260, 0, 1, 4)
2224
2225 /* ASM:DEV_STATISTICS:PMAC_TX_UC_CNT */
2226 #define ASM_PMAC_TX_UC_CNT(g)                                                  \
2227         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2228               264, 0, 1, 4)
2229
2230 /* ASM:DEV_STATISTICS:PMAC_TX_MC_CNT */
2231 #define ASM_PMAC_TX_MC_CNT(g)                                                  \
2232         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2233               268, 0, 1, 4)
2234
2235 /* ASM:DEV_STATISTICS:PMAC_TX_BC_CNT */
2236 #define ASM_PMAC_TX_BC_CNT(g)                                                  \
2237         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2238               272, 0, 1, 4)
2239
2240 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE64_CNT */
2241 #define ASM_PMAC_TX_SIZE64_CNT(g)                                              \
2242         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2243               276, 0, 1, 4)
2244
2245 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE65TO127_CNT */
2246 #define ASM_PMAC_TX_SIZE65TO127_CNT(g)                                         \
2247         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2248               280, 0, 1, 4)
2249
2250 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE128TO255_CNT */
2251 #define ASM_PMAC_TX_SIZE128TO255_CNT(g)                                        \
2252         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2253               284, 0, 1, 4)
2254
2255 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE256TO511_CNT */
2256 #define ASM_PMAC_TX_SIZE256TO511_CNT(g)                                        \
2257         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2258               288, 0, 1, 4)
2259
2260 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE512TO1023_CNT */
2261 #define ASM_PMAC_TX_SIZE512TO1023_CNT(g)                                       \
2262         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2263               292, 0, 1, 4)
2264
2265 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1024TO1518_CNT */
2266 #define ASM_PMAC_TX_SIZE1024TO1518_CNT(g)                                      \
2267         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2268               296, 0, 1, 4)
2269
2270 /* ASM:DEV_STATISTICS:PMAC_TX_SIZE1519TOMAX_CNT */
2271 #define ASM_PMAC_TX_SIZE1519TOMAX_CNT(g)                                       \
2272         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2273               300, 0, 1, 4)
2274
2275 /* ASM:DEV_STATISTICS:PMAC_RX_ALIGNMENT_LOST_CNT */
2276 #define ASM_PMAC_RX_ALIGNMENT_LOST_CNT(g)                                      \
2277         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2278               304, 0, 1, 4)
2279
2280 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_ERR_CNT */
2281 #define ASM_MM_RX_ASSEMBLY_ERR_CNT(g)                                          \
2282         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2283               308, 0, 1, 4)
2284
2285 /* ASM:DEV_STATISTICS:MM_RX_SMD_ERR_CNT */
2286 #define ASM_MM_RX_SMD_ERR_CNT(g)                                               \
2287         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2288               312, 0, 1, 4)
2289
2290 /* ASM:DEV_STATISTICS:MM_RX_ASSEMBLY_OK_CNT */
2291 #define ASM_MM_RX_ASSEMBLY_OK_CNT(g)                                           \
2292         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2293               316, 0, 1, 4)
2294
2295 /* ASM:DEV_STATISTICS:MM_RX_MERGE_FRAG_CNT */
2296 #define ASM_MM_RX_MERGE_FRAG_CNT(g)                                            \
2297         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2298               320, 0, 1, 4)
2299
2300 /* ASM:DEV_STATISTICS:MM_TX_PFRAGMENT_CNT */
2301 #define ASM_MM_TX_PFRAGMENT_CNT(g)                                             \
2302         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2303               324, 0, 1, 4)
2304
2305 /* ASM:DEV_STATISTICS:TX_MULTI_COLL_CNT */
2306 #define ASM_TX_MULTI_COLL_CNT(g)                                               \
2307         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2308               328, 0, 1, 4)
2309
2310 /* ASM:DEV_STATISTICS:TX_LATE_COLL_CNT */
2311 #define ASM_TX_LATE_COLL_CNT(g)                                                \
2312         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2313               332, 0, 1, 4)
2314
2315 /* ASM:DEV_STATISTICS:TX_XCOLL_CNT */
2316 #define ASM_TX_XCOLL_CNT(g)                                                    \
2317         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2318               336, 0, 1, 4)
2319
2320 /* ASM:DEV_STATISTICS:TX_DEFER_CNT */
2321 #define ASM_TX_DEFER_CNT(g)                                                    \
2322         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2323               340, 0, 1, 4)
2324
2325 /* ASM:DEV_STATISTICS:TX_XDEFER_CNT */
2326 #define ASM_TX_XDEFER_CNT(g)                                                   \
2327         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2328               344, 0, 1, 4)
2329
2330 /* ASM:DEV_STATISTICS:TX_BACKOFF1_CNT */
2331 #define ASM_TX_BACKOFF1_CNT(g)                                                 \
2332         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2333               348, 0, 1, 4)
2334
2335 /* ASM:DEV_STATISTICS:TX_CSENSE_CNT */
2336 #define ASM_TX_CSENSE_CNT(g)                                                   \
2337         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2338               352, 0, 1, 4)
2339
2340 /* ASM:DEV_STATISTICS:RX_IN_BYTES_MSB_CNT */
2341 #define ASM_RX_IN_BYTES_MSB_CNT(g)                                             \
2342         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2343               356, 0, 1, 4)
2344
2345 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(3, 0)
2346 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\
2347         FIELD_PREP(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2348 #define ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\
2349         FIELD_GET(ASM_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
2350
2351 /* ASM:DEV_STATISTICS:RX_OK_BYTES_MSB_CNT */
2352 #define ASM_RX_OK_BYTES_MSB_CNT(g)                                             \
2353         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2354               360, 0, 1, 4)
2355
2356 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(3, 0)
2357 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\
2358         FIELD_PREP(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2359 #define ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\
2360         FIELD_GET(ASM_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
2361
2362 /* ASM:DEV_STATISTICS:PMAC_RX_OK_BYTES_MSB_CNT */
2363 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT(g)                                        \
2364         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2365               364, 0, 1, 4)
2366
2367 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(3, 0)
2368 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\
2369         FIELD_PREP(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2370 #define ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\
2371         FIELD_GET(ASM_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
2372
2373 /* ASM:DEV_STATISTICS:RX_BAD_BYTES_MSB_CNT */
2374 #define ASM_RX_BAD_BYTES_MSB_CNT(g)                                            \
2375         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2376               368, 0, 1, 4)
2377
2378 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0)
2379 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\
2380         FIELD_PREP(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2381 #define ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\
2382         FIELD_GET(ASM_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
2383
2384 /* ASM:DEV_STATISTICS:PMAC_RX_BAD_BYTES_MSB_CNT */
2385 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT(g)                                       \
2386         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2387               372, 0, 1, 4)
2388
2389 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(3, 0)
2390 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\
2391         FIELD_PREP(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2392 #define ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\
2393         FIELD_GET(ASM_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
2394
2395 /* ASM:DEV_STATISTICS:TX_OUT_BYTES_MSB_CNT */
2396 #define ASM_TX_OUT_BYTES_MSB_CNT(g)                                            \
2397         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2398               376, 0, 1, 4)
2399
2400 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(3, 0)
2401 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\
2402         FIELD_PREP(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2403 #define ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\
2404         FIELD_GET(ASM_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
2405
2406 /* ASM:DEV_STATISTICS:TX_OK_BYTES_MSB_CNT */
2407 #define ASM_TX_OK_BYTES_MSB_CNT(g)                                             \
2408         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2409               380, 0, 1, 4)
2410
2411 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(3, 0)
2412 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\
2413         FIELD_PREP(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2414 #define ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\
2415         FIELD_GET(ASM_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
2416
2417 /* ASM:DEV_STATISTICS:PMAC_TX_OK_BYTES_MSB_CNT */
2418 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT(g)                                        \
2419         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2420               384, 0, 1, 4)
2421
2422 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(3, 0)
2423 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\
2424         FIELD_PREP(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2425 #define ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\
2426         FIELD_GET(ASM_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
2427
2428 /* ASM:DEV_STATISTICS:RX_SYNC_LOST_ERR_CNT */
2429 #define ASM_RX_SYNC_LOST_ERR_CNT(g)                                            \
2430         __REG(TARGET_ASM, 0, 1, 0, g, regs->gcnt[GC_ASM_DEV_STATISTICS], 512,  \
2431               388, 0, 1, 4)
2432
2433 /* ASM:CFG:STAT_CFG */
2434 #define ASM_STAT_CFG                                                           \
2435         __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1,                 \
2436               regs->gsize[GW_ASM_CFG], 0, 0, 1, 4)
2437
2438 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT           BIT(0)
2439 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(x)\
2440         FIELD_PREP(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
2441 #define ASM_STAT_CFG_STAT_CNT_CLR_SHOT_GET(x)\
2442         FIELD_GET(ASM_STAT_CFG_STAT_CNT_CLR_SHOT, x)
2443
2444 /* ASM:CFG:PORT_CFG */
2445 #define ASM_PORT_CFG(r)                                                        \
2446         __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_CFG], 0, 1,                 \
2447               regs->gsize[GW_ASM_CFG], 540, r, regs->rcnt[RC_ASM_PORT_CFG], 4)
2448
2449 #define ASM_PORT_CFG_CSC_STAT_DIS                BIT(12)
2450 #define ASM_PORT_CFG_CSC_STAT_DIS_SET(x)\
2451         FIELD_PREP(ASM_PORT_CFG_CSC_STAT_DIS, x)
2452 #define ASM_PORT_CFG_CSC_STAT_DIS_GET(x)\
2453         FIELD_GET(ASM_PORT_CFG_CSC_STAT_DIS, x)
2454
2455 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA      BIT(11)
2456 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_SET(x)\
2457         FIELD_PREP(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
2458 #define ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA_GET(x)\
2459         FIELD_GET(ASM_PORT_CFG_HIH_AFTER_PREAMBLE_ENA, x)
2460
2461 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA          BIT(10)
2462 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_SET(x)\
2463         FIELD_PREP(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
2464 #define ASM_PORT_CFG_IGN_TAXI_ABORT_ENA_GET(x)\
2465         FIELD_GET(ASM_PORT_CFG_IGN_TAXI_ABORT_ENA, x)
2466
2467 #define ASM_PORT_CFG_NO_PREAMBLE_ENA             BIT(9)
2468 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x)\
2469         FIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
2470 #define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x)\
2471         FIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)
2472
2473 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA           BIT(8)
2474 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_SET(x)\
2475         FIELD_PREP(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
2476 #define ASM_PORT_CFG_SKIP_PREAMBLE_ENA_GET(x)\
2477         FIELD_GET(ASM_PORT_CFG_SKIP_PREAMBLE_ENA, x)
2478
2479 #define ASM_PORT_CFG_FRM_AGING_DIS               BIT(7)
2480 #define ASM_PORT_CFG_FRM_AGING_DIS_SET(x)\
2481         FIELD_PREP(ASM_PORT_CFG_FRM_AGING_DIS, x)
2482 #define ASM_PORT_CFG_FRM_AGING_DIS_GET(x)\
2483         FIELD_GET(ASM_PORT_CFG_FRM_AGING_DIS, x)
2484
2485 #define ASM_PORT_CFG_PAD_ENA                     BIT(6)
2486 #define ASM_PORT_CFG_PAD_ENA_SET(x)\
2487         FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x)
2488 #define ASM_PORT_CFG_PAD_ENA_GET(x)\
2489         FIELD_GET(ASM_PORT_CFG_PAD_ENA, x)
2490
2491 #define ASM_PORT_CFG_INJ_DISCARD_CFG             GENMASK(5, 4)
2492 #define ASM_PORT_CFG_INJ_DISCARD_CFG_SET(x)\
2493         FIELD_PREP(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
2494 #define ASM_PORT_CFG_INJ_DISCARD_CFG_GET(x)\
2495         FIELD_GET(ASM_PORT_CFG_INJ_DISCARD_CFG, x)
2496
2497 #define ASM_PORT_CFG_INJ_FORMAT_CFG              GENMASK(3, 2)
2498 #define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x)\
2499         FIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
2500 #define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x)\
2501         FIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x)
2502
2503 #define ASM_PORT_CFG_VSTAX2_AWR_ENA              BIT(1)
2504 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_SET(x)\
2505         FIELD_PREP(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
2506 #define ASM_PORT_CFG_VSTAX2_AWR_ENA_GET(x)\
2507         FIELD_GET(ASM_PORT_CFG_VSTAX2_AWR_ENA, x)
2508
2509 #define ASM_PORT_CFG_PFRM_FLUSH                  BIT(0)
2510 #define ASM_PORT_CFG_PFRM_FLUSH_SET(x)\
2511         FIELD_PREP(ASM_PORT_CFG_PFRM_FLUSH, x)
2512 #define ASM_PORT_CFG_PFRM_FLUSH_GET(x)\
2513         FIELD_GET(ASM_PORT_CFG_PFRM_FLUSH, x)
2514
2515 /* ASM:RAM_CTRL:RAM_INIT */
2516 #define ASM_RAM_INIT                                                           \
2517         __REG(TARGET_ASM, 0, 1, regs->gaddr[GA_ASM_RAM_CTRL], 0, 1, 4, 0, 0, 1,\
2518               4)
2519
2520 #define ASM_RAM_INIT_RAM_INIT                    BIT(1)
2521 #define ASM_RAM_INIT_RAM_INIT_SET(x)\
2522         FIELD_PREP(ASM_RAM_INIT_RAM_INIT, x)
2523 #define ASM_RAM_INIT_RAM_INIT_GET(x)\
2524         FIELD_GET(ASM_RAM_INIT_RAM_INIT, x)
2525
2526 #define ASM_RAM_INIT_RAM_CFG_HOOK                BIT(0)
2527 #define ASM_RAM_INIT_RAM_CFG_HOOK_SET(x)\
2528         FIELD_PREP(ASM_RAM_INIT_RAM_CFG_HOOK, x)
2529 #define ASM_RAM_INIT_RAM_CFG_HOOK_GET(x)\
2530         FIELD_GET(ASM_RAM_INIT_RAM_CFG_HOOK, x)
2531
2532 /* SPARX5 ONLY */
2533 /* CLKGEN:LCPLL1:LCPLL1_CORE_CLK_CFG */
2534 #define CLKGEN_LCPLL1_CORE_CLK_CFG                                             \
2535         __REG(TARGET_CLKGEN, 0, 1, 12, 0, 1, 36, 0, 0, 1, 4)
2536
2537 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV  GENMASK(7, 0)
2538 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_SET(x)\
2539         FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
2540 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV_GET(x)\
2541         FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_DIV, x)
2542
2543 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV  GENMASK(10, 8)
2544 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_SET(x)\
2545         FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
2546 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV_GET(x)\
2547         FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_PRE_DIV, x)
2548
2549 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR  BIT(11)
2550 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_SET(x)\
2551         FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
2552 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR_GET(x)\
2553         FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_DIR, x)
2554
2555 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL  GENMASK(13, 12)
2556 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_SET(x)\
2557         FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
2558 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL_GET(x)\
2559         FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_SEL, x)
2560
2561 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA  BIT(14)
2562 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_SET(x)\
2563         FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
2564 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA_GET(x)\
2565         FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_ROT_ENA, x)
2566
2567 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA  BIT(15)
2568 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_SET(x)\
2569         FIELD_PREP(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
2570 #define CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA_GET(x)\
2571         FIELD_GET(CLKGEN_LCPLL1_CORE_CLK_CFG_CORE_CLK_ENA, x)
2572
2573 /* CPU:CPU_REGS:PROC_CTRL */
2574 #define CPU_PROC_CTRL                                                          \
2575         __REG(TARGET_CPU, 0, 1, 0, 0, 1, regs->gsize[GW_CPU_CPU_REGS],         \
2576               regs->raddr[RA_CPU_PROC_CTRL], 0, 1, 4)
2577
2578 #define CPU_PROC_CTRL_AARCH64_MODE_ENA\
2579         BIT(regs->fpos[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA])
2580 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_SET(x)\
2581         spx5_field_prep(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
2582 #define CPU_PROC_CTRL_AARCH64_MODE_ENA_GET(x)\
2583         spx5_field_get(CPU_PROC_CTRL_AARCH64_MODE_ENA, x)
2584
2585 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS\
2586         BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS])
2587 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_SET(x)\
2588         spx5_field_prep(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
2589 #define CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS_GET(x)\
2590         spx5_field_get(CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS, x)
2591
2592 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS\
2593         BIT(regs->fpos[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS])
2594 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_SET(x)\
2595         spx5_field_prep(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
2596 #define CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS_GET(x)\
2597         spx5_field_get(CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS, x)
2598
2599 #define CPU_PROC_CTRL_BE_EXCEP_MODE\
2600         BIT(regs->fpos[FP_CPU_PROC_CTRL_BE_EXCEP_MODE])
2601 #define CPU_PROC_CTRL_BE_EXCEP_MODE_SET(x)\
2602         spx5_field_prep(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
2603 #define CPU_PROC_CTRL_BE_EXCEP_MODE_GET(x)\
2604         spx5_field_get(CPU_PROC_CTRL_BE_EXCEP_MODE, x)
2605
2606 #define CPU_PROC_CTRL_VINITHI\
2607         BIT(regs->fpos[FP_CPU_PROC_CTRL_VINITHI])
2608 #define CPU_PROC_CTRL_VINITHI_SET(x)\
2609         spx5_field_prep(CPU_PROC_CTRL_VINITHI, x)
2610 #define CPU_PROC_CTRL_VINITHI_GET(x)\
2611         spx5_field_get(CPU_PROC_CTRL_VINITHI, x)
2612
2613 #define CPU_PROC_CTRL_CFGTE\
2614         BIT(regs->fpos[FP_CPU_PROC_CTRL_CFGTE])
2615 #define CPU_PROC_CTRL_CFGTE_SET(x)\
2616         spx5_field_prep(CPU_PROC_CTRL_CFGTE, x)
2617 #define CPU_PROC_CTRL_CFGTE_GET(x)\
2618         spx5_field_get(CPU_PROC_CTRL_CFGTE, x)
2619
2620 #define CPU_PROC_CTRL_CP15S_DISABLE\
2621         BIT(regs->fpos[FP_CPU_PROC_CTRL_CP15S_DISABLE])
2622 #define CPU_PROC_CTRL_CP15S_DISABLE_SET(x)\
2623         spx5_field_prep(CPU_PROC_CTRL_CP15S_DISABLE, x)
2624 #define CPU_PROC_CTRL_CP15S_DISABLE_GET(x)\
2625         spx5_field_get(CPU_PROC_CTRL_CP15S_DISABLE, x)
2626
2627 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE\
2628         BIT(regs->fpos[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE])
2629 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_SET(x)\
2630         spx5_field_prep(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
2631 #define CPU_PROC_CTRL_PROC_CRYPTO_DISABLE_GET(x)\
2632         spx5_field_get(CPU_PROC_CTRL_PROC_CRYPTO_DISABLE, x)
2633
2634 /* SPARX5 ONLY */
2635 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA        BIT(4)
2636 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_SET(x)\
2637         FIELD_PREP(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
2638 #define CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA_GET(x)\
2639         FIELD_GET(CPU_PROC_CTRL_ACP_CACHE_FORCE_ENA, x)
2640
2641 /* SPARX5 ONLY */
2642 #define CPU_PROC_CTRL_ACP_AWCACHE                BIT(3)
2643 #define CPU_PROC_CTRL_ACP_AWCACHE_SET(x)\
2644         FIELD_PREP(CPU_PROC_CTRL_ACP_AWCACHE, x)
2645 #define CPU_PROC_CTRL_ACP_AWCACHE_GET(x)\
2646         FIELD_GET(CPU_PROC_CTRL_ACP_AWCACHE, x)
2647
2648 /* SPARX5 ONLY */
2649 #define CPU_PROC_CTRL_ACP_ARCACHE                BIT(2)
2650 #define CPU_PROC_CTRL_ACP_ARCACHE_SET(x)\
2651         FIELD_PREP(CPU_PROC_CTRL_ACP_ARCACHE, x)
2652 #define CPU_PROC_CTRL_ACP_ARCACHE_GET(x)\
2653         FIELD_GET(CPU_PROC_CTRL_ACP_ARCACHE, x)
2654
2655 #define CPU_PROC_CTRL_L2_FLUSH_REQ\
2656         BIT(regs->fpos[FP_CPU_PROC_CTRL_L2_FLUSH_REQ])
2657 #define CPU_PROC_CTRL_L2_FLUSH_REQ_SET(x)\
2658         spx5_field_prep(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
2659 #define CPU_PROC_CTRL_L2_FLUSH_REQ_GET(x)\
2660         spx5_field_get(CPU_PROC_CTRL_L2_FLUSH_REQ, x)
2661
2662 /* SPARX5 ONLY */
2663 #define CPU_PROC_CTRL_ACP_DISABLE                BIT(0)
2664 #define CPU_PROC_CTRL_ACP_DISABLE_SET(x)\
2665         FIELD_PREP(CPU_PROC_CTRL_ACP_DISABLE, x)
2666 #define CPU_PROC_CTRL_ACP_DISABLE_GET(x)\
2667         FIELD_GET(CPU_PROC_CTRL_ACP_DISABLE, x)
2668
2669 /* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */
2670 #define DEV2G5_PHAD_CTRL(t, g)                                                 \
2671         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2,             \
2672               regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4)
2673
2674 #define DEV2G5_PHAD_CTRL_PHAD_ENA\
2675         BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA])
2676 #define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\
2677         spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
2678 #define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\
2679         spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
2680
2681 /* LAN969X ONLY */
2682 #define DEV2G5_PHAD_CTRL_DIV_CFG                 GENMASK(11, 9)
2683 #define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\
2684         FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x)
2685 #define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\
2686         FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x)
2687
2688 /* DEV1G:PHASE_DETECTOR_CTRL:PHAD_CTRL */
2689 #define DEV2G5_PHAD_CTRL(t, g)                                                 \
2690         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 200, g, 2,             \
2691               regs->gsize[GW_DEV2G5_PHASE_DETECTOR_CTRL], 0, 0, 1, 4)
2692
2693 #define DEV2G5_PHAD_CTRL_PHAD_ENA\
2694         BIT(regs->fpos[FP_DEV2G5_PHAD_CTRL_PHAD_ENA])
2695 #define DEV2G5_PHAD_CTRL_PHAD_ENA_SET(x)\
2696         spx5_field_prep(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
2697 #define DEV2G5_PHAD_CTRL_PHAD_ENA_GET(x)\
2698         spx5_field_get(DEV2G5_PHAD_CTRL_PHAD_ENA, x)
2699
2700 /* LAN969X ONLY */
2701 #define DEV2G5_PHAD_CTRL_DIV_CFG                 GENMASK(11, 9)
2702 #define DEV2G5_PHAD_CTRL_DIV_CFG_SET(x)\
2703         FIELD_PREP(DEV2G5_PHAD_CTRL_DIV_CFG, x)
2704 #define DEV2G5_PHAD_CTRL_DIV_CFG_GET(x)\
2705         FIELD_GET(DEV2G5_PHAD_CTRL_DIV_CFG, x)
2706
2707 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
2708 #define DEV10G_MAC_ENA_CFG(t)                                                  \
2709         __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 0, 0, 1,  \
2710               4)
2711
2712 #define DEV10G_MAC_ENA_CFG_RX_ENA                BIT(4)
2713 #define DEV10G_MAC_ENA_CFG_RX_ENA_SET(x)\
2714         FIELD_PREP(DEV10G_MAC_ENA_CFG_RX_ENA, x)
2715 #define DEV10G_MAC_ENA_CFG_RX_ENA_GET(x)\
2716         FIELD_GET(DEV10G_MAC_ENA_CFG_RX_ENA, x)
2717
2718 #define DEV10G_MAC_ENA_CFG_TX_ENA                BIT(0)
2719 #define DEV10G_MAC_ENA_CFG_TX_ENA_SET(x)\
2720         FIELD_PREP(DEV10G_MAC_ENA_CFG_TX_ENA, x)
2721 #define DEV10G_MAC_ENA_CFG_TX_ENA_GET(x)\
2722         FIELD_GET(DEV10G_MAC_ENA_CFG_TX_ENA, x)
2723
2724 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
2725 #define DEV10G_MAC_MAXLEN_CFG(t)                                               \
2726         __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 8, 0, 1,  \
2727               4)
2728
2729 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK    BIT(16)
2730 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
2731         FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2732 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
2733         FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2734
2735 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN            GENMASK(15, 0)
2736 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
2737         FIELD_PREP(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
2738 #define DEV10G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
2739         FIELD_GET(DEV10G_MAC_MAXLEN_CFG_MAX_LEN, x)
2740
2741 /* DEV10G:MAC_CFG_STATUS:MAC_NUM_TAGS_CFG */
2742 #define DEV10G_MAC_NUM_TAGS_CFG(t)                                             \
2743         __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 12, 0, 1, \
2744               4)
2745
2746 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS         GENMASK(1, 0)
2747 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_SET(x)\
2748         FIELD_PREP(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
2749 #define DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS_GET(x)\
2750         FIELD_GET(DEV10G_MAC_NUM_TAGS_CFG_NUM_TAGS, x)
2751
2752 /* DEV10G:MAC_CFG_STATUS:MAC_TAGS_CFG */
2753 #define DEV10G_MAC_TAGS_CFG(t, r)                                              \
2754         __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 16, r, 3, \
2755               4)
2756
2757 #define DEV10G_MAC_TAGS_CFG_TAG_ID               GENMASK(31, 16)
2758 #define DEV10G_MAC_TAGS_CFG_TAG_ID_SET(x)\
2759         FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
2760 #define DEV10G_MAC_TAGS_CFG_TAG_ID_GET(x)\
2761         FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ID, x)
2762
2763 #define DEV10G_MAC_TAGS_CFG_TAG_ENA              BIT(4)
2764 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_SET(x)\
2765         FIELD_PREP(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
2766 #define DEV10G_MAC_TAGS_CFG_TAG_ENA_GET(x)\
2767         FIELD_GET(DEV10G_MAC_TAGS_CFG_TAG_ENA, x)
2768
2769 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
2770 #define DEV10G_MAC_ADV_CHK_CFG(t)                                              \
2771         __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 28, 0, 1, \
2772               4)
2773
2774 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA   BIT(24)
2775 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
2776         FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2777 #define DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
2778         FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2779
2780 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA   BIT(20)
2781 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
2782         FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2783 #define DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
2784         FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2785
2786 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA       BIT(16)
2787 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
2788         FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2789 #define DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
2790         FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2791
2792 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS   BIT(12)
2793 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
2794         FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2795 #define DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
2796         FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2797
2798 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA       BIT(8)
2799 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
2800         FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2801 #define DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
2802         FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2803
2804 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA       BIT(4)
2805 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
2806         FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2807 #define DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
2808         FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2809
2810 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA       BIT(0)
2811 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
2812         FIELD_PREP(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2813 #define DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
2814         FIELD_GET(DEV10G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
2815
2816 /* DEV10G:MAC_CFG_STATUS:MAC_TX_MONITOR_STICKY */
2817 #define DEV10G_MAC_TX_MONITOR_STICKY(t)                                        \
2818         __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 0, 0, 1, 60, 48, 0, 1, \
2819               4)
2820
2821 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY BIT(4)
2822 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_SET(x)\
2823         FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
2824 #define DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY_GET(x)\
2825         FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LOCAL_ERR_STATE_STICKY, x)
2826
2827 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY BIT(3)
2828 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_SET(x)\
2829         FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
2830 #define DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY_GET(x)\
2831         FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_REMOTE_ERR_STATE_STICKY, x)
2832
2833 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY BIT(2)
2834 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_SET(x)\
2835         FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
2836 #define DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY_GET(x)\
2837         FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_LINK_INTERRUPTION_STATE_STICKY, x)
2838
2839 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY BIT(1)
2840 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_SET(x)\
2841         FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
2842 #define DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY_GET(x)\
2843         FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY, x)
2844
2845 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY BIT(0)
2846 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_SET(x)\
2847         FIELD_PREP(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
2848 #define DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY_GET(x)\
2849         FIELD_GET(DEV10G_MAC_TX_MONITOR_STICKY_DIS_STATE_STICKY, x)
2850
2851 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
2852 #define DEV10G_DEV_RST_CTRL(t)                                                 \
2853         __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 0, 0, 1,\
2854               4)
2855
2856 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA      BIT(28)
2857 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
2858         FIELD_PREP(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2859 #define DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
2860         FIELD_GET(DEV10G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
2861
2862 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
2863 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
2864         FIELD_PREP(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2865 #define DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
2866         FIELD_GET(DEV10G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
2867
2868 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
2869 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
2870         FIELD_PREP(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2871 #define DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
2872         FIELD_GET(DEV10G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
2873
2874 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL     GENMASK(24, 23)
2875 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
2876         FIELD_PREP(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2877 #define DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
2878         FIELD_GET(DEV10G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
2879
2880 #define DEV10G_DEV_RST_CTRL_SPEED_SEL            GENMASK(22, 20)
2881 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
2882         FIELD_PREP(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
2883 #define DEV10G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
2884         FIELD_GET(DEV10G_DEV_RST_CTRL_SPEED_SEL, x)
2885
2886 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST           BIT(12)
2887 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
2888         FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
2889 #define DEV10G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
2890         FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_TX_RST, x)
2891
2892 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST           BIT(8)
2893 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
2894         FIELD_PREP(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
2895 #define DEV10G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
2896         FIELD_GET(DEV10G_DEV_RST_CTRL_PCS_RX_RST, x)
2897
2898 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST           BIT(4)
2899 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
2900         FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
2901 #define DEV10G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
2902         FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_TX_RST, x)
2903
2904 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST           BIT(0)
2905 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
2906         FIELD_PREP(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
2907 #define DEV10G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
2908         FIELD_GET(DEV10G_DEV_RST_CTRL_MAC_RX_RST, x)
2909
2910 /* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */
2911 #define DEV10G_PTP_STAMPER_CFG(t)                                              \
2912         __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 436, 0, 1, 52, 20, 0,  \
2913               1, 4)
2914
2915 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */
2916 #define DEV10G_PCS25G_CFG(t)                                                   \
2917         __REG(TARGET_DEV10G, t, regs->tsize[TC_DEV10G], 488, 0, 1, 32, 0, 0, 1,\
2918               4)
2919
2920 #define DEV10G_PCS25G_CFG_PCS25G_ENA             BIT(0)
2921 #define DEV10G_PCS25G_CFG_PCS25G_ENA_SET(x)\
2922         FIELD_PREP(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
2923 #define DEV10G_PCS25G_CFG_PCS25G_ENA_GET(x)\
2924         FIELD_GET(DEV10G_PCS25G_CFG_PCS25G_ENA, x)
2925
2926 /* SPARX5 ONLY */
2927 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
2928 #define DEV25G_MAC_ENA_CFG(t)                                                  \
2929         __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 0, 0, 1, 4)
2930
2931 #define DEV25G_MAC_ENA_CFG_RX_ENA                BIT(4)
2932 #define DEV25G_MAC_ENA_CFG_RX_ENA_SET(x)\
2933         FIELD_PREP(DEV25G_MAC_ENA_CFG_RX_ENA, x)
2934 #define DEV25G_MAC_ENA_CFG_RX_ENA_GET(x)\
2935         FIELD_GET(DEV25G_MAC_ENA_CFG_RX_ENA, x)
2936
2937 #define DEV25G_MAC_ENA_CFG_TX_ENA                BIT(0)
2938 #define DEV25G_MAC_ENA_CFG_TX_ENA_SET(x)\
2939         FIELD_PREP(DEV25G_MAC_ENA_CFG_TX_ENA, x)
2940 #define DEV25G_MAC_ENA_CFG_TX_ENA_GET(x)\
2941         FIELD_GET(DEV25G_MAC_ENA_CFG_TX_ENA, x)
2942
2943 /* SPARX5 ONLY */
2944 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
2945 #define DEV25G_MAC_MAXLEN_CFG(t)                                               \
2946         __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 8, 0, 1, 4)
2947
2948 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK    BIT(16)
2949 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
2950         FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2951 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
2952         FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
2953
2954 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN            GENMASK(15, 0)
2955 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
2956         FIELD_PREP(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
2957 #define DEV25G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
2958         FIELD_GET(DEV25G_MAC_MAXLEN_CFG_MAX_LEN, x)
2959
2960 /* SPARX5 ONLY */
2961 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
2962 #define DEV25G_MAC_ADV_CHK_CFG(t)                                              \
2963         __REG(TARGET_DEV25G, t, 8, 0, 0, 1, 60, 28, 0, 1, 4)
2964
2965 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA   BIT(24)
2966 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
2967         FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2968 #define DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
2969         FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
2970
2971 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA   BIT(20)
2972 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
2973         FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2974 #define DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
2975         FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
2976
2977 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA       BIT(16)
2978 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
2979         FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2980 #define DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
2981         FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
2982
2983 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS   BIT(12)
2984 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
2985         FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2986 #define DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
2987         FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
2988
2989 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA       BIT(8)
2990 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
2991         FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2992 #define DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
2993         FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
2994
2995 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA       BIT(4)
2996 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
2997         FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
2998 #define DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
2999         FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3000
3001 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA       BIT(0)
3002 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
3003         FIELD_PREP(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3004 #define DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
3005         FIELD_GET(DEV25G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3006
3007 /* SPARX5 ONLY */
3008 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
3009 #define DEV25G_DEV_RST_CTRL(t)                                                 \
3010         __REG(TARGET_DEV25G, t, 8, 436, 0, 1, 52, 0, 0, 1, 4)
3011
3012 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA      BIT(28)
3013 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
3014         FIELD_PREP(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
3015 #define DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
3016         FIELD_GET(DEV25G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
3017
3018 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
3019 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
3020         FIELD_PREP(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3021 #define DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
3022         FIELD_GET(DEV25G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3023
3024 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
3025 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
3026         FIELD_PREP(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
3027 #define DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
3028         FIELD_GET(DEV25G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
3029
3030 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL     GENMASK(24, 23)
3031 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
3032         FIELD_PREP(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
3033 #define DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
3034         FIELD_GET(DEV25G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
3035
3036 #define DEV25G_DEV_RST_CTRL_SPEED_SEL            GENMASK(22, 20)
3037 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
3038         FIELD_PREP(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
3039 #define DEV25G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
3040         FIELD_GET(DEV25G_DEV_RST_CTRL_SPEED_SEL, x)
3041
3042 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST           BIT(12)
3043 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
3044         FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
3045 #define DEV25G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
3046         FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_TX_RST, x)
3047
3048 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST           BIT(8)
3049 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
3050         FIELD_PREP(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
3051 #define DEV25G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
3052         FIELD_GET(DEV25G_DEV_RST_CTRL_PCS_RX_RST, x)
3053
3054 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST           BIT(4)
3055 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
3056         FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
3057 #define DEV25G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
3058         FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_TX_RST, x)
3059
3060 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST           BIT(0)
3061 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
3062         FIELD_PREP(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
3063 #define DEV25G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
3064         FIELD_GET(DEV25G_DEV_RST_CTRL_MAC_RX_RST, x)
3065
3066 /* SPARX5 ONLY */
3067 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_CFG */
3068 #define DEV25G_PCS25G_CFG(t)                                                   \
3069         __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 0, 0, 1, 4)
3070
3071 #define DEV25G_PCS25G_CFG_PCS25G_ENA             BIT(0)
3072 #define DEV25G_PCS25G_CFG_PCS25G_ENA_SET(x)\
3073         FIELD_PREP(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
3074 #define DEV25G_PCS25G_CFG_PCS25G_ENA_GET(x)\
3075         FIELD_GET(DEV25G_PCS25G_CFG_PCS25G_ENA, x)
3076
3077 /* SPARX5 ONLY */
3078 /* DEV10G:PCS25G_CFG_STATUS:PCS25G_SD_CFG */
3079 #define DEV25G_PCS25G_SD_CFG(t)                                                \
3080         __REG(TARGET_DEV25G, t, 8, 488, 0, 1, 32, 4, 0, 1, 4)
3081
3082 #define DEV25G_PCS25G_SD_CFG_SD_SEL              BIT(8)
3083 #define DEV25G_PCS25G_SD_CFG_SD_SEL_SET(x)\
3084         FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
3085 #define DEV25G_PCS25G_SD_CFG_SD_SEL_GET(x)\
3086         FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_SEL, x)
3087
3088 #define DEV25G_PCS25G_SD_CFG_SD_POL              BIT(4)
3089 #define DEV25G_PCS25G_SD_CFG_SD_POL_SET(x)\
3090         FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_POL, x)
3091 #define DEV25G_PCS25G_SD_CFG_SD_POL_GET(x)\
3092         FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_POL, x)
3093
3094 #define DEV25G_PCS25G_SD_CFG_SD_ENA              BIT(0)
3095 #define DEV25G_PCS25G_SD_CFG_SD_ENA_SET(x)\
3096         FIELD_PREP(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
3097 #define DEV25G_PCS25G_SD_CFG_SD_ENA_GET(x)\
3098         FIELD_GET(DEV25G_PCS25G_SD_CFG_SD_ENA, x)
3099
3100 /* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */
3101 #define DEV2G5_DEV_RST_CTRL(t)                                                 \
3102         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 0, 0, 1, 36, 0, 0, 1,  \
3103               4)
3104
3105 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(23)
3106 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
3107         FIELD_PREP(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3108 #define DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
3109         FIELD_GET(DEV2G5_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
3110
3111 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL            GENMASK(22, 20)
3112 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x)\
3113         FIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
3114 #define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x)\
3115         FIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)
3116
3117 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST       BIT(17)
3118 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x)\
3119         FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
3120 #define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x)\
3121         FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)
3122
3123 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST       BIT(16)
3124 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x)\
3125         FIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
3126 #define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x)\
3127         FIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)
3128
3129 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST           BIT(12)
3130 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
3131         FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
3132 #define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
3133         FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)
3134
3135 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST           BIT(8)
3136 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
3137         FIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
3138 #define DEV2G5_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
3139         FIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_RX_RST, x)
3140
3141 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST           BIT(4)
3142 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
3143         FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
3144 #define DEV2G5_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
3145         FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_TX_RST, x)
3146
3147 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST           BIT(0)
3148 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
3149         FIELD_PREP(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
3150 #define DEV2G5_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
3151         FIELD_GET(DEV2G5_DEV_RST_CTRL_MAC_RX_RST, x)
3152
3153 /* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */
3154 #define DEV2G5_MAC_ENA_CFG(t)                                                  \
3155         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 0, 0, 1, \
3156               4)
3157
3158 #define DEV2G5_MAC_ENA_CFG_RX_ENA                BIT(4)
3159 #define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x)\
3160         FIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
3161 #define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x)\
3162         FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x)
3163
3164 #define DEV2G5_MAC_ENA_CFG_TX_ENA                BIT(0)
3165 #define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x)\
3166         FIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
3167 #define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x)\
3168         FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x)
3169
3170 /* DEV1G:MAC_CFG_STATUS:MAC_MODE_CFG */
3171 #define DEV2G5_MAC_MODE_CFG(t)                                                 \
3172         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 4, 0, 1, \
3173               4)
3174
3175 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA     BIT(8)
3176 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_SET(x)\
3177         FIELD_PREP(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
3178 #define DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA_GET(x)\
3179         FIELD_GET(DEV2G5_MAC_MODE_CFG_FC_WORD_SYNC_ENA, x)
3180
3181 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA        BIT(4)
3182 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_SET(x)\
3183         FIELD_PREP(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
3184 #define DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA_GET(x)\
3185         FIELD_GET(DEV2G5_MAC_MODE_CFG_GIGA_MODE_ENA, x)
3186
3187 #define DEV2G5_MAC_MODE_CFG_FDX_ENA              BIT(0)
3188 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_SET(x)\
3189         FIELD_PREP(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
3190 #define DEV2G5_MAC_MODE_CFG_FDX_ENA_GET(x)\
3191         FIELD_GET(DEV2G5_MAC_MODE_CFG_FDX_ENA, x)
3192
3193 /* DEV1G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
3194 #define DEV2G5_MAC_MAXLEN_CFG(t)                                               \
3195         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 8, 0, 1, \
3196               4)
3197
3198 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN            GENMASK(15, 0)
3199 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
3200         FIELD_PREP(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
3201 #define DEV2G5_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
3202         FIELD_GET(DEV2G5_MAC_MAXLEN_CFG_MAX_LEN, x)
3203
3204 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG */
3205 #define DEV2G5_MAC_TAGS_CFG(t)                                                 \
3206         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 12, 0, 1,\
3207               4)
3208
3209 #define DEV2G5_MAC_TAGS_CFG_TAG_ID               GENMASK(31, 16)
3210 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_SET(x)\
3211         FIELD_PREP(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
3212 #define DEV2G5_MAC_TAGS_CFG_TAG_ID_GET(x)\
3213         FIELD_GET(DEV2G5_MAC_TAGS_CFG_TAG_ID, x)
3214
3215 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA     BIT(3)
3216 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_SET(x)\
3217         FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
3218 #define DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA_GET(x)\
3219         FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_LEN_AWR_ENA, x)
3220
3221 #define DEV2G5_MAC_TAGS_CFG_PB_ENA               GENMASK(2, 1)
3222 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_SET(x)\
3223         FIELD_PREP(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
3224 #define DEV2G5_MAC_TAGS_CFG_PB_ENA_GET(x)\
3225         FIELD_GET(DEV2G5_MAC_TAGS_CFG_PB_ENA, x)
3226
3227 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA         BIT(0)
3228 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_SET(x)\
3229         FIELD_PREP(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
3230 #define DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA_GET(x)\
3231         FIELD_GET(DEV2G5_MAC_TAGS_CFG_VLAN_AWR_ENA, x)
3232
3233 /* DEV1G:MAC_CFG_STATUS:MAC_TAGS_CFG2 */
3234 #define DEV2G5_MAC_TAGS_CFG2(t)                                                \
3235         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 16, 0, 1,\
3236               4)
3237
3238 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3             GENMASK(31, 16)
3239 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_SET(x)\
3240         FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
3241 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID3_GET(x)\
3242         FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID3, x)
3243
3244 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2             GENMASK(15, 0)
3245 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_SET(x)\
3246         FIELD_PREP(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
3247 #define DEV2G5_MAC_TAGS_CFG2_TAG_ID2_GET(x)\
3248         FIELD_GET(DEV2G5_MAC_TAGS_CFG2_TAG_ID2, x)
3249
3250 /* DEV1G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
3251 #define DEV2G5_MAC_ADV_CHK_CFG(t)                                              \
3252         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 20, 0, 1,\
3253               4)
3254
3255 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA      BIT(0)
3256 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_SET(x)\
3257         FIELD_PREP(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
3258 #define DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA_GET(x)\
3259         FIELD_GET(DEV2G5_MAC_ADV_CHK_CFG_LEN_DROP_ENA, x)
3260
3261 /* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */
3262 #define DEV2G5_MAC_IFG_CFG(t)                                                  \
3263         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 24, 0, 1,\
3264               4)
3265
3266 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)
3267 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x)\
3268         FIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
3269 #define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x)\
3270         FIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)
3271
3272 #define DEV2G5_MAC_IFG_CFG_TX_IFG                GENMASK(12, 8)
3273 #define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x)\
3274         FIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
3275 #define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x)\
3276         FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x)
3277
3278 #define DEV2G5_MAC_IFG_CFG_RX_IFG2               GENMASK(7, 4)
3279 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x)\
3280         FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
3281 #define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x)\
3282         FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)
3283
3284 #define DEV2G5_MAC_IFG_CFG_RX_IFG1               GENMASK(3, 0)
3285 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x)\
3286         FIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
3287 #define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x)\
3288         FIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)
3289
3290 /* DEV1G:MAC_CFG_STATUS:MAC_HDX_CFG */
3291 #define DEV2G5_MAC_HDX_CFG(t)                                                  \
3292         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 52, 0, 1, 36, 28, 0, 1,\
3293               4)
3294
3295 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC       BIT(26)
3296 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_SET(x)\
3297         FIELD_PREP(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
3298 #define DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC_GET(x)\
3299         FIELD_GET(DEV2G5_MAC_HDX_CFG_BYPASS_COL_SYNC, x)
3300
3301 #define DEV2G5_MAC_HDX_CFG_SEED                  GENMASK(23, 16)
3302 #define DEV2G5_MAC_HDX_CFG_SEED_SET(x)\
3303         FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED, x)
3304 #define DEV2G5_MAC_HDX_CFG_SEED_GET(x)\
3305         FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED, x)
3306
3307 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD             BIT(12)
3308 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_SET(x)\
3309         FIELD_PREP(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
3310 #define DEV2G5_MAC_HDX_CFG_SEED_LOAD_GET(x)\
3311         FIELD_GET(DEV2G5_MAC_HDX_CFG_SEED_LOAD, x)
3312
3313 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA BIT(8)
3314 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_SET(x)\
3315         FIELD_PREP(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
3316 #define DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA_GET(x)\
3317         FIELD_GET(DEV2G5_MAC_HDX_CFG_RETRY_AFTER_EXC_COL_ENA, x)
3318
3319 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS          GENMASK(6, 0)
3320 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_SET(x)\
3321         FIELD_PREP(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
3322 #define DEV2G5_MAC_HDX_CFG_LATE_COL_POS_GET(x)\
3323         FIELD_GET(DEV2G5_MAC_HDX_CFG_LATE_COL_POS, x)
3324
3325 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */
3326 #define DEV2G5_PCS1G_CFG(t)                                                    \
3327         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 0, 0, 1, \
3328               4)
3329
3330 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE        BIT(4)
3331 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_SET(x)\
3332         FIELD_PREP(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
3333 #define DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE_GET(x)\
3334         FIELD_GET(DEV2G5_PCS1G_CFG_LINK_STATUS_TYPE, x)
3335
3336 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA        BIT(1)
3337 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_SET(x)\
3338         FIELD_PREP(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
3339 #define DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA_GET(x)\
3340         FIELD_GET(DEV2G5_PCS1G_CFG_AN_LINK_CTRL_ENA, x)
3341
3342 #define DEV2G5_PCS1G_CFG_PCS_ENA                 BIT(0)
3343 #define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x)\
3344         FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x)
3345 #define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x)\
3346         FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x)
3347
3348 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */
3349 #define DEV2G5_PCS1G_MODE_CFG(t)                                               \
3350         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 4, 0, 1, \
3351               4)
3352
3353 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA    BIT(4)
3354 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_SET(x)\
3355         FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
3356 #define DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA_GET(x)\
3357         FIELD_GET(DEV2G5_PCS1G_MODE_CFG_UNIDIR_MODE_ENA, x)
3358
3359 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA  BIT(1)
3360 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_SET(x)\
3361         FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
3362 #define DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA_GET(x)\
3363         FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SAVE_PREAMBLE_ENA, x)
3364
3365 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA     BIT(0)
3366 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x)\
3367         FIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
3368 #define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x)\
3369         FIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)
3370
3371 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_SD_CFG */
3372 #define DEV2G5_PCS1G_SD_CFG(t)                                                 \
3373         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 8, 0, 1, \
3374               4)
3375
3376 #define DEV2G5_PCS1G_SD_CFG_SD_SEL               BIT(8)
3377 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_SET(x)\
3378         FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
3379 #define DEV2G5_PCS1G_SD_CFG_SD_SEL_GET(x)\
3380         FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_SEL, x)
3381
3382 #define DEV2G5_PCS1G_SD_CFG_SD_POL               BIT(4)
3383 #define DEV2G5_PCS1G_SD_CFG_SD_POL_SET(x)\
3384         FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
3385 #define DEV2G5_PCS1G_SD_CFG_SD_POL_GET(x)\
3386         FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_POL, x)
3387
3388 #define DEV2G5_PCS1G_SD_CFG_SD_ENA               BIT(0)
3389 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_SET(x)\
3390         FIELD_PREP(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
3391 #define DEV2G5_PCS1G_SD_CFG_SD_ENA_GET(x)\
3392         FIELD_GET(DEV2G5_PCS1G_SD_CFG_SD_ENA, x)
3393
3394 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */
3395 #define DEV2G5_PCS1G_ANEG_CFG(t)                                               \
3396         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 12, 0, 1,\
3397               4)
3398
3399 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY        GENMASK(31, 16)
3400 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x)\
3401         FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
3402 #define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x)\
3403         FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)
3404
3405 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA     BIT(8)
3406 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x)\
3407         FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
3408 #define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x)\
3409         FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)
3410
3411 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)
3412 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x)\
3413         FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
3414 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x)\
3415         FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)
3416
3417 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA           BIT(0)
3418 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x)\
3419         FIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
3420 #define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x)\
3421         FIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)
3422
3423 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LB_CFG */
3424 #define DEV2G5_PCS1G_LB_CFG(t)                                                 \
3425         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 20, 0, 1,\
3426               4)
3427
3428 #define DEV2G5_PCS1G_LB_CFG_RA_ENA               BIT(4)
3429 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_SET(x)\
3430         FIELD_PREP(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
3431 #define DEV2G5_PCS1G_LB_CFG_RA_ENA_GET(x)\
3432         FIELD_GET(DEV2G5_PCS1G_LB_CFG_RA_ENA, x)
3433
3434 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA      BIT(1)
3435 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_SET(x)\
3436         FIELD_PREP(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
3437 #define DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA_GET(x)\
3438         FIELD_GET(DEV2G5_PCS1G_LB_CFG_GMII_PHY_LB_ENA, x)
3439
3440 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA      BIT(0)
3441 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_SET(x)\
3442         FIELD_PREP(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
3443 #define DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA_GET(x)\
3444         FIELD_GET(DEV2G5_PCS1G_LB_CFG_TBI_HOST_LB_ENA, x)
3445
3446 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */
3447 #define DEV2G5_PCS1G_ANEG_STATUS(t)                                            \
3448         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 32, 0, 1,\
3449               4)
3450
3451 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY  GENMASK(31, 16)
3452 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_SET(x)\
3453         FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
3454 #define DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY_GET(x)\
3455         FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_LP_ADV_ABILITY, x)
3456
3457 #define DEV2G5_PCS1G_ANEG_STATUS_PR              BIT(4)
3458 #define DEV2G5_PCS1G_ANEG_STATUS_PR_SET(x)\
3459         FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
3460 #define DEV2G5_PCS1G_ANEG_STATUS_PR_GET(x)\
3461         FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PR, x)
3462
3463 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY  BIT(3)
3464 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_SET(x)\
3465         FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
3466 #define DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY_GET(x)\
3467         FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_PAGE_RX_STICKY, x)
3468
3469 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE   BIT(0)
3470 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x)\
3471         FIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
3472 #define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x)\
3473         FIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)
3474
3475 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */
3476 #define DEV2G5_PCS1G_LINK_STATUS(t)                                            \
3477         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 40, 0, 1,\
3478               4)
3479
3480 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR       GENMASK(15, 12)
3481 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_SET(x)\
3482         FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
3483 #define DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR_GET(x)\
3484         FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_DELAY_VAR, x)
3485
3486 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT   BIT(8)
3487 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_SET(x)\
3488         FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
3489 #define DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT_GET(x)\
3490         FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SIGNAL_DETECT, x)
3491
3492 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS     BIT(4)
3493 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x)\
3494         FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
3495 #define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x)\
3496         FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)
3497
3498 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS     BIT(0)
3499 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_SET(x)\
3500         FIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
3501 #define DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS_GET(x)\
3502         FIELD_GET(DEV2G5_PCS1G_LINK_STATUS_SYNC_STATUS, x)
3503
3504 /* DEV1G:PCS1G_CFG_STATUS:PCS1G_STICKY */
3505 #define DEV2G5_PCS1G_STICKY(t)                                                 \
3506         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 88, 0, 1, 68, 48, 0, 1,\
3507               4)
3508
3509 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY     BIT(4)
3510 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_SET(x)\
3511         FIELD_PREP(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
3512 #define DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(x)\
3513         FIELD_GET(DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY, x)
3514
3515 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY   BIT(0)
3516 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_SET(x)\
3517         FIELD_PREP(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
3518 #define DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY_GET(x)\
3519         FIELD_GET(DEV2G5_PCS1G_STICKY_OUT_OF_SYNC_STICKY, x)
3520
3521 /* DEV1G:PCS_FX100_CONFIGURATION:PCS_FX100_CFG */
3522 #define DEV2G5_PCS_FX100_CFG(t)                                                \
3523         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 164, 0, 1, 4, 0, 0, 1, \
3524               4)
3525
3526 #define DEV2G5_PCS_FX100_CFG_SD_SEL              BIT(26)
3527 #define DEV2G5_PCS_FX100_CFG_SD_SEL_SET(x)\
3528         FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
3529 #define DEV2G5_PCS_FX100_CFG_SD_SEL_GET(x)\
3530         FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_SEL, x)
3531
3532 #define DEV2G5_PCS_FX100_CFG_SD_POL              BIT(25)
3533 #define DEV2G5_PCS_FX100_CFG_SD_POL_SET(x)\
3534         FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_POL, x)
3535 #define DEV2G5_PCS_FX100_CFG_SD_POL_GET(x)\
3536         FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_POL, x)
3537
3538 #define DEV2G5_PCS_FX100_CFG_SD_ENA              BIT(24)
3539 #define DEV2G5_PCS_FX100_CFG_SD_ENA_SET(x)\
3540         FIELD_PREP(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
3541 #define DEV2G5_PCS_FX100_CFG_SD_ENA_GET(x)\
3542         FIELD_GET(DEV2G5_PCS_FX100_CFG_SD_ENA, x)
3543
3544 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA        BIT(20)
3545 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_SET(x)\
3546         FIELD_PREP(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
3547 #define DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA_GET(x)\
3548         FIELD_GET(DEV2G5_PCS_FX100_CFG_LOOPBACK_ENA, x)
3549
3550 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA        BIT(16)
3551 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_SET(x)\
3552         FIELD_PREP(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
3553 #define DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA_GET(x)\
3554         FIELD_GET(DEV2G5_PCS_FX100_CFG_SWAP_MII_ENA, x)
3555
3556 #define DEV2G5_PCS_FX100_CFG_RXBITSEL            GENMASK(15, 12)
3557 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_SET(x)\
3558         FIELD_PREP(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
3559 #define DEV2G5_PCS_FX100_CFG_RXBITSEL_GET(x)\
3560         FIELD_GET(DEV2G5_PCS_FX100_CFG_RXBITSEL, x)
3561
3562 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG          GENMASK(10, 9)
3563 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_SET(x)\
3564         FIELD_PREP(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
3565 #define DEV2G5_PCS_FX100_CFG_SIGDET_CFG_GET(x)\
3566         FIELD_GET(DEV2G5_PCS_FX100_CFG_SIGDET_CFG, x)
3567
3568 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA     BIT(8)
3569 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_SET(x)\
3570         FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
3571 #define DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA_GET(x)\
3572         FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYST_TM_ENA, x)
3573
3574 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER       GENMASK(7, 4)
3575 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_SET(x)\
3576         FIELD_PREP(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
3577 #define DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER_GET(x)\
3578         FIELD_GET(DEV2G5_PCS_FX100_CFG_LINKHYSTTIMER, x)
3579
3580 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA     BIT(3)
3581 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_SET(x)\
3582         FIELD_PREP(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
3583 #define DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA_GET(x)\
3584         FIELD_GET(DEV2G5_PCS_FX100_CFG_UNIDIR_MODE_ENA, x)
3585
3586 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA          BIT(2)
3587 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_SET(x)\
3588         FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
3589 #define DEV2G5_PCS_FX100_CFG_FEFCHK_ENA_GET(x)\
3590         FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFCHK_ENA, x)
3591
3592 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA          BIT(1)
3593 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_SET(x)\
3594         FIELD_PREP(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
3595 #define DEV2G5_PCS_FX100_CFG_FEFGEN_ENA_GET(x)\
3596         FIELD_GET(DEV2G5_PCS_FX100_CFG_FEFGEN_ENA, x)
3597
3598 #define DEV2G5_PCS_FX100_CFG_PCS_ENA             BIT(0)
3599 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_SET(x)\
3600         FIELD_PREP(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
3601 #define DEV2G5_PCS_FX100_CFG_PCS_ENA_GET(x)\
3602         FIELD_GET(DEV2G5_PCS_FX100_CFG_PCS_ENA, x)
3603
3604 /* DEV1G:PCS_FX100_STATUS:PCS_FX100_STATUS */
3605 #define DEV2G5_PCS_FX100_STATUS(t)                                             \
3606         __REG(TARGET_DEV2G5, t, regs->tsize[TC_DEV2G5], 168, 0, 1, 4, 0, 0, 1, \
3607               4)
3608
3609 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP     GENMASK(11, 8)
3610 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_SET(x)\
3611         FIELD_PREP(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
3612 #define DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP_GET(x)\
3613         FIELD_GET(DEV2G5_PCS_FX100_STATUS_EDGE_POS_PTP, x)
3614
3615 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY BIT(7)
3616 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_SET(x)\
3617         FIELD_PREP(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
3618 #define DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY_GET(x)\
3619         FIELD_GET(DEV2G5_PCS_FX100_STATUS_PCS_ERROR_STICKY, x)
3620
3621 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY BIT(6)
3622 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_SET(x)\
3623         FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
3624 #define DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY_GET(x)\
3625         FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_FOUND_STICKY, x)
3626
3627 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY BIT(5)
3628 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_SET(x)\
3629         FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
3630 #define DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY_GET(x)\
3631         FIELD_GET(DEV2G5_PCS_FX100_STATUS_SSD_ERROR_STICKY, x)
3632
3633 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY BIT(4)
3634 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_SET(x)\
3635         FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
3636 #define DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY_GET(x)\
3637         FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_LOST_STICKY, x)
3638
3639 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS       BIT(2)
3640 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_SET(x)\
3641         FIELD_PREP(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
3642 #define DEV2G5_PCS_FX100_STATUS_FEF_STATUS_GET(x)\
3643         FIELD_GET(DEV2G5_PCS_FX100_STATUS_FEF_STATUS, x)
3644
3645 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT    BIT(1)
3646 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_SET(x)\
3647         FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
3648 #define DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT_GET(x)\
3649         FIELD_GET(DEV2G5_PCS_FX100_STATUS_SIGNAL_DETECT, x)
3650
3651 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS      BIT(0)
3652 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_SET(x)\
3653         FIELD_PREP(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
3654 #define DEV2G5_PCS_FX100_STATUS_SYNC_STATUS_GET(x)\
3655         FIELD_GET(DEV2G5_PCS_FX100_STATUS_SYNC_STATUS, x)
3656
3657 /* DEV10G:MAC_CFG_STATUS:MAC_ENA_CFG */
3658 #define DEV5G_MAC_ENA_CFG(t)                                                   \
3659         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 0, 0, 1, 4)
3660
3661 #define DEV5G_MAC_ENA_CFG_RX_ENA                 BIT(4)
3662 #define DEV5G_MAC_ENA_CFG_RX_ENA_SET(x)\
3663         FIELD_PREP(DEV5G_MAC_ENA_CFG_RX_ENA, x)
3664 #define DEV5G_MAC_ENA_CFG_RX_ENA_GET(x)\
3665         FIELD_GET(DEV5G_MAC_ENA_CFG_RX_ENA, x)
3666
3667 #define DEV5G_MAC_ENA_CFG_TX_ENA                 BIT(0)
3668 #define DEV5G_MAC_ENA_CFG_TX_ENA_SET(x)\
3669         FIELD_PREP(DEV5G_MAC_ENA_CFG_TX_ENA, x)
3670 #define DEV5G_MAC_ENA_CFG_TX_ENA_GET(x)\
3671         FIELD_GET(DEV5G_MAC_ENA_CFG_TX_ENA, x)
3672
3673 /* DEV10G:MAC_CFG_STATUS:MAC_MAXLEN_CFG */
3674 #define DEV5G_MAC_MAXLEN_CFG(t)                                                \
3675         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 8, 0, 1, 4)
3676
3677 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK     BIT(16)
3678 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_SET(x)\
3679         FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
3680 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK_GET(x)\
3681         FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN_TAG_CHK, x)
3682
3683 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN             GENMASK(15, 0)
3684 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_SET(x)\
3685         FIELD_PREP(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
3686 #define DEV5G_MAC_MAXLEN_CFG_MAX_LEN_GET(x)\
3687         FIELD_GET(DEV5G_MAC_MAXLEN_CFG_MAX_LEN, x)
3688
3689 /* DEV10G:MAC_CFG_STATUS:MAC_ADV_CHK_CFG */
3690 #define DEV5G_MAC_ADV_CHK_CFG(t)                                               \
3691         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 0, 0, 1, 60, 28, 0, 1,   \
3692               4)
3693
3694 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA    BIT(24)
3695 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_SET(x)\
3696         FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
3697 #define DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA_GET(x)\
3698         FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_EOP_CHK_ENA, x)
3699
3700 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA    BIT(20)
3701 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_SET(x)\
3702         FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
3703 #define DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA_GET(x)\
3704         FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_EXT_SOP_CHK_ENA, x)
3705
3706 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA        BIT(16)
3707 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_SET(x)\
3708         FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
3709 #define DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA_GET(x)\
3710         FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_SFD_CHK_ENA, x)
3711
3712 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS    BIT(12)
3713 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_SET(x)\
3714         FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
3715 #define DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS_GET(x)\
3716         FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_SHK_CHK_DIS, x)
3717
3718 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA        BIT(8)
3719 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_SET(x)\
3720         FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
3721 #define DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA_GET(x)\
3722         FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_PRM_CHK_ENA, x)
3723
3724 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA        BIT(4)
3725 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_SET(x)\
3726         FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3727 #define DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA_GET(x)\
3728         FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_OOR_ERR_ENA, x)
3729
3730 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA        BIT(0)
3731 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_SET(x)\
3732         FIELD_PREP(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3733 #define DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA_GET(x)\
3734         FIELD_GET(DEV5G_MAC_ADV_CHK_CFG_INR_ERR_ENA, x)
3735
3736 /* DEV10G:DEV_STATISTICS_32BIT:RX_SYMBOL_ERR_CNT */
3737 #define DEV5G_RX_SYMBOL_ERR_CNT(t)                                             \
3738         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 0, 0, 1,  \
3739               4)
3740
3741 /* DEV10G:DEV_STATISTICS_32BIT:RX_PAUSE_CNT */
3742 #define DEV5G_RX_PAUSE_CNT(t)                                                  \
3743         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 4, 0, 1,  \
3744               4)
3745
3746 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNSUP_OPCODE_CNT */
3747 #define DEV5G_RX_UNSUP_OPCODE_CNT(t)                                           \
3748         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 8, 0, 1,  \
3749               4)
3750
3751 /* DEV10G:DEV_STATISTICS_32BIT:RX_UC_CNT */
3752 #define DEV5G_RX_UC_CNT(t)                                                     \
3753         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 12, 0, 1, \
3754               4)
3755
3756 /* DEV10G:DEV_STATISTICS_32BIT:RX_MC_CNT */
3757 #define DEV5G_RX_MC_CNT(t)                                                     \
3758         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 16, 0, 1, \
3759               4)
3760
3761 /* DEV10G:DEV_STATISTICS_32BIT:RX_BC_CNT */
3762 #define DEV5G_RX_BC_CNT(t)                                                     \
3763         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 20, 0, 1, \
3764               4)
3765
3766 /* DEV10G:DEV_STATISTICS_32BIT:RX_CRC_ERR_CNT */
3767 #define DEV5G_RX_CRC_ERR_CNT(t)                                                \
3768         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 24, 0, 1, \
3769               4)
3770
3771 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNDERSIZE_CNT */
3772 #define DEV5G_RX_UNDERSIZE_CNT(t)                                              \
3773         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 28, 0, 1, \
3774               4)
3775
3776 /* DEV10G:DEV_STATISTICS_32BIT:RX_FRAGMENTS_CNT */
3777 #define DEV5G_RX_FRAGMENTS_CNT(t)                                              \
3778         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 32, 0, 1, \
3779               4)
3780
3781 /* DEV10G:DEV_STATISTICS_32BIT:RX_IN_RANGE_LEN_ERR_CNT */
3782 #define DEV5G_RX_IN_RANGE_LEN_ERR_CNT(t)                                       \
3783         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 36, 0, 1, \
3784               4)
3785
3786 /* DEV10G:DEV_STATISTICS_32BIT:RX_OUT_OF_RANGE_LEN_ERR_CNT */
3787 #define DEV5G_RX_OUT_OF_RANGE_LEN_ERR_CNT(t)                                   \
3788         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 40, 0, 1, \
3789               4)
3790
3791 /* DEV10G:DEV_STATISTICS_32BIT:RX_OVERSIZE_CNT */
3792 #define DEV5G_RX_OVERSIZE_CNT(t)                                               \
3793         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 44, 0, 1, \
3794               4)
3795
3796 /* DEV10G:DEV_STATISTICS_32BIT:RX_JABBERS_CNT */
3797 #define DEV5G_RX_JABBERS_CNT(t)                                                \
3798         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 48, 0, 1, \
3799               4)
3800
3801 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE64_CNT */
3802 #define DEV5G_RX_SIZE64_CNT(t)                                                 \
3803         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 52, 0, 1, \
3804               4)
3805
3806 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE65TO127_CNT */
3807 #define DEV5G_RX_SIZE65TO127_CNT(t)                                            \
3808         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 56, 0, 1, \
3809               4)
3810
3811 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE128TO255_CNT */
3812 #define DEV5G_RX_SIZE128TO255_CNT(t)                                           \
3813         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 60, 0, 1, \
3814               4)
3815
3816 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE256TO511_CNT */
3817 #define DEV5G_RX_SIZE256TO511_CNT(t)                                           \
3818         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 64, 0, 1, \
3819               4)
3820
3821 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE512TO1023_CNT */
3822 #define DEV5G_RX_SIZE512TO1023_CNT(t)                                          \
3823         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 68, 0, 1, \
3824               4)
3825
3826 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1024TO1518_CNT */
3827 #define DEV5G_RX_SIZE1024TO1518_CNT(t)                                         \
3828         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 72, 0, 1, \
3829               4)
3830
3831 /* DEV10G:DEV_STATISTICS_32BIT:RX_SIZE1519TOMAX_CNT */
3832 #define DEV5G_RX_SIZE1519TOMAX_CNT(t)                                          \
3833         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 76, 0, 1, \
3834               4)
3835
3836 /* DEV10G:DEV_STATISTICS_32BIT:RX_IPG_SHRINK_CNT */
3837 #define DEV5G_RX_IPG_SHRINK_CNT(t)                                             \
3838         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 80, 0, 1, \
3839               4)
3840
3841 /* DEV10G:DEV_STATISTICS_32BIT:TX_PAUSE_CNT */
3842 #define DEV5G_TX_PAUSE_CNT(t)                                                  \
3843         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 84, 0, 1, \
3844               4)
3845
3846 /* DEV10G:DEV_STATISTICS_32BIT:TX_UC_CNT */
3847 #define DEV5G_TX_UC_CNT(t)                                                     \
3848         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 88, 0, 1, \
3849               4)
3850
3851 /* DEV10G:DEV_STATISTICS_32BIT:TX_MC_CNT */
3852 #define DEV5G_TX_MC_CNT(t)                                                     \
3853         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 92, 0, 1, \
3854               4)
3855
3856 /* DEV10G:DEV_STATISTICS_32BIT:TX_BC_CNT */
3857 #define DEV5G_TX_BC_CNT(t)                                                     \
3858         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 96, 0, 1, \
3859               4)
3860
3861 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE64_CNT */
3862 #define DEV5G_TX_SIZE64_CNT(t)                                                 \
3863         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 100, 0, 1,\
3864               4)
3865
3866 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE65TO127_CNT */
3867 #define DEV5G_TX_SIZE65TO127_CNT(t)                                            \
3868         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 104, 0, 1,\
3869               4)
3870
3871 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE128TO255_CNT */
3872 #define DEV5G_TX_SIZE128TO255_CNT(t)                                           \
3873         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 108, 0, 1,\
3874               4)
3875
3876 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE256TO511_CNT */
3877 #define DEV5G_TX_SIZE256TO511_CNT(t)                                           \
3878         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 112, 0, 1,\
3879               4)
3880
3881 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE512TO1023_CNT */
3882 #define DEV5G_TX_SIZE512TO1023_CNT(t)                                          \
3883         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 116, 0, 1,\
3884               4)
3885
3886 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1024TO1518_CNT */
3887 #define DEV5G_TX_SIZE1024TO1518_CNT(t)                                         \
3888         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 120, 0, 1,\
3889               4)
3890
3891 /* DEV10G:DEV_STATISTICS_32BIT:TX_SIZE1519TOMAX_CNT */
3892 #define DEV5G_TX_SIZE1519TOMAX_CNT(t)                                          \
3893         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 124, 0, 1,\
3894               4)
3895
3896 /* DEV10G:DEV_STATISTICS_32BIT:RX_ALIGNMENT_LOST_CNT */
3897 #define DEV5G_RX_ALIGNMENT_LOST_CNT(t)                                         \
3898         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 128, 0, 1,\
3899               4)
3900
3901 /* DEV10G:DEV_STATISTICS_32BIT:RX_TAGGED_FRMS_CNT */
3902 #define DEV5G_RX_TAGGED_FRMS_CNT(t)                                            \
3903         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 132, 0, 1,\
3904               4)
3905
3906 /* DEV10G:DEV_STATISTICS_32BIT:RX_UNTAGGED_FRMS_CNT */
3907 #define DEV5G_RX_UNTAGGED_FRMS_CNT(t)                                          \
3908         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 136, 0, 1,\
3909               4)
3910
3911 /* DEV10G:DEV_STATISTICS_32BIT:TX_TAGGED_FRMS_CNT */
3912 #define DEV5G_TX_TAGGED_FRMS_CNT(t)                                            \
3913         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 140, 0, 1,\
3914               4)
3915
3916 /* DEV10G:DEV_STATISTICS_32BIT:TX_UNTAGGED_FRMS_CNT */
3917 #define DEV5G_TX_UNTAGGED_FRMS_CNT(t)                                          \
3918         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 144, 0, 1,\
3919               4)
3920
3921 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SYMBOL_ERR_CNT */
3922 #define DEV5G_PMAC_RX_SYMBOL_ERR_CNT(t)                                        \
3923         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 148, 0, 1,\
3924               4)
3925
3926 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_PAUSE_CNT */
3927 #define DEV5G_PMAC_RX_PAUSE_CNT(t)                                             \
3928         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 152, 0, 1,\
3929               4)
3930
3931 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNSUP_OPCODE_CNT */
3932 #define DEV5G_PMAC_RX_UNSUP_OPCODE_CNT(t)                                      \
3933         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 156, 0, 1,\
3934               4)
3935
3936 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UC_CNT */
3937 #define DEV5G_PMAC_RX_UC_CNT(t)                                                \
3938         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 160, 0, 1,\
3939               4)
3940
3941 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_MC_CNT */
3942 #define DEV5G_PMAC_RX_MC_CNT(t)                                                \
3943         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 164, 0, 1,\
3944               4)
3945
3946 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_BC_CNT */
3947 #define DEV5G_PMAC_RX_BC_CNT(t)                                                \
3948         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 168, 0, 1,\
3949               4)
3950
3951 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_CRC_ERR_CNT */
3952 #define DEV5G_PMAC_RX_CRC_ERR_CNT(t)                                           \
3953         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 172, 0, 1,\
3954               4)
3955
3956 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_UNDERSIZE_CNT */
3957 #define DEV5G_PMAC_RX_UNDERSIZE_CNT(t)                                         \
3958         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 176, 0, 1,\
3959               4)
3960
3961 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_FRAGMENTS_CNT */
3962 #define DEV5G_PMAC_RX_FRAGMENTS_CNT(t)                                         \
3963         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 180, 0, 1,\
3964               4)
3965
3966 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_IN_RANGE_LEN_ERR_CNT */
3967 #define DEV5G_PMAC_RX_IN_RANGE_LEN_ERR_CNT(t)                                  \
3968         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 184, 0, 1,\
3969               4)
3970
3971 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT */
3972 #define DEV5G_PMAC_RX_OUT_OF_RANGE_LEN_ERR_CNT(t)                              \
3973         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 188, 0, 1,\
3974               4)
3975
3976 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_OVERSIZE_CNT */
3977 #define DEV5G_PMAC_RX_OVERSIZE_CNT(t)                                          \
3978         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 192, 0, 1,\
3979               4)
3980
3981 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_JABBERS_CNT */
3982 #define DEV5G_PMAC_RX_JABBERS_CNT(t)                                           \
3983         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 196, 0, 1,\
3984               4)
3985
3986 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE64_CNT */
3987 #define DEV5G_PMAC_RX_SIZE64_CNT(t)                                            \
3988         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 200, 0, 1,\
3989               4)
3990
3991 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE65TO127_CNT */
3992 #define DEV5G_PMAC_RX_SIZE65TO127_CNT(t)                                       \
3993         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 204, 0, 1,\
3994               4)
3995
3996 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE128TO255_CNT */
3997 #define DEV5G_PMAC_RX_SIZE128TO255_CNT(t)                                      \
3998         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 208, 0, 1,\
3999               4)
4000
4001 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE256TO511_CNT */
4002 #define DEV5G_PMAC_RX_SIZE256TO511_CNT(t)                                      \
4003         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 212, 0, 1,\
4004               4)
4005
4006 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE512TO1023_CNT */
4007 #define DEV5G_PMAC_RX_SIZE512TO1023_CNT(t)                                     \
4008         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 216, 0, 1,\
4009               4)
4010
4011 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1024TO1518_CNT */
4012 #define DEV5G_PMAC_RX_SIZE1024TO1518_CNT(t)                                    \
4013         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 220, 0, 1,\
4014               4)
4015
4016 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_SIZE1519TOMAX_CNT */
4017 #define DEV5G_PMAC_RX_SIZE1519TOMAX_CNT(t)                                     \
4018         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 224, 0, 1,\
4019               4)
4020
4021 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_PAUSE_CNT */
4022 #define DEV5G_PMAC_TX_PAUSE_CNT(t)                                             \
4023         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 228, 0, 1,\
4024               4)
4025
4026 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_UC_CNT */
4027 #define DEV5G_PMAC_TX_UC_CNT(t)                                                \
4028         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 232, 0, 1,\
4029               4)
4030
4031 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_MC_CNT */
4032 #define DEV5G_PMAC_TX_MC_CNT(t)                                                \
4033         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 236, 0, 1,\
4034               4)
4035
4036 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_BC_CNT */
4037 #define DEV5G_PMAC_TX_BC_CNT(t)                                                \
4038         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 240, 0, 1,\
4039               4)
4040
4041 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE64_CNT */
4042 #define DEV5G_PMAC_TX_SIZE64_CNT(t)                                            \
4043         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 244, 0, 1,\
4044               4)
4045
4046 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE65TO127_CNT */
4047 #define DEV5G_PMAC_TX_SIZE65TO127_CNT(t)                                       \
4048         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 248, 0, 1,\
4049               4)
4050
4051 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE128TO255_CNT */
4052 #define DEV5G_PMAC_TX_SIZE128TO255_CNT(t)                                      \
4053         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 252, 0, 1,\
4054               4)
4055
4056 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE256TO511_CNT */
4057 #define DEV5G_PMAC_TX_SIZE256TO511_CNT(t)                                      \
4058         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 256, 0, 1,\
4059               4)
4060
4061 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE512TO1023_CNT */
4062 #define DEV5G_PMAC_TX_SIZE512TO1023_CNT(t)                                     \
4063         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 260, 0, 1,\
4064               4)
4065
4066 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1024TO1518_CNT */
4067 #define DEV5G_PMAC_TX_SIZE1024TO1518_CNT(t)                                    \
4068         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 264, 0, 1,\
4069               4)
4070
4071 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_TX_SIZE1519TOMAX_CNT */
4072 #define DEV5G_PMAC_TX_SIZE1519TOMAX_CNT(t)                                     \
4073         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 268, 0, 1,\
4074               4)
4075
4076 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_ALIGNMENT_LOST_CNT */
4077 #define DEV5G_PMAC_RX_ALIGNMENT_LOST_CNT(t)                                    \
4078         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 272, 0, 1,\
4079               4)
4080
4081 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_ERR_CNT */
4082 #define DEV5G_MM_RX_ASSEMBLY_ERR_CNT(t)                                        \
4083         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 276, 0, 1,\
4084               4)
4085
4086 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_SMD_ERR_CNT */
4087 #define DEV5G_MM_RX_SMD_ERR_CNT(t)                                             \
4088         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 280, 0, 1,\
4089               4)
4090
4091 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_ASSEMBLY_OK_CNT */
4092 #define DEV5G_MM_RX_ASSEMBLY_OK_CNT(t)                                         \
4093         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 284, 0, 1,\
4094               4)
4095
4096 /* DEV10G:DEV_STATISTICS_32BIT:MM_RX_MERGE_FRAG_CNT */
4097 #define DEV5G_MM_RX_MERGE_FRAG_CNT(t)                                          \
4098         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 288, 0, 1,\
4099               4)
4100
4101 /* DEV10G:DEV_STATISTICS_32BIT:MM_TX_PFRAGMENT_CNT */
4102 #define DEV5G_MM_TX_PFRAGMENT_CNT(t)                                           \
4103         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 292, 0, 1,\
4104               4)
4105
4106 /* DEV10G:DEV_STATISTICS_32BIT:RX_HIH_CKSM_ERR_CNT */
4107 #define DEV5G_RX_HIH_CKSM_ERR_CNT(t)                                           \
4108         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 296, 0, 1,\
4109               4)
4110
4111 /* DEV10G:DEV_STATISTICS_32BIT:RX_XGMII_PROT_ERR_CNT */
4112 #define DEV5G_RX_XGMII_PROT_ERR_CNT(t)                                         \
4113         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 300, 0, 1,\
4114               4)
4115
4116 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_HIH_CKSM_ERR_CNT */
4117 #define DEV5G_PMAC_RX_HIH_CKSM_ERR_CNT(t)                                      \
4118         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 304, 0, 1,\
4119               4)
4120
4121 /* DEV10G:DEV_STATISTICS_32BIT:PMAC_RX_XGMII_PROT_ERR_CNT */
4122 #define DEV5G_PMAC_RX_XGMII_PROT_ERR_CNT(t)                                    \
4123         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 60, 0, 1, 312, 308, 0, 1,\
4124               4)
4125
4126 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_CNT */
4127 #define DEV5G_RX_IN_BYTES_CNT(t)                                               \
4128         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 0, 0, 1,  \
4129               4)
4130
4131 /* DEV10G:DEV_STATISTICS_40BIT:RX_IN_BYTES_MSB_CNT */
4132 #define DEV5G_RX_IN_BYTES_MSB_CNT(t)                                           \
4133         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 4, 0, 1,  \
4134               4)
4135
4136 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT GENMASK(7, 0)
4137 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_SET(x)\
4138         FIELD_PREP(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
4139 #define DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT_GET(x)\
4140         FIELD_GET(DEV5G_RX_IN_BYTES_MSB_CNT_RX_IN_BYTES_MSB_CNT, x)
4141
4142 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_CNT */
4143 #define DEV5G_RX_OK_BYTES_CNT(t)                                               \
4144         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 8, 0, 1,  \
4145               4)
4146
4147 /* DEV10G:DEV_STATISTICS_40BIT:RX_OK_BYTES_MSB_CNT */
4148 #define DEV5G_RX_OK_BYTES_MSB_CNT(t)                                           \
4149         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 12, 0, 1, \
4150               4)
4151
4152 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT GENMASK(7, 0)
4153 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_SET(x)\
4154         FIELD_PREP(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
4155 #define DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT_GET(x)\
4156         FIELD_GET(DEV5G_RX_OK_BYTES_MSB_CNT_RX_OK_BYTES_MSB_CNT, x)
4157
4158 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_CNT */
4159 #define DEV5G_RX_BAD_BYTES_CNT(t)                                              \
4160         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 16, 0, 1, \
4161               4)
4162
4163 /* DEV10G:DEV_STATISTICS_40BIT:RX_BAD_BYTES_MSB_CNT */
4164 #define DEV5G_RX_BAD_BYTES_MSB_CNT(t)                                          \
4165         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 20, 0, 1, \
4166               4)
4167
4168 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0)
4169 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_SET(x)\
4170         FIELD_PREP(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
4171 #define DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT_GET(x)\
4172         FIELD_GET(DEV5G_RX_BAD_BYTES_MSB_CNT_RX_BAD_BYTES_MSB_CNT, x)
4173
4174 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_CNT */
4175 #define DEV5G_TX_OUT_BYTES_CNT(t)                                              \
4176         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 24, 0, 1, \
4177               4)
4178
4179 /* DEV10G:DEV_STATISTICS_40BIT:TX_OUT_BYTES_MSB_CNT */
4180 #define DEV5G_TX_OUT_BYTES_MSB_CNT(t)                                          \
4181         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 28, 0, 1, \
4182               4)
4183
4184 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT GENMASK(7, 0)
4185 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_SET(x)\
4186         FIELD_PREP(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
4187 #define DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT_GET(x)\
4188         FIELD_GET(DEV5G_TX_OUT_BYTES_MSB_CNT_TX_OUT_BYTES_MSB_CNT, x)
4189
4190 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_CNT */
4191 #define DEV5G_TX_OK_BYTES_CNT(t)                                               \
4192         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 32, 0, 1, \
4193               4)
4194
4195 /* DEV10G:DEV_STATISTICS_40BIT:TX_OK_BYTES_MSB_CNT */
4196 #define DEV5G_TX_OK_BYTES_MSB_CNT(t)                                           \
4197         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 36, 0, 1, \
4198               4)
4199
4200 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT GENMASK(7, 0)
4201 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_SET(x)\
4202         FIELD_PREP(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
4203 #define DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT_GET(x)\
4204         FIELD_GET(DEV5G_TX_OK_BYTES_MSB_CNT_TX_OK_BYTES_MSB_CNT, x)
4205
4206 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_CNT */
4207 #define DEV5G_PMAC_RX_OK_BYTES_CNT(t)                                          \
4208         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 40, 0, 1, \
4209               4)
4210
4211 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_OK_BYTES_MSB_CNT */
4212 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT(t)                                      \
4213         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 44, 0, 1, \
4214               4)
4215
4216 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT GENMASK(7, 0)
4217 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_SET(x)\
4218         FIELD_PREP(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
4219 #define DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT_GET(x)\
4220         FIELD_GET(DEV5G_PMAC_RX_OK_BYTES_MSB_CNT_PMAC_RX_OK_BYTES_MSB_CNT, x)
4221
4222 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_CNT */
4223 #define DEV5G_PMAC_RX_BAD_BYTES_CNT(t)                                         \
4224         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 48, 0, 1, \
4225               4)
4226
4227 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_RX_BAD_BYTES_MSB_CNT */
4228 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT(t)                                     \
4229         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 52, 0, 1, \
4230               4)
4231
4232 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT GENMASK(7, 0)
4233 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_SET(x)\
4234         FIELD_PREP(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
4235 #define DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT_GET(x)\
4236         FIELD_GET(DEV5G_PMAC_RX_BAD_BYTES_MSB_CNT_PMAC_RX_BAD_BYTES_MSB_CNT, x)
4237
4238 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_CNT */
4239 #define DEV5G_PMAC_TX_OK_BYTES_CNT(t)                                          \
4240         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 56, 0, 1, \
4241               4)
4242
4243 /* DEV10G:DEV_STATISTICS_40BIT:PMAC_TX_OK_BYTES_MSB_CNT */
4244 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT(t)                                      \
4245         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 372, 0, 1, 64, 60, 0, 1, \
4246               4)
4247
4248 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT GENMASK(7, 0)
4249 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_SET(x)\
4250         FIELD_PREP(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
4251 #define DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT_GET(x)\
4252         FIELD_GET(DEV5G_PMAC_TX_OK_BYTES_MSB_CNT_PMAC_TX_OK_BYTES_MSB_CNT, x)
4253
4254 /* DEV10G:DEV_CFG_STATUS:DEV_RST_CTRL */
4255 #define DEV5G_DEV_RST_CTRL(t)                                                  \
4256         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 0, 0, 1,  \
4257               4)
4258
4259 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA       BIT(28)
4260 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_SET(x)\
4261         FIELD_PREP(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
4262 #define DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA_GET(x)\
4263         FIELD_GET(DEV5G_DEV_RST_CTRL_PARDET_MODE_ENA, x)
4264
4265 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS BIT(27)
4266 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_SET(x)\
4267         FIELD_PREP(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
4268 #define DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS_GET(x)\
4269         FIELD_GET(DEV5G_DEV_RST_CTRL_USXGMII_OSET_FILTER_DIS, x)
4270
4271 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS GENMASK(26, 25)
4272 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_SET(x)\
4273         FIELD_PREP(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
4274 #define DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS_GET(x)\
4275         FIELD_GET(DEV5G_DEV_RST_CTRL_MUXED_USXGMII_NETWORK_PORTS, x)
4276
4277 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL      GENMASK(24, 23)
4278 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_SET(x)\
4279         FIELD_PREP(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
4280 #define DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL_GET(x)\
4281         FIELD_GET(DEV5G_DEV_RST_CTRL_SERDES_SPEED_SEL, x)
4282
4283 #define DEV5G_DEV_RST_CTRL_SPEED_SEL             GENMASK(22, 20)
4284 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_SET(x)\
4285         FIELD_PREP(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
4286 #define DEV5G_DEV_RST_CTRL_SPEED_SEL_GET(x)\
4287         FIELD_GET(DEV5G_DEV_RST_CTRL_SPEED_SEL, x)
4288
4289 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST            BIT(12)
4290 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_SET(x)\
4291         FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
4292 #define DEV5G_DEV_RST_CTRL_PCS_TX_RST_GET(x)\
4293         FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_TX_RST, x)
4294
4295 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST            BIT(8)
4296 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_SET(x)\
4297         FIELD_PREP(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
4298 #define DEV5G_DEV_RST_CTRL_PCS_RX_RST_GET(x)\
4299         FIELD_GET(DEV5G_DEV_RST_CTRL_PCS_RX_RST, x)
4300
4301 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST            BIT(4)
4302 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_SET(x)\
4303         FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
4304 #define DEV5G_DEV_RST_CTRL_MAC_TX_RST_GET(x)\
4305         FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_TX_RST, x)
4306
4307 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST            BIT(0)
4308 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_SET(x)\
4309         FIELD_PREP(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
4310 #define DEV5G_DEV_RST_CTRL_MAC_RX_RST_GET(x)\
4311         FIELD_GET(DEV5G_DEV_RST_CTRL_MAC_RX_RST, x)
4312
4313 /* DEV10G:DEV_CFG_STATUS:PTP_STAMPER_CFG */
4314 #define DEV5G_PTP_STAMPER_CFG(t)                                               \
4315         __REG(TARGET_DEV5G, t, regs->tsize[TC_DEV5G], 436, 0, 1, 52, 20, 0, 1, \
4316               4)
4317
4318 /* DSM:RAM_CTRL:RAM_INIT */
4319 #define DSM_RAM_INIT                                                           \
4320         __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)
4321
4322 #define DSM_RAM_INIT_RAM_INIT                    BIT(1)
4323 #define DSM_RAM_INIT_RAM_INIT_SET(x)\
4324         FIELD_PREP(DSM_RAM_INIT_RAM_INIT, x)
4325 #define DSM_RAM_INIT_RAM_INIT_GET(x)\
4326         FIELD_GET(DSM_RAM_INIT_RAM_INIT, x)
4327
4328 #define DSM_RAM_INIT_RAM_CFG_HOOK                BIT(0)
4329 #define DSM_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4330         FIELD_PREP(DSM_RAM_INIT_RAM_CFG_HOOK, x)
4331 #define DSM_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4332         FIELD_GET(DSM_RAM_INIT_RAM_CFG_HOOK, x)
4333
4334 /* DSM:CFG:BUF_CFG */
4335 #define DSM_BUF_CFG(r)                                                         \
4336         __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 0, r,                          \
4337               regs->rcnt[RC_DSM_BUF_CFG], 4)
4338
4339 #define DSM_BUF_CFG_CSC_STAT_DIS                 BIT(13)
4340 #define DSM_BUF_CFG_CSC_STAT_DIS_SET(x)\
4341         FIELD_PREP(DSM_BUF_CFG_CSC_STAT_DIS, x)
4342 #define DSM_BUF_CFG_CSC_STAT_DIS_GET(x)\
4343         FIELD_GET(DSM_BUF_CFG_CSC_STAT_DIS, x)
4344
4345 #define DSM_BUF_CFG_AGING_ENA                    BIT(12)
4346 #define DSM_BUF_CFG_AGING_ENA_SET(x)\
4347         FIELD_PREP(DSM_BUF_CFG_AGING_ENA, x)
4348 #define DSM_BUF_CFG_AGING_ENA_GET(x)\
4349         FIELD_GET(DSM_BUF_CFG_AGING_ENA, x)
4350
4351 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS       BIT(11)
4352 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_SET(x)\
4353         FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
4354 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS_GET(x)\
4355         FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_DIS, x)
4356
4357 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT   GENMASK(10, 0)
4358 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_SET(x)\
4359         FIELD_PREP(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
4360 #define DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT_GET(x)\
4361         FIELD_GET(DSM_BUF_CFG_UNDERFLOW_WATCHDOG_TIMEOUT, x)
4362
4363 /* DSM:CFG:DEV_TX_STOP_WM_CFG */
4364 #define DSM_DEV_TX_STOP_WM_CFG(r)                                              \
4365         __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r,                       \
4366               regs->rcnt[RC_DSM_DEV_TX_STOP_WM_CFG], 4)
4367
4368 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA  BIT(9)
4369 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_SET(x)\
4370         FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
4371 #define DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA_GET(x)\
4372         FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_FAST_STARTUP_ENA, x)
4373
4374 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8)
4375 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x)\
4376         FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
4377 #define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x)\
4378         FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)
4379
4380 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM    GENMASK(7, 1)
4381 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_SET(x)\
4382         FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
4383 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM_GET(x)\
4384         FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_STOP_WM, x)
4385
4386 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR    BIT(0)
4387 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_SET(x)\
4388         FIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
4389 #define DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR_GET(x)\
4390         FIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV_TX_CNT_CLR, x)
4391
4392 /* DSM:CFG:RX_PAUSE_CFG */
4393 #define DSM_RX_PAUSE_CFG(r)                                                    \
4394         __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1628, r,                       \
4395               regs->rcnt[RC_DSM_RX_PAUSE_CFG], 4)
4396
4397 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN             BIT(1)
4398 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_SET(x)\
4399         FIELD_PREP(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
4400 #define DSM_RX_PAUSE_CFG_RX_PAUSE_EN_GET(x)\
4401         FIELD_GET(DSM_RX_PAUSE_CFG_RX_PAUSE_EN, x)
4402
4403 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL           BIT(0)
4404 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_SET(x)\
4405         FIELD_PREP(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
4406 #define DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL_GET(x)\
4407         FIELD_GET(DSM_RX_PAUSE_CFG_FC_OBEY_LOCAL, x)
4408
4409 /* DSM:CFG:MAC_CFG */
4410 #define DSM_MAC_CFG(r)                                                         \
4411         __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2432, r,                       \
4412               regs->rcnt[RC_DSM_MAC_CFG], 4)
4413
4414 #define DSM_MAC_CFG_TX_PAUSE_VAL                 GENMASK(31, 16)
4415 #define DSM_MAC_CFG_TX_PAUSE_VAL_SET(x)\
4416         FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_VAL, x)
4417 #define DSM_MAC_CFG_TX_PAUSE_VAL_GET(x)\
4418         FIELD_GET(DSM_MAC_CFG_TX_PAUSE_VAL, x)
4419
4420 #define DSM_MAC_CFG_HDX_BACKPREASSURE            BIT(2)
4421 #define DSM_MAC_CFG_HDX_BACKPREASSURE_SET(x)\
4422         FIELD_PREP(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
4423 #define DSM_MAC_CFG_HDX_BACKPREASSURE_GET(x)\
4424         FIELD_GET(DSM_MAC_CFG_HDX_BACKPREASSURE, x)
4425
4426 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE         BIT(1)
4427 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_SET(x)\
4428         FIELD_PREP(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
4429 #define DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE_GET(x)\
4430         FIELD_GET(DSM_MAC_CFG_SEND_PAUSE_FRM_TWICE, x)
4431
4432 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF            BIT(0)
4433 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_SET(x)\
4434         FIELD_PREP(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
4435 #define DSM_MAC_CFG_TX_PAUSE_XON_XOFF_GET(x)\
4436         FIELD_GET(DSM_MAC_CFG_TX_PAUSE_XON_XOFF, x)
4437
4438 /* DSM:CFG:MAC_ADDR_BASE_HIGH_CFG */
4439 #define DSM_MAC_ADDR_BASE_HIGH_CFG(r)                                          \
4440         __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2700, r,                       \
4441               regs->rcnt[RC_DSM_MAC_ADDR_BASE_HIGH_CFG], 4)
4442
4443 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH GENMASK(23, 0)
4444 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_SET(x)\
4445         FIELD_PREP(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
4446 #define DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH_GET(x)\
4447         FIELD_GET(DSM_MAC_ADDR_BASE_HIGH_CFG_MAC_ADDR_HIGH, x)
4448
4449 /* DSM:CFG:MAC_ADDR_BASE_LOW_CFG */
4450 #define DSM_MAC_ADDR_BASE_LOW_CFG(r)                                           \
4451         __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 2960, r,                       \
4452               regs->rcnt[RC_DSM_MAC_ADDR_BASE_LOW_CFG], 4)
4453
4454 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW   GENMASK(23, 0)
4455 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_SET(x)\
4456         FIELD_PREP(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
4457 #define DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW_GET(x)\
4458         FIELD_GET(DSM_MAC_ADDR_BASE_LOW_CFG_MAC_ADDR_LOW, x)
4459
4460 /* DSM:CFG:TAXI_CAL_CFG */
4461 #define DSM_TAXI_CAL_CFG(r)                                                    \
4462         __REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r,                       \
4463               regs->rcnt[RC_DSM_TAXI_CAL_CFG], 4)
4464
4465 #define DSM_TAXI_CAL_CFG_CAL_IDX                 GENMASK(20, 15)
4466 #define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\
4467         FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x)
4468 #define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\
4469         FIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x)
4470
4471 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN             GENMASK(14, 9)
4472 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\
4473         FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
4474 #define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\
4475         FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)
4476
4477 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL             GENMASK(8, 5)
4478 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\
4479         FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
4480 #define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\
4481         FIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)
4482
4483 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL             GENMASK(4, 1)
4484 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\
4485         FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
4486 #define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\
4487         FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)
4488
4489 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA             BIT(0)
4490 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\
4491         FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
4492 #define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\
4493         FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)
4494
4495 /* LAN969X ONLY */
4496 #define DSM_TAXI_CAL_CFG_CAL_SEL_STAT            BIT(23)
4497 #define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\
4498         FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)
4499 #define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\
4500         FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)
4501
4502 /* LAN969X ONLY */
4503 #define DSM_TAXI_CAL_CFG_CAL_SWITCH              BIT(22)
4504 #define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\
4505         FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)
4506 #define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\
4507         FIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)
4508
4509 /* LAN969X ONLY */
4510 #define DSM_TAXI_CAL_CFG_CAL_PGM_SEL             BIT(21)
4511 #define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\
4512         FIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)
4513 #define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\
4514         FIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)
4515
4516 /* EACL:ES2_KEY_SELECT_PROFILE:VCAP_ES2_KEY_SEL */
4517 #define EACL_VCAP_ES2_KEY_SEL(g, r)                                            \
4518         __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_KEY_SELECT_PROFILE],  \
4519               g, regs->gcnt[GC_EACL_ES2_KEY_SELECT_PROFILE], 8, 0, r, 2, 4)
4520
4521 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL        GENMASK(7, 5)
4522 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_SET(x)\
4523         FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x)
4524 #define EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL_GET(x)\
4525         FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP6_KEY_SEL, x)
4526
4527 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL        GENMASK(4, 2)
4528 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_SET(x)\
4529         FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x)
4530 #define EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL_GET(x)\
4531         FIELD_GET(EACL_VCAP_ES2_KEY_SEL_IP4_KEY_SEL, x)
4532
4533 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL        BIT(1)
4534 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_SET(x)\
4535         FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x)
4536 #define EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL_GET(x)\
4537         FIELD_GET(EACL_VCAP_ES2_KEY_SEL_ARP_KEY_SEL, x)
4538
4539 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA            BIT(0)
4540 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_SET(x)\
4541         FIELD_PREP(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x)
4542 #define EACL_VCAP_ES2_KEY_SEL_KEY_ENA_GET(x)\
4543         FIELD_GET(EACL_VCAP_ES2_KEY_SEL_KEY_ENA, x)
4544
4545 /* EACL:CNT_TBL:ES2_CNT */
4546 #define EACL_ES2_CNT(g)                                                        \
4547         __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_CNT_TBL], g,              \
4548               regs->gcnt[GC_EACL_CNT_TBL], 4, 0, 0, 1, 4)
4549
4550 /* EACL:POL_CFG:POL_EACL_CFG */
4551 #define EACL_POL_EACL_CFG                                                      \
4552         __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_POL_CFG], 0, 1, 780, 768, \
4553               0, 1, 4)
4554
4555 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED BIT(5)
4556 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_SET(x)\
4557         FIELD_PREP(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
4558 #define EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED_GET(x)\
4559         FIELD_GET(EACL_POL_EACL_CFG_EACL_CNT_MARKED_AS_DROPPED, x)
4560
4561 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY     BIT(4)
4562 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_SET(x)\
4563         FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
4564 #define EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY_GET(x)\
4565         FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_FP_COPY, x)
4566
4567 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY    BIT(3)
4568 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_SET(x)\
4569         FIELD_PREP(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
4570 #define EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY_GET(x)\
4571         FIELD_GET(EACL_POL_EACL_CFG_EACL_ALLOW_CPU_COPY, x)
4572
4573 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE       BIT(2)
4574 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_SET(x)\
4575         FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
4576 #define EACL_POL_EACL_CFG_EACL_FORCE_CLOSE_GET(x)\
4577         FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_CLOSE, x)
4578
4579 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN        BIT(1)
4580 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_SET(x)\
4581         FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
4582 #define EACL_POL_EACL_CFG_EACL_FORCE_OPEN_GET(x)\
4583         FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_OPEN, x)
4584
4585 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT        BIT(0)
4586 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_SET(x)\
4587         FIELD_PREP(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
4588 #define EACL_POL_EACL_CFG_EACL_FORCE_INIT_GET(x)\
4589         FIELD_GET(EACL_POL_EACL_CFG_EACL_FORCE_INIT, x)
4590
4591 /* EACL:ES2_STICKY:SEC_LOOKUP_STICKY */
4592 #define EACL_SEC_LOOKUP_STICKY(r)                                              \
4593         __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_ES2_STICKY], 0, 1, 8, 0,  \
4594               r, 2, 4)
4595
4596 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY BIT(7)
4597 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_SET(x)\
4598         FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
4599 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY_GET(x)\
4600         FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP_7TUPLE_STICKY, x)
4601
4602 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY BIT(6)
4603 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_SET(x)\
4604         FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
4605 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY_GET(x)\
4606         FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_VID_STICKY, x)
4607
4608 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY BIT(5)
4609 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_SET(x)\
4610         FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
4611 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY_GET(x)\
4612         FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP6_STD_STICKY, x)
4613
4614 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY BIT(4)
4615 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_SET(x)\
4616         FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
4617 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY_GET(x)\
4618         FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_TCPUDP_STICKY, x)
4619
4620 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY BIT(3)
4621 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_SET(x)\
4622         FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
4623 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY_GET(x)\
4624         FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_VID_STICKY, x)
4625
4626 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY BIT(2)
4627 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_SET(x)\
4628         FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
4629 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY_GET(x)\
4630         FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_IP4_OTHER_STICKY, x)
4631
4632 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY BIT(1)
4633 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_SET(x)\
4634         FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
4635 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY_GET(x)\
4636         FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_ARP_STICKY, x)
4637
4638 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY BIT(0)
4639 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_SET(x)\
4640         FIELD_PREP(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
4641 #define EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY_GET(x)\
4642         FIELD_GET(EACL_SEC_LOOKUP_STICKY_SEC_TYPE_MAC_ETYPE_STICKY, x)
4643
4644 /* EACL:RAM_CTRL:RAM_INIT */
4645 #define EACL_RAM_INIT                                                          \
4646         __REG(TARGET_EACL, 0, 1, regs->gaddr[GA_EACL_RAM_CTRL], 0, 1, 4, 0, 0, \
4647               1, 4)
4648
4649 #define EACL_RAM_INIT_RAM_INIT                   BIT(1)
4650 #define EACL_RAM_INIT_RAM_INIT_SET(x)\
4651         FIELD_PREP(EACL_RAM_INIT_RAM_INIT, x)
4652 #define EACL_RAM_INIT_RAM_INIT_GET(x)\
4653         FIELD_GET(EACL_RAM_INIT_RAM_INIT, x)
4654
4655 #define EACL_RAM_INIT_RAM_CFG_HOOK               BIT(0)
4656 #define EACL_RAM_INIT_RAM_CFG_HOOK_SET(x)\
4657         FIELD_PREP(EACL_RAM_INIT_RAM_CFG_HOOK, x)
4658 #define EACL_RAM_INIT_RAM_CFG_HOOK_GET(x)\
4659         FIELD_GET(EACL_RAM_INIT_RAM_CFG_HOOK, x)
4660
4661 /* FDMA:FDMA:FDMA_CH_ACTIVATE */
4662 #define FDMA_CH_ACTIVATE                                                       \
4663         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 0, 0, 1,  \
4664               4)
4665
4666 #define FDMA_CH_ACTIVATE_CH_ACTIVATE             GENMASK(7, 0)
4667 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_SET(x)\
4668         FIELD_PREP(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
4669 #define FDMA_CH_ACTIVATE_CH_ACTIVATE_GET(x)\
4670         FIELD_GET(FDMA_CH_ACTIVATE_CH_ACTIVATE, x)
4671
4672 /* FDMA:FDMA:FDMA_CH_RELOAD */
4673 #define FDMA_CH_RELOAD                                                         \
4674         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 4, 0, 1,  \
4675               4)
4676
4677 #define FDMA_CH_RELOAD_CH_RELOAD                 GENMASK(7, 0)
4678 #define FDMA_CH_RELOAD_CH_RELOAD_SET(x)\
4679         FIELD_PREP(FDMA_CH_RELOAD_CH_RELOAD, x)
4680 #define FDMA_CH_RELOAD_CH_RELOAD_GET(x)\
4681         FIELD_GET(FDMA_CH_RELOAD_CH_RELOAD, x)
4682
4683 /* FDMA:FDMA:FDMA_CH_DISABLE */
4684 #define FDMA_CH_DISABLE                                                        \
4685         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 8, 0, 1,  \
4686               4)
4687
4688 #define FDMA_CH_DISABLE_CH_DISABLE               GENMASK(7, 0)
4689 #define FDMA_CH_DISABLE_CH_DISABLE_SET(x)\
4690         FIELD_PREP(FDMA_CH_DISABLE_CH_DISABLE, x)
4691 #define FDMA_CH_DISABLE_CH_DISABLE_GET(x)\
4692         FIELD_GET(FDMA_CH_DISABLE_CH_DISABLE, x)
4693
4694 /* FDMA:FDMA:FDMA_DCB_LLP */
4695 #define FDMA_DCB_LLP(r)                                                        \
4696         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 52, r, 8, \
4697               4)
4698
4699 /* FDMA:FDMA:FDMA_DCB_LLP1 */
4700 #define FDMA_DCB_LLP1(r)                                                       \
4701         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 84, r, 8, \
4702               4)
4703
4704 /* FDMA:FDMA:FDMA_DCB_LLP_PREV */
4705 #define FDMA_DCB_LLP_PREV(r)                                                   \
4706         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 116, r, 8,\
4707               4)
4708
4709 /* FDMA:FDMA:FDMA_DCB_LLP_PREV1 */
4710 #define FDMA_DCB_LLP_PREV1(r)                                                  \
4711         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 148, r, 8,\
4712               4)
4713
4714 /* FDMA:FDMA:FDMA_CH_CFG */
4715 #define FDMA_CH_CFG(r)                                                         \
4716         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 224, r, 8,\
4717               4)
4718
4719 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE\
4720         BIT(regs->fpos[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE])
4721 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_SET(x)\
4722         spx5_field_prep(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
4723 #define FDMA_CH_CFG_CH_XTR_STATUS_MODE_GET(x)\
4724         spx5_field_get(FDMA_CH_CFG_CH_XTR_STATUS_MODE, x)
4725
4726 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY\
4727         BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY])
4728 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_SET(x)\
4729         spx5_field_prep(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
4730 #define FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY_GET(x)\
4731         spx5_field_get(FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY, x)
4732
4733 #define FDMA_CH_CFG_CH_INJ_PORT\
4734         BIT(regs->fpos[FP_FDMA_CH_CFG_CH_INJ_PORT])
4735 #define FDMA_CH_CFG_CH_INJ_PORT_SET(x)\
4736         spx5_field_prep(FDMA_CH_CFG_CH_INJ_PORT, x)
4737 #define FDMA_CH_CFG_CH_INJ_PORT_GET(x)\
4738         spx5_field_get(FDMA_CH_CFG_CH_INJ_PORT, x)
4739
4740 #define FDMA_CH_CFG_CH_DCB_DB_CNT\
4741         GENMASK(regs->fsize[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] + 1 - 1, 1)
4742 #define FDMA_CH_CFG_CH_DCB_DB_CNT_SET(x)\
4743         spx5_field_prep(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
4744 #define FDMA_CH_CFG_CH_DCB_DB_CNT_GET(x)\
4745         spx5_field_get(FDMA_CH_CFG_CH_DCB_DB_CNT, x)
4746
4747 #define FDMA_CH_CFG_CH_MEM                       BIT(0)
4748 #define FDMA_CH_CFG_CH_MEM_SET(x)\
4749         FIELD_PREP(FDMA_CH_CFG_CH_MEM, x)
4750 #define FDMA_CH_CFG_CH_MEM_GET(x)\
4751         FIELD_GET(FDMA_CH_CFG_CH_MEM, x)
4752
4753 /* FDMA:FDMA:FDMA_CH_TRANSLATE */
4754 #define FDMA_CH_TRANSLATE(r)                                                   \
4755         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 256, r, 8,\
4756               4)
4757
4758 #define FDMA_CH_TRANSLATE_OFFSET                 GENMASK(15, 0)
4759 #define FDMA_CH_TRANSLATE_OFFSET_SET(x)\
4760         FIELD_PREP(FDMA_CH_TRANSLATE_OFFSET, x)
4761 #define FDMA_CH_TRANSLATE_OFFSET_GET(x)\
4762         FIELD_GET(FDMA_CH_TRANSLATE_OFFSET, x)
4763
4764 /* FDMA:FDMA:FDMA_XTR_CFG */
4765 #define FDMA_XTR_CFG                                                           \
4766         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 364, 0, 1,\
4767               4)
4768
4769 #define FDMA_XTR_CFG_XTR_FIFO_WM                 GENMASK(15, 11)
4770 #define FDMA_XTR_CFG_XTR_FIFO_WM_SET(x)\
4771         FIELD_PREP(FDMA_XTR_CFG_XTR_FIFO_WM, x)
4772 #define FDMA_XTR_CFG_XTR_FIFO_WM_GET(x)\
4773         FIELD_GET(FDMA_XTR_CFG_XTR_FIFO_WM, x)
4774
4775 #define FDMA_XTR_CFG_XTR_ARB_SAT                 GENMASK(10, 0)
4776 #define FDMA_XTR_CFG_XTR_ARB_SAT_SET(x)\
4777         FIELD_PREP(FDMA_XTR_CFG_XTR_ARB_SAT, x)
4778 #define FDMA_XTR_CFG_XTR_ARB_SAT_GET(x)\
4779         FIELD_GET(FDMA_XTR_CFG_XTR_ARB_SAT, x)
4780
4781 /* FDMA:FDMA:FDMA_PORT_CTRL */
4782 #define FDMA_PORT_CTRL(r)                                                      \
4783         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 376, r, 2,\
4784               4)
4785
4786 #define FDMA_PORT_CTRL_INJ_STOP                  BIT(4)
4787 #define FDMA_PORT_CTRL_INJ_STOP_SET(x)\
4788         FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP, x)
4789 #define FDMA_PORT_CTRL_INJ_STOP_GET(x)\
4790         FIELD_GET(FDMA_PORT_CTRL_INJ_STOP, x)
4791
4792 #define FDMA_PORT_CTRL_INJ_STOP_FORCE            BIT(3)
4793 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_SET(x)\
4794         FIELD_PREP(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
4795 #define FDMA_PORT_CTRL_INJ_STOP_FORCE_GET(x)\
4796         FIELD_GET(FDMA_PORT_CTRL_INJ_STOP_FORCE, x)
4797
4798 #define FDMA_PORT_CTRL_XTR_STOP                  BIT(2)
4799 #define FDMA_PORT_CTRL_XTR_STOP_SET(x)\
4800         FIELD_PREP(FDMA_PORT_CTRL_XTR_STOP, x)
4801 #define FDMA_PORT_CTRL_XTR_STOP_GET(x)\
4802         FIELD_GET(FDMA_PORT_CTRL_XTR_STOP, x)
4803
4804 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY          BIT(1)
4805 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_SET(x)\
4806         FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
4807 #define FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY_GET(x)\
4808         FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_IS_EMPTY, x)
4809
4810 #define FDMA_PORT_CTRL_XTR_BUF_RST               BIT(0)
4811 #define FDMA_PORT_CTRL_XTR_BUF_RST_SET(x)\
4812         FIELD_PREP(FDMA_PORT_CTRL_XTR_BUF_RST, x)
4813 #define FDMA_PORT_CTRL_XTR_BUF_RST_GET(x)\
4814         FIELD_GET(FDMA_PORT_CTRL_XTR_BUF_RST, x)
4815
4816 /* FDMA:FDMA:FDMA_INTR_DCB */
4817 #define FDMA_INTR_DCB                                                          \
4818         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 384, 0, 1,\
4819               4)
4820
4821 #define FDMA_INTR_DCB_INTR_DCB                   GENMASK(7, 0)
4822 #define FDMA_INTR_DCB_INTR_DCB_SET(x)\
4823         FIELD_PREP(FDMA_INTR_DCB_INTR_DCB, x)
4824 #define FDMA_INTR_DCB_INTR_DCB_GET(x)\
4825         FIELD_GET(FDMA_INTR_DCB_INTR_DCB, x)
4826
4827 /* FDMA:FDMA:FDMA_INTR_DCB_ENA */
4828 #define FDMA_INTR_DCB_ENA                                                      \
4829         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 388, 0, 1,\
4830               4)
4831
4832 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA           GENMASK(7, 0)
4833 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_SET(x)\
4834         FIELD_PREP(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
4835 #define FDMA_INTR_DCB_ENA_INTR_DCB_ENA_GET(x)\
4836         FIELD_GET(FDMA_INTR_DCB_ENA_INTR_DCB_ENA, x)
4837
4838 /* FDMA:FDMA:FDMA_INTR_DB */
4839 #define FDMA_INTR_DB                                                           \
4840         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 392, 0, 1,\
4841               4)
4842
4843 #define FDMA_INTR_DB_INTR_DB                     GENMASK(7, 0)
4844 #define FDMA_INTR_DB_INTR_DB_SET(x)\
4845         FIELD_PREP(FDMA_INTR_DB_INTR_DB, x)
4846 #define FDMA_INTR_DB_INTR_DB_GET(x)\
4847         FIELD_GET(FDMA_INTR_DB_INTR_DB, x)
4848
4849 /* FDMA:FDMA:FDMA_INTR_DB_ENA */
4850 #define FDMA_INTR_DB_ENA                                                       \
4851         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 396, 0, 1,\
4852               4)
4853
4854 #define FDMA_INTR_DB_ENA_INTR_DB_ENA             GENMASK(7, 0)
4855 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_SET(x)\
4856         FIELD_PREP(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
4857 #define FDMA_INTR_DB_ENA_INTR_DB_ENA_GET(x)\
4858         FIELD_GET(FDMA_INTR_DB_ENA_INTR_DB_ENA, x)
4859
4860 /* FDMA:FDMA:FDMA_INTR_ERR */
4861 #define FDMA_INTR_ERR                                                          \
4862         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 400, 0, 1,\
4863               4)
4864
4865 #define FDMA_INTR_ERR_INTR_PORT_ERR              GENMASK(9, 8)
4866 #define FDMA_INTR_ERR_INTR_PORT_ERR_SET(x)\
4867         FIELD_PREP(FDMA_INTR_ERR_INTR_PORT_ERR, x)
4868 #define FDMA_INTR_ERR_INTR_PORT_ERR_GET(x)\
4869         FIELD_GET(FDMA_INTR_ERR_INTR_PORT_ERR, x)
4870
4871 #define FDMA_INTR_ERR_INTR_CH_ERR                GENMASK(7, 0)
4872 #define FDMA_INTR_ERR_INTR_CH_ERR_SET(x)\
4873         FIELD_PREP(FDMA_INTR_ERR_INTR_CH_ERR, x)
4874 #define FDMA_INTR_ERR_INTR_CH_ERR_GET(x)\
4875         FIELD_GET(FDMA_INTR_ERR_INTR_CH_ERR, x)
4876
4877 /* FDMA:FDMA:FDMA_ERRORS */
4878 #define FDMA_ERRORS                                                            \
4879         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 412, 0, 1,\
4880               4)
4881
4882 #define FDMA_ERRORS_ERR_XTR_WR                   GENMASK(31, 30)
4883 #define FDMA_ERRORS_ERR_XTR_WR_SET(x)\
4884         FIELD_PREP(FDMA_ERRORS_ERR_XTR_WR, x)
4885 #define FDMA_ERRORS_ERR_XTR_WR_GET(x)\
4886         FIELD_GET(FDMA_ERRORS_ERR_XTR_WR, x)
4887
4888 #define FDMA_ERRORS_ERR_XTR_OVF                  GENMASK(29, 28)
4889 #define FDMA_ERRORS_ERR_XTR_OVF_SET(x)\
4890         FIELD_PREP(FDMA_ERRORS_ERR_XTR_OVF, x)
4891 #define FDMA_ERRORS_ERR_XTR_OVF_GET(x)\
4892         FIELD_GET(FDMA_ERRORS_ERR_XTR_OVF, x)
4893
4894 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF           GENMASK(27, 26)
4895 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_SET(x)\
4896         FIELD_PREP(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
4897 #define FDMA_ERRORS_ERR_XTR_TAXI32_OVF_GET(x)\
4898         FIELD_GET(FDMA_ERRORS_ERR_XTR_TAXI32_OVF, x)
4899
4900 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL            GENMASK(25, 24)
4901 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_SET(x)\
4902         FIELD_PREP(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
4903 #define FDMA_ERRORS_ERR_DCB_XTR_DATAL_GET(x)\
4904         FIELD_GET(FDMA_ERRORS_ERR_DCB_XTR_DATAL, x)
4905
4906 #define FDMA_ERRORS_ERR_DCB_RD                   GENMASK(23, 16)
4907 #define FDMA_ERRORS_ERR_DCB_RD_SET(x)\
4908         FIELD_PREP(FDMA_ERRORS_ERR_DCB_RD, x)
4909 #define FDMA_ERRORS_ERR_DCB_RD_GET(x)\
4910         FIELD_GET(FDMA_ERRORS_ERR_DCB_RD, x)
4911
4912 #define FDMA_ERRORS_ERR_INJ_RD                   GENMASK(15, 10)
4913 #define FDMA_ERRORS_ERR_INJ_RD_SET(x)\
4914         FIELD_PREP(FDMA_ERRORS_ERR_INJ_RD, x)
4915 #define FDMA_ERRORS_ERR_INJ_RD_GET(x)\
4916         FIELD_GET(FDMA_ERRORS_ERR_INJ_RD, x)
4917
4918 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC          GENMASK(9, 8)
4919 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_SET(x)\
4920         FIELD_PREP(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
4921 #define FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC_GET(x)\
4922         FIELD_GET(FDMA_ERRORS_ERR_INJ_OUT_OF_SYNC, x)
4923
4924 #define FDMA_ERRORS_ERR_CH_WR                    GENMASK(7, 0)
4925 #define FDMA_ERRORS_ERR_CH_WR_SET(x)\
4926         FIELD_PREP(FDMA_ERRORS_ERR_CH_WR, x)
4927 #define FDMA_ERRORS_ERR_CH_WR_GET(x)\
4928         FIELD_GET(FDMA_ERRORS_ERR_CH_WR, x)
4929
4930 /* FDMA:FDMA:FDMA_ERRORS_2 */
4931 #define FDMA_ERRORS_2                                                          \
4932         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 416, 0, 1,\
4933               4)
4934
4935 #define FDMA_ERRORS_2_ERR_XTR_FRAG               GENMASK(1, 0)
4936 #define FDMA_ERRORS_2_ERR_XTR_FRAG_SET(x)\
4937         FIELD_PREP(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
4938 #define FDMA_ERRORS_2_ERR_XTR_FRAG_GET(x)\
4939         FIELD_GET(FDMA_ERRORS_2_ERR_XTR_FRAG, x)
4940
4941 /* FDMA:FDMA:FDMA_CTRL */
4942 #define FDMA_CTRL                                                              \
4943         __REG(TARGET_FDMA, 0, 1, 8, 0, 1, regs->gsize[GW_FDMA_FDMA], 424, 0, 1,\
4944               4)
4945
4946 #define FDMA_CTRL_NRESET                         BIT(0)
4947 #define FDMA_CTRL_NRESET_SET(x)\
4948         FIELD_PREP(FDMA_CTRL_NRESET, x)
4949 #define FDMA_CTRL_NRESET_GET(x)\
4950         FIELD_GET(FDMA_CTRL_NRESET, x)
4951
4952 /* DEVCPU_GCB:CHIP_REGS:CHIP_ID */
4953 #define GCB_CHIP_ID                                                            \
4954         __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 0, 0,  \
4955               1, 4)
4956
4957 #define GCB_CHIP_ID_REV_ID                       GENMASK(31, 28)
4958 #define GCB_CHIP_ID_REV_ID_SET(x)\
4959         FIELD_PREP(GCB_CHIP_ID_REV_ID, x)
4960 #define GCB_CHIP_ID_REV_ID_GET(x)\
4961         FIELD_GET(GCB_CHIP_ID_REV_ID, x)
4962
4963 #define GCB_CHIP_ID_PART_ID                      GENMASK(27, 12)
4964 #define GCB_CHIP_ID_PART_ID_SET(x)\
4965         FIELD_PREP(GCB_CHIP_ID_PART_ID, x)
4966 #define GCB_CHIP_ID_PART_ID_GET(x)\
4967         FIELD_GET(GCB_CHIP_ID_PART_ID, x)
4968
4969 #define GCB_CHIP_ID_MFG_ID                       GENMASK(11, 1)
4970 #define GCB_CHIP_ID_MFG_ID_SET(x)\
4971         FIELD_PREP(GCB_CHIP_ID_MFG_ID, x)
4972 #define GCB_CHIP_ID_MFG_ID_GET(x)\
4973         FIELD_GET(GCB_CHIP_ID_MFG_ID, x)
4974
4975 #define GCB_CHIP_ID_ONE                          BIT(0)
4976 #define GCB_CHIP_ID_ONE_SET(x)\
4977         FIELD_PREP(GCB_CHIP_ID_ONE, x)
4978 #define GCB_CHIP_ID_ONE_GET(x)\
4979         FIELD_GET(GCB_CHIP_ID_ONE, x)
4980
4981 /* DEVCPU_GCB:CHIP_REGS:SOFT_RST */
4982 #define GCB_SOFT_RST                                                           \
4983         __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS],        \
4984               regs->raddr[RA_GCB_SOFT_RST], 0, 1, 4)
4985
4986 /* SPARX5 ONLY */
4987 #define GCB_SOFT_RST_SOFT_NON_CFG_RST            BIT(2)
4988 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_SET(x)\
4989         FIELD_PREP(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
4990 #define GCB_SOFT_RST_SOFT_NON_CFG_RST_GET(x)\
4991         FIELD_GET(GCB_SOFT_RST_SOFT_NON_CFG_RST, x)
4992
4993 #define GCB_SOFT_RST_SOFT_SWC_RST                BIT(1)
4994 #define GCB_SOFT_RST_SOFT_SWC_RST_SET(x)\
4995         FIELD_PREP(GCB_SOFT_RST_SOFT_SWC_RST, x)
4996 #define GCB_SOFT_RST_SOFT_SWC_RST_GET(x)\
4997         FIELD_GET(GCB_SOFT_RST_SOFT_SWC_RST, x)
4998
4999 #define GCB_SOFT_RST_SOFT_CHIP_RST               BIT(0)
5000 #define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\
5001         FIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x)
5002 #define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\
5003         FIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x)
5004
5005 /* SPARX5 ONLY */
5006 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_SD_CFG */
5007 #define GCB_HW_SGPIO_SD_CFG                                                    \
5008         __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS], 20, 0, \
5009               1, 4)
5010
5011 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA          BIT(1)
5012 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_SET(x)\
5013         FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
5014 #define GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA_GET(x)\
5015         FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_HIGH_ENA, x)
5016
5017 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL           BIT(0)
5018 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_SET(x)\
5019         FIELD_PREP(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
5020 #define GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL_GET(x)\
5021         FIELD_GET(GCB_HW_SGPIO_SD_CFG_SD_MAP_SEL, x)
5022
5023 /* DEVCPU_GCB:CHIP_REGS:HW_SGPIO_TO_SD_MAP_CFG */
5024 #define GCB_HW_SGPIO_TO_SD_MAP_CFG(r)                                          \
5025         __REG(TARGET_GCB, 0, 1, 0, 0, 1, regs->gsize[GW_GCB_CHIP_REGS],        \
5026               regs->raddr[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG], r,                   \
5027               regs->rcnt[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG], 4)
5028
5029 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL\
5030         GENMASK(regs->fsize[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] + 0 - 1, 0)
5031 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_SET(x)\
5032         spx5_field_prep(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
5033 #define GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL_GET(x)\
5034         spx5_field_get(GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL, x)
5035
5036 /* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */
5037 #define GCB_SIO_CLOCK(g)                                                       \
5038         __REG(TARGET_GCB, 0, 1, regs->gaddr[GA_GCB_SIO_CTRL], g,               \
5039               regs->gcnt[GC_GCB_SIO_CTRL], 280, 20, 0, 1, 4)
5040
5041 #define GCB_SIO_CLOCK_SIO_CLK_FREQ               GENMASK(19, 8)
5042 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_SET(x)\
5043         FIELD_PREP(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
5044 #define GCB_SIO_CLOCK_SIO_CLK_FREQ_GET(x)\
5045         FIELD_GET(GCB_SIO_CLOCK_SIO_CLK_FREQ, x)
5046
5047 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD             GENMASK(7, 0)
5048 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_SET(x)\
5049         FIELD_PREP(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
5050 #define GCB_SIO_CLOCK_SYS_CLK_PERIOD_GET(x)\
5051         FIELD_GET(GCB_SIO_CLOCK_SYS_CLK_PERIOD, x)
5052
5053 /* HSCH:HSCH_CFG:CIR_CFG */
5054 #define HSCH_CIR_CFG(g)                                                        \
5055         __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 0, 0, \
5056               1, 4)
5057
5058 #define HSCH_CIR_CFG_CIR_RATE                    GENMASK(22, 6)
5059 #define HSCH_CIR_CFG_CIR_RATE_SET(x)\
5060         FIELD_PREP(HSCH_CIR_CFG_CIR_RATE, x)
5061 #define HSCH_CIR_CFG_CIR_RATE_GET(x)\
5062         FIELD_GET(HSCH_CIR_CFG_CIR_RATE, x)
5063
5064 #define HSCH_CIR_CFG_CIR_BURST                   GENMASK(5, 0)
5065 #define HSCH_CIR_CFG_CIR_BURST_SET(x)\
5066         FIELD_PREP(HSCH_CIR_CFG_CIR_BURST, x)
5067 #define HSCH_CIR_CFG_CIR_BURST_GET(x)\
5068         FIELD_GET(HSCH_CIR_CFG_CIR_BURST, x)
5069
5070 /* HSCH:HSCH_CFG:EIR_CFG */
5071 #define HSCH_EIR_CFG(g)                                                        \
5072         __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 4, 0, \
5073               1, 4)
5074
5075 #define HSCH_EIR_CFG_EIR_RATE                    GENMASK(22, 6)
5076 #define HSCH_EIR_CFG_EIR_RATE_SET(x)\
5077         FIELD_PREP(HSCH_EIR_CFG_EIR_RATE, x)
5078 #define HSCH_EIR_CFG_EIR_RATE_GET(x)\
5079         FIELD_GET(HSCH_EIR_CFG_EIR_RATE, x)
5080
5081 #define HSCH_EIR_CFG_EIR_BURST                   GENMASK(5, 0)
5082 #define HSCH_EIR_CFG_EIR_BURST_SET(x)\
5083         FIELD_PREP(HSCH_EIR_CFG_EIR_BURST, x)
5084 #define HSCH_EIR_CFG_EIR_BURST_GET(x)\
5085         FIELD_GET(HSCH_EIR_CFG_EIR_BURST, x)
5086
5087 /* HSCH:HSCH_CFG:SE_CFG */
5088 #define HSCH_SE_CFG(g)                                                         \
5089         __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 8, 0, \
5090               1, 4)
5091
5092 #define HSCH_SE_CFG_SE_DWRR_CNT\
5093         GENMASK(regs->fsize[FW_HSCH_SE_CFG_SE_DWRR_CNT] + 6 - 1, 6)
5094 #define HSCH_SE_CFG_SE_DWRR_CNT_SET(x)\
5095         spx5_field_prep(HSCH_SE_CFG_SE_DWRR_CNT, x)
5096 #define HSCH_SE_CFG_SE_DWRR_CNT_GET(x)\
5097         spx5_field_get(HSCH_SE_CFG_SE_DWRR_CNT, x)
5098
5099 #define HSCH_SE_CFG_SE_AVB_ENA                   BIT(5)
5100 #define HSCH_SE_CFG_SE_AVB_ENA_SET(x)\
5101         FIELD_PREP(HSCH_SE_CFG_SE_AVB_ENA, x)
5102 #define HSCH_SE_CFG_SE_AVB_ENA_GET(x)\
5103         FIELD_GET(HSCH_SE_CFG_SE_AVB_ENA, x)
5104
5105 #define HSCH_SE_CFG_SE_FRM_MODE                  GENMASK(4, 3)
5106 #define HSCH_SE_CFG_SE_FRM_MODE_SET(x)\
5107         FIELD_PREP(HSCH_SE_CFG_SE_FRM_MODE, x)
5108 #define HSCH_SE_CFG_SE_FRM_MODE_GET(x)\
5109         FIELD_GET(HSCH_SE_CFG_SE_FRM_MODE, x)
5110
5111 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE             GENMASK(2, 1)
5112 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_SET(x)\
5113         FIELD_PREP(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x)
5114 #define HSCH_SE_CFG_SE_DWRR_FRM_MODE_GET(x)\
5115         FIELD_GET(HSCH_SE_CFG_SE_DWRR_FRM_MODE, x)
5116
5117 #define HSCH_SE_CFG_SE_STOP                      BIT(0)
5118 #define HSCH_SE_CFG_SE_STOP_SET(x)\
5119         FIELD_PREP(HSCH_SE_CFG_SE_STOP, x)
5120 #define HSCH_SE_CFG_SE_STOP_GET(x)\
5121         FIELD_GET(HSCH_SE_CFG_SE_STOP, x)
5122
5123 /* HSCH:HSCH_CFG:SE_CONNECT */
5124 #define HSCH_SE_CONNECT(g)                                                     \
5125         __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 12, 0,\
5126               1, 4)
5127
5128 #define HSCH_SE_CONNECT_SE_LEAK_LINK\
5129         GENMASK(regs->fsize[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] + 0 - 1, 0)
5130 #define HSCH_SE_CONNECT_SE_LEAK_LINK_SET(x)\
5131         spx5_field_prep(HSCH_SE_CONNECT_SE_LEAK_LINK, x)
5132 #define HSCH_SE_CONNECT_SE_LEAK_LINK_GET(x)\
5133         spx5_field_get(HSCH_SE_CONNECT_SE_LEAK_LINK, x)
5134
5135 /* HSCH:HSCH_CFG:SE_DLB_SENSE */
5136 #define HSCH_SE_DLB_SENSE(g)                                                   \
5137         __REG(TARGET_HSCH, 0, 1, 0, g, regs->gcnt[GC_HSCH_HSCH_CFG], 32, 16, 0,\
5138               1, 4)
5139
5140 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO            GENMASK(12, 10)
5141 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_SET(x)\
5142         FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x)
5143 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_GET(x)\
5144         FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO, x)
5145
5146 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT\
5147         GENMASK(regs->fsize[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] + 3 - 1, 3)
5148 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_SET(x)\
5149         spx5_field_prep(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x)
5150 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_GET(x)\
5151         spx5_field_get(HSCH_SE_DLB_SENSE_SE_DLB_DPORT, x)
5152
5153 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA          BIT(2)
5154 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_SET(x)\
5155         FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x)
5156 #define HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA_GET(x)\
5157         FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_SE_ENA, x)
5158
5159 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA        BIT(1)
5160 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_SET(x)\
5161         FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x)
5162 #define HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA_GET(x)\
5163         FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_PRIO_ENA, x)
5164
5165 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA       BIT(0)
5166 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_SET(x)\
5167         FIELD_PREP(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x)
5168 #define HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA_GET(x)\
5169         FIELD_GET(HSCH_SE_DLB_SENSE_SE_DLB_DPORT_ENA, x)
5170
5171 /* HSCH:HSCH_DWRR:DWRR_ENTRY */
5172 #define HSCH_DWRR_ENTRY(g)                                                     \
5173         __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_DWRR], g,            \
5174               regs->gcnt[GC_HSCH_HSCH_DWRR], 4, 0, 0, 1, 4)
5175
5176 #define HSCH_DWRR_ENTRY_DWRR_COST                GENMASK(24, 20)
5177 #define HSCH_DWRR_ENTRY_DWRR_COST_SET(x)\
5178         FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_COST, x)
5179 #define HSCH_DWRR_ENTRY_DWRR_COST_GET(x)\
5180         FIELD_GET(HSCH_DWRR_ENTRY_DWRR_COST, x)
5181
5182 #define HSCH_DWRR_ENTRY_DWRR_BALANCE             GENMASK(19, 0)
5183 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_SET(x)\
5184         FIELD_PREP(HSCH_DWRR_ENTRY_DWRR_BALANCE, x)
5185 #define HSCH_DWRR_ENTRY_DWRR_BALANCE_GET(x)\
5186         FIELD_GET(HSCH_DWRR_ENTRY_DWRR_BALANCE, x)
5187
5188 /* HSCH:HSCH_MISC:HSCH_CFG_CFG */
5189 #define HSCH_HSCH_CFG_CFG                                                      \
5190         __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648,    \
5191               284, 0, 1, 4)
5192
5193 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX\
5194         GENMASK(regs->fsize[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] + 14 - 1, 14)
5195 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_SET(x)\
5196         spx5_field_prep(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x)
5197 #define HSCH_HSCH_CFG_CFG_CFG_SE_IDX_GET(x)\
5198         spx5_field_get(HSCH_HSCH_CFG_CFG_CFG_SE_IDX, x)
5199
5200 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER             GENMASK(13, 12)
5201 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_SET(x)\
5202         FIELD_PREP(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x)
5203 #define HSCH_HSCH_CFG_CFG_HSCH_LAYER_GET(x)\
5204         FIELD_GET(HSCH_HSCH_CFG_CFG_HSCH_LAYER, x)
5205
5206 #define HSCH_HSCH_CFG_CFG_CSR_GRANT              GENMASK(11, 0)
5207 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_SET(x)\
5208         FIELD_PREP(HSCH_HSCH_CFG_CFG_CSR_GRANT, x)
5209 #define HSCH_HSCH_CFG_CFG_CSR_GRANT_GET(x)\
5210         FIELD_GET(HSCH_HSCH_CFG_CFG_CSR_GRANT, x)
5211
5212 /* SPARX5 ONLY */
5213 /* HSCH:HSCH_MISC:SYS_CLK_PER */
5214 #define HSCH_SYS_CLK_PER                                                       \
5215         __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_MISC], 0, 1, 648,    \
5216               640, 0, 1, 4)
5217
5218 #define HSCH_SYS_CLK_PER_100PS                   GENMASK(7, 0)
5219 #define HSCH_SYS_CLK_PER_100PS_SET(x)\
5220         FIELD_PREP(HSCH_SYS_CLK_PER_100PS, x)
5221 #define HSCH_SYS_CLK_PER_100PS_GET(x)\
5222         FIELD_GET(HSCH_SYS_CLK_PER_100PS, x)
5223
5224 /* HSCH:HSCH_LEAK_LISTS:HSCH_TIMER_CFG */
5225 #define HSCH_HSCH_TIMER_CFG(g, r)                                              \
5226         __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4,   \
5227               32, 0, r, 4, 4)
5228
5229 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME            GENMASK(17, 0)
5230 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_SET(x)\
5231         FIELD_PREP(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x)
5232 #define HSCH_HSCH_TIMER_CFG_LEAK_TIME_GET(x)\
5233         FIELD_GET(HSCH_HSCH_TIMER_CFG_LEAK_TIME, x)
5234
5235 /* HSCH:HSCH_LEAK_LISTS:HSCH_LEAK_CFG */
5236 #define HSCH_HSCH_LEAK_CFG(g, r)                                               \
5237         __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_HSCH_LEAK_LISTS], g, 4,   \
5238               32, 16, r, 4, 4)
5239
5240 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST\
5241         GENMASK(regs->fsize[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] + 1 - 1, 1)
5242 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_SET(x)\
5243         spx5_field_prep(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x)
5244 #define HSCH_HSCH_LEAK_CFG_LEAK_FIRST_GET(x)\
5245         spx5_field_get(HSCH_HSCH_LEAK_CFG_LEAK_FIRST, x)
5246
5247 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR              BIT(0)
5248 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_SET(x)\
5249         FIELD_PREP(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x)
5250 #define HSCH_HSCH_LEAK_CFG_LEAK_ERR_GET(x)\
5251         FIELD_GET(HSCH_HSCH_LEAK_CFG_LEAK_ERR, x)
5252
5253 /* HSCH:SYSTEM:FLUSH_CTRL */
5254 #define HSCH_FLUSH_CTRL                                                        \
5255         __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 4, 0, \
5256               1, 4)
5257
5258 #define HSCH_FLUSH_CTRL_FLUSH_ENA                BIT(27)
5259 #define HSCH_FLUSH_CTRL_FLUSH_ENA_SET(x)\
5260         FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
5261 #define HSCH_FLUSH_CTRL_FLUSH_ENA_GET(x)\
5262         FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_ENA, x)
5263
5264 #define HSCH_FLUSH_CTRL_FLUSH_SRC                BIT(26)
5265 #define HSCH_FLUSH_CTRL_FLUSH_SRC_SET(x)\
5266         FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
5267 #define HSCH_FLUSH_CTRL_FLUSH_SRC_GET(x)\
5268         FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SRC, x)
5269
5270 #define HSCH_FLUSH_CTRL_FLUSH_DST                BIT(25)
5271 #define HSCH_FLUSH_CTRL_FLUSH_DST_SET(x)\
5272         FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_DST, x)
5273 #define HSCH_FLUSH_CTRL_FLUSH_DST_GET(x)\
5274         FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_DST, x)
5275
5276 #define HSCH_FLUSH_CTRL_FLUSH_PORT\
5277         GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] + 18 - 1, 18)
5278 #define HSCH_FLUSH_CTRL_FLUSH_PORT_SET(x)\
5279         spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
5280 #define HSCH_FLUSH_CTRL_FLUSH_PORT_GET(x)\
5281         spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_PORT, x)
5282
5283 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE              BIT(17)
5284 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_SET(x)\
5285         FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
5286 #define HSCH_FLUSH_CTRL_FLUSH_QUEUE_GET(x)\
5287         FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_QUEUE, x)
5288
5289 #define HSCH_FLUSH_CTRL_FLUSH_SE                 BIT(16)
5290 #define HSCH_FLUSH_CTRL_FLUSH_SE_SET(x)\
5291         FIELD_PREP(HSCH_FLUSH_CTRL_FLUSH_SE, x)
5292 #define HSCH_FLUSH_CTRL_FLUSH_SE_GET(x)\
5293         FIELD_GET(HSCH_FLUSH_CTRL_FLUSH_SE, x)
5294
5295 #define HSCH_FLUSH_CTRL_FLUSH_HIER\
5296         GENMASK(regs->fsize[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] + 0 - 1, 0)
5297 #define HSCH_FLUSH_CTRL_FLUSH_HIER_SET(x)\
5298         spx5_field_prep(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
5299 #define HSCH_FLUSH_CTRL_FLUSH_HIER_GET(x)\
5300         spx5_field_get(HSCH_FLUSH_CTRL_FLUSH_HIER, x)
5301
5302 /* HSCH:SYSTEM:PORT_MODE */
5303 #define HSCH_PORT_MODE(r)                                                      \
5304         __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 8, r, \
5305               regs->rcnt[RC_HSCH_PORT_MODE], 4)
5306
5307 #define HSCH_PORT_MODE_DEQUEUE_DIS               BIT(4)
5308 #define HSCH_PORT_MODE_DEQUEUE_DIS_SET(x)\
5309         FIELD_PREP(HSCH_PORT_MODE_DEQUEUE_DIS, x)
5310 #define HSCH_PORT_MODE_DEQUEUE_DIS_GET(x)\
5311         FIELD_GET(HSCH_PORT_MODE_DEQUEUE_DIS, x)
5312
5313 #define HSCH_PORT_MODE_AGE_DIS                   BIT(3)
5314 #define HSCH_PORT_MODE_AGE_DIS_SET(x)\
5315         FIELD_PREP(HSCH_PORT_MODE_AGE_DIS, x)
5316 #define HSCH_PORT_MODE_AGE_DIS_GET(x)\
5317         FIELD_GET(HSCH_PORT_MODE_AGE_DIS, x)
5318
5319 #define HSCH_PORT_MODE_TRUNC_ENA                 BIT(2)
5320 #define HSCH_PORT_MODE_TRUNC_ENA_SET(x)\
5321         FIELD_PREP(HSCH_PORT_MODE_TRUNC_ENA, x)
5322 #define HSCH_PORT_MODE_TRUNC_ENA_GET(x)\
5323         FIELD_GET(HSCH_PORT_MODE_TRUNC_ENA, x)
5324
5325 #define HSCH_PORT_MODE_EIR_REMARK_ENA            BIT(1)
5326 #define HSCH_PORT_MODE_EIR_REMARK_ENA_SET(x)\
5327         FIELD_PREP(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
5328 #define HSCH_PORT_MODE_EIR_REMARK_ENA_GET(x)\
5329         FIELD_GET(HSCH_PORT_MODE_EIR_REMARK_ENA, x)
5330
5331 #define HSCH_PORT_MODE_CPU_PRIO_MODE             BIT(0)
5332 #define HSCH_PORT_MODE_CPU_PRIO_MODE_SET(x)\
5333         FIELD_PREP(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
5334 #define HSCH_PORT_MODE_CPU_PRIO_MODE_GET(x)\
5335         FIELD_GET(HSCH_PORT_MODE_CPU_PRIO_MODE, x)
5336
5337 /* HSCH:SYSTEM:OUTB_SHARE_ENA */
5338 #define HSCH_OUTB_SHARE_ENA(r)                                                 \
5339         __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_SYSTEM], 0, 1, 312, 288,  \
5340               r, 5, 4)
5341
5342 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA       GENMASK(7, 0)
5343 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_SET(x)\
5344         FIELD_PREP(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
5345 #define HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA_GET(x)\
5346         FIELD_GET(HSCH_OUTB_SHARE_ENA_OUTB_SHARE_ENA, x)
5347
5348 /* HSCH:MMGT:RESET_CFG */
5349 #define HSCH_RESET_CFG                                                         \
5350         __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_MMGT], 0, 1, 16, 8, 0, 1, \
5351               4)
5352
5353 #define HSCH_RESET_CFG_CORE_ENA                  BIT(0)
5354 #define HSCH_RESET_CFG_CORE_ENA_SET(x)\
5355         FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x)
5356 #define HSCH_RESET_CFG_CORE_ENA_GET(x)\
5357         FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x)
5358
5359 /* HSCH:TAS_CONFIG:TAS_STATEMACHINE_CFG */
5360 #define HSCH_TAS_STATEMACHINE_CFG                                              \
5361         __REG(TARGET_HSCH, 0, 1, regs->gaddr[GA_HSCH_TAS_CONFIG], 0, 1,        \
5362               regs->gsize[GW_HSCH_TAS_CONFIG], 8, 0, 1, 4)
5363
5364 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY    GENMASK(7, 0)
5365 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_SET(x)\
5366         FIELD_PREP(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
5367 #define HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY_GET(x)\
5368         FIELD_GET(HSCH_TAS_STATEMACHINE_CFG_REVISIT_DLY, x)
5369
5370 /* LRN:COMMON:COMMON_ACCESS_CTRL */
5371 #define LRN_COMMON_ACCESS_CTRL                                                 \
5372         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)
5373
5374 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL GENMASK(21, 20)
5375 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_SET(x)\
5376         FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
5377 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL_GET(x)\
5378         FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_COL, x)
5379
5380 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE BIT(19)
5381 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_SET(x)\
5382         FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
5383 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE_GET(x)\
5384         FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_TYPE, x)
5385
5386 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW\
5387         GENMASK(regs->fsize[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] + 5 - 1, 5)
5388 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_SET(x)\
5389         spx5_field_prep(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
5390 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW_GET(x)\
5391         spx5_field_get(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW, x)
5392
5393 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD    GENMASK(4, 1)
5394 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x)\
5395         FIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
5396 #define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x)\
5397         FIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)
5398
5399 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0)
5400 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x)\
5401         FIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
5402 #define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x)\
5403         FIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)
5404
5405 /* LRN:COMMON:MAC_ACCESS_CFG_0 */
5406 #define LRN_MAC_ACCESS_CFG_0                                                   \
5407         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)
5408
5409 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID       GENMASK(28, 16)
5410 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_SET(x)\
5411         FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
5412 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID_GET(x)\
5413         FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_FID, x)
5414
5415 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB   GENMASK(15, 0)
5416 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_SET(x)\
5417         FIELD_PREP(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
5418 #define LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB_GET(x)\
5419         FIELD_GET(LRN_MAC_ACCESS_CFG_0_MAC_ENTRY_MAC_MSB, x)
5420
5421 /* LRN:COMMON:MAC_ACCESS_CFG_1 */
5422 #define LRN_MAC_ACCESS_CFG_1                                                   \
5423         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)
5424
5425 /* LRN:COMMON:MAC_ACCESS_CFG_2 */
5426 #define LRN_MAC_ACCESS_CFG_2                                                   \
5427         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4)
5428
5429 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD BIT(28)
5430 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_SET(x)\
5431         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
5432 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD_GET(x)\
5433         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_SRC_KILL_FWD, x)
5434
5435 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL BIT(27)
5436 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_SET(x)\
5437         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
5438 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL_GET(x)\
5439         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_NXT_LRN_ALL, x)
5440
5441 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU    GENMASK(26, 24)
5442 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x)\
5443         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
5444 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x)\
5445         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)
5446
5447 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY  BIT(23)
5448 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x)\
5449         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
5450 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x)\
5451         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)
5452
5453 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE BIT(22)
5454 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_SET(x)\
5455         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
5456 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE_GET(x)\
5457         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLAN_IGNORE, x)
5458
5459 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR    BIT(21)
5460 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_SET(x)\
5461         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
5462 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR_GET(x)\
5463         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_MIRROR, x)
5464
5465 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG  GENMASK(20, 19)
5466 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_SET(x)\
5467         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
5468 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG_GET(x)\
5469         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_FLAG, x)
5470
5471 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL GENMASK(18, 17)
5472 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_SET(x)\
5473         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
5474 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL_GET(x)\
5475         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_AGE_INTERVAL, x)
5476
5477 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED    BIT(16)
5478 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x)\
5479         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
5480 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x)\
5481         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)
5482
5483 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD       BIT(15)
5484 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x)\
5485         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
5486 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x)\
5487         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)
5488
5489 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12)
5490 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x)\
5491         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
5492 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x)\
5493         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)
5494
5495 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR      GENMASK(11, 0)
5496 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x)\
5497         FIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
5498 #define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x)\
5499         FIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)
5500
5501 /* LRN:COMMON:MAC_ACCESS_CFG_3 */
5502 #define LRN_MAC_ACCESS_CFG_3                                                   \
5503         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 16, 0, 1, 4)
5504
5505 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX\
5506         GENMASK(regs->fsize[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] + 0 - 1, 0)
5507 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x)\
5508         spx5_field_prep(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
5509 #define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x)\
5510         spx5_field_get(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)
5511
5512 /* LRN:COMMON:SCAN_NEXT_CFG */
5513 #define LRN_SCAN_NEXT_CFG                                                      \
5514         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4)
5515
5516 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL GENMASK(21, 19)
5517 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_SET(x)\
5518         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
5519 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL_GET(x)\
5520         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FLAG_UPDATE_SEL, x)
5521
5522 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL GENMASK(18, 17)
5523 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_SET(x)\
5524         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
5525 #define LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL_GET(x)\
5526         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NXT_LRN_ALL_UPDATE_SEL, x)
5527
5528 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL    GENMASK(16, 15)
5529 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_SET(x)\
5530         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
5531 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL_GET(x)\
5532         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_FILTER_SEL, x)
5533
5534 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA BIT(14)
5535 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_SET(x)\
5536         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
5537 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA_GET(x)\
5538         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_MOVE_FOUND_ENA, x)
5539
5540 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA BIT(13)
5541 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_SET(x)\
5542         FIELD_PREP(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
5543 #define LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA_GET(x)\
5544         FIELD_GET(LRN_SCAN_NEXT_CFG_NXT_LRN_ALL_FILTER_ENA, x)
5545
5546 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA BIT(12)
5547 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_SET(x)\
5548         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
5549 #define LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA_GET(x)\
5550         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_USE_PORT_FILTER_ENA, x)
5551
5552 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA BIT(11)
5553 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_SET(x)\
5554         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
5555 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA_GET(x)\
5556         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_REMOVE_FOUND_ENA, x)
5557
5558 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10)
5559 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x)\
5560         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
5561 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x)\
5562         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)
5563
5564 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA BIT(9)
5565 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_SET(x)\
5566         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
5567 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA_GET(x)\
5568         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_INC_AGE_BITS_ENA, x)
5569
5570 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA BIT(8)
5571 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_SET(x)\
5572         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
5573 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA_GET(x)\
5574         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_AGED_ONLY_ENA, x)
5575
5576 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7)
5577 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x)\
5578         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
5579 #define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x)\
5580         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)
5581
5582 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK GENMASK(6, 3)
5583 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_SET(x)\
5584         FIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
5585 #define LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK_GET(x)\
5586         FIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_AGE_INTERVAL_MASK, x)
5587
5588 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA BIT(2)
5589 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_SET(x)\
5590         FIELD_PREP(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
5591 #define LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA_GET(x)\
5592         FIELD_GET(LRN_SCAN_NEXT_CFG_ISDX_LIMIT_IDX_FILTER_ENA, x)
5593
5594 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA         BIT(1)
5595 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_SET(x)\
5596         FIELD_PREP(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
5597 #define LRN_SCAN_NEXT_CFG_FID_FILTER_ENA_GET(x)\
5598         FIELD_GET(LRN_SCAN_NEXT_CFG_FID_FILTER_ENA, x)
5599
5600 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA        BIT(0)
5601 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_SET(x)\
5602         FIELD_PREP(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
5603 #define LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA_GET(x)\
5604         FIELD_GET(LRN_SCAN_NEXT_CFG_ADDR_FILTER_ENA, x)
5605
5606 /* LRN:COMMON:SCAN_NEXT_CFG_1 */
5607 #define LRN_SCAN_NEXT_CFG_1                                                    \
5608         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 24, 0, 1, 4)
5609
5610 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR   GENMASK(30, 16)
5611 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_SET(x)\
5612         FIELD_PREP(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
5613 #define LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR_GET(x)\
5614         FIELD_GET(LRN_SCAN_NEXT_CFG_1_PORT_MOVE_NEW_ADDR, x)
5615
5616 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK GENMASK(14, 0)
5617 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_SET(x)\
5618         FIELD_PREP(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
5619 #define LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK_GET(x)\
5620         FIELD_GET(LRN_SCAN_NEXT_CFG_1_SCAN_ENTRY_ADDR_MASK, x)
5621
5622 /* LRN:COMMON:AUTOAGE_CFG */
5623 #define LRN_AUTOAGE_CFG(r)                                                     \
5624         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 36, r, 4, 4)
5625
5626 #define LRN_AUTOAGE_CFG_UNIT_SIZE                GENMASK(29, 28)
5627 #define LRN_AUTOAGE_CFG_UNIT_SIZE_SET(x)\
5628         FIELD_PREP(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
5629 #define LRN_AUTOAGE_CFG_UNIT_SIZE_GET(x)\
5630         FIELD_GET(LRN_AUTOAGE_CFG_UNIT_SIZE, x)
5631
5632 #define LRN_AUTOAGE_CFG_PERIOD_VAL               GENMASK(27, 0)
5633 #define LRN_AUTOAGE_CFG_PERIOD_VAL_SET(x)\
5634         FIELD_PREP(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
5635 #define LRN_AUTOAGE_CFG_PERIOD_VAL_GET(x)\
5636         FIELD_GET(LRN_AUTOAGE_CFG_PERIOD_VAL, x)
5637
5638 /* LRN:COMMON:AUTOAGE_CFG_1 */
5639 #define LRN_AUTOAGE_CFG_1                                                      \
5640         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 52, 0, 1, 4)
5641
5642 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA     BIT(25)
5643 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_SET(x)\
5644         FIELD_PREP(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
5645 #define LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA_GET(x)\
5646         FIELD_GET(LRN_AUTOAGE_CFG_1_PAUSE_AUTO_AGE_ENA, x)
5647
5648 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN GENMASK(24, 15)
5649 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_SET(x)\
5650         FIELD_PREP(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
5651 #define LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN_GET(x)\
5652         FIELD_GET(LRN_AUTOAGE_CFG_1_CELLS_BETWEEN_ENTRY_SCAN, x)
5653
5654 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS        GENMASK(14, 7)
5655 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_SET(x)\
5656         FIELD_PREP(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
5657 #define LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS_GET(x)\
5658         FIELD_GET(LRN_AUTOAGE_CFG_1_CLK_PERIOD_01NS, x)
5659
5660 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA    BIT(6)
5661 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_SET(x)\
5662         FIELD_PREP(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
5663 #define LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA_GET(x)\
5664         FIELD_GET(LRN_AUTOAGE_CFG_1_USE_PORT_FILTER_ENA, x)
5665
5666 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT     GENMASK(5, 2)
5667 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_SET(x)\
5668         FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
5669 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT_GET(x)\
5670         FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_SHOT, x)
5671
5672 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT BIT(1)
5673 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_SET(x)\
5674         FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
5675 #define LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT_GET(x)\
5676         FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_HW_SCAN_STOP_SHOT, x)
5677
5678 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA         BIT(0)
5679 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_SET(x)\
5680         FIELD_PREP(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
5681 #define LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA_GET(x)\
5682         FIELD_GET(LRN_AUTOAGE_CFG_1_FORCE_IDLE_ENA, x)
5683
5684 /* LRN:COMMON:AUTOAGE_CFG_2 */
5685 #define LRN_AUTOAGE_CFG_2                                                      \
5686         __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 56, 0, 1, 4)
5687
5688 #define LRN_AUTOAGE_CFG_2_NEXT_ROW\
5689         GENMASK(regs->fsize[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] + 4 - 1, 4)
5690 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_SET(x)\
5691         spx5_field_prep(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
5692 #define LRN_AUTOAGE_CFG_2_NEXT_ROW_GET(x)\
5693         spx5_field_get(LRN_AUTOAGE_CFG_2_NEXT_ROW, x)
5694
5695 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS    GENMASK(3, 0)
5696 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_SET(x)\
5697         FIELD_PREP(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
5698 #define LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS_GET(x)\
5699         FIELD_GET(LRN_AUTOAGE_CFG_2_SCAN_ONGOING_STATUS, x)
5700
5701 /* SPARX5 ONLY */
5702 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_REGION_CTRL_2_OFF_OUTBOUND_0 */
5703 #define PCEP_RCTRL_2_OUT_0                                                     \
5704         __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 4, 0, 1, 4)
5705
5706 #define PCEP_RCTRL_2_OUT_0_MSG_CODE              GENMASK(7, 0)
5707 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_SET(x)\
5708         FIELD_PREP(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
5709 #define PCEP_RCTRL_2_OUT_0_MSG_CODE_GET(x)\
5710         FIELD_GET(PCEP_RCTRL_2_OUT_0_MSG_CODE, x)
5711
5712 #define PCEP_RCTRL_2_OUT_0_TAG                   GENMASK(15, 8)
5713 #define PCEP_RCTRL_2_OUT_0_TAG_SET(x)\
5714         FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG, x)
5715 #define PCEP_RCTRL_2_OUT_0_TAG_GET(x)\
5716         FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG, x)
5717
5718 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN     BIT(16)
5719 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_SET(x)\
5720         FIELD_PREP(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
5721 #define PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN_GET(x)\
5722         FIELD_GET(PCEP_RCTRL_2_OUT_0_TAG_SUBSTITUTE_EN, x)
5723
5724 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS           BIT(19)
5725 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_SET(x)\
5726         FIELD_PREP(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
5727 #define PCEP_RCTRL_2_OUT_0_FUNC_BYPASS_GET(x)\
5728         FIELD_GET(PCEP_RCTRL_2_OUT_0_FUNC_BYPASS, x)
5729
5730 #define PCEP_RCTRL_2_OUT_0_SNP                   BIT(20)
5731 #define PCEP_RCTRL_2_OUT_0_SNP_SET(x)\
5732         FIELD_PREP(PCEP_RCTRL_2_OUT_0_SNP, x)
5733 #define PCEP_RCTRL_2_OUT_0_SNP_GET(x)\
5734         FIELD_GET(PCEP_RCTRL_2_OUT_0_SNP, x)
5735
5736 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD       BIT(22)
5737 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_SET(x)\
5738         FIELD_PREP(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
5739 #define PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD_GET(x)\
5740         FIELD_GET(PCEP_RCTRL_2_OUT_0_INHIBIT_PAYLOAD, x)
5741
5742 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN  BIT(23)
5743 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_SET(x)\
5744         FIELD_PREP(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
5745 #define PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN_GET(x)\
5746         FIELD_GET(PCEP_RCTRL_2_OUT_0_HEADER_SUBSTITUTE_EN, x)
5747
5748 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE        BIT(28)
5749 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_SET(x)\
5750         FIELD_PREP(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
5751 #define PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE_GET(x)\
5752         FIELD_GET(PCEP_RCTRL_2_OUT_0_CFG_SHIFT_MODE, x)
5753
5754 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE           BIT(29)
5755 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_SET(x)\
5756         FIELD_PREP(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
5757 #define PCEP_RCTRL_2_OUT_0_INVERT_MODE_GET(x)\
5758         FIELD_GET(PCEP_RCTRL_2_OUT_0_INVERT_MODE, x)
5759
5760 #define PCEP_RCTRL_2_OUT_0_REGION_EN             BIT(31)
5761 #define PCEP_RCTRL_2_OUT_0_REGION_EN_SET(x)\
5762         FIELD_PREP(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
5763 #define PCEP_RCTRL_2_OUT_0_REGION_EN_GET(x)\
5764         FIELD_GET(PCEP_RCTRL_2_OUT_0_REGION_EN, x)
5765
5766 /* SPARX5 ONLY */
5767 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_BASE_ADDR_OFF_OUTBOUND_0 */
5768 #define PCEP_ADDR_LWR_OUT_0                                                    \
5769         __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 8, 0, 1, 4)
5770
5771 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW          GENMASK(15, 0)
5772 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_SET(x)\
5773         FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
5774 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW_GET(x)\
5775         FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_HW, x)
5776
5777 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW          GENMASK(31, 16)
5778 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_SET(x)\
5779         FIELD_PREP(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
5780 #define PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW_GET(x)\
5781         FIELD_GET(PCEP_ADDR_LWR_OUT_0_LWR_BASE_RW, x)
5782
5783 /* SPARX5 ONLY */
5784 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_0 */
5785 #define PCEP_ADDR_UPR_OUT_0                                                    \
5786         __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 12, 0, 1, 4)
5787
5788 /* SPARX5 ONLY */
5789 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LIMIT_ADDR_OFF_OUTBOUND_0 */
5790 #define PCEP_ADDR_LIM_OUT_0                                                    \
5791         __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 16, 0, 1, 4)
5792
5793 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW        GENMASK(15, 0)
5794 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_SET(x)\
5795         FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
5796 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW_GET(x)\
5797         FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_HW, x)
5798
5799 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW        GENMASK(31, 16)
5800 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_SET(x)\
5801         FIELD_PREP(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
5802 #define PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW_GET(x)\
5803         FIELD_GET(PCEP_ADDR_LIM_OUT_0_LIMIT_ADDR_RW, x)
5804
5805 /* SPARX5 ONLY */
5806 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_0 */
5807 #define PCEP_ADDR_LWR_TGT_OUT_0                                                \
5808         __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 20, 0, 1, 4)
5809
5810 /* SPARX5 ONLY */
5811 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_0 */
5812 #define PCEP_ADDR_UPR_TGT_OUT_0                                                \
5813         __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 24, 0, 1, 4)
5814
5815 /* SPARX5 ONLY */
5816 /* PCIE_DM_EP:PF0_ATU_CAP:IATU_UPPR_LIMIT_ADDR_OFF_OUTBOUND_0 */
5817 #define PCEP_ADDR_UPR_LIM_OUT_0                                                \
5818         __REG(TARGET_PCEP, 0, 1, 3145728, 0, 1, 130852, 32, 0, 1, 4)
5819
5820 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW GENMASK(1, 0)
5821 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_SET(x)\
5822         FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
5823 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW_GET(x)\
5824         FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_RW, x)
5825
5826 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW GENMASK(31, 2)
5827 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_SET(x)\
5828         FIELD_PREP(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
5829 #define PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW_GET(x)\
5830         FIELD_GET(PCEP_ADDR_UPR_LIM_OUT_0_UPPR_LIMIT_ADDR_HW, x)
5831
5832 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
5833 #define PCS10G_BR_PCS_CFG(t)                                                   \
5834         __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 0,  \
5835               0, 1, 4)
5836
5837 #define PCS10G_BR_PCS_CFG_PCS_ENA                BIT(31)
5838 #define PCS10G_BR_PCS_CFG_PCS_ENA_SET(x)\
5839         FIELD_PREP(PCS10G_BR_PCS_CFG_PCS_ENA, x)
5840 #define PCS10G_BR_PCS_CFG_PCS_ENA_GET(x)\
5841         FIELD_GET(PCS10G_BR_PCS_CFG_PCS_ENA, x)
5842
5843 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA       BIT(30)
5844 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
5845         FIELD_PREP(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5846 #define PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
5847         FIELD_GET(PCS10G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5848
5849 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX             GENMASK(29, 24)
5850 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
5851         FIELD_PREP(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
5852 #define PCS10G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
5853         FIELD_GET(PCS10G_BR_PCS_CFG_SH_CNT_MAX, x)
5854
5855 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP           BIT(18)
5856 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
5857         FIELD_PREP(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
5858 #define PCS10G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
5859         FIELD_GET(PCS10G_BR_PCS_CFG_RX_DATA_FLIP, x)
5860
5861 #define PCS10G_BR_PCS_CFG_RESYNC_ENA             BIT(15)
5862 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
5863         FIELD_PREP(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
5864 #define PCS10G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
5865         FIELD_GET(PCS10G_BR_PCS_CFG_RESYNC_ENA, x)
5866
5867 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS             BIT(14)
5868 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
5869         FIELD_PREP(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
5870 #define PCS10G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
5871         FIELD_GET(PCS10G_BR_PCS_CFG_LF_GEN_DIS, x)
5872
5873 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE           BIT(13)
5874 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
5875         FIELD_PREP(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
5876 #define PCS10G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
5877         FIELD_GET(PCS10G_BR_PCS_CFG_RX_TEST_MODE, x)
5878
5879 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE         BIT(12)
5880 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
5881         FIELD_PREP(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5882 #define PCS10G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
5883         FIELD_GET(PCS10G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5884
5885 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP           BIT(7)
5886 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
5887         FIELD_PREP(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
5888 #define PCS10G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
5889         FIELD_GET(PCS10G_BR_PCS_CFG_TX_DATA_FLIP, x)
5890
5891 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA       BIT(6)
5892 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
5893         FIELD_PREP(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5894 #define PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
5895         FIELD_GET(PCS10G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5896
5897 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE           BIT(4)
5898 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
5899         FIELD_PREP(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
5900 #define PCS10G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
5901         FIELD_GET(PCS10G_BR_PCS_CFG_TX_TEST_MODE, x)
5902
5903 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE         BIT(3)
5904 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
5905         FIELD_PREP(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5906 #define PCS10G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
5907         FIELD_GET(PCS10G_BR_PCS_CFG_TX_SCR_DISABLE, x)
5908
5909 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
5910 #define PCS10G_BR_PCS_SD_CFG(t)                                                \
5911         __REG(TARGET_PCS10G_BR, t, regs->tsize[TC_PCS10G_BR], 0, 0, 1, 56, 4,  \
5912               0, 1, 4)
5913
5914 #define PCS10G_BR_PCS_SD_CFG_SD_SEL              BIT(8)
5915 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
5916         FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
5917 #define PCS10G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
5918         FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_SEL, x)
5919
5920 #define PCS10G_BR_PCS_SD_CFG_SD_POL              BIT(4)
5921 #define PCS10G_BR_PCS_SD_CFG_SD_POL_SET(x)\
5922         FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
5923 #define PCS10G_BR_PCS_SD_CFG_SD_POL_GET(x)\
5924         FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_POL, x)
5925
5926 #define PCS10G_BR_PCS_SD_CFG_SD_ENA              BIT(0)
5927 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
5928         FIELD_PREP(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
5929 #define PCS10G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
5930         FIELD_GET(PCS10G_BR_PCS_SD_CFG_SD_ENA, x)
5931
5932 /* SPARX5 ONLY */
5933 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
5934 #define PCS25G_BR_PCS_CFG(t)                                                   \
5935         __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 0, 0, 1, 4)
5936
5937 #define PCS25G_BR_PCS_CFG_PCS_ENA                BIT(31)
5938 #define PCS25G_BR_PCS_CFG_PCS_ENA_SET(x)\
5939         FIELD_PREP(PCS25G_BR_PCS_CFG_PCS_ENA, x)
5940 #define PCS25G_BR_PCS_CFG_PCS_ENA_GET(x)\
5941         FIELD_GET(PCS25G_BR_PCS_CFG_PCS_ENA, x)
5942
5943 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA       BIT(30)
5944 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
5945         FIELD_PREP(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5946 #define PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
5947         FIELD_GET(PCS25G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
5948
5949 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX             GENMASK(29, 24)
5950 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
5951         FIELD_PREP(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
5952 #define PCS25G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
5953         FIELD_GET(PCS25G_BR_PCS_CFG_SH_CNT_MAX, x)
5954
5955 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP           BIT(18)
5956 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
5957         FIELD_PREP(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
5958 #define PCS25G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
5959         FIELD_GET(PCS25G_BR_PCS_CFG_RX_DATA_FLIP, x)
5960
5961 #define PCS25G_BR_PCS_CFG_RESYNC_ENA             BIT(15)
5962 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
5963         FIELD_PREP(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
5964 #define PCS25G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
5965         FIELD_GET(PCS25G_BR_PCS_CFG_RESYNC_ENA, x)
5966
5967 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS             BIT(14)
5968 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
5969         FIELD_PREP(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
5970 #define PCS25G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
5971         FIELD_GET(PCS25G_BR_PCS_CFG_LF_GEN_DIS, x)
5972
5973 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE           BIT(13)
5974 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
5975         FIELD_PREP(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
5976 #define PCS25G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
5977         FIELD_GET(PCS25G_BR_PCS_CFG_RX_TEST_MODE, x)
5978
5979 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE         BIT(12)
5980 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
5981         FIELD_PREP(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5982 #define PCS25G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
5983         FIELD_GET(PCS25G_BR_PCS_CFG_RX_SCR_DISABLE, x)
5984
5985 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP           BIT(7)
5986 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
5987         FIELD_PREP(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
5988 #define PCS25G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
5989         FIELD_GET(PCS25G_BR_PCS_CFG_TX_DATA_FLIP, x)
5990
5991 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA       BIT(6)
5992 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
5993         FIELD_PREP(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5994 #define PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
5995         FIELD_GET(PCS25G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
5996
5997 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE           BIT(4)
5998 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
5999         FIELD_PREP(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
6000 #define PCS25G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
6001         FIELD_GET(PCS25G_BR_PCS_CFG_TX_TEST_MODE, x)
6002
6003 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE         BIT(3)
6004 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
6005         FIELD_PREP(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
6006 #define PCS25G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
6007         FIELD_GET(PCS25G_BR_PCS_CFG_TX_SCR_DISABLE, x)
6008
6009 /* SPARX5 ONLY */
6010 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
6011 #define PCS25G_BR_PCS_SD_CFG(t)                                                \
6012         __REG(TARGET_PCS25G_BR, t, 8, 0, 0, 1, 56, 4, 0, 1, 4)
6013
6014 #define PCS25G_BR_PCS_SD_CFG_SD_SEL              BIT(8)
6015 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
6016         FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
6017 #define PCS25G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
6018         FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_SEL, x)
6019
6020 #define PCS25G_BR_PCS_SD_CFG_SD_POL              BIT(4)
6021 #define PCS25G_BR_PCS_SD_CFG_SD_POL_SET(x)\
6022         FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
6023 #define PCS25G_BR_PCS_SD_CFG_SD_POL_GET(x)\
6024         FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_POL, x)
6025
6026 #define PCS25G_BR_PCS_SD_CFG_SD_ENA              BIT(0)
6027 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
6028         FIELD_PREP(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
6029 #define PCS25G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
6030         FIELD_GET(PCS25G_BR_PCS_SD_CFG_SD_ENA, x)
6031
6032 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_CFG */
6033 #define PCS5G_BR_PCS_CFG(t)                                                    \
6034         __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 0, 0, \
6035               1, 4)
6036
6037 #define PCS5G_BR_PCS_CFG_PCS_ENA                 BIT(31)
6038 #define PCS5G_BR_PCS_CFG_PCS_ENA_SET(x)\
6039         FIELD_PREP(PCS5G_BR_PCS_CFG_PCS_ENA, x)
6040 #define PCS5G_BR_PCS_CFG_PCS_ENA_GET(x)\
6041         FIELD_GET(PCS5G_BR_PCS_CFG_PCS_ENA, x)
6042
6043 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA        BIT(30)
6044 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_SET(x)\
6045         FIELD_PREP(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
6046 #define PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA_GET(x)\
6047         FIELD_GET(PCS5G_BR_PCS_CFG_PMA_LOOPBACK_ENA, x)
6048
6049 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX              GENMASK(29, 24)
6050 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_SET(x)\
6051         FIELD_PREP(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
6052 #define PCS5G_BR_PCS_CFG_SH_CNT_MAX_GET(x)\
6053         FIELD_GET(PCS5G_BR_PCS_CFG_SH_CNT_MAX, x)
6054
6055 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP            BIT(18)
6056 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_SET(x)\
6057         FIELD_PREP(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
6058 #define PCS5G_BR_PCS_CFG_RX_DATA_FLIP_GET(x)\
6059         FIELD_GET(PCS5G_BR_PCS_CFG_RX_DATA_FLIP, x)
6060
6061 #define PCS5G_BR_PCS_CFG_RESYNC_ENA              BIT(15)
6062 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_SET(x)\
6063         FIELD_PREP(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
6064 #define PCS5G_BR_PCS_CFG_RESYNC_ENA_GET(x)\
6065         FIELD_GET(PCS5G_BR_PCS_CFG_RESYNC_ENA, x)
6066
6067 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS              BIT(14)
6068 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_SET(x)\
6069         FIELD_PREP(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
6070 #define PCS5G_BR_PCS_CFG_LF_GEN_DIS_GET(x)\
6071         FIELD_GET(PCS5G_BR_PCS_CFG_LF_GEN_DIS, x)
6072
6073 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE            BIT(13)
6074 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_SET(x)\
6075         FIELD_PREP(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
6076 #define PCS5G_BR_PCS_CFG_RX_TEST_MODE_GET(x)\
6077         FIELD_GET(PCS5G_BR_PCS_CFG_RX_TEST_MODE, x)
6078
6079 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE          BIT(12)
6080 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_SET(x)\
6081         FIELD_PREP(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
6082 #define PCS5G_BR_PCS_CFG_RX_SCR_DISABLE_GET(x)\
6083         FIELD_GET(PCS5G_BR_PCS_CFG_RX_SCR_DISABLE, x)
6084
6085 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP            BIT(7)
6086 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_SET(x)\
6087         FIELD_PREP(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
6088 #define PCS5G_BR_PCS_CFG_TX_DATA_FLIP_GET(x)\
6089         FIELD_GET(PCS5G_BR_PCS_CFG_TX_DATA_FLIP, x)
6090
6091 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA        BIT(6)
6092 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_SET(x)\
6093         FIELD_PREP(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
6094 #define PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA_GET(x)\
6095         FIELD_GET(PCS5G_BR_PCS_CFG_AN_LINK_CTRL_ENA, x)
6096
6097 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE            BIT(4)
6098 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_SET(x)\
6099         FIELD_PREP(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
6100 #define PCS5G_BR_PCS_CFG_TX_TEST_MODE_GET(x)\
6101         FIELD_GET(PCS5G_BR_PCS_CFG_TX_TEST_MODE, x)
6102
6103 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE          BIT(3)
6104 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_SET(x)\
6105         FIELD_PREP(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
6106 #define PCS5G_BR_PCS_CFG_TX_SCR_DISABLE_GET(x)\
6107         FIELD_GET(PCS5G_BR_PCS_CFG_TX_SCR_DISABLE, x)
6108
6109 /* PCS_10GBASE_R:PCS_10GBR_CFG:PCS_SD_CFG */
6110 #define PCS5G_BR_PCS_SD_CFG(t)                                                 \
6111         __REG(TARGET_PCS5G_BR, t, regs->tsize[TC_PCS5G_BR], 0, 0, 1, 56, 4, 0, \
6112               1, 4)
6113
6114 #define PCS5G_BR_PCS_SD_CFG_SD_SEL               BIT(8)
6115 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_SET(x)\
6116         FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
6117 #define PCS5G_BR_PCS_SD_CFG_SD_SEL_GET(x)\
6118         FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_SEL, x)
6119
6120 #define PCS5G_BR_PCS_SD_CFG_SD_POL               BIT(4)
6121 #define PCS5G_BR_PCS_SD_CFG_SD_POL_SET(x)\
6122         FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
6123 #define PCS5G_BR_PCS_SD_CFG_SD_POL_GET(x)\
6124         FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_POL, x)
6125
6126 #define PCS5G_BR_PCS_SD_CFG_SD_ENA               BIT(0)
6127 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_SET(x)\
6128         FIELD_PREP(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
6129 #define PCS5G_BR_PCS_SD_CFG_SD_ENA_GET(x)\
6130         FIELD_GET(PCS5G_BR_PCS_SD_CFG_SD_ENA, x)
6131
6132 /* PORT_CONF:HW_CFG:DEV5G_MODES */
6133 #define PORT_CONF_DEV5G_MODES                                                  \
6134         __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4)
6135
6136 /* SPARX5 ONLY */
6137 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE      BIT(0)
6138 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_SET(x)\
6139         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
6140 #define PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE_GET(x)\
6141         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D0_MODE, x)
6142
6143 /* SPARX5 ONLY */
6144 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE      BIT(1)
6145 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_SET(x)\
6146         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
6147 #define PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE_GET(x)\
6148         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D1_MODE, x)
6149
6150 /* SPARX5 ONLY */
6151 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE      BIT(2)
6152 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_SET(x)\
6153         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
6154 #define PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE_GET(x)\
6155         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D2_MODE, x)
6156
6157 /* SPARX5 ONLY */
6158 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE      BIT(3)
6159 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_SET(x)\
6160         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
6161 #define PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE_GET(x)\
6162         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D3_MODE, x)
6163
6164 /* SPARX5 ONLY */
6165 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE      BIT(4)
6166 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_SET(x)\
6167         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
6168 #define PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE_GET(x)\
6169         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D4_MODE, x)
6170
6171 /* SPARX5 ONLY */
6172 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE      BIT(5)
6173 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_SET(x)\
6174         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
6175 #define PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE_GET(x)\
6176         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D5_MODE, x)
6177
6178 /* SPARX5 ONLY */
6179 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE      BIT(6)
6180 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_SET(x)\
6181         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
6182 #define PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE_GET(x)\
6183         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D6_MODE, x)
6184
6185 /* SPARX5 ONLY */
6186 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE      BIT(7)
6187 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_SET(x)\
6188         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
6189 #define PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE_GET(x)\
6190         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D7_MODE, x)
6191
6192 /* SPARX5 ONLY */
6193 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE      BIT(8)
6194 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_SET(x)\
6195         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
6196 #define PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE_GET(x)\
6197         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D8_MODE, x)
6198
6199 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE      BIT(9)
6200 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_SET(x)\
6201         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
6202 #define PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE_GET(x)\
6203         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D9_MODE, x)
6204
6205 /* SPARX5 ONLY */
6206 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE     BIT(10)
6207 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_SET(x)\
6208         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
6209 #define PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE_GET(x)\
6210         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D10_MODE, x)
6211
6212 /* SPARX5 ONLY */
6213 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE     BIT(11)
6214 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_SET(x)\
6215         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
6216 #define PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE_GET(x)\
6217         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D11_MODE, x)
6218
6219 /* SPARX5 ONLY */
6220 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE     BIT(12)
6221 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x)\
6222         FIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
6223 #define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x)\
6224         FIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)
6225
6226 /* PORT_CONF:HW_CFG:DEV10G_MODES */
6227 #define PORT_CONF_DEV10G_MODES                                                 \
6228         __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4)
6229
6230 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE   BIT(0)
6231 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_SET(x)\
6232         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
6233 #define PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE_GET(x)\
6234         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D12_MODE, x)
6235
6236 /* SPARX5 ONLY */
6237 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE   BIT(1)
6238 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_SET(x)\
6239         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
6240 #define PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE_GET(x)\
6241         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D13_MODE, x)
6242
6243 /* SPARX5 ONLY */
6244 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE   BIT(2)
6245 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_SET(x)\
6246         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
6247 #define PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE_GET(x)\
6248         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D14_MODE, x)
6249
6250 /* SPARX5 ONLY */
6251 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE   BIT(3)
6252 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_SET(x)\
6253         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
6254 #define PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE_GET(x)\
6255         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D15_MODE, x)
6256
6257 /* SPARX5 ONLY */
6258 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE   BIT(4)
6259 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_SET(x)\
6260         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
6261 #define PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE_GET(x)\
6262         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D48_MODE, x)
6263
6264 /* SPARX5 ONLY */
6265 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE   BIT(5)
6266 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_SET(x)\
6267         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
6268 #define PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE_GET(x)\
6269         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D49_MODE, x)
6270
6271 /* SPARX5 ONLY */
6272 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE   BIT(6)
6273 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_SET(x)\
6274         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
6275 #define PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE_GET(x)\
6276         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D50_MODE, x)
6277
6278 /* SPARX5 ONLY */
6279 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE   BIT(7)
6280 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_SET(x)\
6281         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
6282 #define PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE_GET(x)\
6283         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D51_MODE, x)
6284
6285 /* SPARX5 ONLY */
6286 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE   BIT(8)
6287 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_SET(x)\
6288         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
6289 #define PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE_GET(x)\
6290         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D52_MODE, x)
6291
6292 /* SPARX5 ONLY */
6293 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE   BIT(9)
6294 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_SET(x)\
6295         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
6296 #define PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE_GET(x)\
6297         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D53_MODE, x)
6298
6299 /* SPARX5 ONLY */
6300 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE   BIT(10)
6301 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_SET(x)\
6302         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
6303 #define PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE_GET(x)\
6304         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D54_MODE, x)
6305
6306 /* SPARX5 ONLY */
6307 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE   BIT(11)
6308 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_SET(x)\
6309         FIELD_PREP(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
6310 #define PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE_GET(x)\
6311         FIELD_GET(PORT_CONF_DEV10G_MODES_DEV10G_D55_MODE, x)
6312
6313 /* SPARX5 ONLY */
6314 /* PORT_CONF:HW_CFG:DEV25G_MODES */
6315 #define PORT_CONF_DEV25G_MODES                                                 \
6316         __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4)
6317
6318 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE   BIT(0)
6319 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_SET(x)\
6320         FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
6321 #define PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE_GET(x)\
6322         FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D56_MODE, x)
6323
6324 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE   BIT(1)
6325 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_SET(x)\
6326         FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
6327 #define PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE_GET(x)\
6328         FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D57_MODE, x)
6329
6330 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE   BIT(2)
6331 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_SET(x)\
6332         FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
6333 #define PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE_GET(x)\
6334         FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D58_MODE, x)
6335
6336 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE   BIT(3)
6337 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_SET(x)\
6338         FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
6339 #define PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE_GET(x)\
6340         FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D59_MODE, x)
6341
6342 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE   BIT(4)
6343 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_SET(x)\
6344         FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
6345 #define PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE_GET(x)\
6346         FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D60_MODE, x)
6347
6348 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE   BIT(5)
6349 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_SET(x)\
6350         FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
6351 #define PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE_GET(x)\
6352         FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D61_MODE, x)
6353
6354 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE   BIT(6)
6355 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_SET(x)\
6356         FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
6357 #define PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE_GET(x)\
6358         FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D62_MODE, x)
6359
6360 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE   BIT(7)
6361 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_SET(x)\
6362         FIELD_PREP(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
6363 #define PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE_GET(x)\
6364         FIELD_GET(PORT_CONF_DEV25G_MODES_DEV25G_D63_MODE, x)
6365
6366 /* PORT_CONF:HW_CFG:QSGMII_ENA */
6367 #define PORT_CONF_QSGMII_ENA                                                   \
6368         __REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4)
6369
6370 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0        BIT(0)
6371 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_SET(x)\
6372         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
6373 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_0_GET(x)\
6374         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_0, x)
6375
6376 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1        BIT(1)
6377 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_SET(x)\
6378         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
6379 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_1_GET(x)\
6380         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_1, x)
6381
6382 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2        BIT(2)
6383 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_SET(x)\
6384         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
6385 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_2_GET(x)\
6386         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_2, x)
6387
6388 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3        BIT(3)
6389 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_SET(x)\
6390         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
6391 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_3_GET(x)\
6392         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_3, x)
6393
6394 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4        BIT(4)
6395 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_SET(x)\
6396         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
6397 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_4_GET(x)\
6398         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_4, x)
6399
6400 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5        BIT(5)
6401 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_SET(x)\
6402         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
6403 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_5_GET(x)\
6404         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_5, x)
6405
6406 /* SPARX5 ONLY */
6407 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6        BIT(6)
6408 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_SET(x)\
6409         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
6410 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_6_GET(x)\
6411         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_6, x)
6412
6413 /* SPARX5 ONLY */
6414 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7        BIT(7)
6415 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_SET(x)\
6416         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
6417 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_7_GET(x)\
6418         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_7, x)
6419
6420 /* SPARX5 ONLY */
6421 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8        BIT(8)
6422 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_SET(x)\
6423         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
6424 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_8_GET(x)\
6425         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_8, x)
6426
6427 /* SPARX5 ONLY */
6428 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9        BIT(9)
6429 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_SET(x)\
6430         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
6431 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_9_GET(x)\
6432         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_9, x)
6433
6434 /* SPARX5 ONLY */
6435 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10       BIT(10)
6436 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_SET(x)\
6437         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
6438 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_10_GET(x)\
6439         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_10, x)
6440
6441 /* SPARX5 ONLY */
6442 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11       BIT(11)
6443 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_SET(x)\
6444         FIELD_PREP(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
6445 #define PORT_CONF_QSGMII_ENA_QSGMII_ENA_11_GET(x)\
6446         FIELD_GET(PORT_CONF_QSGMII_ENA_QSGMII_ENA_11, x)
6447
6448 /* SPARX5 ONLY */
6449 /* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */
6450 #define PORT_CONF_USGMII_CFG(g)                                                \
6451         __REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4)
6452
6453 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM        BIT(9)
6454 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_SET(x)\
6455         FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
6456 #define PORT_CONF_USGMII_CFG_BYPASS_SCRAM_GET(x)\
6457         FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_SCRAM, x)
6458
6459 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM      BIT(8)
6460 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_SET(x)\
6461         FIELD_PREP(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
6462 #define PORT_CONF_USGMII_CFG_BYPASS_DESCRAM_GET(x)\
6463         FIELD_GET(PORT_CONF_USGMII_CFG_BYPASS_DESCRAM, x)
6464
6465 #define PORT_CONF_USGMII_CFG_FLIP_LANES          BIT(7)
6466 #define PORT_CONF_USGMII_CFG_FLIP_LANES_SET(x)\
6467         FIELD_PREP(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
6468 #define PORT_CONF_USGMII_CFG_FLIP_LANES_GET(x)\
6469         FIELD_GET(PORT_CONF_USGMII_CFG_FLIP_LANES, x)
6470
6471 #define PORT_CONF_USGMII_CFG_SHYST_DIS           BIT(6)
6472 #define PORT_CONF_USGMII_CFG_SHYST_DIS_SET(x)\
6473         FIELD_PREP(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
6474 #define PORT_CONF_USGMII_CFG_SHYST_DIS_GET(x)\
6475         FIELD_GET(PORT_CONF_USGMII_CFG_SHYST_DIS, x)
6476
6477 #define PORT_CONF_USGMII_CFG_E_DET_ENA           BIT(5)
6478 #define PORT_CONF_USGMII_CFG_E_DET_ENA_SET(x)\
6479         FIELD_PREP(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
6480 #define PORT_CONF_USGMII_CFG_E_DET_ENA_GET(x)\
6481         FIELD_GET(PORT_CONF_USGMII_CFG_E_DET_ENA, x)
6482
6483 #define PORT_CONF_USGMII_CFG_USE_I1_ENA          BIT(4)
6484 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_SET(x)\
6485         FIELD_PREP(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
6486 #define PORT_CONF_USGMII_CFG_USE_I1_ENA_GET(x)\
6487         FIELD_GET(PORT_CONF_USGMII_CFG_USE_I1_ENA, x)
6488
6489 #define PORT_CONF_USGMII_CFG_QUAD_MODE           BIT(1)
6490 #define PORT_CONF_USGMII_CFG_QUAD_MODE_SET(x)\
6491         FIELD_PREP(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
6492 #define PORT_CONF_USGMII_CFG_QUAD_MODE_GET(x)\
6493         FIELD_GET(PORT_CONF_USGMII_CFG_QUAD_MODE, x)
6494
6495 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR */
6496 #define PTP_PTP_PIN_INTR                                                       \
6497         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 0, 0, 1,\
6498               4)
6499
6500 #define PTP_PTP_PIN_INTR_INTR_PTP\
6501         GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_INTR_PTP] + 0 - 1, 0)
6502 #define PTP_PTP_PIN_INTR_INTR_PTP_SET(x)\
6503         spx5_field_prep(PTP_PTP_PIN_INTR_INTR_PTP, x)
6504 #define PTP_PTP_PIN_INTR_INTR_PTP_GET(x)\
6505         spx5_field_get(PTP_PTP_PIN_INTR_INTR_PTP, x)
6506
6507 /* DEVCPU_PTP:PTP_CFG:PTP_PIN_INTR_ENA */
6508 #define PTP_PTP_PIN_INTR_ENA                                                   \
6509         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 4, 0, 1,\
6510               4)
6511
6512 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA\
6513         GENMASK(regs->fsize[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] + 0 - 1, 0)
6514 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_SET(x)\
6515         spx5_field_prep(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
6516 #define PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA_GET(x)\
6517         spx5_field_get(PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA, x)
6518
6519 /* DEVCPU_PTP:PTP_CFG:PTP_INTR_IDENT */
6520 #define PTP_PTP_INTR_IDENT                                                     \
6521         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 8, 0, 1,\
6522               4)
6523
6524 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT\
6525         GENMASK(regs->fsize[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] + 0 - 1, 0)
6526 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_SET(x)\
6527         spx5_field_prep(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
6528 #define PTP_PTP_INTR_IDENT_INTR_PTP_IDENT_GET(x)\
6529         spx5_field_get(PTP_PTP_INTR_IDENT_INTR_PTP_IDENT, x)
6530
6531 /* DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */
6532 #define PTP_PTP_DOM_CFG                                                        \
6533         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_CFG], 0, 1, 16, 12, 0,  \
6534               1, 4)
6535
6536 #define PTP_PTP_DOM_CFG_PTP_ENA                  GENMASK(11, 9)
6537 #define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\
6538         FIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x)
6539 #define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\
6540         FIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x)
6541
6542 #define PTP_PTP_DOM_CFG_PTP_HOLD                 GENMASK(8, 6)
6543 #define PTP_PTP_DOM_CFG_PTP_HOLD_SET(x)\
6544         FIELD_PREP(PTP_PTP_DOM_CFG_PTP_HOLD, x)
6545 #define PTP_PTP_DOM_CFG_PTP_HOLD_GET(x)\
6546         FIELD_GET(PTP_PTP_DOM_CFG_PTP_HOLD, x)
6547
6548 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE           GENMASK(5, 3)
6549 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_SET(x)\
6550         FIELD_PREP(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
6551 #define PTP_PTP_DOM_CFG_PTP_TOD_FREEZE_GET(x)\
6552         FIELD_GET(PTP_PTP_DOM_CFG_PTP_TOD_FREEZE, x)
6553
6554 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS           GENMASK(2, 0)
6555 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_SET(x)\
6556         FIELD_PREP(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
6557 #define PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS_GET(x)\
6558         FIELD_GET(PTP_PTP_DOM_CFG_PTP_CLKCFG_DIS, x)
6559
6560 /* DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */
6561 #define PTP_CLK_PER_CFG(g, r)                                                  \
6562         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6563               0, r, 2, 4)
6564
6565 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC */
6566 #define PTP_PTP_CUR_NSEC(g)                                                    \
6567         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6568               8, 0, 1, 4)
6569
6570 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC            GENMASK(29, 0)
6571 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_SET(x)\
6572         FIELD_PREP(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
6573 #define PTP_PTP_CUR_NSEC_PTP_CUR_NSEC_GET(x)\
6574         FIELD_GET(PTP_PTP_CUR_NSEC_PTP_CUR_NSEC, x)
6575
6576 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_NSEC_FRAC */
6577 #define PTP_PTP_CUR_NSEC_FRAC(g)                                               \
6578         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6579               12, 0, 1, 4)
6580
6581 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC  GENMASK(7, 0)
6582 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_SET(x)\
6583         FIELD_PREP(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
6584 #define PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC_GET(x)\
6585         FIELD_GET(PTP_PTP_CUR_NSEC_FRAC_PTP_CUR_NSEC_FRAC, x)
6586
6587 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_LSB */
6588 #define PTP_PTP_CUR_SEC_LSB(g)                                                 \
6589         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6590               16, 0, 1, 4)
6591
6592 /* DEVCPU_PTP:PTP_TOD_DOMAINS:PTP_CUR_SEC_MSB */
6593 #define PTP_PTP_CUR_SEC_MSB(g)                                                 \
6594         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6595               20, 0, 1, 4)
6596
6597 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB      GENMASK(15, 0)
6598 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_SET(x)\
6599         FIELD_PREP(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
6600 #define PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB_GET(x)\
6601         FIELD_GET(PTP_PTP_CUR_SEC_MSB_PTP_CUR_SEC_MSB, x)
6602
6603 /* DEVCPU_PTP:PTP_TOD_DOMAINS:NTP_CUR_NSEC */
6604 #define PTP_NTP_CUR_NSEC(g)                                                    \
6605         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PTP_TOD_DOMAINS], g, 3, 28, \
6606               24, 0, 1, 4)
6607
6608 /* DEVCPU_PTP:PTP_PINS:PTP_PIN_CFG */
6609 #define PTP_PTP_PIN_CFG(g)                                                     \
6610         __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 0, 0, 1,\
6611               4)
6612
6613 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION\
6614         GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] + 2, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION])
6615 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_SET(x)\
6616         spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
6617 #define PTP_PTP_PIN_CFG_PTP_PIN_ACTION_GET(x)\
6618         spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_ACTION, x)
6619
6620 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC\
6621         GENMASK(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] + 1, regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC])
6622 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_SET(x)\
6623         spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
6624 #define PTP_PTP_PIN_CFG_PTP_PIN_SYNC_GET(x)\
6625         spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SYNC, x)
6626
6627 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL\
6628         BIT(regs->fpos[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL])
6629 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_SET(x)\
6630         spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
6631 #define PTP_PTP_PIN_CFG_PTP_PIN_INV_POL_GET(x)\
6632         spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_INV_POL, x)
6633
6634 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT\
6635         GENMASK(regs->fsize[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] + 21 - 1, 21)
6636 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_SET(x)\
6637         spx5_field_prep(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
6638 #define PTP_PTP_PIN_CFG_PTP_PIN_SELECT_GET(x)\
6639         spx5_field_get(PTP_PTP_PIN_CFG_PTP_PIN_SELECT, x)
6640
6641 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT           GENMASK(20, 18)
6642 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_SET(x)\
6643         FIELD_PREP(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
6644 #define PTP_PTP_PIN_CFG_PTP_CLK_SELECT_GET(x)\
6645         FIELD_GET(PTP_PTP_PIN_CFG_PTP_CLK_SELECT, x)
6646
6647 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM              GENMASK(17, 16)
6648 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_SET(x)\
6649         FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
6650 #define PTP_PTP_PIN_CFG_PTP_PIN_DOM_GET(x)\
6651         FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_DOM, x)
6652
6653 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT              GENMASK(15, 14)
6654 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_SET(x)\
6655         FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
6656 #define PTP_PTP_PIN_CFG_PTP_PIN_OPT_GET(x)\
6657         FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OPT, x)
6658
6659 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK     BIT(13)
6660 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_SET(x)\
6661         FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
6662 #define PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK_GET(x)\
6663         FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_EMBEDDED_CLK, x)
6664
6665 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS         GENMASK(12, 0)
6666 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_SET(x)\
6667         FIELD_PREP(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
6668 #define PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS_GET(x)\
6669         FIELD_GET(PTP_PTP_PIN_CFG_PTP_PIN_OUTP_OFS, x)
6670
6671 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_MSB */
6672 #define PTP_PTP_TOD_SEC_MSB(g)                                                 \
6673         __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 4, 0, 1,\
6674               4)
6675
6676 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB      GENMASK(15, 0)
6677 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_SET(x)\
6678         FIELD_PREP(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
6679 #define PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB_GET(x)\
6680         FIELD_GET(PTP_PTP_TOD_SEC_MSB_PTP_TOD_SEC_MSB, x)
6681
6682 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_SEC_LSB */
6683 #define PTP_PTP_TOD_SEC_LSB(g)                                                 \
6684         __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 8, 0, 1,\
6685               4)
6686
6687 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC */
6688 #define PTP_PTP_TOD_NSEC(g)                                                    \
6689         __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 12, 0,  \
6690               1, 4)
6691
6692 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC            GENMASK(29, 0)
6693 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_SET(x)\
6694         FIELD_PREP(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
6695 #define PTP_PTP_TOD_NSEC_PTP_TOD_NSEC_GET(x)\
6696         FIELD_GET(PTP_PTP_TOD_NSEC_PTP_TOD_NSEC, x)
6697
6698 /* DEVCPU_PTP:PTP_PINS:PTP_TOD_NSEC_FRAC */
6699 #define PTP_PTP_TOD_NSEC_FRAC(g)                                               \
6700         __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 16, 0,  \
6701               1, 4)
6702
6703 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC  GENMASK(7, 0)
6704 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_SET(x)\
6705         FIELD_PREP(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
6706 #define PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC_GET(x)\
6707         FIELD_GET(PTP_PTP_TOD_NSEC_FRAC_PTP_TOD_NSEC_FRAC, x)
6708
6709 /* DEVCPU_PTP:PTP_PINS:NTP_NSEC */
6710 #define PTP_NTP_NSEC(g)                                                        \
6711         __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 20, 0,  \
6712               1, 4)
6713
6714 /* DEVCPU_PTP:PTP_PINS:PIN_WF_HIGH_PERIOD */
6715 #define PTP_PIN_WF_HIGH_PERIOD(g)                                              \
6716         __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 24, 0,  \
6717               1, 4)
6718
6719 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH           GENMASK(29, 0)
6720 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_SET(x)\
6721         FIELD_PREP(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
6722 #define PTP_PIN_WF_HIGH_PERIOD_PIN_WFH_GET(x)\
6723         FIELD_GET(PTP_PIN_WF_HIGH_PERIOD_PIN_WFH, x)
6724
6725 /* DEVCPU_PTP:PTP_PINS:PIN_WF_LOW_PERIOD */
6726 #define PTP_PIN_WF_LOW_PERIOD(g)                                               \
6727         __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 28, 0,  \
6728               1, 4)
6729
6730 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL            GENMASK(29, 0)
6731 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_SET(x)\
6732         FIELD_PREP(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
6733 #define PTP_PIN_WF_LOW_PERIOD_PIN_WFL_GET(x)\
6734         FIELD_GET(PTP_PIN_WF_LOW_PERIOD_PIN_WFL, x)
6735
6736 /* DEVCPU_PTP:PTP_PINS:PIN_IOBOUNCH_DELAY */
6737 #define PTP_PIN_IOBOUNCH_DELAY(g)                                              \
6738         __REG(TARGET_PTP, 0, 1, 0, g, regs->gcnt[GC_PTP_PTP_PINS], 64, 32, 0,  \
6739               1, 4)
6740
6741 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL  GENMASK(18, 3)
6742 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_SET(x)\
6743         FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
6744 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL_GET(x)\
6745         FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_VAL, x)
6746
6747 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG  GENMASK(2, 0)
6748 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_SET(x)\
6749         FIELD_PREP(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
6750 #define PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG_GET(x)\
6751         FIELD_GET(PTP_PIN_IOBOUNCH_DELAY_PIN_IOBOUNCH_CFG, x)
6752
6753 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CTRL */
6754 #define PTP_PHAD_CTRL(g)                                                       \
6755         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g,    \
6756               regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL],                          \
6757               regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 0, 0, 1, 4)
6758
6759 #define PTP_PHAD_CTRL_PHAD_ENA\
6760         BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_ENA])
6761 #define PTP_PHAD_CTRL_PHAD_ENA_SET(x)\
6762         spx5_field_prep(PTP_PHAD_CTRL_PHAD_ENA, x)
6763 #define PTP_PHAD_CTRL_PHAD_ENA_GET(x)\
6764         spx5_field_get(PTP_PHAD_CTRL_PHAD_ENA, x)
6765
6766 #define PTP_PHAD_CTRL_PHAD_FAILED\
6767         BIT(regs->fpos[FP_PTP_PHAD_CTRL_PHAD_FAILED])
6768 #define PTP_PHAD_CTRL_PHAD_FAILED_SET(x)\
6769         spx5_field_prep(PTP_PHAD_CTRL_PHAD_FAILED, x)
6770 #define PTP_PHAD_CTRL_PHAD_FAILED_GET(x)\
6771         spx5_field_get(PTP_PHAD_CTRL_PHAD_FAILED, x)
6772
6773 /* SPARX5 ONLY */
6774 #define PTP_PHAD_CTRL_REDUCED_RES                GENMASK(5, 3)
6775 #define PTP_PHAD_CTRL_REDUCED_RES_SET(x)\
6776         FIELD_PREP(PTP_PHAD_CTRL_REDUCED_RES, x)
6777 #define PTP_PHAD_CTRL_REDUCED_RES_GET(x)\
6778         FIELD_GET(PTP_PHAD_CTRL_REDUCED_RES, x)
6779
6780 #define PTP_PHAD_CTRL_LOCK_ACC                   GENMASK(2, 0)
6781 #define PTP_PHAD_CTRL_LOCK_ACC_SET(x)\
6782         FIELD_PREP(PTP_PHAD_CTRL_LOCK_ACC, x)
6783 #define PTP_PHAD_CTRL_LOCK_ACC_GET(x)\
6784         FIELD_GET(PTP_PHAD_CTRL_LOCK_ACC, x)
6785
6786 /* DEVCPU_PTP:PHASE_DETECTOR_CTRL:PHAD_CYC_STAT */
6787 #define PTP_PHAD_CYC_STAT(g)                                                   \
6788         __REG(TARGET_PTP, 0, 1, regs->gaddr[GA_PTP_PHASE_DETECTOR_CTRL], g,    \
6789               regs->gcnt[GC_PTP_PHASE_DETECTOR_CTRL],                          \
6790               regs->gsize[GW_PTP_PHASE_DETECTOR_CTRL], 4, 0, 1, 4)
6791
6792 /* LAN969X ONLY */
6793 /* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_CTRL */
6794 #define PTP_TWOSTEP_CTRL                                                       \
6795         __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 0, 0, 1, 4)
6796
6797 #define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA            BIT(12)
6798 #define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\
6799         FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
6800 #define PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\
6801         FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
6802
6803 #define PTP_TWOSTEP_CTRL_PTP_NXT                 BIT(11)
6804 #define PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\
6805         FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_NXT, x)
6806 #define PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\
6807         FIELD_GET(PTP_TWOSTEP_CTRL_PTP_NXT, x)
6808
6809 #define PTP_TWOSTEP_CTRL_PTP_VLD                 BIT(10)
6810 #define PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\
6811         FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_VLD, x)
6812 #define PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\
6813         FIELD_GET(PTP_TWOSTEP_CTRL_PTP_VLD, x)
6814
6815 #define PTP_TWOSTEP_CTRL_STAMP_TX                BIT(9)
6816 #define PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
6817         FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_TX, x)
6818 #define PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
6819         FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_TX, x)
6820
6821 #define PTP_TWOSTEP_CTRL_STAMP_PORT              GENMASK(8, 1)
6822 #define PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
6823         FIELD_PREP(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
6824 #define PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
6825         FIELD_GET(PTP_TWOSTEP_CTRL_STAMP_PORT, x)
6826
6827 #define PTP_TWOSTEP_CTRL_PTP_OVFL                BIT(0)
6828 #define PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\
6829         FIELD_PREP(PTP_TWOSTEP_CTRL_PTP_OVFL, x)
6830 #define PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\
6831         FIELD_GET(PTP_TWOSTEP_CTRL_PTP_OVFL, x)
6832
6833 /* LAN969X ONLY */
6834 /* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_NSEC */
6835 #define PTP_TWOSTEP_STAMP_NSEC                                                 \
6836         __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 4, 0, 1, 4)
6837
6838 #define PTP_TWOSTEP_STAMP_NSEC_NS                GENMASK(29, 0)
6839 #define PTP_TWOSTEP_STAMP_NSEC_NS_SET(x)\
6840         FIELD_PREP(PTP_TWOSTEP_STAMP_NSEC_NS, x)
6841 #define PTP_TWOSTEP_STAMP_NSEC_NS_GET(x)\
6842         FIELD_GET(PTP_TWOSTEP_STAMP_NSEC_NS, x)
6843
6844 /* LAN969X ONLY */
6845 /* DEVCPU_PTP:PTP_TS_FIFO:PTP_TWOSTEP_STAMP_SUBNS */
6846 #define PTP_TWOSTEP_STAMP_SUBNS                                                \
6847         __REG(TARGET_PTP, 0, 1, 612, 0, 1, 16, 8, 0, 1, 4)
6848
6849 #define PTP_TWOSTEP_STAMP_SUBNS_NS               GENMASK(7, 0)
6850 #define PTP_TWOSTEP_STAMP_SUBNS_NS_SET(x)\
6851         FIELD_PREP(PTP_TWOSTEP_STAMP_SUBNS_NS, x)
6852 #define PTP_TWOSTEP_STAMP_SUBNS_NS_GET(x)\
6853         FIELD_GET(PTP_TWOSTEP_STAMP_SUBNS_NS, x)
6854
6855 /* QFWD:SYSTEM:SWITCH_PORT_MODE */
6856 #define QFWD_SWITCH_PORT_MODE(r)                                               \
6857         __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r,                           \
6858               regs->rcnt[RC_QFWD_SWITCH_PORT_MODE], 4)
6859
6860 #define QFWD_SWITCH_PORT_MODE_PORT_ENA           BIT(19)
6861 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x)\
6862         FIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
6863 #define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x)\
6864         FIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)
6865
6866 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY        GENMASK(18, 10)
6867 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_SET(x)\
6868         FIELD_PREP(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
6869 #define QFWD_SWITCH_PORT_MODE_FWD_URGENCY_GET(x)\
6870         FIELD_GET(QFWD_SWITCH_PORT_MODE_FWD_URGENCY, x)
6871
6872 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD          GENMASK(9, 6)
6873 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_SET(x)\
6874         FIELD_PREP(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
6875 #define QFWD_SWITCH_PORT_MODE_YEL_RSRVD_GET(x)\
6876         FIELD_GET(QFWD_SWITCH_PORT_MODE_YEL_RSRVD, x)
6877
6878 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE  BIT(5)
6879 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_SET(x)\
6880         FIELD_PREP(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
6881 #define QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE_GET(x)\
6882         FIELD_GET(QFWD_SWITCH_PORT_MODE_INGRESS_DROP_MODE, x)
6883
6884 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING     BIT(4)
6885 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_SET(x)\
6886         FIELD_PREP(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
6887 #define QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING_GET(x)\
6888         FIELD_GET(QFWD_SWITCH_PORT_MODE_IGR_NO_SHARING, x)
6889
6890 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING     BIT(3)
6891 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_SET(x)\
6892         FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
6893 #define QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING_GET(x)\
6894         FIELD_GET(QFWD_SWITCH_PORT_MODE_EGR_NO_SHARING, x)
6895
6896 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE   BIT(2)
6897 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_SET(x)\
6898         FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
6899 #define QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE_GET(x)\
6900         FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_DROP_MODE, x)
6901
6902 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS    BIT(1)
6903 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_SET(x)\
6904         FIELD_PREP(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
6905 #define QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS_GET(x)\
6906         FIELD_GET(QFWD_SWITCH_PORT_MODE_EGRESS_RSRV_DIS, x)
6907
6908 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE      BIT(0)
6909 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_SET(x)\
6910         FIELD_PREP(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
6911 #define QFWD_SWITCH_PORT_MODE_LEARNALL_MORE_GET(x)\
6912         FIELD_GET(QFWD_SWITCH_PORT_MODE_LEARNALL_MORE, x)
6913
6914 /* QFWD:SYSTEM:FRAME_COPY_CFG */
6915 #define QFWD_FRAME_COPY_CFG(r)                                                 \
6916         __REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 284, r, 12, 4)
6917
6918 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL\
6919         GENMASK(regs->fsize[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] + 6 - 1, 6)
6920 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_SET(x)\
6921         spx5_field_prep(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x)
6922 #define QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL_GET(x)\
6923         spx5_field_get(QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL, x)
6924
6925 /* QRES:RES_CTRL:RES_CFG */
6926 #define QRES_RES_CFG(g)                                                        \
6927         __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 0, 0, 1, 4)
6928
6929 #define QRES_RES_CFG_WM_HIGH\
6930         GENMASK(regs->fsize[FW_QRES_RES_CFG_WM_HIGH] + 0 - 1, 0)
6931 #define QRES_RES_CFG_WM_HIGH_SET(x)\
6932         spx5_field_prep(QRES_RES_CFG_WM_HIGH, x)
6933 #define QRES_RES_CFG_WM_HIGH_GET(x)\
6934         spx5_field_get(QRES_RES_CFG_WM_HIGH, x)
6935
6936 /* QRES:RES_CTRL:RES_STAT */
6937 #define QRES_RES_STAT(g)                                                       \
6938         __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 4, 0, 1, 4)
6939
6940 #define QRES_RES_STAT_MAXUSE\
6941         GENMASK(regs->fsize[FW_QRES_RES_STAT_MAXUSE] + 0 - 1, 0)
6942 #define QRES_RES_STAT_MAXUSE_SET(x)\
6943         spx5_field_prep(QRES_RES_STAT_MAXUSE, x)
6944 #define QRES_RES_STAT_MAXUSE_GET(x)\
6945         spx5_field_get(QRES_RES_STAT_MAXUSE, x)
6946
6947 /* QRES:RES_CTRL:RES_STAT_CUR */
6948 #define QRES_RES_STAT_CUR(g)                                                   \
6949         __REG(TARGET_QRES, 0, 1, 0, g, 5120, 16, 8, 0, 1, 4)
6950
6951 #define QRES_RES_STAT_CUR_INUSE\
6952         GENMASK(regs->fsize[FW_QRES_RES_STAT_CUR_INUSE] + 0 - 1, 0)
6953 #define QRES_RES_STAT_CUR_INUSE_SET(x)\
6954         spx5_field_prep(QRES_RES_STAT_CUR_INUSE, x)
6955 #define QRES_RES_STAT_CUR_INUSE_GET(x)\
6956         spx5_field_get(QRES_RES_STAT_CUR_INUSE, x)
6957
6958 /* DEVCPU_QS:XTR:XTR_GRP_CFG */
6959 #define QS_XTR_GRP_CFG(r)                                                      \
6960         __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)
6961
6962 #define QS_XTR_GRP_CFG_MODE                      GENMASK(3, 2)
6963 #define QS_XTR_GRP_CFG_MODE_SET(x)\
6964         FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)
6965 #define QS_XTR_GRP_CFG_MODE_GET(x)\
6966         FIELD_GET(QS_XTR_GRP_CFG_MODE, x)
6967
6968 #define QS_XTR_GRP_CFG_STATUS_WORD_POS           BIT(1)
6969 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x)\
6970         FIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
6971 #define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x)\
6972         FIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)
6973
6974 #define QS_XTR_GRP_CFG_BYTE_SWAP                 BIT(0)
6975 #define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x)\
6976         FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)
6977 #define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x)\
6978         FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)
6979
6980 /* DEVCPU_QS:XTR:XTR_RD */
6981 #define QS_XTR_RD(r)                                                           \
6982         __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 8, r, 2, 4)
6983
6984 /* DEVCPU_QS:XTR:XTR_FLUSH */
6985 #define QS_XTR_FLUSH                                                           \
6986         __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 24, 0, 1, 4)
6987
6988 #define QS_XTR_FLUSH_FLUSH                       GENMASK(1, 0)
6989 #define QS_XTR_FLUSH_FLUSH_SET(x)\
6990         FIELD_PREP(QS_XTR_FLUSH_FLUSH, x)
6991 #define QS_XTR_FLUSH_FLUSH_GET(x)\
6992         FIELD_GET(QS_XTR_FLUSH_FLUSH, x)
6993
6994 /* DEVCPU_QS:XTR:XTR_DATA_PRESENT */
6995 #define QS_XTR_DATA_PRESENT                                                    \
6996         __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 28, 0, 1, 4)
6997
6998 #define QS_XTR_DATA_PRESENT_DATA_PRESENT         GENMASK(1, 0)
6999 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_SET(x)\
7000         FIELD_PREP(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
7001 #define QS_XTR_DATA_PRESENT_DATA_PRESENT_GET(x)\
7002         FIELD_GET(QS_XTR_DATA_PRESENT_DATA_PRESENT, x)
7003
7004 /* DEVCPU_QS:INJ:INJ_GRP_CFG */
7005 #define QS_INJ_GRP_CFG(r)                                                      \
7006         __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)
7007
7008 #define QS_INJ_GRP_CFG_MODE                      GENMASK(3, 2)
7009 #define QS_INJ_GRP_CFG_MODE_SET(x)\
7010         FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)
7011 #define QS_INJ_GRP_CFG_MODE_GET(x)\
7012         FIELD_GET(QS_INJ_GRP_CFG_MODE, x)
7013
7014 #define QS_INJ_GRP_CFG_BYTE_SWAP                 BIT(0)
7015 #define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x)\
7016         FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)
7017 #define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x)\
7018         FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)
7019
7020 /* DEVCPU_QS:INJ:INJ_WR */
7021 #define QS_INJ_WR(r)                                                           \
7022         __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 8, r, 2, 4)
7023
7024 /* DEVCPU_QS:INJ:INJ_CTRL */
7025 #define QS_INJ_CTRL(r)                                                         \
7026         __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 16, r, 2, 4)
7027
7028 #define QS_INJ_CTRL_GAP_SIZE                     GENMASK(24, 21)
7029 #define QS_INJ_CTRL_GAP_SIZE_SET(x)\
7030         FIELD_PREP(QS_INJ_CTRL_GAP_SIZE, x)
7031 #define QS_INJ_CTRL_GAP_SIZE_GET(x)\
7032         FIELD_GET(QS_INJ_CTRL_GAP_SIZE, x)
7033
7034 #define QS_INJ_CTRL_ABORT                        BIT(20)
7035 #define QS_INJ_CTRL_ABORT_SET(x)\
7036         FIELD_PREP(QS_INJ_CTRL_ABORT, x)
7037 #define QS_INJ_CTRL_ABORT_GET(x)\
7038         FIELD_GET(QS_INJ_CTRL_ABORT, x)
7039
7040 #define QS_INJ_CTRL_EOF                          BIT(19)
7041 #define QS_INJ_CTRL_EOF_SET(x)\
7042         FIELD_PREP(QS_INJ_CTRL_EOF, x)
7043 #define QS_INJ_CTRL_EOF_GET(x)\
7044         FIELD_GET(QS_INJ_CTRL_EOF, x)
7045
7046 #define QS_INJ_CTRL_SOF                          BIT(18)
7047 #define QS_INJ_CTRL_SOF_SET(x)\
7048         FIELD_PREP(QS_INJ_CTRL_SOF, x)
7049 #define QS_INJ_CTRL_SOF_GET(x)\
7050         FIELD_GET(QS_INJ_CTRL_SOF, x)
7051
7052 #define QS_INJ_CTRL_VLD_BYTES                    GENMASK(17, 16)
7053 #define QS_INJ_CTRL_VLD_BYTES_SET(x)\
7054         FIELD_PREP(QS_INJ_CTRL_VLD_BYTES, x)
7055 #define QS_INJ_CTRL_VLD_BYTES_GET(x)\
7056         FIELD_GET(QS_INJ_CTRL_VLD_BYTES, x)
7057
7058 /* DEVCPU_QS:INJ:INJ_STATUS */
7059 #define QS_INJ_STATUS                                                          \
7060         __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 24, 0, 1, 4)
7061
7062 #define QS_INJ_STATUS_WMARK_REACHED              GENMASK(5, 4)
7063 #define QS_INJ_STATUS_WMARK_REACHED_SET(x)\
7064         FIELD_PREP(QS_INJ_STATUS_WMARK_REACHED, x)
7065 #define QS_INJ_STATUS_WMARK_REACHED_GET(x)\
7066         FIELD_GET(QS_INJ_STATUS_WMARK_REACHED, x)
7067
7068 #define QS_INJ_STATUS_FIFO_RDY                   GENMASK(3, 2)
7069 #define QS_INJ_STATUS_FIFO_RDY_SET(x)\
7070         FIELD_PREP(QS_INJ_STATUS_FIFO_RDY, x)
7071 #define QS_INJ_STATUS_FIFO_RDY_GET(x)\
7072         FIELD_GET(QS_INJ_STATUS_FIFO_RDY, x)
7073
7074 #define QS_INJ_STATUS_INJ_IN_PROGRESS            GENMASK(1, 0)
7075 #define QS_INJ_STATUS_INJ_IN_PROGRESS_SET(x)\
7076         FIELD_PREP(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
7077 #define QS_INJ_STATUS_INJ_IN_PROGRESS_GET(x)\
7078         FIELD_GET(QS_INJ_STATUS_INJ_IN_PROGRESS, x)
7079
7080 /* QSYS:PAUSE_CFG:PAUSE_CFG */
7081 #define QSYS_PAUSE_CFG(r)                                                      \
7082         __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG], 0, \
7083               r, regs->rcnt[RC_QSYS_PAUSE_CFG], 4)
7084
7085 #define QSYS_PAUSE_CFG_PAUSE_START\
7086         GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_START] + 14 - 1, 14)
7087 #define QSYS_PAUSE_CFG_PAUSE_START_SET(x)\
7088         spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_START, x)
7089 #define QSYS_PAUSE_CFG_PAUSE_START_GET(x)\
7090         spx5_field_get(QSYS_PAUSE_CFG_PAUSE_START, x)
7091
7092 #define QSYS_PAUSE_CFG_PAUSE_STOP\
7093         GENMASK(regs->fsize[FW_QSYS_PAUSE_CFG_PAUSE_STOP] + 2 - 1, 2)
7094 #define QSYS_PAUSE_CFG_PAUSE_STOP_SET(x)\
7095         spx5_field_prep(QSYS_PAUSE_CFG_PAUSE_STOP, x)
7096 #define QSYS_PAUSE_CFG_PAUSE_STOP_GET(x)\
7097         spx5_field_get(QSYS_PAUSE_CFG_PAUSE_STOP, x)
7098
7099 #define QSYS_PAUSE_CFG_PAUSE_ENA                 BIT(1)
7100 #define QSYS_PAUSE_CFG_PAUSE_ENA_SET(x)\
7101         FIELD_PREP(QSYS_PAUSE_CFG_PAUSE_ENA, x)
7102 #define QSYS_PAUSE_CFG_PAUSE_ENA_GET(x)\
7103         FIELD_GET(QSYS_PAUSE_CFG_PAUSE_ENA, x)
7104
7105 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA   BIT(0)
7106 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_SET(x)\
7107         FIELD_PREP(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
7108 #define QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA_GET(x)\
7109         FIELD_GET(QSYS_PAUSE_CFG_AGGRESSIVE_TAILDROP_ENA, x)
7110
7111 /* QSYS:PAUSE_CFG:ATOP */
7112 #define QSYS_ATOP(r)                                                           \
7113         __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG],    \
7114               284, r, regs->rcnt[RC_QSYS_ATOP], 4)
7115
7116 #define QSYS_ATOP_ATOP\
7117         GENMASK(regs->fsize[FW_QSYS_ATOP_ATOP] + 0 - 1, 0)
7118 #define QSYS_ATOP_ATOP_SET(x)\
7119         spx5_field_prep(QSYS_ATOP_ATOP, x)
7120 #define QSYS_ATOP_ATOP_GET(x)\
7121         spx5_field_get(QSYS_ATOP_ATOP, x)
7122
7123 /* QSYS:PAUSE_CFG:FWD_PRESSURE */
7124 #define QSYS_FWD_PRESSURE(r)                                                   \
7125         __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG],    \
7126               564, r, regs->rcnt[RC_QSYS_FWD_PRESSURE], 4)
7127
7128 #define QSYS_FWD_PRESSURE_FWD_PRESSURE           GENMASK(11, 1)
7129 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_SET(x)\
7130         FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
7131 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_GET(x)\
7132         FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE, x)
7133
7134 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS       BIT(0)
7135 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_SET(x)\
7136         FIELD_PREP(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
7137 #define QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS_GET(x)\
7138         FIELD_GET(QSYS_FWD_PRESSURE_FWD_PRESSURE_DIS, x)
7139
7140 /* QSYS:PAUSE_CFG:ATOP_TOT_CFG */
7141 #define QSYS_ATOP_TOT_CFG                                                      \
7142         __REG(TARGET_QSYS, 0, 1, 544, 0, 1, regs->gsize[GW_QSYS_PAUSE_CFG],    \
7143               844, 0, 1, 4)
7144
7145 #define QSYS_ATOP_TOT_CFG_ATOP_TOT\
7146         GENMASK(regs->fsize[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] + 0 - 1, 0)
7147 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_SET(x)\
7148         spx5_field_prep(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
7149 #define QSYS_ATOP_TOT_CFG_ATOP_TOT_GET(x)\
7150         spx5_field_get(QSYS_ATOP_TOT_CFG_ATOP_TOT, x)
7151
7152 /* QSYS:CALCFG:CAL_AUTO */
7153 #define QSYS_CAL_AUTO(r)                                                       \
7154         __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 0, r,  \
7155               regs->rcnt[RC_QSYS_CAL_AUTO], 4)
7156
7157 #define QSYS_CAL_AUTO_CAL_AUTO                   GENMASK(29, 0)
7158 #define QSYS_CAL_AUTO_CAL_AUTO_SET(x)\
7159         FIELD_PREP(QSYS_CAL_AUTO_CAL_AUTO, x)
7160 #define QSYS_CAL_AUTO_CAL_AUTO_GET(x)\
7161         FIELD_GET(QSYS_CAL_AUTO_CAL_AUTO, x)
7162
7163 /* QSYS:CALCFG:CAL_CTRL */
7164 #define QSYS_CAL_CTRL                                                          \
7165         __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_CALCFG], 0, 1, 40, 36, 0, \
7166               1, 4)
7167
7168 #define QSYS_CAL_CTRL_CAL_MODE                   GENMASK(14, 11)
7169 #define QSYS_CAL_CTRL_CAL_MODE_SET(x)\
7170         FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x)
7171 #define QSYS_CAL_CTRL_CAL_MODE_GET(x)\
7172         FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x)
7173
7174 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE        GENMASK(10, 1)
7175 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_SET(x)\
7176         FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
7177 #define QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE_GET(x)\
7178         FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_GRANT_RATE, x)
7179
7180 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR             BIT(0)
7181 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_SET(x)\
7182         FIELD_PREP(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
7183 #define QSYS_CAL_CTRL_CAL_AUTO_ERROR_GET(x)\
7184         FIELD_GET(QSYS_CAL_CTRL_CAL_AUTO_ERROR, x)
7185
7186 /* QSYS:RAM_CTRL:RAM_INIT */
7187 #define QSYS_RAM_INIT                                                          \
7188         __REG(TARGET_QSYS, 0, 1, regs->gaddr[GA_QSYS_RAM_CTRL], 0, 1, 4, 0, 0, \
7189               1, 4)
7190
7191 #define QSYS_RAM_INIT_RAM_INIT                   BIT(1)
7192 #define QSYS_RAM_INIT_RAM_INIT_SET(x)\
7193         FIELD_PREP(QSYS_RAM_INIT_RAM_INIT, x)
7194 #define QSYS_RAM_INIT_RAM_INIT_GET(x)\
7195         FIELD_GET(QSYS_RAM_INIT_RAM_INIT, x)
7196
7197 #define QSYS_RAM_INIT_RAM_CFG_HOOK               BIT(0)
7198 #define QSYS_RAM_INIT_RAM_CFG_HOOK_SET(x)\
7199         FIELD_PREP(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
7200 #define QSYS_RAM_INIT_RAM_CFG_HOOK_GET(x)\
7201         FIELD_GET(QSYS_RAM_INIT_RAM_CFG_HOOK, x)
7202
7203 /* REW:COMMON:OWN_UPSID */
7204 #define REW_OWN_UPSID(r)                                                       \
7205         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 0, r,  \
7206               regs->rcnt[RC_REW_OWN_UPSID], 4)
7207
7208 #define REW_OWN_UPSID_OWN_UPSID                  GENMASK(4, 0)
7209 #define REW_OWN_UPSID_OWN_UPSID_SET(x)\
7210         FIELD_PREP(REW_OWN_UPSID_OWN_UPSID, x)
7211 #define REW_OWN_UPSID_OWN_UPSID_GET(x)\
7212         FIELD_GET(REW_OWN_UPSID_OWN_UPSID, x)
7213
7214 /* REW:COMMON:RTAG_ETAG_CTRL */
7215 #define REW_RTAG_ETAG_CTRL(r)                                                  \
7216         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 560, r,\
7217               regs->rcnt[RC_REW_RTAG_ETAG_CTRL], 4)
7218
7219 #define REW_RTAG_ETAG_CTRL_IPE_TBL\
7220         GENMASK(regs->fsize[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] + 3 - 1, 3)
7221 #define REW_RTAG_ETAG_CTRL_IPE_TBL_SET(x)\
7222         spx5_field_prep(REW_RTAG_ETAG_CTRL_IPE_TBL, x)
7223 #define REW_RTAG_ETAG_CTRL_IPE_TBL_GET(x)\
7224         spx5_field_get(REW_RTAG_ETAG_CTRL_IPE_TBL, x)
7225
7226 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA      GENMASK(2, 1)
7227 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_SET(x)\
7228         FIELD_PREP(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x)
7229 #define REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA_GET(x)\
7230         FIELD_GET(REW_RTAG_ETAG_CTRL_ES0_ISDX_KEY_ENA, x)
7231
7232 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG             BIT(0)
7233 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_SET(x)\
7234         FIELD_PREP(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x)
7235 #define REW_RTAG_ETAG_CTRL_KEEP_ETAG_GET(x)\
7236         FIELD_GET(REW_RTAG_ETAG_CTRL_KEEP_ETAG, x)
7237
7238 /* REW:COMMON:ES0_CTRL */
7239 #define REW_ES0_CTRL                                                           \
7240         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_COMMON], 0, 1, 1232, 852, 0,\
7241               1, 4)
7242
7243 #define REW_ES0_CTRL_ES0_BY_RT_FWD               BIT(5)
7244 #define REW_ES0_CTRL_ES0_BY_RT_FWD_SET(x)\
7245         FIELD_PREP(REW_ES0_CTRL_ES0_BY_RT_FWD, x)
7246 #define REW_ES0_CTRL_ES0_BY_RT_FWD_GET(x)\
7247         FIELD_GET(REW_ES0_CTRL_ES0_BY_RT_FWD, x)
7248
7249 #define REW_ES0_CTRL_ES0_BY_RLEG                 BIT(4)
7250 #define REW_ES0_CTRL_ES0_BY_RLEG_SET(x)\
7251         FIELD_PREP(REW_ES0_CTRL_ES0_BY_RLEG, x)
7252 #define REW_ES0_CTRL_ES0_BY_RLEG_GET(x)\
7253         FIELD_GET(REW_ES0_CTRL_ES0_BY_RLEG, x)
7254
7255 #define REW_ES0_CTRL_ES0_DPORT_ENA               BIT(3)
7256 #define REW_ES0_CTRL_ES0_DPORT_ENA_SET(x)\
7257         FIELD_PREP(REW_ES0_CTRL_ES0_DPORT_ENA, x)
7258 #define REW_ES0_CTRL_ES0_DPORT_ENA_GET(x)\
7259         FIELD_GET(REW_ES0_CTRL_ES0_DPORT_ENA, x)
7260
7261 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG             BIT(2)
7262 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_SET(x)\
7263         FIELD_PREP(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x)
7264 #define REW_ES0_CTRL_ES0_FRM_LBK_CFG_GET(x)\
7265         FIELD_GET(REW_ES0_CTRL_ES0_FRM_LBK_CFG, x)
7266
7267 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA        BIT(1)
7268 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_SET(x)\
7269         FIELD_PREP(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x)
7270 #define REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA_GET(x)\
7271         FIELD_GET(REW_ES0_CTRL_ES0_VD2_ENCAP_ID_ENA, x)
7272
7273 #define REW_ES0_CTRL_ES0_LU_ENA                  BIT(0)
7274 #define REW_ES0_CTRL_ES0_LU_ENA_SET(x)\
7275         FIELD_PREP(REW_ES0_CTRL_ES0_LU_ENA, x)
7276 #define REW_ES0_CTRL_ES0_LU_ENA_GET(x)\
7277         FIELD_GET(REW_ES0_CTRL_ES0_LU_ENA, x)
7278
7279 /* REW:PORT:PORT_VLAN_CFG */
7280 #define REW_PORT_VLAN_CFG(g)                                                   \
7281         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g,                   \
7282               regs->gcnt[GC_REW_PORT], 256, 0, 0, 1, 4)
7283
7284 #define REW_PORT_VLAN_CFG_PORT_PCP               GENMASK(15, 13)
7285 #define REW_PORT_VLAN_CFG_PORT_PCP_SET(x)\
7286         FIELD_PREP(REW_PORT_VLAN_CFG_PORT_PCP, x)
7287 #define REW_PORT_VLAN_CFG_PORT_PCP_GET(x)\
7288         FIELD_GET(REW_PORT_VLAN_CFG_PORT_PCP, x)
7289
7290 #define REW_PORT_VLAN_CFG_PORT_DEI               BIT(12)
7291 #define REW_PORT_VLAN_CFG_PORT_DEI_SET(x)\
7292         FIELD_PREP(REW_PORT_VLAN_CFG_PORT_DEI, x)
7293 #define REW_PORT_VLAN_CFG_PORT_DEI_GET(x)\
7294         FIELD_GET(REW_PORT_VLAN_CFG_PORT_DEI, x)
7295
7296 #define REW_PORT_VLAN_CFG_PORT_VID               GENMASK(11, 0)
7297 #define REW_PORT_VLAN_CFG_PORT_VID_SET(x)\
7298         FIELD_PREP(REW_PORT_VLAN_CFG_PORT_VID, x)
7299 #define REW_PORT_VLAN_CFG_PORT_VID_GET(x)\
7300         FIELD_GET(REW_PORT_VLAN_CFG_PORT_VID, x)
7301
7302 /* REW:PORT:PCP_MAP_DE0 */
7303 #define REW_PCP_MAP_DE0(g, r)                                                  \
7304         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g,                   \
7305               regs->gcnt[GC_REW_PORT], 256, 4, r, 8, 4)
7306
7307 #define REW_PCP_MAP_DE0_PCP_DE0                  GENMASK(2, 0)
7308 #define REW_PCP_MAP_DE0_PCP_DE0_SET(x)\
7309         FIELD_PREP(REW_PCP_MAP_DE0_PCP_DE0, x)
7310 #define REW_PCP_MAP_DE0_PCP_DE0_GET(x)\
7311         FIELD_GET(REW_PCP_MAP_DE0_PCP_DE0, x)
7312
7313 /* REW:PORT:PCP_MAP_DE1 */
7314 #define REW_PCP_MAP_DE1(g, r)                                                  \
7315         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g,                   \
7316               regs->gcnt[GC_REW_PORT], 256, 36, r, 8, 4)
7317
7318 #define REW_PCP_MAP_DE1_PCP_DE1                  GENMASK(2, 0)
7319 #define REW_PCP_MAP_DE1_PCP_DE1_SET(x)\
7320         FIELD_PREP(REW_PCP_MAP_DE1_PCP_DE1, x)
7321 #define REW_PCP_MAP_DE1_PCP_DE1_GET(x)\
7322         FIELD_GET(REW_PCP_MAP_DE1_PCP_DE1, x)
7323
7324 /* REW:PORT:DEI_MAP_DE0 */
7325 #define REW_DEI_MAP_DE0(g, r)                                                  \
7326         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g,                   \
7327               regs->gcnt[GC_REW_PORT], 256, 68, r, 8, 4)
7328
7329 #define REW_DEI_MAP_DE0_DEI_DE0                  BIT(0)
7330 #define REW_DEI_MAP_DE0_DEI_DE0_SET(x)\
7331         FIELD_PREP(REW_DEI_MAP_DE0_DEI_DE0, x)
7332 #define REW_DEI_MAP_DE0_DEI_DE0_GET(x)\
7333         FIELD_GET(REW_DEI_MAP_DE0_DEI_DE0, x)
7334
7335 /* REW:PORT:DEI_MAP_DE1 */
7336 #define REW_DEI_MAP_DE1(g, r)                                                  \
7337         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g,                   \
7338               regs->gcnt[GC_REW_PORT], 256, 100, r, 8, 4)
7339
7340 #define REW_DEI_MAP_DE1_DEI_DE1                  BIT(0)
7341 #define REW_DEI_MAP_DE1_DEI_DE1_SET(x)\
7342         FIELD_PREP(REW_DEI_MAP_DE1_DEI_DE1, x)
7343 #define REW_DEI_MAP_DE1_DEI_DE1_GET(x)\
7344         FIELD_GET(REW_DEI_MAP_DE1_DEI_DE1, x)
7345
7346 /* REW:PORT:TAG_CTRL */
7347 #define REW_TAG_CTRL(g)                                                        \
7348         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g,                   \
7349               regs->gcnt[GC_REW_PORT], 256, 132, 0, 1, 4)
7350
7351 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED     BIT(13)
7352 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_SET(x)\
7353         FIELD_PREP(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
7354 #define REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED_GET(x)\
7355         FIELD_GET(REW_TAG_CTRL_TAG_CFG_OBEY_WAS_TAGGED, x)
7356
7357 #define REW_TAG_CTRL_TAG_CFG                     GENMASK(12, 11)
7358 #define REW_TAG_CTRL_TAG_CFG_SET(x)\
7359         FIELD_PREP(REW_TAG_CTRL_TAG_CFG, x)
7360 #define REW_TAG_CTRL_TAG_CFG_GET(x)\
7361         FIELD_GET(REW_TAG_CTRL_TAG_CFG, x)
7362
7363 #define REW_TAG_CTRL_TAG_TPID_CFG                GENMASK(10, 8)
7364 #define REW_TAG_CTRL_TAG_TPID_CFG_SET(x)\
7365         FIELD_PREP(REW_TAG_CTRL_TAG_TPID_CFG, x)
7366 #define REW_TAG_CTRL_TAG_TPID_CFG_GET(x)\
7367         FIELD_GET(REW_TAG_CTRL_TAG_TPID_CFG, x)
7368
7369 #define REW_TAG_CTRL_TAG_VID_CFG                 GENMASK(7, 6)
7370 #define REW_TAG_CTRL_TAG_VID_CFG_SET(x)\
7371         FIELD_PREP(REW_TAG_CTRL_TAG_VID_CFG, x)
7372 #define REW_TAG_CTRL_TAG_VID_CFG_GET(x)\
7373         FIELD_GET(REW_TAG_CTRL_TAG_VID_CFG, x)
7374
7375 #define REW_TAG_CTRL_TAG_PCP_CFG                 GENMASK(5, 3)
7376 #define REW_TAG_CTRL_TAG_PCP_CFG_SET(x)\
7377         FIELD_PREP(REW_TAG_CTRL_TAG_PCP_CFG, x)
7378 #define REW_TAG_CTRL_TAG_PCP_CFG_GET(x)\
7379         FIELD_GET(REW_TAG_CTRL_TAG_PCP_CFG, x)
7380
7381 #define REW_TAG_CTRL_TAG_DEI_CFG                 GENMASK(2, 0)
7382 #define REW_TAG_CTRL_TAG_DEI_CFG_SET(x)\
7383         FIELD_PREP(REW_TAG_CTRL_TAG_DEI_CFG, x)
7384 #define REW_TAG_CTRL_TAG_DEI_CFG_GET(x)\
7385         FIELD_GET(REW_TAG_CTRL_TAG_DEI_CFG, x)
7386
7387 /* REW:PORT:DSCP_MAP */
7388 #define REW_DSCP_MAP(g)                                                        \
7389         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_PORT], g,                   \
7390               regs->gcnt[GC_REW_PORT], 256, 136, 0, 1, 4)
7391
7392 #define REW_DSCP_MAP_DSCP_UPDATE_ENA             BIT(1)
7393 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_SET(x)\
7394         FIELD_PREP(REW_DSCP_MAP_DSCP_UPDATE_ENA, x)
7395 #define REW_DSCP_MAP_DSCP_UPDATE_ENA_GET(x)\
7396         FIELD_GET(REW_DSCP_MAP_DSCP_UPDATE_ENA, x)
7397
7398 #define REW_DSCP_MAP_DSCP_REMAP_ENA              BIT(0)
7399 #define REW_DSCP_MAP_DSCP_REMAP_ENA_SET(x)\
7400         FIELD_PREP(REW_DSCP_MAP_DSCP_REMAP_ENA, x)
7401 #define REW_DSCP_MAP_DSCP_REMAP_ENA_GET(x)\
7402         FIELD_GET(REW_DSCP_MAP_DSCP_REMAP_ENA, x)
7403
7404 /* SPARX5 ONLY */
7405 /* REW:PTP_CTRL:PTP_TWOSTEP_CTRL */
7406 #define REW_PTP_TWOSTEP_CTRL                                                   \
7407         __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 0, 0, 1, 4)
7408
7409 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA        BIT(12)
7410 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_SET(x)\
7411         FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
7412 #define REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA_GET(x)\
7413         FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVWR_ENA, x)
7414
7415 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT             BIT(11)
7416 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_SET(x)\
7417         FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
7418 #define REW_PTP_TWOSTEP_CTRL_PTP_NXT_GET(x)\
7419         FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_NXT, x)
7420
7421 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD             BIT(10)
7422 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_SET(x)\
7423         FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
7424 #define REW_PTP_TWOSTEP_CTRL_PTP_VLD_GET(x)\
7425         FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_VLD, x)
7426
7427 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX            BIT(9)
7428 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_SET(x)\
7429         FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
7430 #define REW_PTP_TWOSTEP_CTRL_STAMP_TX_GET(x)\
7431         FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_TX, x)
7432
7433 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT          GENMASK(8, 1)
7434 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_SET(x)\
7435         FIELD_PREP(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
7436 #define REW_PTP_TWOSTEP_CTRL_STAMP_PORT_GET(x)\
7437         FIELD_GET(REW_PTP_TWOSTEP_CTRL_STAMP_PORT, x)
7438
7439 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL            BIT(0)
7440 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_SET(x)\
7441         FIELD_PREP(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
7442 #define REW_PTP_TWOSTEP_CTRL_PTP_OVFL_GET(x)\
7443         FIELD_GET(REW_PTP_TWOSTEP_CTRL_PTP_OVFL, x)
7444
7445 /* SPARX5 ONLY */
7446 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP */
7447 #define REW_PTP_TWOSTEP_STAMP                                                  \
7448         __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 4, 0, 1, 4)
7449
7450 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC         GENMASK(29, 0)
7451 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_SET(x)\
7452         FIELD_PREP(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
7453 #define REW_PTP_TWOSTEP_STAMP_STAMP_NSEC_GET(x)\
7454         FIELD_GET(REW_PTP_TWOSTEP_STAMP_STAMP_NSEC, x)
7455
7456 /* SPARX5 ONLY */
7457 /* REW:PTP_CTRL:PTP_TWOSTEP_STAMP_SUBNS */
7458 #define REW_PTP_TWOSTEP_STAMP_SUBNS                                            \
7459         __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 8, 0, 1, 4)
7460
7461 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC GENMASK(7, 0)
7462 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_SET(x)\
7463         FIELD_PREP(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
7464 #define REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC_GET(x)\
7465         FIELD_GET(REW_PTP_TWOSTEP_STAMP_SUBNS_STAMP_SUB_NSEC, x)
7466
7467 /* SPARX5 ONLY */
7468 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO */
7469 #define REW_PTP_RSRV_NOT_ZERO                                                  \
7470         __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 12, 0, 1, 4)
7471
7472 /* SPARX5 ONLY */
7473 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO1 */
7474 #define REW_PTP_RSRV_NOT_ZERO1                                                 \
7475         __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 16, 0, 1, 4)
7476
7477 /* SPARX5 ONLY */
7478 /* REW:PTP_CTRL:PTP_RSRV_NOT_ZERO2 */
7479 #define REW_PTP_RSRV_NOT_ZERO2                                                 \
7480         __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 20, 0, 1, 4)
7481
7482 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2 GENMASK(5, 0)
7483 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_SET(x)\
7484         FIELD_PREP(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
7485 #define REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2_GET(x)\
7486         FIELD_GET(REW_PTP_RSRV_NOT_ZERO2_PTP_RSRV_NOT_ZERO2, x)
7487
7488 /* SPARX5 ONLY */
7489 /* REW:PTP_CTRL:PTP_GEN_STAMP_FMT */
7490 #define REW_PTP_GEN_STAMP_FMT(r)                                               \
7491         __REG(TARGET_REW, 0, 1, 378368, 0, 1, 40, 24, r, 4, 4)
7492
7493 #define REW_PTP_GEN_STAMP_FMT_RT_OFS             GENMASK(6, 2)
7494 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_SET(x)\
7495         FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
7496 #define REW_PTP_GEN_STAMP_FMT_RT_OFS_GET(x)\
7497         FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_OFS, x)
7498
7499 #define REW_PTP_GEN_STAMP_FMT_RT_FMT             GENMASK(1, 0)
7500 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_SET(x)\
7501         FIELD_PREP(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
7502 #define REW_PTP_GEN_STAMP_FMT_RT_FMT_GET(x)\
7503         FIELD_GET(REW_PTP_GEN_STAMP_FMT_RT_FMT, x)
7504
7505 /* REW:RAM_CTRL:RAM_INIT */
7506 #define REW_RAM_INIT                                                           \
7507         __REG(TARGET_REW, 0, 1, regs->gaddr[GA_REW_RAM_CTRL], 0, 1, 4, 0, 0, 1,\
7508               4)
7509
7510 #define REW_RAM_INIT_RAM_INIT                    BIT(1)
7511 #define REW_RAM_INIT_RAM_INIT_SET(x)\
7512         FIELD_PREP(REW_RAM_INIT_RAM_INIT, x)
7513 #define REW_RAM_INIT_RAM_INIT_GET(x)\
7514         FIELD_GET(REW_RAM_INIT_RAM_INIT, x)
7515
7516 #define REW_RAM_INIT_RAM_CFG_HOOK                BIT(0)
7517 #define REW_RAM_INIT_RAM_CFG_HOOK_SET(x)\
7518         FIELD_PREP(REW_RAM_INIT_RAM_CFG_HOOK, x)
7519 #define REW_RAM_INIT_RAM_CFG_HOOK_GET(x)\
7520         FIELD_GET(REW_RAM_INIT_RAM_CFG_HOOK, x)
7521
7522 /* VCAP_ES0:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */
7523 #define VCAP_ES0_CTRL                                                          \
7524         __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
7525
7526 #define VCAP_ES0_CTRL_UPDATE_CMD                 GENMASK(24, 22)
7527 #define VCAP_ES0_CTRL_UPDATE_CMD_SET(x)\
7528         FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CMD, x)
7529 #define VCAP_ES0_CTRL_UPDATE_CMD_GET(x)\
7530         FIELD_GET(VCAP_ES0_CTRL_UPDATE_CMD, x)
7531
7532 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS           BIT(21)
7533 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_SET(x)\
7534         FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x)
7535 #define VCAP_ES0_CTRL_UPDATE_ENTRY_DIS_GET(x)\
7536         FIELD_GET(VCAP_ES0_CTRL_UPDATE_ENTRY_DIS, x)
7537
7538 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS          BIT(20)
7539 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_SET(x)\
7540         FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x)
7541 #define VCAP_ES0_CTRL_UPDATE_ACTION_DIS_GET(x)\
7542         FIELD_GET(VCAP_ES0_CTRL_UPDATE_ACTION_DIS, x)
7543
7544 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS             BIT(19)
7545 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_SET(x)\
7546         FIELD_PREP(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x)
7547 #define VCAP_ES0_CTRL_UPDATE_CNT_DIS_GET(x)\
7548         FIELD_GET(VCAP_ES0_CTRL_UPDATE_CNT_DIS, x)
7549
7550 #define VCAP_ES0_CTRL_UPDATE_ADDR                GENMASK(18, 3)
7551 #define VCAP_ES0_CTRL_UPDATE_ADDR_SET(x)\
7552         FIELD_PREP(VCAP_ES0_CTRL_UPDATE_ADDR, x)
7553 #define VCAP_ES0_CTRL_UPDATE_ADDR_GET(x)\
7554         FIELD_GET(VCAP_ES0_CTRL_UPDATE_ADDR, x)
7555
7556 #define VCAP_ES0_CTRL_UPDATE_SHOT                BIT(2)
7557 #define VCAP_ES0_CTRL_UPDATE_SHOT_SET(x)\
7558         FIELD_PREP(VCAP_ES0_CTRL_UPDATE_SHOT, x)
7559 #define VCAP_ES0_CTRL_UPDATE_SHOT_GET(x)\
7560         FIELD_GET(VCAP_ES0_CTRL_UPDATE_SHOT, x)
7561
7562 #define VCAP_ES0_CTRL_CLEAR_CACHE                BIT(1)
7563 #define VCAP_ES0_CTRL_CLEAR_CACHE_SET(x)\
7564         FIELD_PREP(VCAP_ES0_CTRL_CLEAR_CACHE, x)
7565 #define VCAP_ES0_CTRL_CLEAR_CACHE_GET(x)\
7566         FIELD_GET(VCAP_ES0_CTRL_CLEAR_CACHE, x)
7567
7568 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN             BIT(0)
7569 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_SET(x)\
7570         FIELD_PREP(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x)
7571 #define VCAP_ES0_CTRL_MV_TRAFFIC_IGN_GET(x)\
7572         FIELD_GET(VCAP_ES0_CTRL_MV_TRAFFIC_IGN, x)
7573
7574 /* VCAP_ES0:VCAP_CORE_CFG:VCAP_MV_CFG */
7575 #define VCAP_ES0_CFG                                                           \
7576         __REG(TARGET_VCAP_ES0, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7577
7578 #define VCAP_ES0_CFG_MV_NUM_POS                  GENMASK(31, 16)
7579 #define VCAP_ES0_CFG_MV_NUM_POS_SET(x)\
7580         FIELD_PREP(VCAP_ES0_CFG_MV_NUM_POS, x)
7581 #define VCAP_ES0_CFG_MV_NUM_POS_GET(x)\
7582         FIELD_GET(VCAP_ES0_CFG_MV_NUM_POS, x)
7583
7584 #define VCAP_ES0_CFG_MV_SIZE                     GENMASK(15, 0)
7585 #define VCAP_ES0_CFG_MV_SIZE_SET(x)\
7586         FIELD_PREP(VCAP_ES0_CFG_MV_SIZE, x)
7587 #define VCAP_ES0_CFG_MV_SIZE_GET(x)\
7588         FIELD_GET(VCAP_ES0_CFG_MV_SIZE, x)
7589
7590 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */
7591 #define VCAP_ES0_VCAP_ENTRY_DAT(r)                                             \
7592         __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7593
7594 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_MASK_DAT */
7595 #define VCAP_ES0_VCAP_MASK_DAT(r)                                              \
7596         __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7597
7598 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_ACTION_DAT */
7599 #define VCAP_ES0_VCAP_ACTION_DAT(r)                                            \
7600         __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7601
7602 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_DAT */
7603 #define VCAP_ES0_VCAP_CNT_DAT(r)                                               \
7604         __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7605
7606 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */
7607 #define VCAP_ES0_VCAP_CNT_FW_DAT                                               \
7608         __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7609
7610 /* VCAP_ES0:VCAP_CORE_CACHE:VCAP_TG_DAT */
7611 #define VCAP_ES0_VCAP_TG_DAT                                                   \
7612         __REG(TARGET_VCAP_ES0, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7613
7614 /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_IDX */
7615 #define VCAP_ES0_IDX                                                           \
7616         __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7617
7618 #define VCAP_ES0_IDX_CORE_IDX                    GENMASK(3, 0)
7619 #define VCAP_ES0_IDX_CORE_IDX_SET(x)\
7620         FIELD_PREP(VCAP_ES0_IDX_CORE_IDX, x)
7621 #define VCAP_ES0_IDX_CORE_IDX_GET(x)\
7622         FIELD_GET(VCAP_ES0_IDX_CORE_IDX, x)
7623
7624 /* VCAP_ES0:VCAP_CORE_MAP:VCAP_CORE_MAP */
7625 #define VCAP_ES0_MAP                                                           \
7626         __REG(TARGET_VCAP_ES0, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7627
7628 #define VCAP_ES0_MAP_CORE_MAP                    GENMASK(2, 0)
7629 #define VCAP_ES0_MAP_CORE_MAP_SET(x)\
7630         FIELD_PREP(VCAP_ES0_MAP_CORE_MAP, x)
7631 #define VCAP_ES0_MAP_CORE_MAP_GET(x)\
7632         FIELD_GET(VCAP_ES0_MAP_CORE_MAP, x)
7633
7634 /* VCAP_ES0:VCAP_CORE_STICKY:VCAP_STICKY */
7635 #define VCAP_ES0_VCAP_STICKY                                                   \
7636         __REG(TARGET_VCAP_ES0, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4)
7637
7638 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
7639 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\
7640         FIELD_PREP(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7641 #define VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\
7642         FIELD_GET(VCAP_ES0_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7643
7644 /* VCAP_ES0:VCAP_CONST:VCAP_VER */
7645 #define VCAP_ES0_VCAP_VER                                                      \
7646         __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7647
7648 /* VCAP_ES0:VCAP_CONST:ENTRY_WIDTH */
7649 #define VCAP_ES0_ENTRY_WIDTH                                                   \
7650         __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7651
7652 /* VCAP_ES0:VCAP_CONST:ENTRY_CNT */
7653 #define VCAP_ES0_ENTRY_CNT                                                     \
7654         __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7655
7656 /* VCAP_ES0:VCAP_CONST:ENTRY_SWCNT */
7657 #define VCAP_ES0_ENTRY_SWCNT                                                   \
7658         __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7659
7660 /* VCAP_ES0:VCAP_CONST:ENTRY_TG_WIDTH */
7661 #define VCAP_ES0_ENTRY_TG_WIDTH                                                \
7662         __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7663
7664 /* VCAP_ES0:VCAP_CONST:ACTION_DEF_CNT */
7665 #define VCAP_ES0_ACTION_DEF_CNT                                                \
7666         __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7667
7668 /* VCAP_ES0:VCAP_CONST:ACTION_WIDTH */
7669 #define VCAP_ES0_ACTION_WIDTH                                                  \
7670         __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7671
7672 /* VCAP_ES0:VCAP_CONST:CNT_WIDTH */
7673 #define VCAP_ES0_CNT_WIDTH                                                     \
7674         __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7675
7676 /* VCAP_ES0:VCAP_CONST:CORE_CNT */
7677 #define VCAP_ES0_CORE_CNT                                                      \
7678         __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7679
7680 /* VCAP_ES0:VCAP_CONST:IF_CNT */
7681 #define VCAP_ES0_IF_CNT                                                        \
7682         __REG(TARGET_VCAP_ES0, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7683
7684 /* VCAP_ES2:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */
7685 #define VCAP_ES2_CTRL                                                          \
7686         __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
7687
7688 #define VCAP_ES2_CTRL_UPDATE_CMD                 GENMASK(24, 22)
7689 #define VCAP_ES2_CTRL_UPDATE_CMD_SET(x)\
7690         FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CMD, x)
7691 #define VCAP_ES2_CTRL_UPDATE_CMD_GET(x)\
7692         FIELD_GET(VCAP_ES2_CTRL_UPDATE_CMD, x)
7693
7694 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS           BIT(21)
7695 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_SET(x)\
7696         FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x)
7697 #define VCAP_ES2_CTRL_UPDATE_ENTRY_DIS_GET(x)\
7698         FIELD_GET(VCAP_ES2_CTRL_UPDATE_ENTRY_DIS, x)
7699
7700 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS          BIT(20)
7701 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_SET(x)\
7702         FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x)
7703 #define VCAP_ES2_CTRL_UPDATE_ACTION_DIS_GET(x)\
7704         FIELD_GET(VCAP_ES2_CTRL_UPDATE_ACTION_DIS, x)
7705
7706 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS             BIT(19)
7707 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_SET(x)\
7708         FIELD_PREP(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x)
7709 #define VCAP_ES2_CTRL_UPDATE_CNT_DIS_GET(x)\
7710         FIELD_GET(VCAP_ES2_CTRL_UPDATE_CNT_DIS, x)
7711
7712 #define VCAP_ES2_CTRL_UPDATE_ADDR                GENMASK(18, 3)
7713 #define VCAP_ES2_CTRL_UPDATE_ADDR_SET(x)\
7714         FIELD_PREP(VCAP_ES2_CTRL_UPDATE_ADDR, x)
7715 #define VCAP_ES2_CTRL_UPDATE_ADDR_GET(x)\
7716         FIELD_GET(VCAP_ES2_CTRL_UPDATE_ADDR, x)
7717
7718 #define VCAP_ES2_CTRL_UPDATE_SHOT                BIT(2)
7719 #define VCAP_ES2_CTRL_UPDATE_SHOT_SET(x)\
7720         FIELD_PREP(VCAP_ES2_CTRL_UPDATE_SHOT, x)
7721 #define VCAP_ES2_CTRL_UPDATE_SHOT_GET(x)\
7722         FIELD_GET(VCAP_ES2_CTRL_UPDATE_SHOT, x)
7723
7724 #define VCAP_ES2_CTRL_CLEAR_CACHE                BIT(1)
7725 #define VCAP_ES2_CTRL_CLEAR_CACHE_SET(x)\
7726         FIELD_PREP(VCAP_ES2_CTRL_CLEAR_CACHE, x)
7727 #define VCAP_ES2_CTRL_CLEAR_CACHE_GET(x)\
7728         FIELD_GET(VCAP_ES2_CTRL_CLEAR_CACHE, x)
7729
7730 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN             BIT(0)
7731 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_SET(x)\
7732         FIELD_PREP(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x)
7733 #define VCAP_ES2_CTRL_MV_TRAFFIC_IGN_GET(x)\
7734         FIELD_GET(VCAP_ES2_CTRL_MV_TRAFFIC_IGN, x)
7735
7736 /* VCAP_ES2:VCAP_CORE_CFG:VCAP_MV_CFG */
7737 #define VCAP_ES2_CFG                                                           \
7738         __REG(TARGET_VCAP_ES2, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7739
7740 #define VCAP_ES2_CFG_MV_NUM_POS                  GENMASK(31, 16)
7741 #define VCAP_ES2_CFG_MV_NUM_POS_SET(x)\
7742         FIELD_PREP(VCAP_ES2_CFG_MV_NUM_POS, x)
7743 #define VCAP_ES2_CFG_MV_NUM_POS_GET(x)\
7744         FIELD_GET(VCAP_ES2_CFG_MV_NUM_POS, x)
7745
7746 #define VCAP_ES2_CFG_MV_SIZE                     GENMASK(15, 0)
7747 #define VCAP_ES2_CFG_MV_SIZE_SET(x)\
7748         FIELD_PREP(VCAP_ES2_CFG_MV_SIZE, x)
7749 #define VCAP_ES2_CFG_MV_SIZE_GET(x)\
7750         FIELD_GET(VCAP_ES2_CFG_MV_SIZE, x)
7751
7752 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */
7753 #define VCAP_ES2_VCAP_ENTRY_DAT(r)                                             \
7754         __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7755
7756 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_MASK_DAT */
7757 #define VCAP_ES2_VCAP_MASK_DAT(r)                                              \
7758         __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7759
7760 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_ACTION_DAT */
7761 #define VCAP_ES2_VCAP_ACTION_DAT(r)                                            \
7762         __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7763
7764 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_DAT */
7765 #define VCAP_ES2_VCAP_CNT_DAT(r)                                               \
7766         __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7767
7768 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */
7769 #define VCAP_ES2_VCAP_CNT_FW_DAT                                               \
7770         __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7771
7772 /* VCAP_ES2:VCAP_CORE_CACHE:VCAP_TG_DAT */
7773 #define VCAP_ES2_VCAP_TG_DAT                                                   \
7774         __REG(TARGET_VCAP_ES2, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7775
7776 /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_IDX */
7777 #define VCAP_ES2_IDX                                                           \
7778         __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7779
7780 #define VCAP_ES2_IDX_CORE_IDX                    GENMASK(3, 0)
7781 #define VCAP_ES2_IDX_CORE_IDX_SET(x)\
7782         FIELD_PREP(VCAP_ES2_IDX_CORE_IDX, x)
7783 #define VCAP_ES2_IDX_CORE_IDX_GET(x)\
7784         FIELD_GET(VCAP_ES2_IDX_CORE_IDX, x)
7785
7786 /* VCAP_ES2:VCAP_CORE_MAP:VCAP_CORE_MAP */
7787 #define VCAP_ES2_MAP                                                           \
7788         __REG(TARGET_VCAP_ES2, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7789
7790 #define VCAP_ES2_MAP_CORE_MAP                    GENMASK(2, 0)
7791 #define VCAP_ES2_MAP_CORE_MAP_SET(x)\
7792         FIELD_PREP(VCAP_ES2_MAP_CORE_MAP, x)
7793 #define VCAP_ES2_MAP_CORE_MAP_GET(x)\
7794         FIELD_GET(VCAP_ES2_MAP_CORE_MAP, x)
7795
7796 /* VCAP_ES2:VCAP_CORE_STICKY:VCAP_STICKY */
7797 #define VCAP_ES2_VCAP_STICKY                                                   \
7798         __REG(TARGET_VCAP_ES2, 0, 1, 920, 0, 1, 4, 0, 0, 1, 4)
7799
7800 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY BIT(0)
7801 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_SET(x)\
7802         FIELD_PREP(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7803 #define VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY_GET(x)\
7804         FIELD_GET(VCAP_ES2_VCAP_STICKY_VCAP_ROW_DELETED_STICKY, x)
7805
7806 /* VCAP_ES2:VCAP_CONST:VCAP_VER */
7807 #define VCAP_ES2_VCAP_VER                                                      \
7808         __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7809
7810 /* VCAP_ES2:VCAP_CONST:ENTRY_WIDTH */
7811 #define VCAP_ES2_ENTRY_WIDTH                                                   \
7812         __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7813
7814 /* VCAP_ES2:VCAP_CONST:ENTRY_CNT */
7815 #define VCAP_ES2_ENTRY_CNT                                                     \
7816         __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7817
7818 /* VCAP_ES2:VCAP_CONST:ENTRY_SWCNT */
7819 #define VCAP_ES2_ENTRY_SWCNT                                                   \
7820         __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7821
7822 /* VCAP_ES2:VCAP_CONST:ENTRY_TG_WIDTH */
7823 #define VCAP_ES2_ENTRY_TG_WIDTH                                                \
7824         __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7825
7826 /* VCAP_ES2:VCAP_CONST:ACTION_DEF_CNT */
7827 #define VCAP_ES2_ACTION_DEF_CNT                                                \
7828         __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7829
7830 /* VCAP_ES2:VCAP_CONST:ACTION_WIDTH */
7831 #define VCAP_ES2_ACTION_WIDTH                                                  \
7832         __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7833
7834 /* VCAP_ES2:VCAP_CONST:CNT_WIDTH */
7835 #define VCAP_ES2_CNT_WIDTH                                                     \
7836         __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7837
7838 /* VCAP_ES2:VCAP_CONST:CORE_CNT */
7839 #define VCAP_ES2_CORE_CNT                                                      \
7840         __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7841
7842 /* VCAP_ES2:VCAP_CONST:IF_CNT */
7843 #define VCAP_ES2_IF_CNT                                                        \
7844         __REG(TARGET_VCAP_ES2, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7845
7846 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_UPDATE_CTRL */
7847 #define VCAP_SUPER_CTRL                                                        \
7848         __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 0, 0, 1, 4)
7849
7850 #define VCAP_SUPER_CTRL_UPDATE_CMD               GENMASK(24, 22)
7851 #define VCAP_SUPER_CTRL_UPDATE_CMD_SET(x)\
7852         FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CMD, x)
7853 #define VCAP_SUPER_CTRL_UPDATE_CMD_GET(x)\
7854         FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CMD, x)
7855
7856 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS         BIT(21)
7857 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_SET(x)\
7858         FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x)
7859 #define VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS_GET(x)\
7860         FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ENTRY_DIS, x)
7861
7862 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS        BIT(20)
7863 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_SET(x)\
7864         FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x)
7865 #define VCAP_SUPER_CTRL_UPDATE_ACTION_DIS_GET(x)\
7866         FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ACTION_DIS, x)
7867
7868 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS           BIT(19)
7869 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_SET(x)\
7870         FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x)
7871 #define VCAP_SUPER_CTRL_UPDATE_CNT_DIS_GET(x)\
7872         FIELD_GET(VCAP_SUPER_CTRL_UPDATE_CNT_DIS, x)
7873
7874 #define VCAP_SUPER_CTRL_UPDATE_ADDR              GENMASK(18, 3)
7875 #define VCAP_SUPER_CTRL_UPDATE_ADDR_SET(x)\
7876         FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_ADDR, x)
7877 #define VCAP_SUPER_CTRL_UPDATE_ADDR_GET(x)\
7878         FIELD_GET(VCAP_SUPER_CTRL_UPDATE_ADDR, x)
7879
7880 #define VCAP_SUPER_CTRL_UPDATE_SHOT              BIT(2)
7881 #define VCAP_SUPER_CTRL_UPDATE_SHOT_SET(x)\
7882         FIELD_PREP(VCAP_SUPER_CTRL_UPDATE_SHOT, x)
7883 #define VCAP_SUPER_CTRL_UPDATE_SHOT_GET(x)\
7884         FIELD_GET(VCAP_SUPER_CTRL_UPDATE_SHOT, x)
7885
7886 #define VCAP_SUPER_CTRL_CLEAR_CACHE              BIT(1)
7887 #define VCAP_SUPER_CTRL_CLEAR_CACHE_SET(x)\
7888         FIELD_PREP(VCAP_SUPER_CTRL_CLEAR_CACHE, x)
7889 #define VCAP_SUPER_CTRL_CLEAR_CACHE_GET(x)\
7890         FIELD_GET(VCAP_SUPER_CTRL_CLEAR_CACHE, x)
7891
7892 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN           BIT(0)
7893 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_SET(x)\
7894         FIELD_PREP(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x)
7895 #define VCAP_SUPER_CTRL_MV_TRAFFIC_IGN_GET(x)\
7896         FIELD_GET(VCAP_SUPER_CTRL_MV_TRAFFIC_IGN, x)
7897
7898 /* VCAP_SUPER:VCAP_CORE_CFG:VCAP_MV_CFG */
7899 #define VCAP_SUPER_CFG                                                         \
7900         __REG(TARGET_VCAP_SUPER, 0, 1, 0, 0, 1, 8, 4, 0, 1, 4)
7901
7902 #define VCAP_SUPER_CFG_MV_NUM_POS                GENMASK(31, 16)
7903 #define VCAP_SUPER_CFG_MV_NUM_POS_SET(x)\
7904         FIELD_PREP(VCAP_SUPER_CFG_MV_NUM_POS, x)
7905 #define VCAP_SUPER_CFG_MV_NUM_POS_GET(x)\
7906         FIELD_GET(VCAP_SUPER_CFG_MV_NUM_POS, x)
7907
7908 #define VCAP_SUPER_CFG_MV_SIZE                   GENMASK(15, 0)
7909 #define VCAP_SUPER_CFG_MV_SIZE_SET(x)\
7910         FIELD_PREP(VCAP_SUPER_CFG_MV_SIZE, x)
7911 #define VCAP_SUPER_CFG_MV_SIZE_GET(x)\
7912         FIELD_GET(VCAP_SUPER_CFG_MV_SIZE, x)
7913
7914 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ENTRY_DAT */
7915 #define VCAP_SUPER_VCAP_ENTRY_DAT(r)                                           \
7916         __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 0, r, 64, 4)
7917
7918 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_MASK_DAT */
7919 #define VCAP_SUPER_VCAP_MASK_DAT(r)                                            \
7920         __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 256, r, 64, 4)
7921
7922 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_ACTION_DAT */
7923 #define VCAP_SUPER_VCAP_ACTION_DAT(r)                                          \
7924         __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 512, r, 64, 4)
7925
7926 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_DAT */
7927 #define VCAP_SUPER_VCAP_CNT_DAT(r)                                             \
7928         __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 768, r, 32, 4)
7929
7930 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_CNT_FW_DAT */
7931 #define VCAP_SUPER_VCAP_CNT_FW_DAT                                             \
7932         __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 896, 0, 1, 4)
7933
7934 /* VCAP_SUPER:VCAP_CORE_CACHE:VCAP_TG_DAT */
7935 #define VCAP_SUPER_VCAP_TG_DAT                                                 \
7936         __REG(TARGET_VCAP_SUPER, 0, 1, 8, 0, 1, 904, 900, 0, 1, 4)
7937
7938 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_IDX */
7939 #define VCAP_SUPER_IDX                                                         \
7940         __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 0, 0, 1, 4)
7941
7942 #define VCAP_SUPER_IDX_CORE_IDX                  GENMASK(3, 0)
7943 #define VCAP_SUPER_IDX_CORE_IDX_SET(x)\
7944         FIELD_PREP(VCAP_SUPER_IDX_CORE_IDX, x)
7945 #define VCAP_SUPER_IDX_CORE_IDX_GET(x)\
7946         FIELD_GET(VCAP_SUPER_IDX_CORE_IDX, x)
7947
7948 /* VCAP_SUPER:VCAP_CORE_MAP:VCAP_CORE_MAP */
7949 #define VCAP_SUPER_MAP                                                         \
7950         __REG(TARGET_VCAP_SUPER, 0, 1, 912, 0, 1, 8, 4, 0, 1, 4)
7951
7952 #define VCAP_SUPER_MAP_CORE_MAP                  GENMASK(2, 0)
7953 #define VCAP_SUPER_MAP_CORE_MAP_SET(x)\
7954         FIELD_PREP(VCAP_SUPER_MAP_CORE_MAP, x)
7955 #define VCAP_SUPER_MAP_CORE_MAP_GET(x)\
7956         FIELD_GET(VCAP_SUPER_MAP_CORE_MAP, x)
7957
7958 /* VCAP_SUPER:VCAP_CONST:VCAP_VER */
7959 #define VCAP_SUPER_VCAP_VER                                                    \
7960         __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 0, 0, 1, 4)
7961
7962 /* VCAP_SUPER:VCAP_CONST:ENTRY_WIDTH */
7963 #define VCAP_SUPER_ENTRY_WIDTH                                                 \
7964         __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 4, 0, 1, 4)
7965
7966 /* VCAP_SUPER:VCAP_CONST:ENTRY_CNT */
7967 #define VCAP_SUPER_ENTRY_CNT                                                   \
7968         __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 8, 0, 1, 4)
7969
7970 /* VCAP_SUPER:VCAP_CONST:ENTRY_SWCNT */
7971 #define VCAP_SUPER_ENTRY_SWCNT                                                 \
7972         __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 12, 0, 1, 4)
7973
7974 /* VCAP_SUPER:VCAP_CONST:ENTRY_TG_WIDTH */
7975 #define VCAP_SUPER_ENTRY_TG_WIDTH                                              \
7976         __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 16, 0, 1, 4)
7977
7978 /* VCAP_SUPER:VCAP_CONST:ACTION_DEF_CNT */
7979 #define VCAP_SUPER_ACTION_DEF_CNT                                              \
7980         __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 20, 0, 1, 4)
7981
7982 /* VCAP_SUPER:VCAP_CONST:ACTION_WIDTH */
7983 #define VCAP_SUPER_ACTION_WIDTH                                                \
7984         __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 24, 0, 1, 4)
7985
7986 /* VCAP_SUPER:VCAP_CONST:CNT_WIDTH */
7987 #define VCAP_SUPER_CNT_WIDTH                                                   \
7988         __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 28, 0, 1, 4)
7989
7990 /* VCAP_SUPER:VCAP_CONST:CORE_CNT */
7991 #define VCAP_SUPER_CORE_CNT                                                    \
7992         __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 32, 0, 1, 4)
7993
7994 /* VCAP_SUPER:VCAP_CONST:IF_CNT */
7995 #define VCAP_SUPER_IF_CNT                                                      \
7996         __REG(TARGET_VCAP_SUPER, 0, 1, 924, 0, 1, 40, 36, 0, 1, 4)
7997
7998 /* VCAP_SUPER:RAM_CTRL:RAM_INIT */
7999 #define VCAP_SUPER_RAM_INIT                                                    \
8000         __REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4)
8001
8002 #define VCAP_SUPER_RAM_INIT_RAM_INIT             BIT(1)
8003 #define VCAP_SUPER_RAM_INIT_RAM_INIT_SET(x)\
8004         FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
8005 #define VCAP_SUPER_RAM_INIT_RAM_INIT_GET(x)\
8006         FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_INIT, x)
8007
8008 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK         BIT(0)
8009 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_SET(x)\
8010         FIELD_PREP(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
8011 #define VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK_GET(x)\
8012         FIELD_GET(VCAP_SUPER_RAM_INIT_RAM_CFG_HOOK, x)
8013
8014 /* VOP:RAM_CTRL:RAM_INIT */
8015 #define VOP_RAM_INIT                                                           \
8016         __REG(TARGET_VOP, 0, 1, regs->gaddr[GA_VOP_RAM_CTRL], 0, 1, 4, 0, 0, 1,\
8017               4)
8018
8019 #define VOP_RAM_INIT_RAM_INIT                    BIT(1)
8020 #define VOP_RAM_INIT_RAM_INIT_SET(x)\
8021         FIELD_PREP(VOP_RAM_INIT_RAM_INIT, x)
8022 #define VOP_RAM_INIT_RAM_INIT_GET(x)\
8023         FIELD_GET(VOP_RAM_INIT_RAM_INIT, x)
8024
8025 #define VOP_RAM_INIT_RAM_CFG_HOOK                BIT(0)
8026 #define VOP_RAM_INIT_RAM_CFG_HOOK_SET(x)\
8027         FIELD_PREP(VOP_RAM_INIT_RAM_CFG_HOOK, x)
8028 #define VOP_RAM_INIT_RAM_CFG_HOOK_GET(x)\
8029         FIELD_GET(VOP_RAM_INIT_RAM_CFG_HOOK, x)
8030
8031 /* XQS:SYSTEM:STAT_CFG */
8032 #define XQS_STAT_CFG                                                           \
8033         __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_SYSTEM], 0, 1, 872, 860, 0, \
8034               1, 4)
8035
8036 #define XQS_STAT_CFG_STAT_CLEAR_SHOT             GENMASK(21, 18)
8037 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_SET(x)\
8038         FIELD_PREP(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
8039 #define XQS_STAT_CFG_STAT_CLEAR_SHOT_GET(x)\
8040         FIELD_GET(XQS_STAT_CFG_STAT_CLEAR_SHOT, x)
8041
8042 #define XQS_STAT_CFG_STAT_VIEW\
8043         GENMASK(regs->fsize[FW_XQS_STAT_CFG_STAT_VIEW] + 5 - 1, 5)
8044 #define XQS_STAT_CFG_STAT_VIEW_SET(x)\
8045         spx5_field_prep(XQS_STAT_CFG_STAT_VIEW, x)
8046 #define XQS_STAT_CFG_STAT_VIEW_GET(x)\
8047         spx5_field_get(XQS_STAT_CFG_STAT_VIEW, x)
8048
8049 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY           BIT(4)
8050 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_SET(x)\
8051         FIELD_PREP(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
8052 #define XQS_STAT_CFG_STAT_SRV_PKT_ONLY_GET(x)\
8053         FIELD_GET(XQS_STAT_CFG_STAT_SRV_PKT_ONLY, x)
8054
8055 #define XQS_STAT_CFG_STAT_WRAP_DIS               GENMASK(3, 0)
8056 #define XQS_STAT_CFG_STAT_WRAP_DIS_SET(x)\
8057         FIELD_PREP(XQS_STAT_CFG_STAT_WRAP_DIS, x)
8058 #define XQS_STAT_CFG_STAT_WRAP_DIS_GET(x)\
8059         FIELD_GET(XQS_STAT_CFG_STAT_WRAP_DIS, x)
8060
8061 /* XQS:QLIMIT_SHR:QLIMIT_SHR_TOP_CFG */
8062 #define XQS_QLIMIT_SHR_TOP_CFG(g)                                              \
8063         __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 0, 0,\
8064               1, 4)
8065
8066 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP\
8067         GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] + 0 - 1, 0)
8068 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_SET(x)\
8069         spx5_field_prep(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
8070 #define XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP_GET(x)\
8071         spx5_field_get(XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP, x)
8072
8073 /* XQS:QLIMIT_SHR:QLIMIT_SHR_ATOP_CFG */
8074 #define XQS_QLIMIT_SHR_ATOP_CFG(g)                                             \
8075         __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 4, 0,\
8076               1, 4)
8077
8078 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP\
8079         GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] + 0 - 1, 0)
8080 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_SET(x)\
8081         spx5_field_prep(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
8082 #define XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP_GET(x)\
8083         spx5_field_get(XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP, x)
8084
8085 /* XQS:QLIMIT_SHR:QLIMIT_SHR_CTOP_CFG */
8086 #define XQS_QLIMIT_SHR_CTOP_CFG(g)                                             \
8087         __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 8, 0,\
8088               1, 4)
8089
8090 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP\
8091         GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] + 0 - 1, 0)
8092 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_SET(x)\
8093         spx5_field_prep(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
8094 #define XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP_GET(x)\
8095         spx5_field_get(XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP, x)
8096
8097 /* XQS:QLIMIT_SHR:QLIMIT_SHR_QLIM_CFG */
8098 #define XQS_QLIMIT_SHR_QLIM_CFG(g)                                             \
8099         __REG(TARGET_XQS, 0, 1, regs->gaddr[GA_XQS_QLIMIT_SHR], g, 4, 48, 12,  \
8100               0, 1, 4)
8101
8102 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM\
8103         GENMASK(regs->fsize[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] + 0 - 1, 0)
8104 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_SET(x)\
8105         spx5_field_prep(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
8106 #define XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM_GET(x)\
8107         spx5_field_get(XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM, x)
8108
8109 /* XQS:STAT:CNT */
8110 #define XQS_CNT(g)                                                             \
8111         __REG(TARGET_XQS, 0, 1, 0, g, 1024, 4, 0, 0, 1, 4)
8112
8113 #endif /* _SPARX5_MAIN_REGS_H_ */