drivers/net/ethernet/realtek/r8169_phy_config.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * r8169_phy_config.c: RealTek 8169/8168/8101 ethernet driver.
   4  *
   5  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   6  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   7  * Copyright (c) a lot of people too. Please respect their work.
   8  *
   9  * See MAINTAINERS file for support contact information.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/phy.h>
  14
  15 #include "r8169.h"
  16
  17 typedef void (*rtl_phy_cfg_fct)(struct rtl8169_private *tp,
  18                                 struct phy_device *phydev);
  19
  20 static void r8168d_modify_extpage(struct phy_device *phydev, int extpage,
  21                                   int reg, u16 mask, u16 val)
  22 {
  23         int oldpage = phy_select_page(phydev, 0x0007);
  24
  25         __phy_write(phydev, 0x1e, extpage);
  26         __phy_modify(phydev, reg, mask, val);
  27
  28         phy_restore_page(phydev, oldpage, 0);
  29 }
  30
  31 static void r8168d_phy_param(struct phy_device *phydev, u16 parm,
  32                              u16 mask, u16 val)
  33 {
  34         int oldpage = phy_select_page(phydev, 0x0005);
  35
  36         __phy_write(phydev, 0x05, parm);
  37         __phy_modify(phydev, 0x06, mask, val);
  38
  39         phy_restore_page(phydev, oldpage, 0);
  40 }
  41
  42 static void r8168g_phy_param(struct phy_device *phydev, u16 parm,
  43                              u16 mask, u16 val)
  44 {
  45         int oldpage = phy_select_page(phydev, 0x0a43);
  46
  47         __phy_write(phydev, 0x13, parm);
  48         __phy_modify(phydev, 0x14, mask, val);
  49
  50         phy_restore_page(phydev, oldpage, 0);
  51 }
  52
  53 struct phy_reg {
  54         u16 reg;
  55         u16 val;
  56 };
  57
  58 static void __rtl_writephy_batch(struct phy_device *phydev,
  59                                  const struct phy_reg *regs, int len)
  60 {
  61         phy_lock_mdio_bus(phydev);
  62
  63         while (len-- > 0) {
  64                 __phy_write(phydev, regs->reg, regs->val);
  65                 regs++;
  66         }
  67
  68         phy_unlock_mdio_bus(phydev);
  69 }
  70
  71 #define rtl_writephy_batch(p, a) __rtl_writephy_batch(p, a, ARRAY_SIZE(a))
  72
  73 static void rtl8168f_config_eee_phy(struct phy_device *phydev)
  74 {
  75         r8168d_modify_extpage(phydev, 0x0020, 0x15, 0, BIT(8));
  76         r8168d_phy_param(phydev, 0x8b85, 0, BIT(13));
  77 }
  78
  79 static void rtl8168g_config_eee_phy(struct phy_device *phydev)
  80 {
  81         phy_modify_paged(phydev, 0x0a43, 0x11, 0, BIT(4));
  82 }
  83
  84 static void rtl8168h_config_eee_phy(struct phy_device *phydev)
  85 {
  86         rtl8168g_config_eee_phy(phydev);
  87
  88         phy_modify_paged(phydev, 0xa4a, 0x11, 0x0000, 0x0200);
  89         phy_modify_paged(phydev, 0xa42, 0x14, 0x0000, 0x0080);
  90 }
  91
  92 static void rtl8125_common_config_eee_phy(struct phy_device *phydev)
  93 {
  94         phy_modify_paged(phydev, 0xa6d, 0x14, 0x0010, 0x0000);
  95         phy_modify_paged(phydev, 0xa42, 0x14, 0x0080, 0x0000);
  96         phy_modify_paged(phydev, 0xa4a, 0x11, 0x0200, 0x0000);
  97 }
  98
  99 static void rtl8125_config_eee_phy(struct phy_device *phydev)
 100 {
 101         rtl8168g_config_eee_phy(phydev);
 102         rtl8125_common_config_eee_phy(phydev);
 103 }
 104
 105 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp,
 106                                    struct phy_device *phydev)
 107 {
 108         static const struct phy_reg phy_reg_init[] = {
 109                 { 0x1f, 0x0001 },
 110                 { 0x06, 0x006e },
 111                 { 0x08, 0x0708 },
 112                 { 0x15, 0x4000 },
 113                 { 0x18, 0x65c7 },
 114
 115                 { 0x1f, 0x0001 },
 116                 { 0x03, 0x00a1 },
 117                 { 0x02, 0x0008 },
 118                 { 0x01, 0x0120 },
 119                 { 0x00, 0x1000 },
 120                 { 0x04, 0x0800 },
 121                 { 0x04, 0x0000 },
 122
 123                 { 0x03, 0xff41 },
 124                 { 0x02, 0xdf60 },
 125                 { 0x01, 0x0140 },
 126                 { 0x00, 0x0077 },
 127                 { 0x04, 0x7800 },
 128                 { 0x04, 0x7000 },
 129
 130                 { 0x03, 0x802f },
 131                 { 0x02, 0x4f02 },
 132                 { 0x01, 0x0409 },
 133                 { 0x00, 0xf0f9 },
 134                 { 0x04, 0x9800 },
 135                 { 0x04, 0x9000 },
 136
 137                 { 0x03, 0xdf01 },
 138                 { 0x02, 0xdf20 },
 139                 { 0x01, 0xff95 },
 140                 { 0x00, 0xba00 },
 141                 { 0x04, 0xa800 },
 142                 { 0x04, 0xa000 },
 143
 144                 { 0x03, 0xff41 },
 145                 { 0x02, 0xdf20 },
 146                 { 0x01, 0x0140 },
 147                 { 0x00, 0x00bb },
 148                 { 0x04, 0xb800 },
 149                 { 0x04, 0xb000 },
 150
 151                 { 0x03, 0xdf41 },
 152                 { 0x02, 0xdc60 },
 153                 { 0x01, 0x6340 },
 154                 { 0x00, 0x007d },
 155                 { 0x04, 0xd800 },
 156                 { 0x04, 0xd000 },
 157
 158                 { 0x03, 0xdf01 },
 159                 { 0x02, 0xdf20 },
 160                 { 0x01, 0x100a },
 161                 { 0x00, 0xa0ff },
 162                 { 0x04, 0xf800 },
 163                 { 0x04, 0xf000 },
 164
 165                 { 0x1f, 0x0000 },
 166                 { 0x0b, 0x0000 },
 167                 { 0x00, 0x9200 }
 168         };
 169
 170         rtl_writephy_batch(phydev, phy_reg_init);
 171 }
 172
 173 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp,
 174                                     struct phy_device *phydev)
 175 {
 176         phy_write_paged(phydev, 0x0002, 0x01, 0x90d0);
 177 }
 178
 179 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp,
 180                                      struct phy_device *phydev)
 181 {
 182         static const struct phy_reg phy_reg_init[] = {
 183                 { 0x1f, 0x0001 },
 184                 { 0x04, 0x0000 },
 185                 { 0x03, 0x00a1 },
 186                 { 0x02, 0x0008 },
 187                 { 0x01, 0x0120 },
 188                 { 0x00, 0x1000 },
 189                 { 0x04, 0x0800 },
 190                 { 0x04, 0x9000 },
 191                 { 0x03, 0x802f },
 192                 { 0x02, 0x4f02 },
 193                 { 0x01, 0x0409 },
 194                 { 0x00, 0xf099 },
 195                 { 0x04, 0x9800 },
 196                 { 0x04, 0xa000 },
 197                 { 0x03, 0xdf01 },
 198                 { 0x02, 0xdf20 },
 199                 { 0x01, 0xff95 },
 200                 { 0x00, 0xba00 },
 201                 { 0x04, 0xa800 },
 202                 { 0x04, 0xf000 },
 203                 { 0x03, 0xdf01 },
 204                 { 0x02, 0xdf20 },
 205                 { 0x01, 0x101a },
 206                 { 0x00, 0xa0ff },
 207                 { 0x04, 0xf800 },
 208                 { 0x04, 0x0000 },
 209                 { 0x1f, 0x0000 },
 210
 211                 { 0x1f, 0x0001 },
 212                 { 0x10, 0xf41b },
 213                 { 0x14, 0xfb54 },
 214                 { 0x18, 0xf5c7 },
 215                 { 0x1f, 0x0000 },
 216
 217                 { 0x1f, 0x0001 },
 218                 { 0x17, 0x0cc0 },
 219                 { 0x1f, 0x0000 }
 220         };
 221
 222         rtl_writephy_batch(phydev, phy_reg_init);
 223 }
 224
 225 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp,
 226                                      struct phy_device *phydev)
 227 {
 228         static const struct phy_reg phy_reg_init[] = {
 229                 { 0x1f, 0x0001 },
 230                 { 0x04, 0x0000 },
 231                 { 0x03, 0x00a1 },
 232                 { 0x02, 0x0008 },
 233                 { 0x01, 0x0120 },
 234                 { 0x00, 0x1000 },
 235                 { 0x04, 0x0800 },
 236                 { 0x04, 0x9000 },
 237                 { 0x03, 0x802f },
 238                 { 0x02, 0x4f02 },
 239                 { 0x01, 0x0409 },
 240                 { 0x00, 0xf099 },
 241                 { 0x04, 0x9800 },
 242                 { 0x04, 0xa000 },
 243                 { 0x03, 0xdf01 },
 244                 { 0x02, 0xdf20 },
 245                 { 0x01, 0xff95 },
 246                 { 0x00, 0xba00 },
 247                 { 0x04, 0xa800 },
 248                 { 0x04, 0xf000 },
 249                 { 0x03, 0xdf01 },
 250                 { 0x02, 0xdf20 },
 251                 { 0x01, 0x101a },
 252                 { 0x00, 0xa0ff },
 253                 { 0x04, 0xf800 },
 254                 { 0x04, 0x0000 },
 255                 { 0x1f, 0x0000 },
 256
 257                 { 0x1f, 0x0001 },
 258                 { 0x0b, 0x8480 },
 259                 { 0x1f, 0x0000 },
 260
 261                 { 0x1f, 0x0001 },
 262                 { 0x18, 0x67c7 },
 263                 { 0x04, 0x2000 },
 264                 { 0x03, 0x002f },
 265                 { 0x02, 0x4360 },
 266                 { 0x01, 0x0109 },
 267                 { 0x00, 0x3022 },
 268                 { 0x04, 0x2800 },
 269                 { 0x1f, 0x0000 },
 270
 271                 { 0x1f, 0x0001 },
 272                 { 0x17, 0x0cc0 },
 273                 { 0x1f, 0x0000 }
 274         };
 275
 276         rtl_writephy_batch(phydev, phy_reg_init);
 277 }
 278
 279 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp,
 280                                     struct phy_device *phydev)
 281 {
 282         phy_write(phydev, 0x1f, 0x0001);
 283         phy_set_bits(phydev, 0x16, BIT(0));
 284         phy_write(phydev, 0x10, 0xf41b);
 285         phy_write(phydev, 0x1f, 0x0000);
 286 }
 287
 288 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp,
 289                                      struct phy_device *phydev)
 290 {
 291         phy_write_paged(phydev, 0x0001, 0x10, 0xf41b);
 292 }
 293
 294 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp,
 295                                       struct phy_device *phydev)
 296 {
 297         phy_write(phydev, 0x1d, 0x0f00);
 298         phy_write_paged(phydev, 0x0002, 0x0c, 0x1ec8);
 299 }
 300
 301 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp,
 302                                       struct phy_device *phydev)
 303 {
 304         phy_set_bits(phydev, 0x14, BIT(5));
 305         phy_set_bits(phydev, 0x0d, BIT(5));
 306         phy_write_paged(phydev, 0x0001, 0x1d, 0x3d98);
 307 }
 308
 309 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp,
 310                                      struct phy_device *phydev)
 311 {
 312         static const struct phy_reg phy_reg_init[] = {
 313                 { 0x1f, 0x0001 },
 314                 { 0x12, 0x2300 },
 315                 { 0x1f, 0x0002 },
 316                 { 0x00, 0x88d4 },
 317                 { 0x01, 0x82b1 },
 318                 { 0x03, 0x7002 },
 319                 { 0x08, 0x9e30 },
 320                 { 0x09, 0x01f0 },
 321                 { 0x0a, 0x5500 },
 322                 { 0x0c, 0x00c8 },
 323                 { 0x1f, 0x0003 },
 324                 { 0x12, 0xc096 },
 325                 { 0x16, 0x000a },
 326                 { 0x1f, 0x0000 },
 327                 { 0x1f, 0x0000 },
 328                 { 0x09, 0x2000 },
 329                 { 0x09, 0x0000 }
 330         };
 331
 332         rtl_writephy_batch(phydev, phy_reg_init);
 333
 334         phy_set_bits(phydev, 0x14, BIT(5));
 335         phy_set_bits(phydev, 0x0d, BIT(5));
 336 }
 337
 338 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp,
 339                                      struct phy_device *phydev)
 340 {
 341         static const struct phy_reg phy_reg_init[] = {
 342                 { 0x1f, 0x0001 },
 343                 { 0x12, 0x2300 },
 344                 { 0x03, 0x802f },
 345                 { 0x02, 0x4f02 },
 346                 { 0x01, 0x0409 },
 347                 { 0x00, 0xf099 },
 348                 { 0x04, 0x9800 },
 349                 { 0x04, 0x9000 },
 350                 { 0x1d, 0x3d98 },
 351                 { 0x1f, 0x0002 },
 352                 { 0x0c, 0x7eb8 },
 353                 { 0x06, 0x0761 },
 354                 { 0x1f, 0x0003 },
 355                 { 0x16, 0x0f0a },
 356                 { 0x1f, 0x0000 }
 357         };
 358
 359         rtl_writephy_batch(phydev, phy_reg_init);
 360
 361         phy_set_bits(phydev, 0x16, BIT(0));
 362         phy_set_bits(phydev, 0x14, BIT(5));
 363         phy_set_bits(phydev, 0x0d, BIT(5));
 364 }
 365
 366 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp,
 367                                      struct phy_device *phydev)
 368 {
 369         static const struct phy_reg phy_reg_init[] = {
 370                 { 0x1f, 0x0001 },
 371                 { 0x12, 0x2300 },
 372                 { 0x1d, 0x3d98 },
 373                 { 0x1f, 0x0002 },
 374                 { 0x0c, 0x7eb8 },
 375                 { 0x06, 0x5461 },
 376                 { 0x1f, 0x0003 },
 377                 { 0x16, 0x0f0a },
 378                 { 0x1f, 0x0000 }
 379         };
 380
 381         rtl_writephy_batch(phydev, phy_reg_init);
 382
 383         phy_set_bits(phydev, 0x16, BIT(0));
 384         phy_set_bits(phydev, 0x14, BIT(5));
 385         phy_set_bits(phydev, 0x0d, BIT(5));
 386 }
 387
 388 static const struct phy_reg rtl8168d_1_phy_reg_init_0[] = {
 389         /* Channel Estimation */
 390         { 0x1f, 0x0001 },
 391         { 0x06, 0x4064 },
 392         { 0x07, 0x2863 },
 393         { 0x08, 0x059c },
 394         { 0x09, 0x26b4 },
 395         { 0x0a, 0x6a19 },
 396         { 0x0b, 0xdcc8 },
 397         { 0x10, 0xf06d },
 398         { 0x14, 0x7f68 },
 399         { 0x18, 0x7fd9 },
 400         { 0x1c, 0xf0ff },
 401         { 0x1d, 0x3d9c },
 402         { 0x1f, 0x0003 },
 403         { 0x12, 0xf49f },
 404         { 0x13, 0x070b },
 405         { 0x1a, 0x05ad },
 406         { 0x14, 0x94c0 },
 407
 408         /*
 409          * Tx Error Issue
 410          * Enhance line driver power
 411          */
 412         { 0x1f, 0x0002 },
 413         { 0x06, 0x5561 },
 414         { 0x1f, 0x0005 },
 415         { 0x05, 0x8332 },
 416         { 0x06, 0x5561 },
 417
 418         /*
 419          * Can not link to 1Gbps with bad cable
 420          * Decrease SNR threshold form 21.07dB to 19.04dB
 421          */
 422         { 0x1f, 0x0001 },
 423         { 0x17, 0x0cc0 },
 424
 425         { 0x1f, 0x0000 },
 426         { 0x0d, 0xf880 }
 427 };
 428
 429 static void rtl8168d_apply_firmware_cond(struct rtl8169_private *tp,
 430                                          struct phy_device *phydev,
 431                                          u16 val)
 432 {
 433         u16 reg_val;
 434
 435         phy_write(phydev, 0x1f, 0x0005);
 436         phy_write(phydev, 0x05, 0x001b);
 437         reg_val = phy_read(phydev, 0x06);
 438         phy_write(phydev, 0x1f, 0x0000);
 439
 440         if (reg_val != val)
 441                 phydev_warn(phydev, "chipset not ready for firmware\n");
 442         else
 443                 r8169_apply_firmware(tp);
 444 }
 445
 446 static void rtl8168d_1_common(struct phy_device *phydev)
 447 {
 448         u16 val;
 449
 450         phy_write_paged(phydev, 0x0002, 0x05, 0x669a);
 451         r8168d_phy_param(phydev, 0x8330, 0xffff, 0x669a);
 452         phy_write(phydev, 0x1f, 0x0002);
 453
 454         val = phy_read(phydev, 0x0d);
 455
 456         if ((val & 0x00ff) != 0x006c) {
 457                 static const u16 set[] = {
 458                         0x0065, 0x0066, 0x0067, 0x0068,
 459                         0x0069, 0x006a, 0x006b, 0x006c
 460                 };
 461                 int i;
 462
 463                 val &= 0xff00;
 464                 for (i = 0; i < ARRAY_SIZE(set); i++)
 465                         phy_write(phydev, 0x0d, val | set[i]);
 466         }
 467 }
 468
 469 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp,
 470                                      struct phy_device *phydev)
 471 {
 472         rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0);
 473
 474         /*
 475          * Rx Error Issue
 476          * Fine Tune Switching regulator parameter
 477          */
 478         phy_write(phydev, 0x1f, 0x0002);
 479         phy_modify(phydev, 0x0b, 0x00ef, 0x0010);
 480         phy_modify(phydev, 0x0c, 0x5d00, 0xa200);
 481
 482         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
 483                 rtl8168d_1_common(phydev);
 484         } else {
 485                 phy_write_paged(phydev, 0x0002, 0x05, 0x6662);
 486                 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x6662);
 487         }
 488
 489         /* RSET couple improve */
 490         phy_write(phydev, 0x1f, 0x0002);
 491         phy_set_bits(phydev, 0x0d, 0x0300);
 492         phy_set_bits(phydev, 0x0f, 0x0010);
 493
 494         /* Fine tune PLL performance */
 495         phy_write(phydev, 0x1f, 0x0002);
 496         phy_modify(phydev, 0x02, 0x0600, 0x0100);
 497         phy_clear_bits(phydev, 0x03, 0xe000);
 498         phy_write(phydev, 0x1f, 0x0000);
 499
 500         rtl8168d_apply_firmware_cond(tp, phydev, 0xbf00);
 501 }
 502
 503 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp,
 504                                      struct phy_device *phydev)
 505 {
 506         rtl_writephy_batch(phydev, rtl8168d_1_phy_reg_init_0);
 507
 508         if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
 509                 rtl8168d_1_common(phydev);
 510         } else {
 511                 phy_write_paged(phydev, 0x0002, 0x05, 0x2642);
 512                 r8168d_phy_param(phydev, 0x8330, 0xffff, 0x2642);
 513         }
 514
 515         /* Fine tune PLL performance */
 516         phy_write(phydev, 0x1f, 0x0002);
 517         phy_modify(phydev, 0x02, 0x0600, 0x0100);
 518         phy_clear_bits(phydev, 0x03, 0xe000);
 519         phy_write(phydev, 0x1f, 0x0000);
 520
 521         /* Switching regulator Slew rate */
 522         phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0017);
 523
 524         rtl8168d_apply_firmware_cond(tp, phydev, 0xb300);
 525 }
 526
 527 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp,
 528                                      struct phy_device *phydev)
 529 {
 530         phy_write_paged(phydev, 0x0001, 0x17, 0x0cc0);
 531         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0xffff, 0x0040);
 532         phy_set_bits(phydev, 0x0d, BIT(5));
 533 }
 534
 535 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp,
 536                                      struct phy_device *phydev)
 537 {
 538         static const struct phy_reg phy_reg_init[] = {
 539                 /* Channel estimation fine tune */
 540                 { 0x1f, 0x0001 },
 541                 { 0x0b, 0x6c20 },
 542                 { 0x07, 0x2872 },
 543                 { 0x1c, 0xefff },
 544                 { 0x1f, 0x0003 },
 545                 { 0x14, 0x6420 },
 546                 { 0x1f, 0x0000 },
 547         };
 548
 549         r8169_apply_firmware(tp);
 550
 551         /* Enable Delay cap */
 552         r8168d_phy_param(phydev, 0x8b80, 0xffff, 0xc896);
 553
 554         rtl_writephy_batch(phydev, phy_reg_init);
 555
 556         /* Update PFM & 10M TX idle timer */
 557         r8168d_modify_extpage(phydev, 0x002f, 0x15, 0xffff, 0x1919);
 558
 559         r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006);
 560
 561         /* DCO enable for 10M IDLE Power */
 562         r8168d_modify_extpage(phydev, 0x0023, 0x17, 0x0000, 0x0006);
 563
 564         /* For impedance matching */
 565         phy_modify_paged(phydev, 0x0002, 0x08, 0x7f00, 0x8000);
 566
 567         /* PHY auto speed down */
 568         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0050);
 569         phy_set_bits(phydev, 0x14, BIT(15));
 570
 571         r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
 572         r8168d_phy_param(phydev, 0x8b85, 0x2000, 0x0000);
 573
 574         r8168d_modify_extpage(phydev, 0x0020, 0x15, 0x1100, 0x0000);
 575         phy_write_paged(phydev, 0x0006, 0x00, 0x5a00);
 576
 577         phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0000);
 578 }
 579
 580 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp,
 581                                      struct phy_device *phydev)
 582 {
 583         r8169_apply_firmware(tp);
 584
 585         /* Enable Delay cap */
 586         r8168d_modify_extpage(phydev, 0x00ac, 0x18, 0xffff, 0x0006);
 587
 588         /* Channel estimation fine tune */
 589         phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
 590
 591         /* Green Setting */
 592         r8168d_phy_param(phydev, 0x8b5b, 0xffff, 0x9222);
 593         r8168d_phy_param(phydev, 0x8b6d, 0xffff, 0x8000);
 594         r8168d_phy_param(phydev, 0x8b76, 0xffff, 0x8000);
 595
 596         /* For 4-corner performance improve */
 597         phy_write(phydev, 0x1f, 0x0005);
 598         phy_write(phydev, 0x05, 0x8b80);
 599         phy_set_bits(phydev, 0x17, 0x0006);
 600         phy_write(phydev, 0x1f, 0x0000);
 601
 602         /* PHY auto speed down */
 603         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010);
 604         phy_set_bits(phydev, 0x14, BIT(15));
 605
 606         /* improve 10M EEE waveform */
 607         r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
 608
 609         /* Improve 2-pair detection performance */
 610         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
 611
 612         rtl8168f_config_eee_phy(phydev);
 613
 614         /* Green feature */
 615         phy_write(phydev, 0x1f, 0x0003);
 616         phy_set_bits(phydev, 0x19, BIT(0));
 617         phy_set_bits(phydev, 0x10, BIT(10));
 618         phy_write(phydev, 0x1f, 0x0000);
 619         phy_modify_paged(phydev, 0x0005, 0x01, 0, BIT(8));
 620 }
 621
 622 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp,
 623                                    struct phy_device *phydev)
 624 {
 625         /* For 4-corner performance improve */
 626         r8168d_phy_param(phydev, 0x8b80, 0x0000, 0x0006);
 627
 628         /* PHY auto speed down */
 629         r8168d_modify_extpage(phydev, 0x002d, 0x18, 0x0000, 0x0010);
 630         phy_set_bits(phydev, 0x14, BIT(15));
 631
 632         /* Improve 10M EEE waveform */
 633         r8168d_phy_param(phydev, 0x8b86, 0x0000, 0x0001);
 634
 635         rtl8168f_config_eee_phy(phydev);
 636 }
 637
 638 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp,
 639                                      struct phy_device *phydev)
 640 {
 641         r8169_apply_firmware(tp);
 642
 643         /* Channel estimation fine tune */
 644         phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
 645
 646         /* Modify green table for giga & fnet */
 647         r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000);
 648         r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000);
 649         r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000);
 650         r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000);
 651         r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000);
 652         r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00fb);
 653
 654         /* Modify green table for 10M */
 655         r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00);
 656
 657         /* Disable hiimpedance detection (RTCT) */
 658         phy_write_paged(phydev, 0x0003, 0x01, 0x328a);
 659
 660         rtl8168f_hw_phy_config(tp, phydev);
 661
 662         /* Improve 2-pair detection performance */
 663         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
 664 }
 665
 666 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp,
 667                                      struct phy_device *phydev)
 668 {
 669         r8169_apply_firmware(tp);
 670
 671         rtl8168f_hw_phy_config(tp, phydev);
 672 }
 673
 674 static void rtl8411_hw_phy_config(struct rtl8169_private *tp,
 675                                   struct phy_device *phydev)
 676 {
 677         r8169_apply_firmware(tp);
 678
 679         rtl8168f_hw_phy_config(tp, phydev);
 680
 681         /* Improve 2-pair detection performance */
 682         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x4000);
 683
 684         /* Channel estimation fine tune */
 685         phy_write_paged(phydev, 0x0003, 0x09, 0xa20f);
 686
 687         /* Modify green table for giga & fnet */
 688         r8168d_phy_param(phydev, 0x8b55, 0xffff, 0x0000);
 689         r8168d_phy_param(phydev, 0x8b5e, 0xffff, 0x0000);
 690         r8168d_phy_param(phydev, 0x8b67, 0xffff, 0x0000);
 691         r8168d_phy_param(phydev, 0x8b70, 0xffff, 0x0000);
 692         r8168d_modify_extpage(phydev, 0x0078, 0x17, 0xffff, 0x0000);
 693         r8168d_modify_extpage(phydev, 0x0078, 0x19, 0xffff, 0x00aa);
 694
 695         /* Modify green table for 10M */
 696         r8168d_phy_param(phydev, 0x8b79, 0xffff, 0xaa00);
 697
 698         /* Disable hiimpedance detection (RTCT) */
 699         phy_write_paged(phydev, 0x0003, 0x01, 0x328a);
 700
 701         /* Modify green table for giga */
 702         r8168d_phy_param(phydev, 0x8b54, 0x0800, 0x0000);
 703         r8168d_phy_param(phydev, 0x8b5d, 0x0800, 0x0000);
 704         r8168d_phy_param(phydev, 0x8a7c, 0x0100, 0x0000);
 705         r8168d_phy_param(phydev, 0x8a7f, 0x0000, 0x0100);
 706         r8168d_phy_param(phydev, 0x8a82, 0x0100, 0x0000);
 707         r8168d_phy_param(phydev, 0x8a85, 0x0100, 0x0000);
 708         r8168d_phy_param(phydev, 0x8a88, 0x0100, 0x0000);
 709
 710         /* uc same-seed solution */
 711         r8168d_phy_param(phydev, 0x8b85, 0x0000, 0x8000);
 712
 713         /* Green feature */
 714         phy_write(phydev, 0x1f, 0x0003);
 715         phy_clear_bits(phydev, 0x19, BIT(0));
 716         phy_clear_bits(phydev, 0x10, BIT(10));
 717         phy_write(phydev, 0x1f, 0x0000);
 718 }
 719
 720 static void rtl8168g_disable_aldps(struct phy_device *phydev)
 721 {
 722         phy_modify_paged(phydev, 0x0a43, 0x10, BIT(2), 0);
 723 }
 724
 725 static void rtl8168g_enable_gphy_10m(struct phy_device *phydev)
 726 {
 727         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(11));
 728 }
 729
 730 static void rtl8168g_phy_adjust_10m_aldps(struct phy_device *phydev)
 731 {
 732         phy_modify_paged(phydev, 0x0bcc, 0x14, BIT(8), 0);
 733         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(7) | BIT(6));
 734         r8168g_phy_param(phydev, 0x8084, 0x6000, 0x0000);
 735         phy_modify_paged(phydev, 0x0a43, 0x10, 0x0000, 0x1003);
 736 }
 737
 738 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp,
 739                                      struct phy_device *phydev)
 740 {
 741         int ret;
 742
 743         r8169_apply_firmware(tp);
 744
 745         ret = phy_read_paged(phydev, 0x0a46, 0x10);
 746         if (ret & BIT(8))
 747                 phy_modify_paged(phydev, 0x0bcc, 0x12, BIT(15), 0);
 748         else
 749                 phy_modify_paged(phydev, 0x0bcc, 0x12, 0, BIT(15));
 750
 751         ret = phy_read_paged(phydev, 0x0a46, 0x13);
 752         if (ret & BIT(8))
 753                 phy_modify_paged(phydev, 0x0c41, 0x15, 0, BIT(1));
 754         else
 755                 phy_modify_paged(phydev, 0x0c41, 0x15, BIT(1), 0);
 756
 757         /* Enable PHY auto speed down */
 758         phy_modify_paged(phydev, 0x0a44, 0x11, 0, BIT(3) | BIT(2));
 759
 760         rtl8168g_phy_adjust_10m_aldps(phydev);
 761
 762         /* EEE auto-fallback function */
 763         phy_modify_paged(phydev, 0x0a4b, 0x11, 0, BIT(2));
 764
 765         /* Enable UC LPF tune function */
 766         r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
 767
 768         phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
 769
 770         /* Improve SWR Efficiency */
 771         phy_write(phydev, 0x1f, 0x0bcd);
 772         phy_write(phydev, 0x14, 0x5065);
 773         phy_write(phydev, 0x14, 0xd065);
 774         phy_write(phydev, 0x1f, 0x0bc8);
 775         phy_write(phydev, 0x11, 0x5655);
 776         phy_write(phydev, 0x1f, 0x0bcd);
 777         phy_write(phydev, 0x14, 0x1065);
 778         phy_write(phydev, 0x14, 0x9065);
 779         phy_write(phydev, 0x14, 0x1065);
 780         phy_write(phydev, 0x1f, 0x0000);
 781
 782         rtl8168g_disable_aldps(phydev);
 783         rtl8168g_config_eee_phy(phydev);
 784 }
 785
 786 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp,
 787                                      struct phy_device *phydev)
 788 {
 789         r8169_apply_firmware(tp);
 790         rtl8168g_config_eee_phy(phydev);
 791 }
 792
 793 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp,
 794                                      struct phy_device *phydev)
 795 {
 796         u16 ioffset, rlen;
 797         u32 data;
 798
 799         r8169_apply_firmware(tp);
 800
 801         /* CHIN EST parameter update */
 802         r8168g_phy_param(phydev, 0x808a, 0x003f, 0x000a);
 803
 804         /* enable R-tune & PGA-retune function */
 805         r8168g_phy_param(phydev, 0x0811, 0x0000, 0x0800);
 806         phy_modify_paged(phydev, 0x0a42, 0x16, 0x0000, 0x0002);
 807
 808         rtl8168g_enable_gphy_10m(phydev);
 809
 810         ioffset = rtl8168h_2_get_adc_bias_ioffset(tp);
 811         if (ioffset != 0xffff)
 812                 phy_write_paged(phydev, 0x0bcf, 0x16, ioffset);
 813
 814         /* Modify rlen (TX LPF corner frequency) level */
 815         data = phy_read_paged(phydev, 0x0bcd, 0x16);
 816         data &= 0x000f;
 817         rlen = 0;
 818         if (data > 3)
 819                 rlen = data - 3;
 820         data = rlen | (rlen << 4) | (rlen << 8) | (rlen << 12);
 821         phy_write_paged(phydev, 0x0bcd, 0x17, data);
 822
 823         /* disable phy pfm mode */
 824         phy_modify_paged(phydev, 0x0a44, 0x11, BIT(7), 0);
 825
 826         /* disable 10m pll off */
 827         phy_modify_paged(phydev, 0x0a43, 0x10, BIT(0), 0);
 828
 829         rtl8168g_disable_aldps(phydev);
 830         rtl8168g_config_eee_phy(phydev);
 831 }
 832
 833 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp,
 834                                       struct phy_device *phydev)
 835 {
 836         rtl8168g_phy_adjust_10m_aldps(phydev);
 837
 838         /* Enable UC LPF tune function */
 839         r8168g_phy_param(phydev, 0x8012, 0x0000, 0x8000);
 840
 841         /* Set rg_sel_sdm_rate */
 842         phy_modify_paged(phydev, 0x0c42, 0x11, BIT(13), BIT(14));
 843
 844         /* Channel estimation parameters */
 845         r8168g_phy_param(phydev, 0x80f3, 0xff00, 0x8b00);
 846         r8168g_phy_param(phydev, 0x80f0, 0xff00, 0x3a00);
 847         r8168g_phy_param(phydev, 0x80ef, 0xff00, 0x0500);
 848         r8168g_phy_param(phydev, 0x80f6, 0xff00, 0x6e00);
 849         r8168g_phy_param(phydev, 0x80ec, 0xff00, 0x6800);
 850         r8168g_phy_param(phydev, 0x80ed, 0xff00, 0x7c00);
 851         r8168g_phy_param(phydev, 0x80f2, 0xff00, 0xf400);
 852         r8168g_phy_param(phydev, 0x80f4, 0xff00, 0x8500);
 853         r8168g_phy_param(phydev, 0x8110, 0xff00, 0xa800);
 854         r8168g_phy_param(phydev, 0x810f, 0xff00, 0x1d00);
 855         r8168g_phy_param(phydev, 0x8111, 0xff00, 0xf500);
 856         r8168g_phy_param(phydev, 0x8113, 0xff00, 0x6100);
 857         r8168g_phy_param(phydev, 0x8115, 0xff00, 0x9200);
 858         r8168g_phy_param(phydev, 0x810e, 0xff00, 0x0400);
 859         r8168g_phy_param(phydev, 0x810c, 0xff00, 0x7c00);
 860         r8168g_phy_param(phydev, 0x810b, 0xff00, 0x5a00);
 861         r8168g_phy_param(phydev, 0x80d1, 0xff00, 0xff00);
 862         r8168g_phy_param(phydev, 0x80cd, 0xff00, 0x9e00);
 863         r8168g_phy_param(phydev, 0x80d3, 0xff00, 0x0e00);
 864         r8168g_phy_param(phydev, 0x80d5, 0xff00, 0xca00);
 865         r8168g_phy_param(phydev, 0x80d7, 0xff00, 0x8400);
 866
 867         /* Force PWM-mode */
 868         phy_write(phydev, 0x1f, 0x0bcd);
 869         phy_write(phydev, 0x14, 0x5065);
 870         phy_write(phydev, 0x14, 0xd065);
 871         phy_write(phydev, 0x1f, 0x0bc8);
 872         phy_write(phydev, 0x12, 0x00ed);
 873         phy_write(phydev, 0x1f, 0x0bcd);
 874         phy_write(phydev, 0x14, 0x1065);
 875         phy_write(phydev, 0x14, 0x9065);
 876         phy_write(phydev, 0x14, 0x1065);
 877         phy_write(phydev, 0x1f, 0x0000);
 878
 879         rtl8168g_disable_aldps(phydev);
 880         rtl8168g_config_eee_phy(phydev);
 881 }
 882
 883 static void rtl8117_hw_phy_config(struct rtl8169_private *tp,
 884                                   struct phy_device *phydev)
 885 {
 886         /* CHN EST parameters adjust - fnet */
 887         r8168g_phy_param(phydev, 0x808e, 0xff00, 0x4800);
 888         r8168g_phy_param(phydev, 0x8090, 0xff00, 0xcc00);
 889         r8168g_phy_param(phydev, 0x8092, 0xff00, 0xb000);
 890
 891         r8168g_phy_param(phydev, 0x8088, 0xff00, 0x6000);
 892         r8168g_phy_param(phydev, 0x808b, 0x3f00, 0x0b00);
 893         r8168g_phy_param(phydev, 0x808d, 0x1f00, 0x0600);
 894         r8168g_phy_param(phydev, 0x808c, 0xff00, 0xb000);
 895         r8168g_phy_param(phydev, 0x80a0, 0xff00, 0x2800);
 896         r8168g_phy_param(phydev, 0x80a2, 0xff00, 0x5000);
 897         r8168g_phy_param(phydev, 0x809b, 0xf800, 0xb000);
 898         r8168g_phy_param(phydev, 0x809a, 0xff00, 0x4b00);
 899         r8168g_phy_param(phydev, 0x809d, 0x3f00, 0x0800);
 900         r8168g_phy_param(phydev, 0x80a1, 0xff00, 0x7000);
 901         r8168g_phy_param(phydev, 0x809f, 0x1f00, 0x0300);
 902         r8168g_phy_param(phydev, 0x809e, 0xff00, 0x8800);
 903         r8168g_phy_param(phydev, 0x80b2, 0xff00, 0x2200);
 904         r8168g_phy_param(phydev, 0x80ad, 0xf800, 0x9800);
 905         r8168g_phy_param(phydev, 0x80af, 0x3f00, 0x0800);
 906         r8168g_phy_param(phydev, 0x80b3, 0xff00, 0x6f00);
 907         r8168g_phy_param(phydev, 0x80b1, 0x1f00, 0x0300);
 908         r8168g_phy_param(phydev, 0x80b0, 0xff00, 0x9300);
 909
 910         r8168g_phy_param(phydev, 0x8011, 0x0000, 0x0800);
 911
 912         rtl8168g_enable_gphy_10m(phydev);
 913
 914         r8168g_phy_param(phydev, 0x8016, 0x0000, 0x0400);
 915
 916         rtl8168g_disable_aldps(phydev);
 917         rtl8168h_config_eee_phy(phydev);
 918 }
 919
 920 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp,
 921                                    struct phy_device *phydev)
 922 {
 923         static const struct phy_reg phy_reg_init[] = {
 924                 { 0x1f, 0x0003 },
 925                 { 0x08, 0x441d },
 926                 { 0x01, 0x9100 },
 927                 { 0x1f, 0x0000 }
 928         };
 929
 930         phy_set_bits(phydev, 0x11, BIT(12));
 931         phy_set_bits(phydev, 0x19, BIT(13));
 932         phy_set_bits(phydev, 0x10, BIT(15));
 933
 934         rtl_writephy_batch(phydev, phy_reg_init);
 935 }
 936
 937 static void rtl8401_hw_phy_config(struct rtl8169_private *tp,
 938                                   struct phy_device *phydev)
 939 {
 940         phy_set_bits(phydev, 0x11, BIT(12));
 941         phy_modify_paged(phydev, 0x0002, 0x0f, 0x0000, 0x0003);
 942 }
 943
 944 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp,
 945                                    struct phy_device *phydev)
 946 {
 947         /* Disable ALDPS before ram code */
 948         phy_write(phydev, 0x18, 0x0310);
 949         msleep(100);
 950
 951         r8169_apply_firmware(tp);
 952
 953         phy_write_paged(phydev, 0x0005, 0x1a, 0x0000);
 954         phy_write_paged(phydev, 0x0004, 0x1c, 0x0000);
 955         phy_write_paged(phydev, 0x0001, 0x15, 0x7701);
 956 }
 957
 958 static void rtl8402_hw_phy_config(struct rtl8169_private *tp,
 959                                   struct phy_device *phydev)
 960 {
 961         /* Disable ALDPS before setting firmware */
 962         phy_write(phydev, 0x18, 0x0310);
 963         msleep(20);
 964
 965         r8169_apply_firmware(tp);
 966
 967         /* EEE setting */
 968         phy_write(phydev, 0x1f, 0x0004);
 969         phy_write(phydev, 0x10, 0x401f);
 970         phy_write(phydev, 0x19, 0x7030);
 971         phy_write(phydev, 0x1f, 0x0000);
 972 }
 973
 974 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp,
 975                                    struct phy_device *phydev)
 976 {
 977         static const struct phy_reg phy_reg_init[] = {
 978                 { 0x1f, 0x0004 },
 979                 { 0x10, 0xc07f },
 980                 { 0x19, 0x7030 },
 981                 { 0x1f, 0x0000 }
 982         };
 983
 984         /* Disable ALDPS before ram code */
 985         phy_write(phydev, 0x18, 0x0310);
 986         msleep(100);
 987
 988         r8169_apply_firmware(tp);
 989
 990         rtl_writephy_batch(phydev, phy_reg_init);
 991 }
 992
 993 static void rtl8125_legacy_force_mode(struct phy_device *phydev)
 994 {
 995         phy_modify_paged(phydev, 0xa5b, 0x12, BIT(15), 0);
 996 }
 997
 998 static void rtl8125a_2_hw_phy_config(struct rtl8169_private *tp,
 999                                      struct phy_device *phydev)
1000 {
1001         int i;
1002
1003         phy_modify_paged(phydev, 0xad4, 0x17, 0x0000, 0x0010);
1004         phy_modify_paged(phydev, 0xad1, 0x13, 0x03ff, 0x03ff);
1005         phy_modify_paged(phydev, 0xad3, 0x11, 0x003f, 0x0006);
1006         phy_modify_paged(phydev, 0xac0, 0x14, 0x1100, 0x0000);
1007         phy_modify_paged(phydev, 0xacc, 0x10, 0x0003, 0x0002);
1008         phy_modify_paged(phydev, 0xad4, 0x10, 0x00e7, 0x0044);
1009         phy_modify_paged(phydev, 0xac1, 0x12, 0x0080, 0x0000);
1010         phy_modify_paged(phydev, 0xac8, 0x10, 0x0300, 0x0000);
1011         phy_modify_paged(phydev, 0xac5, 0x17, 0x0007, 0x0002);
1012         phy_write_paged(phydev, 0xad4, 0x16, 0x00a8);
1013         phy_write_paged(phydev, 0xac5, 0x16, 0x01ff);
1014         phy_modify_paged(phydev, 0xac8, 0x15, 0x00f0, 0x0030);
1015
1016         phy_write(phydev, 0x1f, 0x0b87);
1017         phy_write(phydev, 0x16, 0x80a2);
1018         phy_write(phydev, 0x17, 0x0153);
1019         phy_write(phydev, 0x16, 0x809c);
1020         phy_write(phydev, 0x17, 0x0153);
1021         phy_write(phydev, 0x1f, 0x0000);
1022
1023         phy_write(phydev, 0x1f, 0x0a43);
1024         phy_write(phydev, 0x13, 0x81B3);
1025         phy_write(phydev, 0x14, 0x0043);
1026         phy_write(phydev, 0x14, 0x00A7);
1027         phy_write(phydev, 0x14, 0x00D6);
1028         phy_write(phydev, 0x14, 0x00EC);
1029         phy_write(phydev, 0x14, 0x00F6);
1030         phy_write(phydev, 0x14, 0x00FB);
1031         phy_write(phydev, 0x14, 0x00FD);
1032         phy_write(phydev, 0x14, 0x00FF);
1033         phy_write(phydev, 0x14, 0x00BB);
1034         phy_write(phydev, 0x14, 0x0058);
1035         phy_write(phydev, 0x14, 0x0029);
1036         phy_write(phydev, 0x14, 0x0013);
1037         phy_write(phydev, 0x14, 0x0009);
1038         phy_write(phydev, 0x14, 0x0004);
1039         phy_write(phydev, 0x14, 0x0002);
1040         for (i = 0; i < 25; i++)
1041                 phy_write(phydev, 0x14, 0x0000);
1042         phy_write(phydev, 0x1f, 0x0000);
1043
1044         r8168g_phy_param(phydev, 0x8257, 0xffff, 0x020F);
1045         r8168g_phy_param(phydev, 0x80ea, 0xffff, 0x7843);
1046
1047         r8169_apply_firmware(tp);
1048
1049         phy_modify_paged(phydev, 0xd06, 0x14, 0x0000, 0x2000);
1050
1051         r8168g_phy_param(phydev, 0x81a2, 0x0000, 0x0100);
1052
1053         phy_modify_paged(phydev, 0xb54, 0x16, 0xff00, 0xdb00);
1054         phy_modify_paged(phydev, 0xa45, 0x12, 0x0001, 0x0000);
1055         phy_modify_paged(phydev, 0xa5d, 0x12, 0x0000, 0x0020);
1056         phy_modify_paged(phydev, 0xad4, 0x17, 0x0010, 0x0000);
1057         phy_modify_paged(phydev, 0xa86, 0x15, 0x0001, 0x0000);
1058         rtl8168g_enable_gphy_10m(phydev);
1059
1060         rtl8168g_disable_aldps(phydev);
1061         rtl8125_config_eee_phy(phydev);
1062 }
1063
1064 static void rtl8125b_hw_phy_config(struct rtl8169_private *tp,
1065                                    struct phy_device *phydev)
1066 {
1067         r8169_apply_firmware(tp);
1068         rtl8168g_enable_gphy_10m(phydev);
1069
1070         phy_modify_paged(phydev, 0xac4, 0x13, 0x00f0, 0x0090);
1071         phy_modify_paged(phydev, 0xad3, 0x10, 0x0003, 0x0001);
1072
1073         phy_write(phydev, 0x1f, 0x0b87);
1074         phy_write(phydev, 0x16, 0x80f5);
1075         phy_write(phydev, 0x17, 0x760e);
1076         phy_write(phydev, 0x16, 0x8107);
1077         phy_write(phydev, 0x17, 0x360e);
1078         phy_write(phydev, 0x16, 0x8551);
1079         phy_modify(phydev, 0x17, 0xff00, 0x0800);
1080         phy_write(phydev, 0x1f, 0x0000);
1081
1082         phy_modify_paged(phydev, 0xbf0, 0x10, 0xe000, 0xa000);
1083         phy_modify_paged(phydev, 0xbf4, 0x13, 0x0f00, 0x0300);
1084
1085         r8168g_phy_param(phydev, 0x8044, 0xffff, 0x2417);
1086         r8168g_phy_param(phydev, 0x804a, 0xffff, 0x2417);
1087         r8168g_phy_param(phydev, 0x8050, 0xffff, 0x2417);
1088         r8168g_phy_param(phydev, 0x8056, 0xffff, 0x2417);
1089         r8168g_phy_param(phydev, 0x805c, 0xffff, 0x2417);
1090         r8168g_phy_param(phydev, 0x8062, 0xffff, 0x2417);
1091         r8168g_phy_param(phydev, 0x8068, 0xffff, 0x2417);
1092         r8168g_phy_param(phydev, 0x806e, 0xffff, 0x2417);
1093         r8168g_phy_param(phydev, 0x8074, 0xffff, 0x2417);
1094         r8168g_phy_param(phydev, 0x807a, 0xffff, 0x2417);
1095
1096         phy_modify_paged(phydev, 0xa4c, 0x15, 0x0000, 0x0040);
1097         phy_modify_paged(phydev, 0xbf8, 0x12, 0xe000, 0xa000);
1098
1099         rtl8125_legacy_force_mode(phydev);
1100         rtl8168g_disable_aldps(phydev);
1101         rtl8125_config_eee_phy(phydev);
1102 }
1103
1104 static void rtl8125d_hw_phy_config(struct rtl8169_private *tp,
1105                                    struct phy_device *phydev)
1106 {
1107         r8169_apply_firmware(tp);
1108         rtl8168g_enable_gphy_10m(phydev);
1109         rtl8125_legacy_force_mode(phydev);
1110         rtl8168g_disable_aldps(phydev);
1111         rtl8125_config_eee_phy(phydev);
1112 }
1113
1114 static void rtl8126a_hw_phy_config(struct rtl8169_private *tp,
1115                                    struct phy_device *phydev)
1116 {
1117         r8169_apply_firmware(tp);
1118         rtl8168g_enable_gphy_10m(phydev);
1119         rtl8125_legacy_force_mode(phydev);
1120         rtl8168g_disable_aldps(phydev);
1121         rtl8125_common_config_eee_phy(phydev);
1122 }
1123
1124 void r8169_hw_phy_config(struct rtl8169_private *tp, struct phy_device *phydev,
1125                          enum mac_version ver)
1126 {
1127         static const rtl_phy_cfg_fct phy_configs[] = {
1128                 /* PCI devices. */
1129                 [RTL_GIGA_MAC_VER_02] = rtl8169s_hw_phy_config,
1130                 [RTL_GIGA_MAC_VER_03] = rtl8169s_hw_phy_config,
1131                 [RTL_GIGA_MAC_VER_04] = rtl8169sb_hw_phy_config,
1132                 [RTL_GIGA_MAC_VER_05] = rtl8169scd_hw_phy_config,
1133                 [RTL_GIGA_MAC_VER_06] = rtl8169sce_hw_phy_config,
1134                 /* PCI-E devices. */
1135                 [RTL_GIGA_MAC_VER_07] = rtl8102e_hw_phy_config,
1136                 [RTL_GIGA_MAC_VER_08] = rtl8102e_hw_phy_config,
1137                 [RTL_GIGA_MAC_VER_09] = rtl8102e_hw_phy_config,
1138                 [RTL_GIGA_MAC_VER_10] = NULL,
1139                 [RTL_GIGA_MAC_VER_11] = rtl8168bb_hw_phy_config,
1140                 [RTL_GIGA_MAC_VER_14] = rtl8401_hw_phy_config,
1141                 [RTL_GIGA_MAC_VER_17] = rtl8168bef_hw_phy_config,
1142                 [RTL_GIGA_MAC_VER_18] = rtl8168cp_1_hw_phy_config,
1143                 [RTL_GIGA_MAC_VER_19] = rtl8168c_1_hw_phy_config,
1144                 [RTL_GIGA_MAC_VER_20] = rtl8168c_2_hw_phy_config,
1145                 [RTL_GIGA_MAC_VER_21] = rtl8168c_3_hw_phy_config,
1146                 [RTL_GIGA_MAC_VER_22] = rtl8168c_3_hw_phy_config,
1147                 [RTL_GIGA_MAC_VER_23] = rtl8168cp_2_hw_phy_config,
1148                 [RTL_GIGA_MAC_VER_24] = rtl8168cp_2_hw_phy_config,
1149                 [RTL_GIGA_MAC_VER_25] = rtl8168d_1_hw_phy_config,
1150                 [RTL_GIGA_MAC_VER_26] = rtl8168d_2_hw_phy_config,
1151                 [RTL_GIGA_MAC_VER_28] = rtl8168d_4_hw_phy_config,
1152                 [RTL_GIGA_MAC_VER_29] = rtl8105e_hw_phy_config,
1153                 [RTL_GIGA_MAC_VER_30] = rtl8105e_hw_phy_config,
1154                 [RTL_GIGA_MAC_VER_31] = NULL,
1155                 [RTL_GIGA_MAC_VER_32] = rtl8168e_1_hw_phy_config,
1156                 [RTL_GIGA_MAC_VER_33] = rtl8168e_1_hw_phy_config,
1157                 [RTL_GIGA_MAC_VER_34] = rtl8168e_2_hw_phy_config,
1158                 [RTL_GIGA_MAC_VER_35] = rtl8168f_1_hw_phy_config,
1159                 [RTL_GIGA_MAC_VER_36] = rtl8168f_2_hw_phy_config,
1160                 [RTL_GIGA_MAC_VER_37] = rtl8402_hw_phy_config,
1161                 [RTL_GIGA_MAC_VER_38] = rtl8411_hw_phy_config,
1162                 [RTL_GIGA_MAC_VER_39] = rtl8106e_hw_phy_config,
1163                 [RTL_GIGA_MAC_VER_40] = rtl8168g_1_hw_phy_config,
1164                 [RTL_GIGA_MAC_VER_42] = rtl8168g_2_hw_phy_config,
1165                 [RTL_GIGA_MAC_VER_43] = rtl8168g_2_hw_phy_config,
1166                 [RTL_GIGA_MAC_VER_44] = rtl8168g_2_hw_phy_config,
1167                 [RTL_GIGA_MAC_VER_46] = rtl8168h_2_hw_phy_config,
1168                 [RTL_GIGA_MAC_VER_48] = rtl8168h_2_hw_phy_config,
1169                 [RTL_GIGA_MAC_VER_51] = rtl8168ep_2_hw_phy_config,
1170                 [RTL_GIGA_MAC_VER_52] = rtl8117_hw_phy_config,
1171                 [RTL_GIGA_MAC_VER_53] = rtl8117_hw_phy_config,
1172                 [RTL_GIGA_MAC_VER_61] = rtl8125a_2_hw_phy_config,
1173                 [RTL_GIGA_MAC_VER_63] = rtl8125b_hw_phy_config,
1174                 [RTL_GIGA_MAC_VER_64] = rtl8125d_hw_phy_config,
1175                 [RTL_GIGA_MAC_VER_65] = rtl8126a_hw_phy_config,
1176                 [RTL_GIGA_MAC_VER_66] = rtl8126a_hw_phy_config,
1177         };
1178
1179         if (phy_configs[ver])
1180                 phy_configs[ver](tp, phydev);
1181 }