drivers/net/ethernet/sfc/nic.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /****************************************************************************
   3  * Driver for Solarflare network controllers and boards
   4  * Copyright 2005-2006 Fen Systems Ltd.
   5  * Copyright 2006-2013 Solarflare Communications Inc.
   6  */
   7
   8 #include <linux/bitops.h>
   9 #include <linux/delay.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/pci.h>
  12 #include <linux/module.h>
  13 #include <linux/seq_file.h>
  14 #include <linux/cpu_rmap.h>
  15 #include "net_driver.h"
  16 #include "bitfield.h"
  17 #include "efx.h"
  18 #include "nic.h"
  19 #include "ef10_regs.h"
  20 #include "io.h"
  21 #include "workarounds.h"
  22 #include "mcdi_pcol.h"
  23
  24 /**************************************************************************
  25  *
  26  * Generic buffer handling
  27  * These buffers are used for interrupt status, MAC stats, etc.
  28  *
  29  **************************************************************************/
  30
  31 int efx_nic_alloc_buffer(struct efx_nic *efx, struct efx_buffer *buffer,
  32                          unsigned int len, gfp_t gfp_flags)
  33 {
  34         buffer->addr = dma_alloc_coherent(&efx->pci_dev->dev, len,
  35                                           &buffer->dma_addr, gfp_flags);
  36         if (!buffer->addr)
  37                 return -ENOMEM;
  38         buffer->len = len;
  39         return 0;
  40 }
  41
  42 void efx_nic_free_buffer(struct efx_nic *efx, struct efx_buffer *buffer)
  43 {
  44         if (buffer->addr) {
  45                 dma_free_coherent(&efx->pci_dev->dev, buffer->len,
  46                                   buffer->addr, buffer->dma_addr);
  47                 buffer->addr = NULL;
  48         }
  49 }
  50
  51 /* Check whether an event is present in the eventq at the current
  52  * read pointer.  Only useful for self-test.
  53  */
  54 bool efx_nic_event_present(struct efx_channel *channel)
  55 {
  56         return efx_event_present(efx_event(channel, channel->eventq_read_ptr));
  57 }
  58
  59 void efx_nic_event_test_start(struct efx_channel *channel)
  60 {
  61         channel->event_test_cpu = -1;
  62         smp_wmb();
  63         channel->efx->type->ev_test_generate(channel);
  64 }
  65
  66 int efx_nic_irq_test_start(struct efx_nic *efx)
  67 {
  68         efx->last_irq_cpu = -1;
  69         smp_wmb();
  70         return efx->type->irq_test_generate(efx);
  71 }
  72
  73 /* Hook interrupt handler(s)
  74  * Try MSI and then legacy interrupts.
  75  */
  76 int efx_nic_init_interrupt(struct efx_nic *efx)
  77 {
  78         struct efx_channel *channel;
  79         unsigned int n_irqs;
  80         int rc;
  81
  82         if (!EFX_INT_MODE_USE_MSI(efx)) {
  83                 rc = request_irq(efx->legacy_irq,
  84                                  efx->type->irq_handle_legacy, IRQF_SHARED,
  85                                  efx->name, efx);
  86                 if (rc) {
  87                         netif_err(efx, drv, efx->net_dev,
  88                                   "failed to hook legacy IRQ %d\n",
  89                                   efx->pci_dev->irq);
  90                         goto fail1;
  91                 }
  92                 efx->irqs_hooked = true;
  93                 return 0;
  94         }
  95
  96 #ifdef CONFIG_RFS_ACCEL
  97         if (efx->interrupt_mode == EFX_INT_MODE_MSIX) {
  98                 efx->net_dev->rx_cpu_rmap =
  99                         alloc_irq_cpu_rmap(efx->n_rx_channels);
 100                 if (!efx->net_dev->rx_cpu_rmap) {
 101                         rc = -ENOMEM;
 102                         goto fail1;
 103                 }
 104         }
 105 #endif
 106
 107         /* Hook MSI or MSI-X interrupt */
 108         n_irqs = 0;
 109         efx_for_each_channel(channel, efx) {
 110                 rc = request_irq(channel->irq, efx->type->irq_handle_msi,
 111                                  IRQF_PROBE_SHARED, /* Not shared */
 112                                  efx->msi_context[channel->channel].name,
 113                                  &efx->msi_context[channel->channel]);
 114                 if (rc) {
 115                         netif_err(efx, drv, efx->net_dev,
 116                                   "failed to hook IRQ %d\n", channel->irq);
 117                         goto fail2;
 118                 }
 119                 ++n_irqs;
 120
 121 #ifdef CONFIG_RFS_ACCEL
 122                 if (efx->interrupt_mode == EFX_INT_MODE_MSIX &&
 123                     channel->channel < efx->n_rx_channels) {
 124                         rc = irq_cpu_rmap_add(efx->net_dev->rx_cpu_rmap,
 125                                               channel->irq);
 126                         if (rc)
 127                                 goto fail2;
 128                 }
 129 #endif
 130         }
 131
 132         efx->irqs_hooked = true;
 133         return 0;
 134
 135  fail2:
 136 #ifdef CONFIG_RFS_ACCEL
 137         free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
 138         efx->net_dev->rx_cpu_rmap = NULL;
 139 #endif
 140         efx_for_each_channel(channel, efx) {
 141                 if (n_irqs-- == 0)
 142                         break;
 143                 free_irq(channel->irq, &efx->msi_context[channel->channel]);
 144         }
 145  fail1:
 146         return rc;
 147 }
 148
 149 void efx_nic_fini_interrupt(struct efx_nic *efx)
 150 {
 151         struct efx_channel *channel;
 152
 153 #ifdef CONFIG_RFS_ACCEL
 154         free_irq_cpu_rmap(efx->net_dev->rx_cpu_rmap);
 155         efx->net_dev->rx_cpu_rmap = NULL;
 156 #endif
 157
 158         if (!efx->irqs_hooked)
 159                 return;
 160         if (EFX_INT_MODE_USE_MSI(efx)) {
 161                 /* Disable MSI/MSI-X interrupts */
 162                 efx_for_each_channel(channel, efx)
 163                         free_irq(channel->irq,
 164                                  &efx->msi_context[channel->channel]);
 165         } else {
 166                 /* Disable legacy interrupt */
 167                 free_irq(efx->legacy_irq, efx);
 168         }
 169         efx->irqs_hooked = false;
 170 }
 171
 172 /* Register dump */
 173
 174 #define REGISTER_REVISION_ED    4
 175 #define REGISTER_REVISION_EZ    4       /* latest EF10 revision */
 176
 177 struct efx_nic_reg {
 178         u32 offset:24;
 179         u32 min_revision:3, max_revision:3;
 180 };
 181
 182 #define REGISTER(name, arch, min_rev, max_rev) {                        \
 183         arch ## R_ ## min_rev ## max_rev ## _ ## name,                  \
 184         REGISTER_REVISION_ ## arch ## min_rev,                          \
 185         REGISTER_REVISION_ ## arch ## max_rev                           \
 186 }
 187 #define REGISTER_DZ(name) REGISTER(name, E, D, Z)
 188
 189 static const struct efx_nic_reg efx_nic_regs[] = {
 190         /* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */
 191         /* XX_CORE_STAT is partly RC */
 192         REGISTER_DZ(BIU_HW_REV_ID),
 193         REGISTER_DZ(MC_DB_LWRD),
 194         REGISTER_DZ(MC_DB_HWRD),
 195 };
 196
 197 struct efx_nic_reg_table {
 198         u32 offset:24;
 199         u32 min_revision:3, max_revision:3;
 200         u32 step:6, rows:21;
 201 };
 202
 203 #define REGISTER_TABLE_DIMENSIONS(_, offset, arch, min_rev, max_rev, step, rows) { \
 204         offset,                                                         \
 205         REGISTER_REVISION_ ## arch ## min_rev,                          \
 206         REGISTER_REVISION_ ## arch ## max_rev,                          \
 207         step, rows                                                      \
 208 }
 209 #define REGISTER_TABLE(name, arch, min_rev, max_rev)                    \
 210         REGISTER_TABLE_DIMENSIONS(                                      \
 211                 name, arch ## R_ ## min_rev ## max_rev ## _ ## name,    \
 212                 arch, min_rev, max_rev,                                 \
 213                 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP, \
 214                 arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)
 215 #define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)
 216
 217 static const struct efx_nic_reg_table efx_nic_reg_tables[] = {
 218         REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),
 219 };
 220
 221 size_t efx_nic_get_regs_len(struct efx_nic *efx)
 222 {
 223         const struct efx_nic_reg *reg;
 224         const struct efx_nic_reg_table *table;
 225         size_t len = 0;
 226
 227         for (reg = efx_nic_regs;
 228              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
 229              reg++)
 230                 if (efx->type->revision >= reg->min_revision &&
 231                     efx->type->revision <= reg->max_revision)
 232                         len += sizeof(efx_oword_t);
 233
 234         for (table = efx_nic_reg_tables;
 235              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
 236              table++)
 237                 if (efx->type->revision >= table->min_revision &&
 238                     efx->type->revision <= table->max_revision)
 239                         len += table->rows * min_t(size_t, table->step, 16);
 240
 241         return len;
 242 }
 243
 244 void efx_nic_get_regs(struct efx_nic *efx, void *buf)
 245 {
 246         const struct efx_nic_reg *reg;
 247         const struct efx_nic_reg_table *table;
 248
 249         for (reg = efx_nic_regs;
 250              reg < efx_nic_regs + ARRAY_SIZE(efx_nic_regs);
 251              reg++) {
 252                 if (efx->type->revision >= reg->min_revision &&
 253                     efx->type->revision <= reg->max_revision) {
 254                         efx_reado(efx, (efx_oword_t *)buf, reg->offset);
 255                         buf += sizeof(efx_oword_t);
 256                 }
 257         }
 258
 259         for (table = efx_nic_reg_tables;
 260              table < efx_nic_reg_tables + ARRAY_SIZE(efx_nic_reg_tables);
 261              table++) {
 262                 size_t size, i;
 263
 264                 if (!(efx->type->revision >= table->min_revision &&
 265                       efx->type->revision <= table->max_revision))
 266                         continue;
 267
 268                 size = min_t(size_t, table->step, 16);
 269
 270                 for (i = 0; i < table->rows; i++) {
 271                         switch (table->step) {
 272                         case 4: /* 32-bit SRAM */
 273                                 efx_readd(efx, buf, table->offset + 4 * i);
 274                                 break;
 275                         case 16: /* 128-bit-readable register */
 276                                 efx_reado_table(efx, buf, table->offset, i);
 277                                 break;
 278                         case 32: /* 128-bit register, interleaved */
 279                                 efx_reado_table(efx, buf, table->offset, 2 * i);
 280                                 break;
 281                         default:
 282                                 WARN_ON(1);
 283                                 return;
 284                         }
 285                         buf += size;
 286                 }
 287         }
 288 }
 289
 290 /**
 291  * efx_nic_describe_stats - Describe supported statistics for ethtool
 292  * @desc: Array of &struct efx_hw_stat_desc describing the statistics
 293  * @count: Length of the @desc array
 294  * @mask: Bitmask of which elements of @desc are enabled
 295  * @names: Buffer to copy names to, or %NULL.  The names are copied
 296  *      starting at intervals of %ETH_GSTRING_LEN bytes.
 297  *
 298  * Returns the number of visible statistics, i.e. the number of set
 299  * bits in the first @count bits of @mask for which a name is defined.
 300  */
 301 size_t efx_nic_describe_stats(const struct efx_hw_stat_desc *desc, size_t count,
 302                               const unsigned long *mask, u8 **names)
 303 {
 304         size_t visible = 0;
 305         size_t index;
 306
 307         for_each_set_bit(index, mask, count) {
 308                 if (desc[index].name) {
 309                         if (names)
 310                                 ethtool_puts(names, desc[index].name);
 311                         ++visible;
 312                 }
 313         }
 314
 315         return visible;
 316 }
 317
 318 /**
 319  * efx_nic_copy_stats - Copy stats from the DMA buffer in to an
 320  *      intermediate buffer. This is used to get a consistent
 321  *      set of stats while the DMA buffer can be written at any time
 322  *      by the NIC.
 323  * @efx: The associated NIC.
 324  * @dest: Destination buffer. Must be the same size as the DMA buffer.
 325  */
 326 int efx_nic_copy_stats(struct efx_nic *efx, __le64 *dest)
 327 {
 328         __le64 *dma_stats = efx->stats_buffer.addr;
 329         __le64 generation_start, generation_end;
 330         int rc = 0, retry;
 331
 332         if (!dest)
 333                 return 0;
 334
 335         if (!dma_stats)
 336                 goto return_zeroes;
 337
 338         /* If we're unlucky enough to read statistics during the DMA, wait
 339          * up to 10ms for it to finish (typically takes <500us)
 340          */
 341         for (retry = 0; retry < 100; ++retry) {
 342                 generation_end = dma_stats[efx->num_mac_stats - 1];
 343                 if (generation_end == EFX_MC_STATS_GENERATION_INVALID)
 344                         goto return_zeroes;
 345                 rmb();
 346                 memcpy(dest, dma_stats, efx->num_mac_stats * sizeof(__le64));
 347                 rmb();
 348                 generation_start = dma_stats[MC_CMD_MAC_GENERATION_START];
 349                 if (generation_end == generation_start)
 350                         return 0; /* return good data */
 351                 udelay(100);
 352         }
 353
 354         rc = -EIO;
 355
 356 return_zeroes:
 357         memset(dest, 0, efx->num_mac_stats * sizeof(u64));
 358         return rc;
 359 }
 360
 361 /**
 362  * efx_nic_update_stats - Convert statistics DMA buffer to array of u64
 363  * @desc: Array of &struct efx_hw_stat_desc describing the DMA buffer
 364  *      layout.  DMA widths of 0, 16, 32 and 64 are supported; where
 365  *      the width is specified as 0 the corresponding element of
 366  *      @stats is not updated.
 367  * @count: Length of the @desc array
 368  * @mask: Bitmask of which elements of @desc are enabled
 369  * @stats: Buffer to update with the converted statistics.  The length
 370  *      of this array must be at least @count.
 371  * @dma_buf: DMA buffer containing hardware statistics
 372  * @accumulate: If set, the converted values will be added rather than
 373  *      directly stored to the corresponding elements of @stats
 374  */
 375 void efx_nic_update_stats(const struct efx_hw_stat_desc *desc, size_t count,
 376                           const unsigned long *mask,
 377                           u64 *stats, const void *dma_buf, bool accumulate)
 378 {
 379         size_t index;
 380
 381         for_each_set_bit(index, mask, count) {
 382                 if (desc[index].dma_width) {
 383                         const void *addr = dma_buf + desc[index].offset;
 384                         u64 val;
 385
 386                         switch (desc[index].dma_width) {
 387                         case 16:
 388                                 val = le16_to_cpup((__le16 *)addr);
 389                                 break;
 390                         case 32:
 391                                 val = le32_to_cpup((__le32 *)addr);
 392                                 break;
 393                         case 64:
 394                                 val = le64_to_cpup((__le64 *)addr);
 395                                 break;
 396                         default:
 397                                 WARN_ON(1);
 398                                 val = 0;
 399                                 break;
 400                         }
 401
 402                         if (accumulate)
 403                                 stats[index] += val;
 404                         else
 405                                 stats[index] = val;
 406                 }
 407         }
 408 }
 409
 410 void efx_nic_fix_nodesc_drop_stat(struct efx_nic *efx, u64 *rx_nodesc_drops)
 411 {
 412         /* if down, or this is the first update after coming up */
 413         if (!(efx->net_dev->flags & IFF_UP) || !efx->rx_nodesc_drops_prev_state)
 414                 efx->rx_nodesc_drops_while_down +=
 415                         *rx_nodesc_drops - efx->rx_nodesc_drops_total;
 416         efx->rx_nodesc_drops_total = *rx_nodesc_drops;
 417         efx->rx_nodesc_drops_prev_state = !!(efx->net_dev->flags & IFF_UP);
 418         *rx_nodesc_drops -= efx->rx_nodesc_drops_while_down;
 419 }