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drm/nouveau: consume the return of large GSP message
[drm/drm-misc.git] / drivers / net / ethernet / ti / cpsw_priv.h
blob1f448290b9f4b319284ee8dba3920b7173258f2f
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Texas Instruments Ethernet Switch Driver
4 */
5
6 #ifndef DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
7 #define DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_
8
9 #include <net/xdp.h>
10 #include <uapi/linux/bpf.h>
11
12 #include "davinci_cpdma.h"
13
14 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \
15 NETIF_MSG_DRV | NETIF_MSG_LINK | \
16 NETIF_MSG_IFUP | NETIF_MSG_INTR | \
17 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \
18 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \
19 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \
20 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \
21 NETIF_MSG_RX_STATUS)
22
23 #define cpsw_info(priv, type, format, ...) \
24 do { \
25 if (netif_msg_##type(priv) && net_ratelimit()) \
26 dev_info(priv->dev, format, ## __VA_ARGS__); \
27 } while (0)
28
29 #define cpsw_err(priv, type, format, ...) \
30 do { \
31 if (netif_msg_##type(priv) && net_ratelimit()) \
32 dev_err(priv->dev, format, ## __VA_ARGS__); \
33 } while (0)
34
35 #define cpsw_dbg(priv, type, format, ...) \
36 do { \
37 if (netif_msg_##type(priv) && net_ratelimit()) \
38 dev_dbg(priv->dev, format, ## __VA_ARGS__); \
39 } while (0)
40
41 #define cpsw_notice(priv, type, format, ...) \
42 do { \
43 if (netif_msg_##type(priv) && net_ratelimit()) \
44 dev_notice(priv->dev, format, ## __VA_ARGS__); \
45 } while (0)
46
47 #define ALE_ALL_PORTS 0x7
48
49 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7)
50 #define CPSW_MINOR_VERSION(reg) (reg & 0xff)
51 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f)
52
53 #define CPSW_VERSION_1 0x19010a
54 #define CPSW_VERSION_2 0x19010c
55 #define CPSW_VERSION_3 0x19010f
56 #define CPSW_VERSION_4 0x190112
57
58 #define HOST_PORT_NUM 0
59 #define CPSW_ALE_PORTS_NUM 3
60 #define CPSW_SLAVE_PORTS_NUM 2
61 #define SLIVER_SIZE 0x40
62
63 #define CPSW1_HOST_PORT_OFFSET 0x028
64 #define CPSW1_SLAVE_OFFSET 0x050
65 #define CPSW1_SLAVE_SIZE 0x040
66 #define CPSW1_CPDMA_OFFSET 0x100
67 #define CPSW1_STATERAM_OFFSET 0x200
68 #define CPSW1_HW_STATS 0x400
69 #define CPSW1_CPTS_OFFSET 0x500
70 #define CPSW1_ALE_OFFSET 0x600
71 #define CPSW1_SLIVER_OFFSET 0x700
72 #define CPSW1_WR_OFFSET 0x900
73
74 #define CPSW2_HOST_PORT_OFFSET 0x108
75 #define CPSW2_SLAVE_OFFSET 0x200
76 #define CPSW2_SLAVE_SIZE 0x100
77 #define CPSW2_CPDMA_OFFSET 0x800
78 #define CPSW2_HW_STATS 0x900
79 #define CPSW2_STATERAM_OFFSET 0xa00
80 #define CPSW2_CPTS_OFFSET 0xc00
81 #define CPSW2_ALE_OFFSET 0xd00
82 #define CPSW2_SLIVER_OFFSET 0xd80
83 #define CPSW2_BD_OFFSET 0x2000
84 #define CPSW2_WR_OFFSET 0x1200
85
86 #define CPDMA_RXTHRESH 0x0c0
87 #define CPDMA_RXFREE 0x0e0
88 #define CPDMA_TXHDP 0x00
89 #define CPDMA_RXHDP 0x20
90 #define CPDMA_TXCP 0x40
91 #define CPDMA_RXCP 0x60
92
93 #define CPSW_RX_VLAN_ENCAP_HDR_SIZE 4
94 #define CPSW_MIN_PACKET_SIZE_VLAN (VLAN_ETH_ZLEN)
95 #define CPSW_MIN_PACKET_SIZE (ETH_ZLEN)
96 #define CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN +\
97 ETH_FCS_LEN +\
98 CPSW_RX_VLAN_ENCAP_HDR_SIZE)
99
100 #define RX_PRIORITY_MAPPING 0x76543210
101 #define TX_PRIORITY_MAPPING 0x33221100
102 #define CPDMA_TX_PRIORITY_MAP 0x76543210
103
104 #define CPSW_VLAN_AWARE BIT(1)
105 #define CPSW_RX_VLAN_ENCAP BIT(2)
106 #define CPSW_ALE_VLAN_AWARE 1
107
108 #define CPSW_FIFO_NORMAL_MODE (0 << 16)
109 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 16)
110 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 16)
111
112 #define CPSW_INTPACEEN (0x3f << 16)
113 #define CPSW_INTPRESCALE_MASK (0x7FF << 0)
114 #define CPSW_CMINTMAX_CNT 63
115 #define CPSW_CMINTMIN_CNT 2
116 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT)
117 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1)
118
119 #define IRQ_NUM 2
120 #define CPSW_MAX_QUEUES 8
121 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
122 #define CPSW_ALE_AGEOUT_DEFAULT 10 /* sec */
123 #define CPSW_FIFO_QUEUE_TYPE_SHIFT 16
124 #define CPSW_FIFO_SHAPE_EN_SHIFT 16
125 #define CPSW_FIFO_RATE_EN_SHIFT 20
126 #define CPSW_TC_NUM 4
127 #define CPSW_FIFO_SHAPERS_NUM (CPSW_TC_NUM - 1)
128 #define CPSW_PCT_MASK 0x7f
129 #define CPSW_BD_RAM_SIZE 0x2000
130
131 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_SHIFT 29
132 #define CPSW_RX_VLAN_ENCAP_HDR_PRIO_MSK GENMASK(2, 0)
133 #define CPSW_RX_VLAN_ENCAP_HDR_VID_SHIFT 16
134 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_SHIFT 8
135 #define CPSW_RX_VLAN_ENCAP_HDR_PKT_TYPE_MSK GENMASK(1, 0)
136 enum {
137 CPSW_RX_VLAN_ENCAP_HDR_PKT_VLAN_TAG = 0,
138 CPSW_RX_VLAN_ENCAP_HDR_PKT_RESERV,
139 CPSW_RX_VLAN_ENCAP_HDR_PKT_PRIO_TAG,
140 CPSW_RX_VLAN_ENCAP_HDR_PKT_UNTAG,
141 };
142
143 struct cpsw_wr_regs {
144 u32 id_ver;
145 u32 soft_reset;
146 u32 control;
147 u32 int_control;
148 u32 rx_thresh_en;
149 u32 rx_en;
150 u32 tx_en;
151 u32 misc_en;
152 u32 mem_allign1[8];
153 u32 rx_thresh_stat;
154 u32 rx_stat;
155 u32 tx_stat;
156 u32 misc_stat;
157 u32 mem_allign2[8];
158 u32 rx_imax;
159 u32 tx_imax;
160
161 };
162
163 struct cpsw_ss_regs {
164 u32 id_ver;
165 u32 control;
166 u32 soft_reset;
167 u32 stat_port_en;
168 u32 ptype;
169 u32 soft_idle;
170 u32 thru_rate;
171 u32 gap_thresh;
172 u32 tx_start_wds;
173 u32 flow_control;
174 u32 vlan_ltype;
175 u32 ts_ltype;
176 u32 dlr_ltype;
177 };
178
179 /* CPSW_PORT_V1 */
180 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */
181 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */
182 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */
183 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */
184 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */
185 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */
186 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */
187 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */
188
189 /* CPSW_PORT_V2 */
190 #define CPSW2_CONTROL 0x00 /* Control Register */
191 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */
192 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */
193 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */
194 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */
195 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */
196 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */
197
198 /* CPSW_PORT_V1 and V2 */
199 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */
200 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */
201 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */
202
203 /* CPSW_PORT_V2 only */
204 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */
205 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */
206 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */
207 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */
208 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */
209 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */
210 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */
211 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */
212
213 /* Bit definitions for the CPSW2_CONTROL register */
214 #define PASS_PRI_TAGGED BIT(24) /* Pass Priority Tagged */
215 #define VLAN_LTYPE2_EN BIT(21) /* VLAN LTYPE 2 enable */
216 #define VLAN_LTYPE1_EN BIT(20) /* VLAN LTYPE 1 enable */
217 #define DSCP_PRI_EN BIT(16) /* DSCP Priority Enable */
218 #define TS_107 BIT(15) /* Tyme Sync Dest IP Address 107 */
219 #define TS_320 BIT(14) /* Time Sync Dest Port 320 enable */
220 #define TS_319 BIT(13) /* Time Sync Dest Port 319 enable */
221 #define TS_132 BIT(12) /* Time Sync Dest IP Addr 132 enable */
222 #define TS_131 BIT(11) /* Time Sync Dest IP Addr 131 enable */
223 #define TS_130 BIT(10) /* Time Sync Dest IP Addr 130 enable */
224 #define TS_129 BIT(9) /* Time Sync Dest IP Addr 129 enable */
225 #define TS_TTL_NONZERO BIT(8) /* Time Sync Time To Live Non-zero enable */
226 #define TS_ANNEX_F_EN BIT(6) /* Time Sync Annex F enable */
227 #define TS_ANNEX_D_EN BIT(4) /* Time Sync Annex D enable */
228 #define TS_LTYPE2_EN BIT(3) /* Time Sync LTYPE 2 enable */
229 #define TS_LTYPE1_EN BIT(2) /* Time Sync LTYPE 1 enable */
230 #define TS_TX_EN BIT(1) /* Time Sync Transmit Enable */
231 #define TS_RX_EN BIT(0) /* Time Sync Receive Enable */
232
233 #define CTRL_V2_TS_BITS \
234 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
235 TS_TTL_NONZERO | TS_ANNEX_D_EN | TS_LTYPE1_EN | VLAN_LTYPE1_EN)
236
237 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
238 #define CTRL_V2_TX_TS_BITS (CTRL_V2_TS_BITS | TS_TX_EN)
239 #define CTRL_V2_RX_TS_BITS (CTRL_V2_TS_BITS | TS_RX_EN)
240
241
242 #define CTRL_V3_TS_BITS \
243 (TS_107 | TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
244 TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
245 TS_LTYPE1_EN | VLAN_LTYPE1_EN)
246
247 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
248 #define CTRL_V3_TX_TS_BITS (CTRL_V3_TS_BITS | TS_TX_EN)
249 #define CTRL_V3_RX_TS_BITS (CTRL_V3_TS_BITS | TS_RX_EN)
250
251 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
252 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */
253 #define TS_SEQ_ID_OFFSET_MASK (0x3f)
254 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */
255 #define TS_MSG_TYPE_EN_MASK (0xffff)
256
257 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
258 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
259
260 /* Bit definitions for the CPSW1_TS_CTL register */
261 #define CPSW_V1_TS_RX_EN BIT(0)
262 #define CPSW_V1_TS_TX_EN BIT(4)
263 #define CPSW_V1_MSG_TYPE_OFS 16
264
265 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
266 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16
267
268 #define CPSW_MAX_BLKS_TX 15
269 #define CPSW_MAX_BLKS_TX_SHIFT 4
270 #define CPSW_MAX_BLKS_RX 5
271
272 struct cpsw_host_regs {
273 u32 max_blks;
274 u32 blk_cnt;
275 u32 tx_in_ctl;
276 u32 port_vlan;
277 u32 tx_pri_map;
278 u32 cpdma_tx_pri_map;
279 u32 cpdma_rx_chan_map;
280 };
281
282 struct cpsw_slave_data {
283 struct device_node *slave_node;
284 struct device_node *phy_node;
285 char phy_id[MII_BUS_ID_SIZE];
286 phy_interface_t phy_if;
287 u8 mac_addr[ETH_ALEN];
288 u16 dual_emac_res_vlan; /* Reserved VLAN for DualEMAC */
289 struct phy *ifphy;
290 bool disabled;
291 };
292
293 struct cpsw_platform_data {
294 struct cpsw_slave_data *slave_data;
295 u32 ss_reg_ofs; /* Subsystem control register offset */
296 u32 channels; /* number of cpdma channels (symmetric) */
297 u32 slaves; /* number of slave cpgmac ports */
298 u32 active_slave;/* time stamping, ethtool and SIOCGMIIPHY slave */
299 u32 bd_ram_size; /*buffer descriptor ram size */
300 u32 mac_control; /* Mac control register */
301 u16 default_vlan; /* Def VLAN for ALE lookup in VLAN aware mode*/
302 bool dual_emac; /* Enable Dual EMAC mode */
303 };
304
305 struct cpsw_slave {
306 void __iomem *regs;
307 int slave_num;
308 u32 mac_control;
309 struct cpsw_slave_data *data;
310 struct phy_device *phy;
311 struct net_device *ndev;
312 u32 port_vlan;
313 struct cpsw_sl *mac_sl;
314 };
315
316 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
317 {
318 return readl_relaxed(slave->regs + offset);
319 }
320
321 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
322 {
323 writel_relaxed(val, slave->regs + offset);
324 }
325
326 struct cpsw_vector {
327 struct cpdma_chan *ch;
328 int budget;
329 };
330
331 struct cpsw_common {
332 struct device *dev;
333 struct cpsw_platform_data data;
334 struct napi_struct napi_rx;
335 struct napi_struct napi_tx;
336 struct cpsw_ss_regs __iomem *regs;
337 struct cpsw_wr_regs __iomem *wr_regs;
338 u8 __iomem *hw_stats;
339 struct cpsw_host_regs __iomem *host_port_regs;
340 u32 version;
341 u32 coal_intvl;
342 u32 bus_freq_mhz;
343 int rx_packet_max;
344 int descs_pool_size;
345 struct cpsw_slave *slaves;
346 struct cpdma_ctlr *dma;
347 struct cpsw_vector txv[CPSW_MAX_QUEUES];
348 struct cpsw_vector rxv[CPSW_MAX_QUEUES];
349 struct cpsw_ale *ale;
350 bool quirk_irq;
351 bool rx_irq_disabled;
352 bool tx_irq_disabled;
353 u32 irqs_table[IRQ_NUM];
354 int misc_irq;
355 struct cpts *cpts;
356 struct devlink *devlink;
357 int rx_ch_num, tx_ch_num;
358 int speed;
359 int usage_count;
360 struct page_pool *page_pool[CPSW_MAX_QUEUES];
361 u8 br_members;
362 struct net_device *hw_bridge_dev;
363 bool ale_bypass;
364 u8 base_mac[ETH_ALEN];
365 };
366
367 struct cpsw_ale_ratelimit {
368 unsigned long cookie;
369 u64 rate_packet_ps;
370 };
371
372 struct cpsw_priv {
373 struct net_device *ndev;
374 struct device *dev;
375 u32 msg_enable;
376 u8 mac_addr[ETH_ALEN];
377 bool rx_pause;
378 bool tx_pause;
379 bool mqprio_hw;
380 int fifo_bw[CPSW_TC_NUM];
381 int shp_cfg_speed;
382 int tx_ts_enabled;
383 int rx_ts_enabled;
384 struct bpf_prog *xdp_prog;
385 struct xdp_rxq_info xdp_rxq[CPSW_MAX_QUEUES];
386 struct xdp_attachment_info xdpi;
387
388 u32 emac_port;
389 struct cpsw_common *cpsw;
390 int offload_fwd_mark;
391 u32 tx_packet_min;
392 struct cpsw_ale_ratelimit ale_bc_ratelimit;
393 struct cpsw_ale_ratelimit ale_mc_ratelimit;
394 };
395
396 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
397 #define napi_to_cpsw(napi) container_of(napi, struct cpsw_common, napi)
398
399 extern int (*cpsw_slave_index)(struct cpsw_common *cpsw,
400 struct cpsw_priv *priv);
401
402 struct addr_sync_ctx {
403 struct net_device *ndev;
404 const u8 *addr; /* address to be synched */
405 int consumed; /* number of address instances */
406 int flush; /* flush flag */
407 };
408
409 #define CPSW_XMETA_OFFSET ALIGN(sizeof(struct xdp_frame), sizeof(long))
410
411 #define CPSW_XDP_CONSUMED 1
412 #define CPSW_XDP_PASS 0
413
414 struct __aligned(sizeof(long)) cpsw_meta_xdp {
415 struct net_device *ndev;
416 int ch;
417 };
418
419 /* The buf includes headroom compatible with both skb and xdpf */
420 #define CPSW_HEADROOM_NA (max(XDP_PACKET_HEADROOM, NET_SKB_PAD) + NET_IP_ALIGN)
421
422 static inline int cpsw_is_xdpf_handle(void *handle)
423 {
424 return (unsigned long)handle & BIT(0);
425 }
426
427 static inline void *cpsw_xdpf_to_handle(struct xdp_frame *xdpf)
428 {
429 return (void *)((unsigned long)xdpf | BIT(0));
430 }
431
432 static inline struct xdp_frame *cpsw_handle_to_xdpf(void *handle)
433 {
434 return (struct xdp_frame *)((unsigned long)handle & ~BIT(0));
435 }
436
437 int cpsw_init_common(struct cpsw_common *cpsw, void __iomem *ss_regs,
438 int ale_ageout, phys_addr_t desc_mem_phys,
439 int descs_pool_size);
440 void cpsw_split_res(struct cpsw_common *cpsw);
441 int cpsw_fill_rx_channels(struct cpsw_priv *priv);
442 void cpsw_intr_enable(struct cpsw_common *cpsw);
443 void cpsw_intr_disable(struct cpsw_common *cpsw);
444 void cpsw_tx_handler(void *token, int len, int status);
445 int cpsw_create_xdp_rxqs(struct cpsw_common *cpsw);
446 void cpsw_destroy_xdp_rxqs(struct cpsw_common *cpsw);
447 int cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf);
448 int cpsw_xdp_tx_frame(struct cpsw_priv *priv, struct xdp_frame *xdpf,
449 struct page *page, int port);
450 int cpsw_run_xdp(struct cpsw_priv *priv, int ch, struct xdp_buff *xdp,
451 struct page *page, int port, int *len);
452 irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id);
453 irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id);
454 irqreturn_t cpsw_misc_interrupt(int irq, void *dev_id);
455 int cpsw_tx_mq_poll(struct napi_struct *napi_tx, int budget);
456 int cpsw_tx_poll(struct napi_struct *napi_tx, int budget);
457 int cpsw_rx_mq_poll(struct napi_struct *napi_rx, int budget);
458 int cpsw_rx_poll(struct napi_struct *napi_rx, int budget);
459 void cpsw_rx_vlan_encap(struct sk_buff *skb);
460 void soft_reset(const char *module, void __iomem *reg);
461 void cpsw_set_slave_mac(struct cpsw_slave *slave, struct cpsw_priv *priv);
462 void cpsw_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue);
463 int cpsw_need_resplit(struct cpsw_common *cpsw);
464 int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd);
465 int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate);
466 int cpsw_ndo_setup_tc(struct net_device *ndev, enum tc_setup_type type,
467 void *type_data);
468 bool cpsw_shp_is_off(struct cpsw_priv *priv);
469 void cpsw_cbs_resume(struct cpsw_slave *slave, struct cpsw_priv *priv);
470 void cpsw_mqprio_resume(struct cpsw_slave *slave, struct cpsw_priv *priv);
471 void cpsw_qos_clsflower_resume(struct cpsw_priv *priv);
472
473 /* ethtool */
474 u32 cpsw_get_msglevel(struct net_device *ndev);
475 void cpsw_set_msglevel(struct net_device *ndev, u32 value);
476 int cpsw_get_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal,
477 struct kernel_ethtool_coalesce *kernel_coal,
478 struct netlink_ext_ack *extack);
479 int cpsw_set_coalesce(struct net_device *ndev, struct ethtool_coalesce *coal,
480 struct kernel_ethtool_coalesce *kernel_coal,
481 struct netlink_ext_ack *extack);
482 int cpsw_get_sset_count(struct net_device *ndev, int sset);
483 void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data);
484 void cpsw_get_ethtool_stats(struct net_device *ndev,
485 struct ethtool_stats *stats, u64 *data);
486 void cpsw_get_pauseparam(struct net_device *ndev,
487 struct ethtool_pauseparam *pause);
488 void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
489 int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol);
490 int cpsw_get_regs_len(struct net_device *ndev);
491 void cpsw_get_regs(struct net_device *ndev, struct ethtool_regs *regs, void *p);
492 int cpsw_ethtool_op_begin(struct net_device *ndev);
493 void cpsw_ethtool_op_complete(struct net_device *ndev);
494 void cpsw_get_channels(struct net_device *ndev, struct ethtool_channels *ch);
495 int cpsw_get_link_ksettings(struct net_device *ndev,
496 struct ethtool_link_ksettings *ecmd);
497 int cpsw_set_link_ksettings(struct net_device *ndev,
498 const struct ethtool_link_ksettings *ecmd);
499 int cpsw_get_eee(struct net_device *ndev, struct ethtool_keee *edata);
500 int cpsw_set_eee(struct net_device *ndev, struct ethtool_keee *edata);
501 int cpsw_nway_reset(struct net_device *ndev);
502 void cpsw_get_ringparam(struct net_device *ndev,
503 struct ethtool_ringparam *ering,
504 struct kernel_ethtool_ringparam *kernel_ering,
505 struct netlink_ext_ack *extack);
506 int cpsw_set_ringparam(struct net_device *ndev,
507 struct ethtool_ringparam *ering,
508 struct kernel_ethtool_ringparam *kernel_ering,
509 struct netlink_ext_ack *extack);
510 int cpsw_set_channels_common(struct net_device *ndev,
511 struct ethtool_channels *chs,
512 cpdma_handler_fn rx_handler);
513 int cpsw_get_ts_info(struct net_device *ndev, struct kernel_ethtool_ts_info *info);
514
515 #endif /* DRIVERS_NET_ETHERNET_TI_CPSW_PRIV_H_ */
Kernel DRM miscellaneous fixes and cross-tree changes