drm/rockchip: Don't change hdmi reference clock rate
[drm/drm-misc.git] / drivers / net / phy / mdio-open-alliance.h
blob931e14660d759ac77549a48217b07f4b97301790
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * mdio-open-alliance.h - definition of OPEN Alliance SIG standard registers
4 */
6 #ifndef __MDIO_OPEN_ALLIANCE__
7 #define __MDIO_OPEN_ALLIANCE__
9 #include <linux/mdio.h>
11 /* NOTE: all OATC14 registers are located in MDIO_MMD_VEND2 */
13 /* Open Alliance TC14 (10BASE-T1S) registers */
14 #define MDIO_OATC14_PLCA_IDVER 0xca00 /* PLCA ID and version */
15 #define MDIO_OATC14_PLCA_CTRL0 0xca01 /* PLCA Control register 0 */
16 #define MDIO_OATC14_PLCA_CTRL1 0xca02 /* PLCA Control register 1 */
17 #define MDIO_OATC14_PLCA_STATUS 0xca03 /* PLCA Status register */
18 #define MDIO_OATC14_PLCA_TOTMR 0xca04 /* PLCA TO Timer register */
19 #define MDIO_OATC14_PLCA_BURST 0xca05 /* PLCA BURST mode register */
21 /* Open Alliance TC14 PLCA IDVER register */
22 #define MDIO_OATC14_PLCA_IDM 0xff00 /* PLCA MAP ID */
23 #define MDIO_OATC14_PLCA_VER 0x00ff /* PLCA MAP version */
25 /* Open Alliance TC14 PLCA CTRL0 register */
26 #define MDIO_OATC14_PLCA_EN BIT(15) /* PLCA enable */
27 #define MDIO_OATC14_PLCA_RST BIT(14) /* PLCA reset */
29 /* Open Alliance TC14 PLCA CTRL1 register */
30 #define MDIO_OATC14_PLCA_NCNT 0xff00 /* PLCA node count */
31 #define MDIO_OATC14_PLCA_ID 0x00ff /* PLCA local node ID */
33 /* Open Alliance TC14 PLCA STATUS register */
34 #define MDIO_OATC14_PLCA_PST BIT(15) /* PLCA status indication */
36 /* Open Alliance TC14 PLCA TOTMR register */
37 #define MDIO_OATC14_PLCA_TOT 0x00ff
39 /* Open Alliance TC14 PLCA BURST register */
40 #define MDIO_OATC14_PLCA_MAXBC 0xff00
41 #define MDIO_OATC14_PLCA_BTMR 0x00ff
43 /* Version Identifiers */
44 #define OATC14_IDM 0x0a00
46 #endif /* __MDIO_OPEN_ALLIANCE__ */