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accel/ivpu: Move recovery work to system_unbound_wq
[drm/drm-misc.git] / drivers / net / usb / asix_devices.c
blob57d6e5abc30e88555308ec18aa5d7dce1cf8f9f3
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * ASIX AX8817X based USB 2.0 Ethernet Devices
4 * Copyright (C) 2003-2006 David Hollis <dhollis@davehollis.com>
5 * Copyright (C) 2005 Phil Chang <pchang23@sbcglobal.net>
6 * Copyright (C) 2006 James Painter <jamie.painter@iname.com>
7 * Copyright (c) 2002-2003 TiVo Inc.
8 */
9
10 #include "asix.h"
11
12 #define PHY_MODE_MARVELL 0x0000
13 #define MII_MARVELL_LED_CTRL 0x0018
14 #define MII_MARVELL_STATUS 0x001b
15 #define MII_MARVELL_CTRL 0x0014
16
17 #define MARVELL_LED_MANUAL 0x0019
18
19 #define MARVELL_STATUS_HWCFG 0x0004
20
21 #define MARVELL_CTRL_TXDELAY 0x0002
22 #define MARVELL_CTRL_RXDELAY 0x0080
23
24 #define PHY_MODE_RTL8211CL 0x000C
25
26 #define AX88772A_PHY14H 0x14
27 #define AX88772A_PHY14H_DEFAULT 0x442C
28
29 #define AX88772A_PHY15H 0x15
30 #define AX88772A_PHY15H_DEFAULT 0x03C8
31
32 #define AX88772A_PHY16H 0x16
33 #define AX88772A_PHY16H_DEFAULT 0x4044
34
35 struct ax88172_int_data {
36 __le16 res1;
37 u8 link;
38 __le16 res2;
39 u8 status;
40 __le16 res3;
41 } __packed;
42
43 static void asix_status(struct usbnet *dev, struct urb *urb)
44 {
45 struct ax88172_int_data *event;
46 int link;
47
48 if (urb->actual_length < 8)
49 return;
50
51 event = urb->transfer_buffer;
52 link = event->link & 0x01;
53 if (netif_carrier_ok(dev->net) != link) {
54 usbnet_link_change(dev, link, 1);
55 netdev_dbg(dev->net, "Link Status is: %d\n", link);
56 }
57 }
58
59 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
60 {
61 if (is_valid_ether_addr(addr)) {
62 eth_hw_addr_set(dev->net, addr);
63 } else {
64 netdev_info(dev->net, "invalid hw address, using random\n");
65 eth_hw_addr_random(dev->net);
66 }
67 }
68
69 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
70 static u32 asix_get_phyid(struct usbnet *dev)
71 {
72 int phy_reg;
73 u32 phy_id;
74 int i;
75
76 /* Poll for the rare case the FW or phy isn't ready yet. */
77 for (i = 0; i < 100; i++) {
78 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
79 if (phy_reg < 0)
80 return 0;
81 if (phy_reg != 0 && phy_reg != 0xFFFF)
82 break;
83 mdelay(1);
84 }
85
86 if (phy_reg <= 0 || phy_reg == 0xFFFF)
87 return 0;
88
89 phy_id = (phy_reg & 0xffff) << 16;
90
91 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
92 if (phy_reg < 0)
93 return 0;
94
95 phy_id |= (phy_reg & 0xffff);
96
97 return phy_id;
98 }
99
100 static u32 asix_get_link(struct net_device *net)
101 {
102 struct usbnet *dev = netdev_priv(net);
103
104 return mii_link_ok(&dev->mii);
105 }
106
107 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
108 {
109 struct usbnet *dev = netdev_priv(net);
110
111 return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
112 }
113
114 /* We need to override some ethtool_ops so we require our
115 own structure so we don't interfere with other usbnet
116 devices that may be connected at the same time. */
117 static const struct ethtool_ops ax88172_ethtool_ops = {
118 .get_drvinfo = asix_get_drvinfo,
119 .get_link = asix_get_link,
120 .get_msglevel = usbnet_get_msglevel,
121 .set_msglevel = usbnet_set_msglevel,
122 .get_wol = asix_get_wol,
123 .set_wol = asix_set_wol,
124 .get_eeprom_len = asix_get_eeprom_len,
125 .get_eeprom = asix_get_eeprom,
126 .set_eeprom = asix_set_eeprom,
127 .nway_reset = usbnet_nway_reset,
128 .get_link_ksettings = usbnet_get_link_ksettings_mii,
129 .set_link_ksettings = usbnet_set_link_ksettings_mii,
130 };
131
132 static void ax88172_set_multicast(struct net_device *net)
133 {
134 struct usbnet *dev = netdev_priv(net);
135 struct asix_data *data = (struct asix_data *)&dev->data;
136 u8 rx_ctl = 0x8c;
137
138 if (net->flags & IFF_PROMISC) {
139 rx_ctl |= 0x01;
140 } else if (net->flags & IFF_ALLMULTI ||
141 netdev_mc_count(net) > AX_MAX_MCAST) {
142 rx_ctl |= 0x02;
143 } else if (netdev_mc_empty(net)) {
144 /* just broadcast and directed */
145 } else {
146 /* We use the 20 byte dev->data
147 * for our 8 byte filter buffer
148 * to avoid allocating memory that
149 * is tricky to free later */
150 struct netdev_hw_addr *ha;
151 u32 crc_bits;
152
153 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
154
155 /* Build the multicast hash filter. */
156 netdev_for_each_mc_addr(ha, net) {
157 crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
158 data->multi_filter[crc_bits >> 3] |=
159 1 << (crc_bits & 7);
160 }
161
162 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
163 AX_MCAST_FILTER_SIZE, data->multi_filter);
164
165 rx_ctl |= 0x10;
166 }
167
168 asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
169 }
170
171 static int ax88172_link_reset(struct usbnet *dev)
172 {
173 u8 mode;
174 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
175
176 mii_check_media(&dev->mii, 1, 1);
177 mii_ethtool_gset(&dev->mii, &ecmd);
178 mode = AX88172_MEDIUM_DEFAULT;
179
180 if (ecmd.duplex != DUPLEX_FULL)
181 mode |= ~AX88172_MEDIUM_FD;
182
183 netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
184 ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
185
186 asix_write_medium_mode(dev, mode, 0);
187
188 return 0;
189 }
190
191 static const struct net_device_ops ax88172_netdev_ops = {
192 .ndo_open = usbnet_open,
193 .ndo_stop = usbnet_stop,
194 .ndo_start_xmit = usbnet_start_xmit,
195 .ndo_tx_timeout = usbnet_tx_timeout,
196 .ndo_change_mtu = usbnet_change_mtu,
197 .ndo_get_stats64 = dev_get_tstats64,
198 .ndo_set_mac_address = eth_mac_addr,
199 .ndo_validate_addr = eth_validate_addr,
200 .ndo_eth_ioctl = asix_ioctl,
201 .ndo_set_rx_mode = ax88172_set_multicast,
202 };
203
204 static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits)
205 {
206 unsigned int timeout = 5000;
207
208 asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
209
210 /* give phy_id a chance to process reset */
211 udelay(500);
212
213 /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */
214 while (timeout--) {
215 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
216 & BMCR_RESET)
217 udelay(100);
218 else
219 return;
220 }
221
222 netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
223 dev->mii.phy_id);
224 }
225
226 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
227 {
228 int ret = 0;
229 u8 buf[ETH_ALEN] = {0};
230 int i;
231 unsigned long gpio_bits = dev->driver_info->data;
232
233 usbnet_get_endpoints(dev,intf);
234
235 /* Toggle the GPIOs in a manufacturer/model specific way */
236 for (i = 2; i >= 0; i--) {
237 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
238 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
239 if (ret < 0)
240 goto out;
241 msleep(5);
242 }
243
244 ret = asix_write_rx_ctl(dev, 0x80, 0);
245 if (ret < 0)
246 goto out;
247
248 /* Get the MAC address */
249 ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
250 0, 0, ETH_ALEN, buf, 0);
251 if (ret < 0) {
252 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
253 ret);
254 goto out;
255 }
256
257 asix_set_netdev_dev_addr(dev, buf);
258
259 /* Initialize MII structure */
260 dev->mii.dev = dev->net;
261 dev->mii.mdio_read = asix_mdio_read;
262 dev->mii.mdio_write = asix_mdio_write;
263 dev->mii.phy_id_mask = 0x3f;
264 dev->mii.reg_num_mask = 0x1f;
265
266 dev->mii.phy_id = asix_read_phy_addr(dev, true);
267 if (dev->mii.phy_id < 0)
268 return dev->mii.phy_id;
269
270 dev->net->netdev_ops = &ax88172_netdev_ops;
271 dev->net->ethtool_ops = &ax88172_ethtool_ops;
272 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
273 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
274
275 asix_phy_reset(dev, BMCR_RESET);
276 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
277 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
278 mii_nway_restart(&dev->mii);
279
280 return 0;
281
282 out:
283 return ret;
284 }
285
286 static void ax88772_ethtool_get_strings(struct net_device *netdev, u32 sset,
287 u8 *data)
288 {
289 switch (sset) {
290 case ETH_SS_TEST:
291 net_selftest_get_strings(data);
292 break;
293 }
294 }
295
296 static int ax88772_ethtool_get_sset_count(struct net_device *ndev, int sset)
297 {
298 switch (sset) {
299 case ETH_SS_TEST:
300 return net_selftest_get_count();
301 default:
302 return -EOPNOTSUPP;
303 }
304 }
305
306 static void ax88772_ethtool_get_pauseparam(struct net_device *ndev,
307 struct ethtool_pauseparam *pause)
308 {
309 struct usbnet *dev = netdev_priv(ndev);
310 struct asix_common_private *priv = dev->driver_priv;
311
312 phylink_ethtool_get_pauseparam(priv->phylink, pause);
313 }
314
315 static int ax88772_ethtool_set_pauseparam(struct net_device *ndev,
316 struct ethtool_pauseparam *pause)
317 {
318 struct usbnet *dev = netdev_priv(ndev);
319 struct asix_common_private *priv = dev->driver_priv;
320
321 return phylink_ethtool_set_pauseparam(priv->phylink, pause);
322 }
323
324 static const struct ethtool_ops ax88772_ethtool_ops = {
325 .get_drvinfo = asix_get_drvinfo,
326 .get_link = usbnet_get_link,
327 .get_msglevel = usbnet_get_msglevel,
328 .set_msglevel = usbnet_set_msglevel,
329 .get_wol = asix_get_wol,
330 .set_wol = asix_set_wol,
331 .get_eeprom_len = asix_get_eeprom_len,
332 .get_eeprom = asix_get_eeprom,
333 .set_eeprom = asix_set_eeprom,
334 .nway_reset = phy_ethtool_nway_reset,
335 .get_link_ksettings = phy_ethtool_get_link_ksettings,
336 .set_link_ksettings = phy_ethtool_set_link_ksettings,
337 .self_test = net_selftest,
338 .get_strings = ax88772_ethtool_get_strings,
339 .get_sset_count = ax88772_ethtool_get_sset_count,
340 .get_pauseparam = ax88772_ethtool_get_pauseparam,
341 .set_pauseparam = ax88772_ethtool_set_pauseparam,
342 };
343
344 static int ax88772_reset(struct usbnet *dev)
345 {
346 struct asix_data *data = (struct asix_data *)&dev->data;
347 struct asix_common_private *priv = dev->driver_priv;
348 int ret;
349
350 /* Rewrite MAC address */
351 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
352 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
353 ETH_ALEN, data->mac_addr, 0);
354 if (ret < 0)
355 goto out;
356
357 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
358 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
359 if (ret < 0)
360 goto out;
361
362 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
363 if (ret < 0)
364 goto out;
365
366 phylink_start(priv->phylink);
367
368 return 0;
369
370 out:
371 return ret;
372 }
373
374 static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
375 {
376 struct asix_data *data = (struct asix_data *)&dev->data;
377 struct asix_common_private *priv = dev->driver_priv;
378 u16 rx_ctl;
379 int ret;
380
381 ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
382 AX_GPIO_GPO2EN, 5, in_pm);
383 if (ret < 0)
384 goto out;
385
386 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy,
387 0, 0, NULL, in_pm);
388 if (ret < 0) {
389 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
390 goto out;
391 }
392
393 if (priv->embd_phy) {
394 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
395 if (ret < 0)
396 goto out;
397
398 usleep_range(10000, 11000);
399
400 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
401 if (ret < 0)
402 goto out;
403
404 msleep(60);
405
406 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
407 in_pm);
408 if (ret < 0)
409 goto out;
410 } else {
411 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
412 in_pm);
413 if (ret < 0)
414 goto out;
415 }
416
417 msleep(150);
418
419 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
420 MII_PHYSID1))){
421 ret = -EIO;
422 goto out;
423 }
424
425 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
426 if (ret < 0)
427 goto out;
428
429 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
430 if (ret < 0)
431 goto out;
432
433 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
434 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
435 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
436 if (ret < 0) {
437 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
438 goto out;
439 }
440
441 /* Rewrite MAC address */
442 ether_addr_copy(data->mac_addr, dev->net->dev_addr);
443 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
444 ETH_ALEN, data->mac_addr, in_pm);
445 if (ret < 0)
446 goto out;
447
448 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
449 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
450 if (ret < 0)
451 goto out;
452
453 rx_ctl = asix_read_rx_ctl(dev, in_pm);
454 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
455 rx_ctl);
456
457 rx_ctl = asix_read_medium_status(dev, in_pm);
458 netdev_dbg(dev->net,
459 "Medium Status is 0x%04x after all initializations\n",
460 rx_ctl);
461
462 return 0;
463
464 out:
465 return ret;
466 }
467
468 static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
469 {
470 struct asix_data *data = (struct asix_data *)&dev->data;
471 struct asix_common_private *priv = dev->driver_priv;
472 u16 rx_ctl, phy14h, phy15h, phy16h;
473 int ret;
474
475 ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
476 if (ret < 0)
477 goto out;
478
479 ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy |
480 AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
481 if (ret < 0) {
482 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
483 goto out;
484 }
485 usleep_range(10000, 11000);
486
487 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
488 if (ret < 0)
489 goto out;
490
491 usleep_range(10000, 11000);
492
493 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
494 if (ret < 0)
495 goto out;
496
497 msleep(160);
498
499 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
500 if (ret < 0)
501 goto out;
502
503 ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
504 if (ret < 0)
505 goto out;
506
507 msleep(200);
508
509 if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
510 MII_PHYSID1))) {
511 ret = -1;
512 goto out;
513 }
514
515 if (priv->chipcode == AX_AX88772B_CHIPCODE) {
516 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
517 0, NULL, in_pm);
518 if (ret < 0) {
519 netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
520 ret);
521 goto out;
522 }
523 } else if (priv->chipcode == AX_AX88772A_CHIPCODE) {
524 /* Check if the PHY registers have default settings */
525 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
526 AX88772A_PHY14H);
527 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
528 AX88772A_PHY15H);
529 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
530 AX88772A_PHY16H);
531
532 netdev_dbg(dev->net,
533 "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
534 phy14h, phy15h, phy16h);
535
536 /* Restore PHY registers default setting if not */
537 if (phy14h != AX88772A_PHY14H_DEFAULT)
538 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
539 AX88772A_PHY14H,
540 AX88772A_PHY14H_DEFAULT);
541 if (phy15h != AX88772A_PHY15H_DEFAULT)
542 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
543 AX88772A_PHY15H,
544 AX88772A_PHY15H_DEFAULT);
545 if (phy16h != AX88772A_PHY16H_DEFAULT)
546 asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
547 AX88772A_PHY16H,
548 AX88772A_PHY16H_DEFAULT);
549 }
550
551 ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
552 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
553 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
554 if (ret < 0) {
555 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
556 goto out;
557 }
558
559 /* Rewrite MAC address */
560 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
561 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
562 data->mac_addr, in_pm);
563 if (ret < 0)
564 goto out;
565
566 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
567 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
568 if (ret < 0)
569 goto out;
570
571 ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
572 if (ret < 0)
573 return ret;
574
575 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
576 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
577 if (ret < 0)
578 goto out;
579
580 rx_ctl = asix_read_rx_ctl(dev, in_pm);
581 netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
582 rx_ctl);
583
584 rx_ctl = asix_read_medium_status(dev, in_pm);
585 netdev_dbg(dev->net,
586 "Medium Status is 0x%04x after all initializations\n",
587 rx_ctl);
588
589 return 0;
590
591 out:
592 return ret;
593 }
594
595 static const struct net_device_ops ax88772_netdev_ops = {
596 .ndo_open = usbnet_open,
597 .ndo_stop = usbnet_stop,
598 .ndo_start_xmit = usbnet_start_xmit,
599 .ndo_tx_timeout = usbnet_tx_timeout,
600 .ndo_change_mtu = usbnet_change_mtu,
601 .ndo_get_stats64 = dev_get_tstats64,
602 .ndo_set_mac_address = asix_set_mac_address,
603 .ndo_validate_addr = eth_validate_addr,
604 .ndo_eth_ioctl = phy_do_ioctl_running,
605 .ndo_set_rx_mode = asix_set_multicast,
606 };
607
608 static void ax88772_suspend(struct usbnet *dev)
609 {
610 struct asix_common_private *priv = dev->driver_priv;
611 u16 medium;
612
613 if (netif_running(dev->net)) {
614 rtnl_lock();
615 phylink_suspend(priv->phylink, false);
616 rtnl_unlock();
617 }
618
619 /* Stop MAC operation */
620 medium = asix_read_medium_status(dev, 1);
621 medium &= ~AX_MEDIUM_RE;
622 asix_write_medium_mode(dev, medium, 1);
623
624 netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
625 asix_read_medium_status(dev, 1));
626 }
627
628 static int asix_suspend(struct usb_interface *intf, pm_message_t message)
629 {
630 struct usbnet *dev = usb_get_intfdata(intf);
631 struct asix_common_private *priv = dev->driver_priv;
632
633 if (priv && priv->suspend)
634 priv->suspend(dev);
635
636 return usbnet_suspend(intf, message);
637 }
638
639 static void ax88772_resume(struct usbnet *dev)
640 {
641 struct asix_common_private *priv = dev->driver_priv;
642 int i;
643
644 for (i = 0; i < 3; i++)
645 if (!priv->reset(dev, 1))
646 break;
647
648 if (netif_running(dev->net)) {
649 rtnl_lock();
650 phylink_resume(priv->phylink);
651 rtnl_unlock();
652 }
653 }
654
655 static int asix_resume(struct usb_interface *intf)
656 {
657 struct usbnet *dev = usb_get_intfdata(intf);
658 struct asix_common_private *priv = dev->driver_priv;
659
660 if (priv && priv->resume)
661 priv->resume(dev);
662
663 return usbnet_resume(intf);
664 }
665
666 static int ax88772_init_mdio(struct usbnet *dev)
667 {
668 struct asix_common_private *priv = dev->driver_priv;
669 int ret;
670
671 priv->mdio = mdiobus_alloc();
672 if (!priv->mdio)
673 return -ENOMEM;
674
675 priv->mdio->priv = dev;
676 priv->mdio->read = &asix_mdio_bus_read;
677 priv->mdio->write = &asix_mdio_bus_write;
678 priv->mdio->name = "Asix MDIO Bus";
679 /* mii bus name is usb-<usb bus number>-<usb device number> */
680 snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "usb-%03d:%03d",
681 dev->udev->bus->busnum, dev->udev->devnum);
682
683 ret = mdiobus_register(priv->mdio);
684 if (ret) {
685 netdev_err(dev->net, "Could not register MDIO bus (err %d)\n", ret);
686 mdiobus_free(priv->mdio);
687 priv->mdio = NULL;
688 }
689
690 return ret;
691 }
692
693 static void ax88772_mdio_unregister(struct asix_common_private *priv)
694 {
695 mdiobus_unregister(priv->mdio);
696 mdiobus_free(priv->mdio);
697 }
698
699 static int ax88772_init_phy(struct usbnet *dev)
700 {
701 struct asix_common_private *priv = dev->driver_priv;
702 int ret;
703
704 priv->phydev = mdiobus_get_phy(priv->mdio, priv->phy_addr);
705 if (!priv->phydev) {
706 netdev_err(dev->net, "Could not find PHY\n");
707 return -ENODEV;
708 }
709
710 ret = phylink_connect_phy(priv->phylink, priv->phydev);
711 if (ret) {
712 netdev_err(dev->net, "Could not connect PHY\n");
713 return ret;
714 }
715
716 phy_suspend(priv->phydev);
717 priv->phydev->mac_managed_pm = true;
718
719 phy_attached_info(priv->phydev);
720
721 if (priv->embd_phy)
722 return 0;
723
724 /* In case main PHY is not the embedded PHY and MAC is RMII clock
725 * provider, we need to suspend embedded PHY by keeping PLL enabled
726 * (AX_SWRESET_IPPD == 0).
727 */
728 priv->phydev_int = mdiobus_get_phy(priv->mdio, AX_EMBD_PHY_ADDR);
729 if (!priv->phydev_int) {
730 rtnl_lock();
731 phylink_disconnect_phy(priv->phylink);
732 rtnl_unlock();
733 netdev_err(dev->net, "Could not find internal PHY\n");
734 return -ENODEV;
735 }
736
737 priv->phydev_int->mac_managed_pm = true;
738 phy_suspend(priv->phydev_int);
739
740 return 0;
741 }
742
743 static void ax88772_mac_config(struct phylink_config *config, unsigned int mode,
744 const struct phylink_link_state *state)
745 {
746 /* Nothing to do */
747 }
748
749 static void ax88772_mac_link_down(struct phylink_config *config,
750 unsigned int mode, phy_interface_t interface)
751 {
752 struct usbnet *dev = netdev_priv(to_net_dev(config->dev));
753
754 asix_write_medium_mode(dev, 0, 0);
755 usbnet_link_change(dev, false, false);
756 }
757
758 static void ax88772_mac_link_up(struct phylink_config *config,
759 struct phy_device *phy,
760 unsigned int mode, phy_interface_t interface,
761 int speed, int duplex,
762 bool tx_pause, bool rx_pause)
763 {
764 struct usbnet *dev = netdev_priv(to_net_dev(config->dev));
765 u16 m = AX_MEDIUM_AC | AX_MEDIUM_RE;
766
767 m |= duplex ? AX_MEDIUM_FD : 0;
768
769 switch (speed) {
770 case SPEED_100:
771 m |= AX_MEDIUM_PS;
772 break;
773 case SPEED_10:
774 break;
775 default:
776 return;
777 }
778
779 if (tx_pause)
780 m |= AX_MEDIUM_TFC;
781
782 if (rx_pause)
783 m |= AX_MEDIUM_RFC;
784
785 asix_write_medium_mode(dev, m, 0);
786 usbnet_link_change(dev, true, false);
787 }
788
789 static const struct phylink_mac_ops ax88772_phylink_mac_ops = {
790 .mac_config = ax88772_mac_config,
791 .mac_link_down = ax88772_mac_link_down,
792 .mac_link_up = ax88772_mac_link_up,
793 };
794
795 static int ax88772_phylink_setup(struct usbnet *dev)
796 {
797 struct asix_common_private *priv = dev->driver_priv;
798 phy_interface_t phy_if_mode;
799 struct phylink *phylink;
800
801 priv->phylink_config.dev = &dev->net->dev;
802 priv->phylink_config.type = PHYLINK_NETDEV;
803 priv->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
804 MAC_10 | MAC_100;
805
806 __set_bit(PHY_INTERFACE_MODE_INTERNAL,
807 priv->phylink_config.supported_interfaces);
808 __set_bit(PHY_INTERFACE_MODE_RMII,
809 priv->phylink_config.supported_interfaces);
810
811 if (priv->embd_phy)
812 phy_if_mode = PHY_INTERFACE_MODE_INTERNAL;
813 else
814 phy_if_mode = PHY_INTERFACE_MODE_RMII;
815
816 phylink = phylink_create(&priv->phylink_config, dev->net->dev.fwnode,
817 phy_if_mode, &ax88772_phylink_mac_ops);
818 if (IS_ERR(phylink))
819 return PTR_ERR(phylink);
820
821 priv->phylink = phylink;
822 return 0;
823 }
824
825 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
826 {
827 struct asix_common_private *priv;
828 u8 buf[ETH_ALEN] = {0};
829 int ret, i;
830
831 priv = devm_kzalloc(&dev->udev->dev, sizeof(*priv), GFP_KERNEL);
832 if (!priv)
833 return -ENOMEM;
834
835 dev->driver_priv = priv;
836
837 usbnet_get_endpoints(dev, intf);
838
839 /* Maybe the boot loader passed the MAC address via device tree */
840 if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) {
841 netif_dbg(dev, ifup, dev->net,
842 "MAC address read from device tree");
843 } else {
844 /* Try getting the MAC address from EEPROM */
845 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
846 for (i = 0; i < (ETH_ALEN >> 1); i++) {
847 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM,
848 0x04 + i, 0, 2, buf + i * 2,
849 0);
850 if (ret < 0)
851 break;
852 }
853 } else {
854 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
855 0, 0, ETH_ALEN, buf, 0);
856 }
857
858 if (ret < 0) {
859 netdev_dbg(dev->net, "Failed to read MAC address: %d\n",
860 ret);
861 return ret;
862 }
863 }
864
865 asix_set_netdev_dev_addr(dev, buf);
866
867 dev->net->netdev_ops = &ax88772_netdev_ops;
868 dev->net->ethtool_ops = &ax88772_ethtool_ops;
869 dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
870 dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
871
872 ret = asix_read_phy_addr(dev, true);
873 if (ret < 0)
874 return ret;
875
876 priv->phy_addr = ret;
877 priv->embd_phy = ((priv->phy_addr & 0x1f) == AX_EMBD_PHY_ADDR);
878
879 ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1,
880 &priv->chipcode, 0);
881 if (ret < 0) {
882 netdev_dbg(dev->net, "Failed to read STATMNGSTS_REG: %d\n", ret);
883 return ret;
884 }
885
886 priv->chipcode &= AX_CHIPCODE_MASK;
887
888 priv->resume = ax88772_resume;
889 priv->suspend = ax88772_suspend;
890 if (priv->chipcode == AX_AX88772_CHIPCODE)
891 priv->reset = ax88772_hw_reset;
892 else
893 priv->reset = ax88772a_hw_reset;
894
895 ret = priv->reset(dev, 0);
896 if (ret < 0) {
897 netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret);
898 return ret;
899 }
900
901 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
902 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
903 /* hard_mtu is still the default - the device does not support
904 jumbo eth frames */
905 dev->rx_urb_size = 2048;
906 }
907
908 priv->presvd_phy_bmcr = 0;
909 priv->presvd_phy_advertise = 0;
910
911 ret = ax88772_init_mdio(dev);
912 if (ret)
913 goto mdio_err;
914
915 ret = ax88772_phylink_setup(dev);
916 if (ret)
917 goto phylink_err;
918
919 ret = ax88772_init_phy(dev);
920 if (ret)
921 goto initphy_err;
922
923 return 0;
924
925 initphy_err:
926 phylink_destroy(priv->phylink);
927 phylink_err:
928 ax88772_mdio_unregister(priv);
929 mdio_err:
930 return ret;
931 }
932
933 static int ax88772_stop(struct usbnet *dev)
934 {
935 struct asix_common_private *priv = dev->driver_priv;
936
937 phylink_stop(priv->phylink);
938
939 return 0;
940 }
941
942 static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
943 {
944 struct asix_common_private *priv = dev->driver_priv;
945
946 rtnl_lock();
947 phylink_disconnect_phy(priv->phylink);
948 rtnl_unlock();
949 phylink_destroy(priv->phylink);
950 ax88772_mdio_unregister(priv);
951 asix_rx_fixup_common_free(dev->driver_priv);
952 }
953
954 static void ax88178_unbind(struct usbnet *dev, struct usb_interface *intf)
955 {
956 asix_rx_fixup_common_free(dev->driver_priv);
957 kfree(dev->driver_priv);
958 }
959
960 static const struct ethtool_ops ax88178_ethtool_ops = {
961 .get_drvinfo = asix_get_drvinfo,
962 .get_link = asix_get_link,
963 .get_msglevel = usbnet_get_msglevel,
964 .set_msglevel = usbnet_set_msglevel,
965 .get_wol = asix_get_wol,
966 .set_wol = asix_set_wol,
967 .get_eeprom_len = asix_get_eeprom_len,
968 .get_eeprom = asix_get_eeprom,
969 .set_eeprom = asix_set_eeprom,
970 .nway_reset = usbnet_nway_reset,
971 .get_link_ksettings = usbnet_get_link_ksettings_mii,
972 .set_link_ksettings = usbnet_set_link_ksettings_mii,
973 };
974
975 static int marvell_phy_init(struct usbnet *dev)
976 {
977 struct asix_data *data = (struct asix_data *)&dev->data;
978 u16 reg;
979
980 netdev_dbg(dev->net, "marvell_phy_init()\n");
981
982 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
983 netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
984
985 asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
986 MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
987
988 if (data->ledmode) {
989 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
990 MII_MARVELL_LED_CTRL);
991 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
992
993 reg &= 0xf8ff;
994 reg |= (1 + 0x0100);
995 asix_mdio_write(dev->net, dev->mii.phy_id,
996 MII_MARVELL_LED_CTRL, reg);
997
998 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
999 MII_MARVELL_LED_CTRL);
1000 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
1001 }
1002
1003 return 0;
1004 }
1005
1006 static int rtl8211cl_phy_init(struct usbnet *dev)
1007 {
1008 struct asix_data *data = (struct asix_data *)&dev->data;
1009
1010 netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
1011
1012 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
1013 asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
1014 asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
1015 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
1016 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
1017
1018 if (data->ledmode == 12) {
1019 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
1020 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
1021 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
1022 }
1023
1024 return 0;
1025 }
1026
1027 static int marvell_led_status(struct usbnet *dev, u16 speed)
1028 {
1029 u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
1030
1031 netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
1032
1033 /* Clear out the center LED bits - 0x03F0 */
1034 reg &= 0xfc0f;
1035
1036 switch (speed) {
1037 case SPEED_1000:
1038 reg |= 0x03e0;
1039 break;
1040 case SPEED_100:
1041 reg |= 0x03b0;
1042 break;
1043 default:
1044 reg |= 0x02f0;
1045 }
1046
1047 netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
1048 asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
1049
1050 return 0;
1051 }
1052
1053 static int ax88178_reset(struct usbnet *dev)
1054 {
1055 struct asix_data *data = (struct asix_data *)&dev->data;
1056 int ret;
1057 __le16 eeprom;
1058 u8 status;
1059 int gpio0 = 0;
1060 u32 phyid;
1061
1062 ret = asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
1063 if (ret < 0) {
1064 netdev_dbg(dev->net, "Failed to read GPIOS: %d\n", ret);
1065 return ret;
1066 }
1067
1068 netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
1069
1070 asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
1071 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
1072 if (ret < 0) {
1073 netdev_dbg(dev->net, "Failed to read EEPROM: %d\n", ret);
1074 return ret;
1075 }
1076
1077 asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
1078
1079 netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
1080
1081 if (eeprom == cpu_to_le16(0xffff)) {
1082 data->phymode = PHY_MODE_MARVELL;
1083 data->ledmode = 0;
1084 gpio0 = 1;
1085 } else {
1086 data->phymode = le16_to_cpu(eeprom) & 0x7F;
1087 data->ledmode = le16_to_cpu(eeprom) >> 8;
1088 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
1089 }
1090 netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
1091
1092 /* Power up external GigaPHY through AX88178 GPIO pin */
1093 asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
1094 AX_GPIO_GPO1EN, 40, 0);
1095 if ((le16_to_cpu(eeprom) >> 8) != 1) {
1096 asix_write_gpio(dev, 0x003c, 30, 0);
1097 asix_write_gpio(dev, 0x001c, 300, 0);
1098 asix_write_gpio(dev, 0x003c, 30, 0);
1099 } else {
1100 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
1101 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
1102 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
1103 }
1104
1105 /* Read PHYID register *AFTER* powering up PHY */
1106 phyid = asix_get_phyid(dev);
1107 netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
1108
1109 /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
1110 asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
1111
1112 asix_sw_reset(dev, 0, 0);
1113 msleep(150);
1114
1115 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
1116 msleep(150);
1117
1118 asix_write_rx_ctl(dev, 0, 0);
1119
1120 if (data->phymode == PHY_MODE_MARVELL) {
1121 marvell_phy_init(dev);
1122 msleep(60);
1123 } else if (data->phymode == PHY_MODE_RTL8211CL)
1124 rtl8211cl_phy_init(dev);
1125
1126 asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
1127 asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
1128 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1129 asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
1130 ADVERTISE_1000FULL);
1131
1132 asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
1133 mii_nway_restart(&dev->mii);
1134
1135 /* Rewrite MAC address */
1136 memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
1137 ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
1138 data->mac_addr, 0);
1139 if (ret < 0)
1140 return ret;
1141
1142 ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
1143 if (ret < 0)
1144 return ret;
1145
1146 return 0;
1147 }
1148
1149 static int ax88178_link_reset(struct usbnet *dev)
1150 {
1151 u16 mode;
1152 struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
1153 struct asix_data *data = (struct asix_data *)&dev->data;
1154 u32 speed;
1155
1156 netdev_dbg(dev->net, "ax88178_link_reset()\n");
1157
1158 mii_check_media(&dev->mii, 1, 1);
1159 mii_ethtool_gset(&dev->mii, &ecmd);
1160 mode = AX88178_MEDIUM_DEFAULT;
1161 speed = ethtool_cmd_speed(&ecmd);
1162
1163 if (speed == SPEED_1000)
1164 mode |= AX_MEDIUM_GM;
1165 else if (speed == SPEED_100)
1166 mode |= AX_MEDIUM_PS;
1167 else
1168 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
1169
1170 mode |= AX_MEDIUM_ENCK;
1171
1172 if (ecmd.duplex == DUPLEX_FULL)
1173 mode |= AX_MEDIUM_FD;
1174 else
1175 mode &= ~AX_MEDIUM_FD;
1176
1177 netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
1178 speed, ecmd.duplex, mode);
1179
1180 asix_write_medium_mode(dev, mode, 0);
1181
1182 if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
1183 marvell_led_status(dev, speed);
1184
1185 return 0;
1186 }
1187
1188 static void ax88178_set_mfb(struct usbnet *dev)
1189 {
1190 u16 mfb = AX_RX_CTL_MFB_16384;
1191 u16 rxctl;
1192 u16 medium;
1193 int old_rx_urb_size = dev->rx_urb_size;
1194
1195 if (dev->hard_mtu < 2048) {
1196 dev->rx_urb_size = 2048;
1197 mfb = AX_RX_CTL_MFB_2048;
1198 } else if (dev->hard_mtu < 4096) {
1199 dev->rx_urb_size = 4096;
1200 mfb = AX_RX_CTL_MFB_4096;
1201 } else if (dev->hard_mtu < 8192) {
1202 dev->rx_urb_size = 8192;
1203 mfb = AX_RX_CTL_MFB_8192;
1204 } else if (dev->hard_mtu < 16384) {
1205 dev->rx_urb_size = 16384;
1206 mfb = AX_RX_CTL_MFB_16384;
1207 }
1208
1209 rxctl = asix_read_rx_ctl(dev, 0);
1210 asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
1211
1212 medium = asix_read_medium_status(dev, 0);
1213 if (dev->net->mtu > 1500)
1214 medium |= AX_MEDIUM_JFE;
1215 else
1216 medium &= ~AX_MEDIUM_JFE;
1217 asix_write_medium_mode(dev, medium, 0);
1218
1219 if (dev->rx_urb_size > old_rx_urb_size)
1220 usbnet_unlink_rx_urbs(dev);
1221 }
1222
1223 static int ax88178_change_mtu(struct net_device *net, int new_mtu)
1224 {
1225 struct usbnet *dev = netdev_priv(net);
1226 int ll_mtu = new_mtu + net->hard_header_len + 4;
1227
1228 netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
1229
1230 if ((ll_mtu % dev->maxpacket) == 0)
1231 return -EDOM;
1232
1233 WRITE_ONCE(net->mtu, new_mtu);
1234 dev->hard_mtu = net->mtu + net->hard_header_len;
1235 ax88178_set_mfb(dev);
1236
1237 /* max qlen depend on hard_mtu and rx_urb_size */
1238 usbnet_update_max_qlen(dev);
1239
1240 return 0;
1241 }
1242
1243 static const struct net_device_ops ax88178_netdev_ops = {
1244 .ndo_open = usbnet_open,
1245 .ndo_stop = usbnet_stop,
1246 .ndo_start_xmit = usbnet_start_xmit,
1247 .ndo_tx_timeout = usbnet_tx_timeout,
1248 .ndo_get_stats64 = dev_get_tstats64,
1249 .ndo_set_mac_address = asix_set_mac_address,
1250 .ndo_validate_addr = eth_validate_addr,
1251 .ndo_set_rx_mode = asix_set_multicast,
1252 .ndo_eth_ioctl = asix_ioctl,
1253 .ndo_change_mtu = ax88178_change_mtu,
1254 };
1255
1256 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1257 {
1258 int ret;
1259 u8 buf[ETH_ALEN] = {0};
1260
1261 usbnet_get_endpoints(dev,intf);
1262
1263 /* Get the MAC address */
1264 ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
1265 if (ret < 0) {
1266 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
1267 return ret;
1268 }
1269
1270 asix_set_netdev_dev_addr(dev, buf);
1271
1272 /* Initialize MII structure */
1273 dev->mii.dev = dev->net;
1274 dev->mii.mdio_read = asix_mdio_read;
1275 dev->mii.mdio_write = asix_mdio_write;
1276 dev->mii.phy_id_mask = 0x1f;
1277 dev->mii.reg_num_mask = 0xff;
1278 dev->mii.supports_gmii = 1;
1279
1280 dev->mii.phy_id = asix_read_phy_addr(dev, true);
1281 if (dev->mii.phy_id < 0)
1282 return dev->mii.phy_id;
1283
1284 dev->net->netdev_ops = &ax88178_netdev_ops;
1285 dev->net->ethtool_ops = &ax88178_ethtool_ops;
1286 dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4);
1287
1288 /* Blink LEDS so users know driver saw dongle */
1289 asix_sw_reset(dev, 0, 0);
1290 msleep(150);
1291
1292 asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
1293 msleep(150);
1294
1295 /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1296 if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1297 /* hard_mtu is still the default - the device does not support
1298 jumbo eth frames */
1299 dev->rx_urb_size = 2048;
1300 }
1301
1302 dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
1303 if (!dev->driver_priv)
1304 return -ENOMEM;
1305
1306 return 0;
1307 }
1308
1309 static const struct driver_info ax8817x_info = {
1310 .description = "ASIX AX8817x USB 2.0 Ethernet",
1311 .bind = ax88172_bind,
1312 .status = asix_status,
1313 .link_reset = ax88172_link_reset,
1314 .reset = ax88172_link_reset,
1315 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1316 .data = 0x00130103,
1317 };
1318
1319 static const struct driver_info dlink_dub_e100_info = {
1320 .description = "DLink DUB-E100 USB Ethernet",
1321 .bind = ax88172_bind,
1322 .status = asix_status,
1323 .link_reset = ax88172_link_reset,
1324 .reset = ax88172_link_reset,
1325 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1326 .data = 0x009f9d9f,
1327 };
1328
1329 static const struct driver_info netgear_fa120_info = {
1330 .description = "Netgear FA-120 USB Ethernet",
1331 .bind = ax88172_bind,
1332 .status = asix_status,
1333 .link_reset = ax88172_link_reset,
1334 .reset = ax88172_link_reset,
1335 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1336 .data = 0x00130103,
1337 };
1338
1339 static const struct driver_info hawking_uf200_info = {
1340 .description = "Hawking UF200 USB Ethernet",
1341 .bind = ax88172_bind,
1342 .status = asix_status,
1343 .link_reset = ax88172_link_reset,
1344 .reset = ax88172_link_reset,
1345 .flags = FLAG_ETHER | FLAG_LINK_INTR,
1346 .data = 0x001f1d1f,
1347 };
1348
1349 static const struct driver_info ax88772_info = {
1350 .description = "ASIX AX88772 USB 2.0 Ethernet",
1351 .bind = ax88772_bind,
1352 .unbind = ax88772_unbind,
1353 .status = asix_status,
1354 .reset = ax88772_reset,
1355 .stop = ax88772_stop,
1356 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
1357 .rx_fixup = asix_rx_fixup_common,
1358 .tx_fixup = asix_tx_fixup,
1359 };
1360
1361 static const struct driver_info ax88772b_info = {
1362 .description = "ASIX AX88772B USB 2.0 Ethernet",
1363 .bind = ax88772_bind,
1364 .unbind = ax88772_unbind,
1365 .status = asix_status,
1366 .reset = ax88772_reset,
1367 .stop = ax88772_stop,
1368 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1369 FLAG_MULTI_PACKET,
1370 .rx_fixup = asix_rx_fixup_common,
1371 .tx_fixup = asix_tx_fixup,
1372 .data = FLAG_EEPROM_MAC,
1373 };
1374
1375 static const struct driver_info lxausb_t1l_info = {
1376 .description = "Linux Automation GmbH USB 10Base-T1L",
1377 .bind = ax88772_bind,
1378 .unbind = ax88772_unbind,
1379 .status = asix_status,
1380 .reset = ax88772_reset,
1381 .stop = ax88772_stop,
1382 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1383 FLAG_MULTI_PACKET,
1384 .rx_fixup = asix_rx_fixup_common,
1385 .tx_fixup = asix_tx_fixup,
1386 .data = FLAG_EEPROM_MAC,
1387 };
1388
1389 static const struct driver_info ax88178_info = {
1390 .description = "ASIX AX88178 USB 2.0 Ethernet",
1391 .bind = ax88178_bind,
1392 .unbind = ax88178_unbind,
1393 .status = asix_status,
1394 .link_reset = ax88178_link_reset,
1395 .reset = ax88178_reset,
1396 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1397 FLAG_MULTI_PACKET,
1398 .rx_fixup = asix_rx_fixup_common,
1399 .tx_fixup = asix_tx_fixup,
1400 };
1401
1402 /*
1403 * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
1404 * no-name packaging.
1405 * USB device strings are:
1406 * 1: Manufacturer: USBLINK
1407 * 2: Product: HG20F9 USB2.0
1408 * 3: Serial: 000003
1409 * Appears to be compatible with Asix 88772B.
1410 */
1411 static const struct driver_info hg20f9_info = {
1412 .description = "HG20F9 USB 2.0 Ethernet",
1413 .bind = ax88772_bind,
1414 .unbind = ax88772_unbind,
1415 .status = asix_status,
1416 .reset = ax88772_reset,
1417 .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1418 FLAG_MULTI_PACKET,
1419 .rx_fixup = asix_rx_fixup_common,
1420 .tx_fixup = asix_tx_fixup,
1421 .data = FLAG_EEPROM_MAC,
1422 };
1423
1424 static const struct usb_device_id products [] = {
1425 {
1426 // Linksys USB200M
1427 USB_DEVICE (0x077b, 0x2226),
1428 .driver_info = (unsigned long) &ax8817x_info,
1429 }, {
1430 // Netgear FA120
1431 USB_DEVICE (0x0846, 0x1040),
1432 .driver_info = (unsigned long) &netgear_fa120_info,
1433 }, {
1434 // DLink DUB-E100
1435 USB_DEVICE (0x2001, 0x1a00),
1436 .driver_info = (unsigned long) &dlink_dub_e100_info,
1437 }, {
1438 // Intellinet, ST Lab USB Ethernet
1439 USB_DEVICE (0x0b95, 0x1720),
1440 .driver_info = (unsigned long) &ax8817x_info,
1441 }, {
1442 // Hawking UF200, TrendNet TU2-ET100
1443 USB_DEVICE (0x07b8, 0x420a),
1444 .driver_info = (unsigned long) &hawking_uf200_info,
1445 }, {
1446 // Billionton Systems, USB2AR
1447 USB_DEVICE (0x08dd, 0x90ff),
1448 .driver_info = (unsigned long) &ax8817x_info,
1449 }, {
1450 // Billionton Systems, GUSB2AM-1G-B
1451 USB_DEVICE(0x08dd, 0x0114),
1452 .driver_info = (unsigned long) &ax88178_info,
1453 }, {
1454 // ATEN UC210T
1455 USB_DEVICE (0x0557, 0x2009),
1456 .driver_info = (unsigned long) &ax8817x_info,
1457 }, {
1458 // Buffalo LUA-U2-KTX
1459 USB_DEVICE (0x0411, 0x003d),
1460 .driver_info = (unsigned long) &ax8817x_info,
1461 }, {
1462 // Buffalo LUA-U2-GT 10/100/1000
1463 USB_DEVICE (0x0411, 0x006e),
1464 .driver_info = (unsigned long) &ax88178_info,
1465 }, {
1466 // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1467 USB_DEVICE (0x6189, 0x182d),
1468 .driver_info = (unsigned long) &ax8817x_info,
1469 }, {
1470 // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1471 USB_DEVICE (0x0df6, 0x0056),
1472 .driver_info = (unsigned long) &ax88178_info,
1473 }, {
1474 // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1475 USB_DEVICE (0x0df6, 0x061c),
1476 .driver_info = (unsigned long) &ax88178_info,
1477 }, {
1478 // corega FEther USB2-TX
1479 USB_DEVICE (0x07aa, 0x0017),
1480 .driver_info = (unsigned long) &ax8817x_info,
1481 }, {
1482 // Surecom EP-1427X-2
1483 USB_DEVICE (0x1189, 0x0893),
1484 .driver_info = (unsigned long) &ax8817x_info,
1485 }, {
1486 // goodway corp usb gwusb2e
1487 USB_DEVICE (0x1631, 0x6200),
1488 .driver_info = (unsigned long) &ax8817x_info,
1489 }, {
1490 // JVC MP-PRX1 Port Replicator
1491 USB_DEVICE (0x04f1, 0x3008),
1492 .driver_info = (unsigned long) &ax8817x_info,
1493 }, {
1494 // Lenovo U2L100P 10/100
1495 USB_DEVICE (0x17ef, 0x7203),
1496 .driver_info = (unsigned long)&ax88772b_info,
1497 }, {
1498 // ASIX AX88772B 10/100
1499 USB_DEVICE (0x0b95, 0x772b),
1500 .driver_info = (unsigned long) &ax88772b_info,
1501 }, {
1502 // ASIX AX88772 10/100
1503 USB_DEVICE (0x0b95, 0x7720),
1504 .driver_info = (unsigned long) &ax88772_info,
1505 }, {
1506 // ASIX AX88178 10/100/1000
1507 USB_DEVICE (0x0b95, 0x1780),
1508 .driver_info = (unsigned long) &ax88178_info,
1509 }, {
1510 // Logitec LAN-GTJ/U2A
1511 USB_DEVICE (0x0789, 0x0160),
1512 .driver_info = (unsigned long) &ax88178_info,
1513 }, {
1514 // Linksys USB200M Rev 2
1515 USB_DEVICE (0x13b1, 0x0018),
1516 .driver_info = (unsigned long) &ax88772_info,
1517 }, {
1518 // 0Q0 cable ethernet
1519 USB_DEVICE (0x1557, 0x7720),
1520 .driver_info = (unsigned long) &ax88772_info,
1521 }, {
1522 // DLink DUB-E100 H/W Ver B1
1523 USB_DEVICE (0x07d1, 0x3c05),
1524 .driver_info = (unsigned long) &ax88772_info,
1525 }, {
1526 // DLink DUB-E100 H/W Ver B1 Alternate
1527 USB_DEVICE (0x2001, 0x3c05),
1528 .driver_info = (unsigned long) &ax88772_info,
1529 }, {
1530 // DLink DUB-E100 H/W Ver C1
1531 USB_DEVICE (0x2001, 0x1a02),
1532 .driver_info = (unsigned long) &ax88772_info,
1533 }, {
1534 // Linksys USB1000
1535 USB_DEVICE (0x1737, 0x0039),
1536 .driver_info = (unsigned long) &ax88178_info,
1537 }, {
1538 // IO-DATA ETG-US2
1539 USB_DEVICE (0x04bb, 0x0930),
1540 .driver_info = (unsigned long) &ax88178_info,
1541 }, {
1542 // Belkin F5D5055
1543 USB_DEVICE(0x050d, 0x5055),
1544 .driver_info = (unsigned long) &ax88178_info,
1545 }, {
1546 // Apple USB Ethernet Adapter
1547 USB_DEVICE(0x05ac, 0x1402),
1548 .driver_info = (unsigned long) &ax88772_info,
1549 }, {
1550 // Cables-to-Go USB Ethernet Adapter
1551 USB_DEVICE(0x0b95, 0x772a),
1552 .driver_info = (unsigned long) &ax88772_info,
1553 }, {
1554 // ABOCOM for pci
1555 USB_DEVICE(0x14ea, 0xab11),
1556 .driver_info = (unsigned long) &ax88178_info,
1557 }, {
1558 // ASIX 88772a
1559 USB_DEVICE(0x0db0, 0xa877),
1560 .driver_info = (unsigned long) &ax88772_info,
1561 }, {
1562 // Asus USB Ethernet Adapter
1563 USB_DEVICE (0x0b95, 0x7e2b),
1564 .driver_info = (unsigned long)&ax88772b_info,
1565 }, {
1566 /* ASIX 88172a demo board */
1567 USB_DEVICE(0x0b95, 0x172a),
1568 .driver_info = (unsigned long) &ax88172a_info,
1569 }, {
1570 /*
1571 * USBLINK HG20F9 "USB 2.0 LAN"
1572 * Appears to have gazumped Linksys's manufacturer ID but
1573 * doesn't (yet) conflict with any known Linksys product.
1574 */
1575 USB_DEVICE(0x066b, 0x20f9),
1576 .driver_info = (unsigned long) &hg20f9_info,
1577 }, {
1578 // Linux Automation GmbH USB 10Base-T1L
1579 USB_DEVICE(0x33f7, 0x0004),
1580 .driver_info = (unsigned long) &lxausb_t1l_info,
1581 },
1582 { }, // END
1583 };
1584 MODULE_DEVICE_TABLE(usb, products);
1585
1586 static struct usb_driver asix_driver = {
1587 .name = DRIVER_NAME,
1588 .id_table = products,
1589 .probe = usbnet_probe,
1590 .suspend = asix_suspend,
1591 .resume = asix_resume,
1592 .reset_resume = asix_resume,
1593 .disconnect = usbnet_disconnect,
1594 .supports_autosuspend = 1,
1595 .disable_hub_initiated_lpm = 1,
1596 };
1597
1598 module_usb_driver(asix_driver);
1599
1600 MODULE_AUTHOR("David Hollis");
1601 MODULE_VERSION(DRIVER_VERSION);
1602 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1603 MODULE_LICENSE("GPL");
1604
Kernel DRM miscellaneous fixes and cross-tree changes