drivers/net/wireless/ath/ath12k/ce.h

   1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2 /*
   3  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021-2022, 2024 Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #ifndef ATH12K_CE_H
   8 #define ATH12K_CE_H
   9
  10 #define CE_COUNT_MAX 16
  11
  12 /* Byte swap data words */
  13 #define CE_ATTR_BYTE_SWAP_DATA 2
  14
  15 /* no interrupt on copy completion */
  16 #define CE_ATTR_DIS_INTR                8
  17
  18 /* Host software's Copy Engine configuration. */
  19 #define CE_ATTR_FLAGS 0
  20
  21 /* Threshold to poll for tx completion in case of Interrupt disabled CE's */
  22 #define ATH12K_CE_USAGE_THRESHOLD 32
  23
  24 /* Directions for interconnect pipe configuration.
  25  * These definitions may be used during configuration and are shared
  26  * between Host and Target.
  27  *
  28  * Pipe Directions are relative to the Host, so PIPEDIR_IN means
  29  * "coming IN over air through Target to Host" as with a WiFi Rx operation.
  30  * Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
  31  * as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
  32  * Target since things that are "PIPEDIR_OUT" are coming IN to the Target
  33  * over the interconnect.
  34  */
  35 #define PIPEDIR_NONE            0
  36 #define PIPEDIR_IN              1 /* Target-->Host, WiFi Rx direction */
  37 #define PIPEDIR_OUT             2 /* Host->Target, WiFi Tx direction */
  38 #define PIPEDIR_INOUT           3 /* bidirectional */
  39 #define PIPEDIR_INOUT_H2H       4 /* bidirectional, host to host */
  40
  41 /* CE address/mask */
  42 #define CE_HOST_IE_ADDRESS      0x00A1803C
  43 #define CE_HOST_IE_2_ADDRESS    0x00A18040
  44 #define CE_HOST_IE_3_ADDRESS    CE_HOST_IE_ADDRESS
  45
  46 #define CE_HOST_IE_3_SHIFT      0xC
  47
  48 #define CE_RING_IDX_INCR(nentries_mask, idx) (((idx) + 1) & (nentries_mask))
  49
  50 #define ATH12K_CE_RX_POST_RETRY_JIFFIES 50
  51
  52 struct ath12k_base;
  53
  54 /* Establish a mapping between a service/direction and a pipe.
  55  * Configuration information for a Copy Engine pipe and services.
  56  * Passed from Host to Target through QMI message and must be in
  57  * little endian format.
  58  */
  59 struct service_to_pipe {
  60         __le32 service_id;
  61         __le32 pipedir;
  62         __le32 pipenum;
  63 };
  64
  65 /* Configuration information for a Copy Engine pipe.
  66  * Passed from Host to Target through QMI message during startup (one per CE).
  67  *
  68  * NOTE: Structure is shared between Host software and Target firmware!
  69  */
  70 struct ce_pipe_config {
  71         __le32 pipenum;
  72         __le32 pipedir;
  73         __le32 nentries;
  74         __le32 nbytes_max;
  75         __le32 flags;
  76         __le32 reserved;
  77 };
  78
  79 struct ce_attr {
  80         /* CE_ATTR_* values */
  81         unsigned int flags;
  82
  83         /* #entries in source ring - Must be a power of 2 */
  84         unsigned int src_nentries;
  85
  86         /* Max source send size for this CE.
  87          * This is also the minimum size of a destination buffer.
  88          */
  89         unsigned int src_sz_max;
  90
  91         /* #entries in destination ring - Must be a power of 2 */
  92         unsigned int dest_nentries;
  93
  94         void (*recv_cb)(struct ath12k_base *ab, struct sk_buff *skb);
  95 };
  96
  97 #define CE_DESC_RING_ALIGN 8
  98
  99 struct ath12k_ce_ring {
 100         /* Number of entries in this ring; must be power of 2 */
 101         unsigned int nentries;
 102         unsigned int nentries_mask;
 103
 104         /* For dest ring, this is the next index to be processed
 105          * by software after it was/is received into.
 106          *
 107          * For src ring, this is the last descriptor that was sent
 108          * and completion processed by software.
 109          *
 110          * Regardless of src or dest ring, this is an invariant
 111          * (modulo ring size):
 112          *     write index >= read index >= sw_index
 113          */
 114         unsigned int sw_index;
 115         /* cached copy */
 116         unsigned int write_index;
 117
 118         /* Start of DMA-coherent area reserved for descriptors */
 119         /* Host address space */
 120         void *base_addr_owner_space_unaligned;
 121         /* CE address space */
 122         dma_addr_t base_addr_ce_space_unaligned;
 123
 124         /* Actual start of descriptors.
 125          * Aligned to descriptor-size boundary.
 126          * Points into reserved DMA-coherent area, above.
 127          */
 128         /* Host address space */
 129         void *base_addr_owner_space;
 130
 131         /* CE address space */
 132         dma_addr_t base_addr_ce_space;
 133
 134         /* HAL ring id */
 135         u32 hal_ring_id;
 136
 137         /* keep last */
 138         struct sk_buff *skb[];
 139 };
 140
 141 struct ath12k_ce_pipe {
 142         struct ath12k_base *ab;
 143         u16 pipe_num;
 144         unsigned int attr_flags;
 145         unsigned int buf_sz;
 146         unsigned int rx_buf_needed;
 147
 148         void (*send_cb)(struct ath12k_ce_pipe *pipe);
 149         void (*recv_cb)(struct ath12k_base *ab, struct sk_buff *skb);
 150
 151         struct work_struct intr_wq;
 152         struct ath12k_ce_ring *src_ring;
 153         struct ath12k_ce_ring *dest_ring;
 154         struct ath12k_ce_ring *status_ring;
 155         u64 timestamp;
 156 };
 157
 158 struct ath12k_ce {
 159         struct ath12k_ce_pipe ce_pipe[CE_COUNT_MAX];
 160         /* Protects rings of all ce pipes */
 161         spinlock_t ce_lock;
 162         struct ath12k_hp_update_timer hp_timer[CE_COUNT_MAX];
 163 };
 164
 165 extern const struct ce_attr ath12k_host_ce_config_qcn9274[];
 166 extern const struct ce_attr ath12k_host_ce_config_wcn7850[];
 167
 168 void ath12k_ce_cleanup_pipes(struct ath12k_base *ab);
 169 void ath12k_ce_rx_replenish_retry(struct timer_list *t);
 170 void ath12k_ce_per_engine_service(struct ath12k_base *ab, u16 ce_id);
 171 int ath12k_ce_send(struct ath12k_base *ab, struct sk_buff *skb, u8 pipe_id,
 172                    u16 transfer_id);
 173 void ath12k_ce_rx_post_buf(struct ath12k_base *ab);
 174 int ath12k_ce_init_pipes(struct ath12k_base *ab);
 175 int ath12k_ce_alloc_pipes(struct ath12k_base *ab);
 176 void ath12k_ce_free_pipes(struct ath12k_base *ab);
 177 int ath12k_ce_get_attr_flags(struct ath12k_base *ab, int ce_id);
 178 void ath12k_ce_poll_send_completed(struct ath12k_base *ab, u8 pipe_id);
 179 void ath12k_ce_get_shadow_config(struct ath12k_base *ab,
 180                                  u32 **shadow_cfg, u32 *shadow_cfg_len);
 181 #endif