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drm: bridge: adv7511: remove s32 format from i2s capabilities
[drm/drm-misc.git] / drivers / net / wireless / ath / ath12k / hal.h
blob8a78bb9a10bc15a3c715c2c2b03ed18e21b5816e
1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_HAL_H
8 #define ATH12K_HAL_H
9
10 #include "hal_desc.h"
11 #include "rx_desc.h"
12
13 struct ath12k_base;
14
15 #define HAL_LINK_DESC_SIZE (32 << 2)
16 #define HAL_LINK_DESC_ALIGN 128
17 #define HAL_NUM_MPDUS_PER_LINK_DESC 6
18 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7
19 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6
20 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12
21 #define HAL_MAX_AVAIL_BLK_RES 3
22
23 #define HAL_RING_BASE_ALIGN 8
24
25 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704
26 /* TODO: Check with hw team on the supported scatter buf size */
27 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8
28 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \
29 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE)
30
31 /* TODO: 16 entries per radio times MAX_VAPS_SUPPORTED */
32 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 32
33 #define HAL_DSCP_TID_TBL_SIZE 24
34
35 /* calculate the register address from bar0 of shadow register x */
36 #define HAL_SHADOW_BASE_ADDR 0x000008fc
37 #define HAL_SHADOW_NUM_REGS 40
38 #define HAL_HP_OFFSET_IN_REG_START 1
39 #define HAL_OFFSET_FROM_HP_TO_TP 4
40
41 #define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x)))
42
43 /* WCSS Relative address */
44 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
45 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
46 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000
47 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x01b80000
48 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x01b81000
49 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x01b82000
50 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x01b83000
51 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000
52
53 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000
54
55 #define HAL_TCL_SW_CONFIG_BANK_ADDR 0x00a4408c
56
57 /* SW2TCL(x) R0 ring configuration address */
58 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000020
59 #define HAL_TCL1_RING_DSCP_TID_MAP 0x00000240
60 #define HAL_TCL1_RING_BASE_LSB 0x00000900
61 #define HAL_TCL1_RING_BASE_MSB 0x00000904
62 #define HAL_TCL1_RING_ID(ab) ((ab)->hw_params->regs->hal_tcl1_ring_id)
63 #define HAL_TCL1_RING_MISC(ab) \
64 ((ab)->hw_params->regs->hal_tcl1_ring_misc)
65 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \
66 ((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_lsb)
67 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \
68 ((ab)->hw_params->regs->hal_tcl1_ring_tp_addr_msb)
69 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \
70 ((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix0)
71 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \
72 ((ab)->hw_params->regs->hal_tcl1_ring_consumer_int_setup_ix1)
73 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \
74 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_lsb)
75 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \
76 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_base_msb)
77 #define HAL_TCL1_RING_MSI1_DATA(ab) \
78 ((ab)->hw_params->regs->hal_tcl1_ring_msi1_data)
79 #define HAL_TCL2_RING_BASE_LSB 0x00000978
80 #define HAL_TCL_RING_BASE_LSB(ab) \
81 ((ab)->hw_params->regs->hal_tcl_ring_base_lsb)
82
83 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab) \
84 (HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB)
85 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab) \
86 (HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB)
87 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab) \
88 (HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB)
89 #define HAL_TCL1_RING_BASE_MSB_OFFSET \
90 (HAL_TCL1_RING_BASE_MSB - HAL_TCL1_RING_BASE_LSB)
91 #define HAL_TCL1_RING_ID_OFFSET(ab) \
92 (HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB)
93 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab) \
94 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB)
95 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) \
96 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB)
97 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) \
98 (HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB)
99 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) \
100 (HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB)
101 #define HAL_TCL1_RING_MISC_OFFSET(ab) \
102 (HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB)
103
104 /* SW2TCL(x) R2 ring pointers (head/tail) address */
105 #define HAL_TCL1_RING_HP 0x00002000
106 #define HAL_TCL1_RING_TP 0x00002004
107 #define HAL_TCL2_RING_HP 0x00002008
108 #define HAL_TCL_RING_HP 0x00002028
109
110 #define HAL_TCL1_RING_TP_OFFSET \
111 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP)
112
113 /* TCL STATUS ring address */
114 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \
115 ((ab)->hw_params->regs->hal_tcl_status_ring_base_lsb)
116 #define HAL_TCL_STATUS_RING_HP 0x00002048
117
118 /* PPE2TCL1 Ring address */
119 #define HAL_TCL_PPE2TCL1_RING_BASE_LSB 0x00000c48
120 #define HAL_TCL_PPE2TCL1_RING_HP 0x00002038
121
122 /* WBM PPE Release Ring address */
123 #define HAL_WBM_PPE_RELEASE_RING_BASE_LSB(ab) \
124 ((ab)->hw_params->regs->hal_ppe_rel_ring_base)
125 #define HAL_WBM_PPE_RELEASE_RING_HP 0x00003020
126
127 /* REO2SW(x) R0 ring configuration address */
128 #define HAL_REO1_GEN_ENABLE 0x00000000
129 #define HAL_REO1_MISC_CTRL_ADDR(ab) \
130 ((ab)->hw_params->regs->hal_reo1_misc_ctrl_addr)
131 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004
132 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008
133 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c
134 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010
135 #define HAL_REO1_SW_COOKIE_CFG0(ab) ((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg0)
136 #define HAL_REO1_SW_COOKIE_CFG1(ab) ((ab)->hw_params->regs->hal_reo1_sw_cookie_cfg1)
137 #define HAL_REO1_QDESC_LUT_BASE0(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_lut_base0)
138 #define HAL_REO1_QDESC_LUT_BASE1(ab) ((ab)->hw_params->regs->hal_reo1_qdesc_lut_base1)
139 #define HAL_REO1_RING_BASE_LSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_base_lsb)
140 #define HAL_REO1_RING_BASE_MSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_base_msb)
141 #define HAL_REO1_RING_ID(ab) ((ab)->hw_params->regs->hal_reo1_ring_id)
142 #define HAL_REO1_RING_MISC(ab) ((ab)->hw_params->regs->hal_reo1_ring_misc)
143 #define HAL_REO1_RING_HP_ADDR_LSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_hp_addr_lsb)
144 #define HAL_REO1_RING_HP_ADDR_MSB(ab) ((ab)->hw_params->regs->hal_reo1_ring_hp_addr_msb)
145 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \
146 ((ab)->hw_params->regs->hal_reo1_ring_producer_int_setup)
147 #define HAL_REO1_RING_MSI1_BASE_LSB(ab) \
148 ((ab)->hw_params->regs->hal_reo1_ring_msi1_base_lsb)
149 #define HAL_REO1_RING_MSI1_BASE_MSB(ab) \
150 ((ab)->hw_params->regs->hal_reo1_ring_msi1_base_msb)
151 #define HAL_REO1_RING_MSI1_DATA(ab) ((ab)->hw_params->regs->hal_reo1_ring_msi1_data)
152 #define HAL_REO2_RING_BASE_LSB(ab) ((ab)->hw_params->regs->hal_reo2_ring_base)
153 #define HAL_REO1_AGING_THRESH_IX_0(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix0)
154 #define HAL_REO1_AGING_THRESH_IX_1(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix1)
155 #define HAL_REO1_AGING_THRESH_IX_2(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix2)
156 #define HAL_REO1_AGING_THRESH_IX_3(ab) ((ab)->hw_params->regs->hal_reo1_aging_thres_ix3)
157
158 /* REO2SW(x) R2 ring pointers (head/tail) address */
159 #define HAL_REO1_RING_HP 0x00003048
160 #define HAL_REO1_RING_TP 0x0000304c
161 #define HAL_REO2_RING_HP 0x00003050
162
163 #define HAL_REO1_RING_TP_OFFSET (HAL_REO1_RING_TP - HAL_REO1_RING_HP)
164
165 /* REO2SW0 ring configuration address */
166 #define HAL_REO_SW0_RING_BASE_LSB(ab) \
167 ((ab)->hw_params->regs->hal_reo2_sw0_ring_base)
168
169 /* REO2SW0 R2 ring pointer (head/tail) address */
170 #define HAL_REO_SW0_RING_HP 0x00003088
171
172 /* REO CMD R0 address */
173 #define HAL_REO_CMD_RING_BASE_LSB(ab) \
174 ((ab)->hw_params->regs->hal_reo_cmd_ring_base)
175
176 /* REO CMD R2 address */
177 #define HAL_REO_CMD_HP 0x00003020
178
179 /* SW2REO R0 address */
180 #define HAL_SW2REO_RING_BASE_LSB(ab) \
181 ((ab)->hw_params->regs->hal_sw2reo_ring_base)
182 #define HAL_SW2REO1_RING_BASE_LSB(ab) \
183 ((ab)->hw_params->regs->hal_sw2reo1_ring_base)
184
185 /* SW2REO R2 address */
186 #define HAL_SW2REO_RING_HP 0x00003028
187 #define HAL_SW2REO1_RING_HP 0x00003030
188
189 /* CE ring R0 address */
190 #define HAL_CE_SRC_RING_BASE_LSB 0x00000000
191 #define HAL_CE_DST_RING_BASE_LSB 0x00000000
192 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058
193 #define HAL_CE_DST_RING_CTRL 0x000000b0
194
195 /* CE ring R2 address */
196 #define HAL_CE_DST_RING_HP 0x00000400
197 #define HAL_CE_DST_STATUS_RING_HP 0x00000408
198
199 /* REO status address */
200 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \
201 ((ab)->hw_params->regs->hal_reo_status_ring_base)
202 #define HAL_REO_STATUS_HP 0x000030a8
203
204 /* WBM Idle R0 address */
205 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(ab) \
206 ((ab)->hw_params->regs->hal_wbm_idle_ring_base_lsb)
207 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(ab) \
208 ((ab)->hw_params->regs->hal_wbm_idle_ring_misc_addr)
209 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR(ab) \
210 ((ab)->hw_params->regs->hal_wbm_r0_idle_list_cntl_addr)
211 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR(ab) \
212 ((ab)->hw_params->regs->hal_wbm_r0_idle_list_size_addr)
213 #define HAL_WBM_SCATTERED_RING_BASE_LSB(ab) \
214 ((ab)->hw_params->regs->hal_wbm_scattered_ring_base_lsb)
215 #define HAL_WBM_SCATTERED_RING_BASE_MSB(ab) \
216 ((ab)->hw_params->regs->hal_wbm_scattered_ring_base_msb)
217 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0(ab) \
218 ((ab)->hw_params->regs->hal_wbm_scattered_desc_head_info_ix0)
219 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1(ab) \
220 ((ab)->hw_params->regs->hal_wbm_scattered_desc_head_info_ix1)
221 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0(ab) \
222 ((ab)->hw_params->regs->hal_wbm_scattered_desc_tail_info_ix0)
223 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1(ab) \
224 ((ab)->hw_params->regs->hal_wbm_scattered_desc_tail_info_ix1)
225 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR(ab) \
226 ((ab)->hw_params->regs->hal_wbm_scattered_desc_ptr_hp_addr)
227
228 /* WBM Idle R2 address */
229 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b8
230
231 /* SW2WBM R0 release address */
232 #define HAL_WBM_SW_RELEASE_RING_BASE_LSB(ab) \
233 ((ab)->hw_params->regs->hal_wbm_sw_release_ring_base_lsb)
234 #define HAL_WBM_SW1_RELEASE_RING_BASE_LSB(ab) \
235 ((ab)->hw_params->regs->hal_wbm_sw1_release_ring_base_lsb)
236
237 /* SW2WBM R2 release address */
238 #define HAL_WBM_SW_RELEASE_RING_HP 0x00003010
239 #define HAL_WBM_SW1_RELEASE_RING_HP 0x00003018
240
241 /* WBM2SW R0 release address */
242 #define HAL_WBM0_RELEASE_RING_BASE_LSB(ab) \
243 ((ab)->hw_params->regs->hal_wbm0_release_ring_base_lsb)
244
245 #define HAL_WBM1_RELEASE_RING_BASE_LSB(ab) \
246 ((ab)->hw_params->regs->hal_wbm1_release_ring_base_lsb)
247
248 /* WBM2SW R2 release address */
249 #define HAL_WBM0_RELEASE_RING_HP 0x000030c8
250 #define HAL_WBM1_RELEASE_RING_HP 0x000030d0
251
252 /* WBM cookie config address and mask */
253 #define HAL_WBM_SW_COOKIE_CFG0 0x00000040
254 #define HAL_WBM_SW_COOKIE_CFG1 0x00000044
255 #define HAL_WBM_SW_COOKIE_CFG2 0x00000090
256 #define HAL_WBM_SW_COOKIE_CONVERT_CFG 0x00000094
257
258 #define HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0)
259 #define HAL_WBM_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8)
260 #define HAL_WBM_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13)
261 #define HAL_WBM_SW_COOKIE_CFG_ALIGN BIT(18)
262 #define HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN BIT(0)
263 #define HAL_WBM_SW_COOKIE_CFG_ERR_PATH_EN BIT(1)
264 #define HAL_WBM_SW_COOKIE_CFG_CONV_IND_EN BIT(3)
265
266 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN BIT(1)
267 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN BIT(2)
268 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN BIT(3)
269 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN BIT(4)
270 #define HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN BIT(5)
271 #define HAL_WBM_SW_COOKIE_CONV_CFG_GLOBAL_EN BIT(8)
272
273 /* TCL ring field mask and offset */
274 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
275 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
276 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
277 #define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE BIT(0)
278 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1)
279 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3)
280 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4)
281 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5)
282 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6)
283 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16)
284 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)
285 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0)
286 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8)
287 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
288 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(23)
289 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0)
290 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0)
291 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3)
292 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6)
293 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9)
294 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12)
295 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15)
296 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18)
297 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21)
298
299 /* REO ring field mask and offset */
300 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8)
301 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
302 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8)
303 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
304 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3)
305 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4)
306 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5)
307 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6)
308 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16)
309 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
310 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8)
311 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
312 #define HAL_REO1_MISC_CTL_FRAG_DST_RING GENMASK(20, 17)
313 #define HAL_REO1_MISC_CTL_BAR_DST_RING GENMASK(24, 21)
314 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2)
315 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3)
316 #define HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0)
317 #define HAL_REO1_SW_COOKIE_CFG_COOKIE_PPT_MSB GENMASK(12, 8)
318 #define HAL_REO1_SW_COOKIE_CFG_COOKIE_SPT_MSB GENMASK(17, 13)
319 #define HAL_REO1_SW_COOKIE_CFG_ALIGN BIT(18)
320 #define HAL_REO1_SW_COOKIE_CFG_ENABLE BIT(19)
321 #define HAL_REO1_SW_COOKIE_CFG_GLOBAL_ENABLE BIT(20)
322
323 /* CE ring bit field mask and shift */
324 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)
325
326 #define HAL_ADDR_LSB_REG_MASK 0xffffffff
327
328 #define HAL_ADDR_MSB_REG_SHIFT 32
329
330 /* WBM ring bit field mask and shift */
331 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1)
332 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2)
333 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16)
334 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0)
335 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8)
336
337 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8)
338 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8)
339
340 #define HAL_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE BIT(6)
341 #define HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE BIT(0)
342
343 #define BASE_ADDR_MATCH_TAG_VAL 0x5
344
345 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff
346 #define HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE 0x000fffff
347 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff
348 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff
349 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
350 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff
351 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff
352 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
353 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff
354 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff
355 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
356 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x000fffff
357 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff
358 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff
359 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff
360 #define HAL_RXDMA_RING_MAX_SIZE_BE 0x000fffff
361 #define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff
362
363 #define HAL_WBM2SW_REL_ERR_RING_NUM 3
364 /* Add any other errors here and return them in
365 * ath12k_hal_rx_desc_get_err().
366 */
367
368 enum hal_srng_ring_id {
369 HAL_SRNG_RING_ID_REO2SW0 = 0,
370 HAL_SRNG_RING_ID_REO2SW1,
371 HAL_SRNG_RING_ID_REO2SW2,
372 HAL_SRNG_RING_ID_REO2SW3,
373 HAL_SRNG_RING_ID_REO2SW4,
374 HAL_SRNG_RING_ID_REO2SW5,
375 HAL_SRNG_RING_ID_REO2SW6,
376 HAL_SRNG_RING_ID_REO2SW7,
377 HAL_SRNG_RING_ID_REO2SW8,
378 HAL_SRNG_RING_ID_REO2TCL,
379 HAL_SRNG_RING_ID_REO2PPE,
380
381 HAL_SRNG_RING_ID_SW2REO = 16,
382 HAL_SRNG_RING_ID_SW2REO1,
383 HAL_SRNG_RING_ID_SW2REO2,
384 HAL_SRNG_RING_ID_SW2REO3,
385
386 HAL_SRNG_RING_ID_REO_CMD,
387 HAL_SRNG_RING_ID_REO_STATUS,
388
389 HAL_SRNG_RING_ID_SW2TCL1 = 24,
390 HAL_SRNG_RING_ID_SW2TCL2,
391 HAL_SRNG_RING_ID_SW2TCL3,
392 HAL_SRNG_RING_ID_SW2TCL4,
393 HAL_SRNG_RING_ID_SW2TCL5,
394 HAL_SRNG_RING_ID_SW2TCL6,
395 HAL_SRNG_RING_ID_PPE2TCL1 = 30,
396
397 HAL_SRNG_RING_ID_SW2TCL_CMD = 40,
398 HAL_SRNG_RING_ID_SW2TCL1_CMD,
399 HAL_SRNG_RING_ID_TCL_STATUS,
400
401 HAL_SRNG_RING_ID_CE0_SRC = 64,
402 HAL_SRNG_RING_ID_CE1_SRC,
403 HAL_SRNG_RING_ID_CE2_SRC,
404 HAL_SRNG_RING_ID_CE3_SRC,
405 HAL_SRNG_RING_ID_CE4_SRC,
406 HAL_SRNG_RING_ID_CE5_SRC,
407 HAL_SRNG_RING_ID_CE6_SRC,
408 HAL_SRNG_RING_ID_CE7_SRC,
409 HAL_SRNG_RING_ID_CE8_SRC,
410 HAL_SRNG_RING_ID_CE9_SRC,
411 HAL_SRNG_RING_ID_CE10_SRC,
412 HAL_SRNG_RING_ID_CE11_SRC,
413 HAL_SRNG_RING_ID_CE12_SRC,
414 HAL_SRNG_RING_ID_CE13_SRC,
415 HAL_SRNG_RING_ID_CE14_SRC,
416 HAL_SRNG_RING_ID_CE15_SRC,
417
418 HAL_SRNG_RING_ID_CE0_DST = 81,
419 HAL_SRNG_RING_ID_CE1_DST,
420 HAL_SRNG_RING_ID_CE2_DST,
421 HAL_SRNG_RING_ID_CE3_DST,
422 HAL_SRNG_RING_ID_CE4_DST,
423 HAL_SRNG_RING_ID_CE5_DST,
424 HAL_SRNG_RING_ID_CE6_DST,
425 HAL_SRNG_RING_ID_CE7_DST,
426 HAL_SRNG_RING_ID_CE8_DST,
427 HAL_SRNG_RING_ID_CE9_DST,
428 HAL_SRNG_RING_ID_CE10_DST,
429 HAL_SRNG_RING_ID_CE11_DST,
430 HAL_SRNG_RING_ID_CE12_DST,
431 HAL_SRNG_RING_ID_CE13_DST,
432 HAL_SRNG_RING_ID_CE14_DST,
433 HAL_SRNG_RING_ID_CE15_DST,
434
435 HAL_SRNG_RING_ID_CE0_DST_STATUS = 100,
436 HAL_SRNG_RING_ID_CE1_DST_STATUS,
437 HAL_SRNG_RING_ID_CE2_DST_STATUS,
438 HAL_SRNG_RING_ID_CE3_DST_STATUS,
439 HAL_SRNG_RING_ID_CE4_DST_STATUS,
440 HAL_SRNG_RING_ID_CE5_DST_STATUS,
441 HAL_SRNG_RING_ID_CE6_DST_STATUS,
442 HAL_SRNG_RING_ID_CE7_DST_STATUS,
443 HAL_SRNG_RING_ID_CE8_DST_STATUS,
444 HAL_SRNG_RING_ID_CE9_DST_STATUS,
445 HAL_SRNG_RING_ID_CE10_DST_STATUS,
446 HAL_SRNG_RING_ID_CE11_DST_STATUS,
447 HAL_SRNG_RING_ID_CE12_DST_STATUS,
448 HAL_SRNG_RING_ID_CE13_DST_STATUS,
449 HAL_SRNG_RING_ID_CE14_DST_STATUS,
450 HAL_SRNG_RING_ID_CE15_DST_STATUS,
451
452 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 120,
453 HAL_SRNG_RING_ID_WBM_SW0_RELEASE,
454 HAL_SRNG_RING_ID_WBM_SW1_RELEASE,
455 HAL_SRNG_RING_ID_WBM_PPE_RELEASE = 123,
456
457 HAL_SRNG_RING_ID_WBM2SW0_RELEASE = 128,
458 HAL_SRNG_RING_ID_WBM2SW1_RELEASE,
459 HAL_SRNG_RING_ID_WBM2SW2_RELEASE,
460 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, /* RX ERROR RING */
461 HAL_SRNG_RING_ID_WBM2SW4_RELEASE,
462 HAL_SRNG_RING_ID_WBM2SW5_RELEASE,
463 HAL_SRNG_RING_ID_WBM2SW6_RELEASE,
464 HAL_SRNG_RING_ID_WBM2SW7_RELEASE,
465
466 HAL_SRNG_RING_ID_UMAC_ID_END = 159,
467
468 /* Common DMAC rings shared by all LMACs */
469 HAL_SRNG_RING_ID_DMAC_CMN_ID_START = 160,
470 HAL_SRNG_SW2RXDMA_BUF0 = HAL_SRNG_RING_ID_DMAC_CMN_ID_START,
471 HAL_SRNG_SW2RXDMA_BUF1 = 161,
472 HAL_SRNG_SW2RXDMA_BUF2 = 162,
473
474 HAL_SRNG_SW2RXMON_BUF0 = 168,
475
476 HAL_SRNG_SW2TXMON_BUF0 = 176,
477
478 HAL_SRNG_RING_ID_DMAC_CMN_ID_END = 183,
479 HAL_SRNG_RING_ID_PMAC1_ID_START = 184,
480
481 HAL_SRNG_RING_ID_WMAC1_SW2RXMON_BUF0 = HAL_SRNG_RING_ID_PMAC1_ID_START,
482
483 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0,
484 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1,
485 HAL_SRNG_RING_ID_WMAC1_RXMON2SW0 = HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1,
486 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC,
487 HAL_SRNG_RING_ID_RXDMA_DIR_BUF,
488 HAL_SRNG_RING_ID_WMAC1_SW2TXMON_BUF0,
489 HAL_SRNG_RING_ID_WMAC1_TXMON2SW0_BUF0,
490
491 HAL_SRNG_RING_ID_PMAC1_ID_END,
492 };
493
494 /* SRNG registers are split into two groups R0 and R2 */
495 #define HAL_SRNG_REG_GRP_R0 0
496 #define HAL_SRNG_REG_GRP_R2 1
497 #define HAL_SRNG_NUM_REG_GRP 2
498
499 /* TODO: number of PMACs */
500 #define HAL_SRNG_NUM_PMACS 3
501 #define HAL_SRNG_NUM_DMAC_RINGS (HAL_SRNG_RING_ID_DMAC_CMN_ID_END - \
502 HAL_SRNG_RING_ID_DMAC_CMN_ID_START)
503 #define HAL_SRNG_RINGS_PER_PMAC (HAL_SRNG_RING_ID_PMAC1_ID_END - \
504 HAL_SRNG_RING_ID_PMAC1_ID_START)
505 #define HAL_SRNG_NUM_PMAC_RINGS (HAL_SRNG_NUM_PMACS * HAL_SRNG_RINGS_PER_PMAC)
506 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_DMAC_CMN_ID_END + \
507 HAL_SRNG_NUM_PMAC_RINGS)
508
509 enum hal_ring_type {
510 HAL_REO_DST,
511 HAL_REO_EXCEPTION,
512 HAL_REO_REINJECT,
513 HAL_REO_CMD,
514 HAL_REO_STATUS,
515 HAL_TCL_DATA,
516 HAL_TCL_CMD,
517 HAL_TCL_STATUS,
518 HAL_CE_SRC,
519 HAL_CE_DST,
520 HAL_CE_DST_STATUS,
521 HAL_WBM_IDLE_LINK,
522 HAL_SW2WBM_RELEASE,
523 HAL_WBM2SW_RELEASE,
524 HAL_RXDMA_BUF,
525 HAL_RXDMA_DST,
526 HAL_RXDMA_MONITOR_BUF,
527 HAL_RXDMA_MONITOR_STATUS,
528 HAL_RXDMA_MONITOR_DST,
529 HAL_RXDMA_MONITOR_DESC,
530 HAL_RXDMA_DIR_BUF,
531 HAL_PPE2TCL,
532 HAL_PPE_RELEASE,
533 HAL_TX_MONITOR_BUF,
534 HAL_TX_MONITOR_DST,
535 HAL_MAX_RING_TYPES,
536 };
537
538 #define HAL_RX_MAX_BA_WINDOW 256
539
540 #define HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC (100 * 1000)
541 #define HAL_DEFAULT_VO_REO_TIMEOUT_USEC (40 * 1000)
542
543 /**
544 * enum hal_reo_cmd_type: Enum for REO command type
545 * @HAL_REO_CMD_GET_QUEUE_STATS: Get REO queue status/stats
546 * @HAL_REO_CMD_FLUSH_QUEUE: Flush all frames in REO queue
547 * @HAL_REO_CMD_FLUSH_CACHE: Flush descriptor entries in the cache
548 * @HAL_REO_CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked
549 * earlier with a 'REO_FLUSH_CACHE' command
550 * @HAL_REO_CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
551 * @HAL_REO_CMD_UPDATE_RX_QUEUE: Update REO queue settings
552 */
553 enum hal_reo_cmd_type {
554 HAL_REO_CMD_GET_QUEUE_STATS = 0,
555 HAL_REO_CMD_FLUSH_QUEUE = 1,
556 HAL_REO_CMD_FLUSH_CACHE = 2,
557 HAL_REO_CMD_UNBLOCK_CACHE = 3,
558 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4,
559 HAL_REO_CMD_UPDATE_RX_QUEUE = 5,
560 };
561
562 /**
563 * enum hal_reo_cmd_status: Enum for execution status of REO command
564 * @HAL_REO_CMD_SUCCESS: Command has successfully executed
565 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue
566 * or cache was blocked
567 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to
568 * invalid queue desc
569 * @HAL_REO_CMD_RESOURCE_BLOCKED:
570 * @HAL_REO_CMD_DRAIN:
571 */
572 enum hal_reo_cmd_status {
573 HAL_REO_CMD_SUCCESS = 0,
574 HAL_REO_CMD_BLOCKED = 1,
575 HAL_REO_CMD_FAILED = 2,
576 HAL_REO_CMD_RESOURCE_BLOCKED = 3,
577 HAL_REO_CMD_DRAIN = 0xff,
578 };
579
580 struct hal_wbm_idle_scatter_list {
581 dma_addr_t paddr;
582 struct hal_wbm_link_desc *vaddr;
583 };
584
585 struct hal_srng_params {
586 dma_addr_t ring_base_paddr;
587 u32 *ring_base_vaddr;
588 int num_entries;
589 u32 intr_batch_cntr_thres_entries;
590 u32 intr_timer_thres_us;
591 u32 flags;
592 u32 max_buffer_len;
593 u32 low_threshold;
594 u32 high_threshold;
595 dma_addr_t msi_addr;
596 dma_addr_t msi2_addr;
597 u32 msi_data;
598 u32 msi2_data;
599
600 /* Add more params as needed */
601 };
602
603 enum hal_srng_dir {
604 HAL_SRNG_DIR_SRC,
605 HAL_SRNG_DIR_DST
606 };
607
608 /* srng flags */
609 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008
610 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010
611 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020
612 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000
613 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000
614 #define HAL_SRNG_FLAGS_HIGH_THRESH_INTR_EN 0x00080000
615 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000
616
617 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1)
618 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10)
619
620 /* Common SRNG ring structure for source and destination rings */
621 struct hal_srng {
622 /* Unique SRNG ring ID */
623 u8 ring_id;
624
625 /* Ring initialization done */
626 u8 initialized;
627
628 /* Interrupt/MSI value assigned to this ring */
629 int irq;
630
631 /* Physical base address of the ring */
632 dma_addr_t ring_base_paddr;
633
634 /* Virtual base address of the ring */
635 u32 *ring_base_vaddr;
636
637 /* Number of entries in ring */
638 u32 num_entries;
639
640 /* Ring size */
641 u32 ring_size;
642
643 /* Ring size mask */
644 u32 ring_size_mask;
645
646 /* Size of ring entry */
647 u32 entry_size;
648
649 /* Interrupt timer threshold - in micro seconds */
650 u32 intr_timer_thres_us;
651
652 /* Interrupt batch counter threshold - in number of ring entries */
653 u32 intr_batch_cntr_thres_entries;
654
655 /* MSI Address */
656 dma_addr_t msi_addr;
657
658 /* MSI data */
659 u32 msi_data;
660
661 /* MSI2 Address */
662 dma_addr_t msi2_addr;
663
664 /* MSI2 data */
665 u32 msi2_data;
666
667 /* Misc flags */
668 u32 flags;
669
670 /* Lock for serializing ring index updates */
671 spinlock_t lock;
672
673 struct lock_class_key lock_key;
674
675 /* Start offset of SRNG register groups for this ring
676 * TBD: See if this is required - register address can be derived
677 * from ring ID
678 */
679 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP];
680
681 u64 timestamp;
682
683 /* Source or Destination ring */
684 enum hal_srng_dir ring_dir;
685
686 union {
687 struct {
688 /* SW tail pointer */
689 u32 tp;
690
691 /* Shadow head pointer location to be updated by HW */
692 volatile u32 *hp_addr;
693
694 /* Cached head pointer */
695 u32 cached_hp;
696
697 /* Tail pointer location to be updated by SW - This
698 * will be a register address and need not be
699 * accessed through SW structure
700 */
701 u32 *tp_addr;
702
703 /* Current SW loop cnt */
704 u32 loop_cnt;
705
706 /* max transfer size */
707 u16 max_buffer_length;
708
709 /* head pointer at access end */
710 u32 last_hp;
711 } dst_ring;
712
713 struct {
714 /* SW head pointer */
715 u32 hp;
716
717 /* SW reap head pointer */
718 u32 reap_hp;
719
720 /* Shadow tail pointer location to be updated by HW */
721 u32 *tp_addr;
722
723 /* Cached tail pointer */
724 u32 cached_tp;
725
726 /* Head pointer location to be updated by SW - This
727 * will be a register address and need not be accessed
728 * through SW structure
729 */
730 u32 *hp_addr;
731
732 /* Low threshold - in number of ring entries */
733 u32 low_threshold;
734
735 /* tail pointer at access end */
736 u32 last_tp;
737 } src_ring;
738 } u;
739 };
740
741 /* Interrupt mitigation - Batch threshold in terms of number of frames */
742 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256
743 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128
744 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1
745
746 /* Interrupt mitigation - timer threshold in us */
747 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000
748 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500
749 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256
750
751 enum hal_srng_mac_type {
752 ATH12K_HAL_SRNG_UMAC,
753 ATH12K_HAL_SRNG_DMAC,
754 ATH12K_HAL_SRNG_PMAC
755 };
756
757 /* HW SRNG configuration table */
758 struct hal_srng_config {
759 int start_ring_id;
760 u16 max_rings;
761 u16 entry_size;
762 u32 reg_start[HAL_SRNG_NUM_REG_GRP];
763 u16 reg_size[HAL_SRNG_NUM_REG_GRP];
764 enum hal_srng_mac_type mac_type;
765 enum hal_srng_dir ring_dir;
766 u32 max_size;
767 };
768
769 /**
770 * enum hal_rx_buf_return_buf_manager - manager for returned rx buffers
771 *
772 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list
773 * @HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST: Descriptor returned to WBM idle
774 * descriptor list, where the device 0 WBM is chosen in case of a multi-device config
775 * @HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST: Descriptor returned to WBM idle
776 * descriptor list, where the device 1 WBM is chosen in case of a multi-device config
777 * @HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST: Descriptor returned to WBM idle
778 * descriptor list, where the device 2 WBM is chosen in case of a multi-device config
779 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW
780 * @HAL_RX_BUF_RBM_SW0_BM: For ring 0 -- returned to host
781 * @HAL_RX_BUF_RBM_SW1_BM: For ring 1 -- returned to host
782 * @HAL_RX_BUF_RBM_SW2_BM: For ring 2 -- returned to host
783 * @HAL_RX_BUF_RBM_SW3_BM: For ring 3 -- returned to host
784 * @HAL_RX_BUF_RBM_SW4_BM: For ring 4 -- returned to host
785 * @HAL_RX_BUF_RBM_SW5_BM: For ring 5 -- returned to host
786 * @HAL_RX_BUF_RBM_SW6_BM: For ring 6 -- returned to host
787 */
788
789 enum hal_rx_buf_return_buf_manager {
790 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST,
791 HAL_RX_BUF_RBM_WBM_DEV0_IDLE_DESC_LIST,
792 HAL_RX_BUF_RBM_WBM_DEV1_IDLE_DESC_LIST,
793 HAL_RX_BUF_RBM_WBM_DEV2_IDLE_DESC_LIST,
794 HAL_RX_BUF_RBM_FW_BM,
795 HAL_RX_BUF_RBM_SW0_BM,
796 HAL_RX_BUF_RBM_SW1_BM,
797 HAL_RX_BUF_RBM_SW2_BM,
798 HAL_RX_BUF_RBM_SW3_BM,
799 HAL_RX_BUF_RBM_SW4_BM,
800 HAL_RX_BUF_RBM_SW5_BM,
801 HAL_RX_BUF_RBM_SW6_BM,
802 };
803
804 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000
805
806 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0)
807 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1)
808 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2)
809 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3)
810 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4)
811 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5)
812 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6)
813 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7)
814 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8)
815
816 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* fields */
817 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8)
818 #define HAL_REO_CMD_UPD0_VLD BIT(9)
819 #define HAL_REO_CMD_UPD0_ALDC BIT(10)
820 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11)
821 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12)
822 #define HAL_REO_CMD_UPD0_AC BIT(13)
823 #define HAL_REO_CMD_UPD0_BAR BIT(14)
824 #define HAL_REO_CMD_UPD0_RETRY BIT(15)
825 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16)
826 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17)
827 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18)
828 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19)
829 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20)
830 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21)
831 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22)
832 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23)
833 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24)
834 #define HAL_REO_CMD_UPD0_SVLD BIT(25)
835 #define HAL_REO_CMD_UPD0_SSN BIT(26)
836 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27)
837 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28)
838 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29)
839 #define HAL_REO_CMD_UPD0_PN BIT(30)
840
841 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* fields */
842 #define HAL_REO_CMD_UPD1_VLD BIT(16)
843 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17)
844 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19)
845 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20)
846 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21)
847 #define HAL_REO_CMD_UPD1_BAR BIT(23)
848 #define HAL_REO_CMD_UPD1_RETRY BIT(24)
849 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25)
850 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26)
851 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27)
852 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28)
853 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29)
854 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30)
855 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31)
856
857 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* fields */
858 #define HAL_REO_CMD_UPD2_SVLD BIT(10)
859 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11)
860 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23)
861 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24)
862
863 struct ath12k_hal_reo_cmd {
864 u32 addr_lo;
865 u32 flag;
866 u32 upd0;
867 u32 upd1;
868 u32 upd2;
869 u32 pn[4];
870 u16 rx_queue_num;
871 u16 min_rel;
872 u16 min_fwd;
873 u8 addr_hi;
874 u8 ac_list;
875 u8 blocking_idx;
876 u16 ba_window_size;
877 u8 pn_size;
878 };
879
880 enum hal_pn_type {
881 HAL_PN_TYPE_NONE,
882 HAL_PN_TYPE_WPA,
883 HAL_PN_TYPE_WAPI_EVEN,
884 HAL_PN_TYPE_WAPI_UNEVEN,
885 };
886
887 enum hal_ce_desc {
888 HAL_CE_DESC_SRC,
889 HAL_CE_DESC_DST,
890 HAL_CE_DESC_DST_STATUS,
891 };
892
893 #define HAL_HASH_ROUTING_RING_TCL 0
894 #define HAL_HASH_ROUTING_RING_SW1 1
895 #define HAL_HASH_ROUTING_RING_SW2 2
896 #define HAL_HASH_ROUTING_RING_SW3 3
897 #define HAL_HASH_ROUTING_RING_SW4 4
898 #define HAL_HASH_ROUTING_RING_REL 5
899 #define HAL_HASH_ROUTING_RING_FW 6
900
901 struct hal_reo_status_header {
902 u16 cmd_num;
903 enum hal_reo_cmd_status cmd_status;
904 u16 cmd_exe_time;
905 u32 timestamp;
906 };
907
908 struct hal_reo_status_queue_stats {
909 u16 ssn;
910 u16 curr_idx;
911 u32 pn[4];
912 u32 last_rx_queue_ts;
913 u32 last_rx_dequeue_ts;
914 u32 rx_bitmap[8]; /* Bitmap from 0-255 */
915 u32 curr_mpdu_cnt;
916 u32 curr_msdu_cnt;
917 u16 fwd_due_to_bar_cnt;
918 u16 dup_cnt;
919 u32 frames_in_order_cnt;
920 u32 num_mpdu_processed_cnt;
921 u32 num_msdu_processed_cnt;
922 u32 total_num_processed_byte_cnt;
923 u32 late_rx_mpdu_cnt;
924 u32 reorder_hole_cnt;
925 u8 timeout_cnt;
926 u8 bar_rx_cnt;
927 u8 num_window_2k_jump_cnt;
928 };
929
930 struct hal_reo_status_flush_queue {
931 bool err_detected;
932 };
933
934 enum hal_reo_status_flush_cache_err_code {
935 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS,
936 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE,
937 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND,
938 };
939
940 struct hal_reo_status_flush_cache {
941 bool err_detected;
942 enum hal_reo_status_flush_cache_err_code err_code;
943 bool cache_controller_flush_status_hit;
944 u8 cache_controller_flush_status_desc_type;
945 u8 cache_controller_flush_status_client_id;
946 u8 cache_controller_flush_status_err;
947 u8 cache_controller_flush_status_cnt;
948 };
949
950 enum hal_reo_status_unblock_cache_type {
951 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE,
952 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE,
953 };
954
955 struct hal_reo_status_unblock_cache {
956 bool err_detected;
957 enum hal_reo_status_unblock_cache_type unblock_type;
958 };
959
960 struct hal_reo_status_flush_timeout_list {
961 bool err_detected;
962 bool list_empty;
963 u16 release_desc_cnt;
964 u16 fwd_buf_cnt;
965 };
966
967 enum hal_reo_threshold_idx {
968 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0,
969 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1,
970 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2,
971 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM,
972 };
973
974 struct hal_reo_status_desc_thresh_reached {
975 enum hal_reo_threshold_idx threshold_idx;
976 u32 link_desc_counter0;
977 u32 link_desc_counter1;
978 u32 link_desc_counter2;
979 u32 link_desc_counter_sum;
980 };
981
982 struct hal_reo_status {
983 struct hal_reo_status_header uniform_hdr;
984 u8 loop_cnt;
985 union {
986 struct hal_reo_status_queue_stats queue_stats;
987 struct hal_reo_status_flush_queue flush_queue;
988 struct hal_reo_status_flush_cache flush_cache;
989 struct hal_reo_status_unblock_cache unblock_cache;
990 struct hal_reo_status_flush_timeout_list timeout_list;
991 struct hal_reo_status_desc_thresh_reached desc_thresh_reached;
992 } u;
993 };
994
995 /* HAL context to be used to access SRNG APIs (currently used by data path
996 * and transport (CE) modules)
997 */
998 struct ath12k_hal {
999 /* HAL internal state for all SRNG rings.
1000 */
1001 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX];
1002
1003 /* SRNG configuration table */
1004 struct hal_srng_config *srng_config;
1005
1006 /* Remote pointer memory for HW/FW updates */
1007 struct {
1008 u32 *vaddr;
1009 dma_addr_t paddr;
1010 } rdp;
1011
1012 /* Shared memory for ring pointer updates from host to FW */
1013 struct {
1014 u32 *vaddr;
1015 dma_addr_t paddr;
1016 } wrp;
1017
1018 /* Available REO blocking resources bitmap */
1019 u8 avail_blk_resource;
1020
1021 u8 current_blk_index;
1022
1023 /* shadow register configuration */
1024 u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS];
1025 int num_shadow_reg_configured;
1026
1027 u32 hal_desc_sz;
1028 };
1029
1030 /* Maps WBM ring number and Return Buffer Manager Id per TCL ring */
1031 struct ath12k_hal_tcl_to_wbm_rbm_map {
1032 u8 wbm_ring_num;
1033 u8 rbm_id;
1034 };
1035
1036 struct hal_rx_ops {
1037 bool (*rx_desc_get_first_msdu)(struct hal_rx_desc *desc);
1038 bool (*rx_desc_get_last_msdu)(struct hal_rx_desc *desc);
1039 u8 (*rx_desc_get_l3_pad_bytes)(struct hal_rx_desc *desc);
1040 u8 *(*rx_desc_get_hdr_status)(struct hal_rx_desc *desc);
1041 bool (*rx_desc_encrypt_valid)(struct hal_rx_desc *desc);
1042 u32 (*rx_desc_get_encrypt_type)(struct hal_rx_desc *desc);
1043 u8 (*rx_desc_get_decap_type)(struct hal_rx_desc *desc);
1044 u8 (*rx_desc_get_mesh_ctl)(struct hal_rx_desc *desc);
1045 bool (*rx_desc_get_mpdu_seq_ctl_vld)(struct hal_rx_desc *desc);
1046 bool (*rx_desc_get_mpdu_fc_valid)(struct hal_rx_desc *desc);
1047 u16 (*rx_desc_get_mpdu_start_seq_no)(struct hal_rx_desc *desc);
1048 u16 (*rx_desc_get_msdu_len)(struct hal_rx_desc *desc);
1049 u8 (*rx_desc_get_msdu_sgi)(struct hal_rx_desc *desc);
1050 u8 (*rx_desc_get_msdu_rate_mcs)(struct hal_rx_desc *desc);
1051 u8 (*rx_desc_get_msdu_rx_bw)(struct hal_rx_desc *desc);
1052 u32 (*rx_desc_get_msdu_freq)(struct hal_rx_desc *desc);
1053 u8 (*rx_desc_get_msdu_pkt_type)(struct hal_rx_desc *desc);
1054 u8 (*rx_desc_get_msdu_nss)(struct hal_rx_desc *desc);
1055 u8 (*rx_desc_get_mpdu_tid)(struct hal_rx_desc *desc);
1056 u16 (*rx_desc_get_mpdu_peer_id)(struct hal_rx_desc *desc);
1057 void (*rx_desc_copy_end_tlv)(struct hal_rx_desc *fdesc,
1058 struct hal_rx_desc *ldesc);
1059 u32 (*rx_desc_get_mpdu_start_tag)(struct hal_rx_desc *desc);
1060 u32 (*rx_desc_get_mpdu_ppdu_id)(struct hal_rx_desc *desc);
1061 void (*rx_desc_set_msdu_len)(struct hal_rx_desc *desc, u16 len);
1062 struct rx_attention *(*rx_desc_get_attention)(struct hal_rx_desc *desc);
1063 u8 *(*rx_desc_get_msdu_payload)(struct hal_rx_desc *desc);
1064 u32 (*rx_desc_get_mpdu_start_offset)(void);
1065 u32 (*rx_desc_get_msdu_end_offset)(void);
1066 bool (*rx_desc_mac_addr2_valid)(struct hal_rx_desc *desc);
1067 u8* (*rx_desc_mpdu_start_addr2)(struct hal_rx_desc *desc);
1068 bool (*rx_desc_is_da_mcbc)(struct hal_rx_desc *desc);
1069 void (*rx_desc_get_dot11_hdr)(struct hal_rx_desc *desc,
1070 struct ieee80211_hdr *hdr);
1071 u16 (*rx_desc_get_mpdu_frame_ctl)(struct hal_rx_desc *desc);
1072 void (*rx_desc_get_crypto_header)(struct hal_rx_desc *desc,
1073 u8 *crypto_hdr,
1074 enum hal_encrypt_type enctype);
1075 bool (*dp_rx_h_msdu_done)(struct hal_rx_desc *desc);
1076 bool (*dp_rx_h_l4_cksum_fail)(struct hal_rx_desc *desc);
1077 bool (*dp_rx_h_ip_cksum_fail)(struct hal_rx_desc *desc);
1078 bool (*dp_rx_h_is_decrypted)(struct hal_rx_desc *desc);
1079 u32 (*dp_rx_h_mpdu_err)(struct hal_rx_desc *desc);
1080 u32 (*rx_desc_get_desc_size)(void);
1081 u8 (*rx_desc_get_msdu_src_link_id)(struct hal_rx_desc *desc);
1082 };
1083
1084 struct hal_ops {
1085 int (*create_srng_config)(struct ath12k_base *ab);
1086 u16 (*rxdma_ring_wmask_rx_mpdu_start)(void);
1087 u32 (*rxdma_ring_wmask_rx_msdu_end)(void);
1088 const struct hal_rx_ops *(*get_hal_rx_compact_ops)(void);
1089 const struct ath12k_hal_tcl_to_wbm_rbm_map *tcl_to_wbm_rbm_map;
1090 };
1091
1092 extern const struct hal_ops hal_qcn9274_ops;
1093 extern const struct hal_ops hal_wcn7850_ops;
1094
1095 extern const struct hal_rx_ops hal_rx_qcn9274_ops;
1096 extern const struct hal_rx_ops hal_rx_qcn9274_compact_ops;
1097 extern const struct hal_rx_ops hal_rx_wcn7850_ops;
1098
1099 u32 ath12k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid);
1100 void ath12k_hal_reo_qdesc_setup(struct hal_rx_reo_queue *qdesc,
1101 int tid, u32 ba_window_size,
1102 u32 start_seq, enum hal_pn_type type);
1103 void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab,
1104 struct hal_srng *srng);
1105 void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map);
1106 void ath12k_hal_setup_link_idle_list(struct ath12k_base *ab,
1107 struct hal_wbm_idle_scatter_list *sbuf,
1108 u32 nsbufs, u32 tot_link_desc,
1109 u32 end_offset);
1110
1111 dma_addr_t ath12k_hal_srng_get_tp_addr(struct ath12k_base *ab,
1112 struct hal_srng *srng);
1113 dma_addr_t ath12k_hal_srng_get_hp_addr(struct ath12k_base *ab,
1114 struct hal_srng *srng);
1115 void ath12k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie,
1116 dma_addr_t paddr,
1117 enum hal_rx_buf_return_buf_manager rbm);
1118 u32 ath12k_hal_ce_get_desc_size(enum hal_ce_desc type);
1119 void ath12k_hal_ce_src_set_desc(struct hal_ce_srng_src_desc *desc, dma_addr_t paddr,
1120 u32 len, u32 id, u8 byte_swap_data);
1121 void ath12k_hal_ce_dst_set_desc(struct hal_ce_srng_dest_desc *desc, dma_addr_t paddr);
1122 u32 ath12k_hal_ce_dst_status_get_length(struct hal_ce_srng_dst_status_desc *desc);
1123 int ath12k_hal_srng_get_entrysize(struct ath12k_base *ab, u32 ring_type);
1124 int ath12k_hal_srng_get_max_entries(struct ath12k_base *ab, u32 ring_type);
1125 void ath12k_hal_srng_get_params(struct ath12k_base *ab, struct hal_srng *srng,
1126 struct hal_srng_params *params);
1127 void *ath12k_hal_srng_dst_get_next_entry(struct ath12k_base *ab,
1128 struct hal_srng *srng);
1129 void *ath12k_hal_srng_dst_peek(struct ath12k_base *ab, struct hal_srng *srng);
1130 int ath12k_hal_srng_dst_num_free(struct ath12k_base *ab, struct hal_srng *srng,
1131 bool sync_hw_ptr);
1132 void *ath12k_hal_srng_src_get_next_reaped(struct ath12k_base *ab,
1133 struct hal_srng *srng);
1134 void *ath12k_hal_srng_src_reap_next(struct ath12k_base *ab,
1135 struct hal_srng *srng);
1136 void *ath12k_hal_srng_src_get_next_entry(struct ath12k_base *ab,
1137 struct hal_srng *srng);
1138 int ath12k_hal_srng_src_num_free(struct ath12k_base *ab, struct hal_srng *srng,
1139 bool sync_hw_ptr);
1140 void ath12k_hal_srng_access_begin(struct ath12k_base *ab,
1141 struct hal_srng *srng);
1142 void ath12k_hal_srng_access_end(struct ath12k_base *ab, struct hal_srng *srng);
1143 int ath12k_hal_srng_setup(struct ath12k_base *ab, enum hal_ring_type type,
1144 int ring_num, int mac_id,
1145 struct hal_srng_params *params);
1146 int ath12k_hal_srng_init(struct ath12k_base *ath12k);
1147 void ath12k_hal_srng_deinit(struct ath12k_base *ath12k);
1148 void ath12k_hal_dump_srng_stats(struct ath12k_base *ab);
1149 void ath12k_hal_srng_get_shadow_config(struct ath12k_base *ab,
1150 u32 **cfg, u32 *len);
1151 int ath12k_hal_srng_update_shadow_config(struct ath12k_base *ab,
1152 enum hal_ring_type ring_type,
1153 int ring_num);
1154 void ath12k_hal_srng_shadow_config(struct ath12k_base *ab);
1155 void ath12k_hal_srng_shadow_update_hp_tp(struct ath12k_base *ab,
1156 struct hal_srng *srng);
1157 #endif
Kernel DRM miscellaneous fixes and cross-tree changes