drivers/net/wireless/ath/ath12k/hal_rx.h

   1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2 /*
   3  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved.
   5  */
   6
   7 #ifndef ATH12K_HAL_RX_H
   8 #define ATH12K_HAL_RX_H
   9
  10 struct hal_rx_wbm_rel_info {
  11         u32 cookie;
  12         enum hal_wbm_rel_src_module err_rel_src;
  13         enum hal_reo_dest_ring_push_reason push_reason;
  14         u32 err_code;
  15         bool first_msdu;
  16         bool last_msdu;
  17         bool continuation;
  18         void *rx_desc;
  19         bool hw_cc_done;
  20 };
  21
  22 #define HAL_INVALID_PEERID 0xffff
  23 #define VHT_SIG_SU_NSS_MASK 0x7
  24
  25 #define HAL_RX_MAX_MCS 12
  26 #define HAL_RX_MAX_NSS 8
  27
  28 #define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) \
  29         le32_get_bits((__val), GENMASK(7, 0))
  30
  31 #define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) \
  32         le32_get_bits((__val), GENMASK(15, 8))
  33
  34 #define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) \
  35         le32_get_bits((__val), GENMASK(23, 16))
  36
  37 #define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) \
  38         le32_get_bits((__val), GENMASK(31, 24))
  39
  40 struct hal_rx_mon_status_tlv_hdr {
  41         u32 hdr;
  42         u8 value[];
  43 };
  44
  45 enum hal_rx_su_mu_coding {
  46         HAL_RX_SU_MU_CODING_BCC,
  47         HAL_RX_SU_MU_CODING_LDPC,
  48         HAL_RX_SU_MU_CODING_MAX,
  49 };
  50
  51 enum hal_rx_gi {
  52         HAL_RX_GI_0_8_US,
  53         HAL_RX_GI_0_4_US,
  54         HAL_RX_GI_1_6_US,
  55         HAL_RX_GI_3_2_US,
  56         HAL_RX_GI_MAX,
  57 };
  58
  59 enum hal_rx_bw {
  60         HAL_RX_BW_20MHZ,
  61         HAL_RX_BW_40MHZ,
  62         HAL_RX_BW_80MHZ,
  63         HAL_RX_BW_160MHZ,
  64         HAL_RX_BW_320MHZ,
  65         HAL_RX_BW_MAX,
  66 };
  67
  68 enum hal_rx_preamble {
  69         HAL_RX_PREAMBLE_11A,
  70         HAL_RX_PREAMBLE_11B,
  71         HAL_RX_PREAMBLE_11N,
  72         HAL_RX_PREAMBLE_11AC,
  73         HAL_RX_PREAMBLE_11AX,
  74         HAL_RX_PREAMBLE_MAX,
  75 };
  76
  77 enum hal_rx_reception_type {
  78         HAL_RX_RECEPTION_TYPE_SU,
  79         HAL_RX_RECEPTION_TYPE_MU_MIMO,
  80         HAL_RX_RECEPTION_TYPE_MU_OFDMA,
  81         HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
  82         HAL_RX_RECEPTION_TYPE_MAX,
  83 };
  84
  85 enum hal_rx_legacy_rate {
  86         HAL_RX_LEGACY_RATE_1_MBPS,
  87         HAL_RX_LEGACY_RATE_2_MBPS,
  88         HAL_RX_LEGACY_RATE_5_5_MBPS,
  89         HAL_RX_LEGACY_RATE_6_MBPS,
  90         HAL_RX_LEGACY_RATE_9_MBPS,
  91         HAL_RX_LEGACY_RATE_11_MBPS,
  92         HAL_RX_LEGACY_RATE_12_MBPS,
  93         HAL_RX_LEGACY_RATE_18_MBPS,
  94         HAL_RX_LEGACY_RATE_24_MBPS,
  95         HAL_RX_LEGACY_RATE_36_MBPS,
  96         HAL_RX_LEGACY_RATE_48_MBPS,
  97         HAL_RX_LEGACY_RATE_54_MBPS,
  98         HAL_RX_LEGACY_RATE_INVALID,
  99 };
 100
 101 #define HAL_TLV_STATUS_PPDU_NOT_DONE            0
 102 #define HAL_TLV_STATUS_PPDU_DONE                1
 103 #define HAL_TLV_STATUS_BUF_DONE                 2
 104 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE        3
 105 #define HAL_RX_FCS_LEN                          4
 106
 107 enum hal_rx_mon_status {
 108         HAL_RX_MON_STATUS_PPDU_NOT_DONE,
 109         HAL_RX_MON_STATUS_PPDU_DONE,
 110         HAL_RX_MON_STATUS_BUF_DONE,
 111 };
 112
 113 #define HAL_RX_MAX_MPDU         256
 114 #define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP        (HAL_RX_MAX_MPDU >> 5)
 115
 116 struct hal_rx_user_status {
 117         u32 mcs:4,
 118         nss:3,
 119         ofdma_info_valid:1,
 120         ul_ofdma_ru_start_index:7,
 121         ul_ofdma_ru_width:7,
 122         ul_ofdma_ru_size:8;
 123         u32 ul_ofdma_user_v0_word0;
 124         u32 ul_ofdma_user_v0_word1;
 125         u32 ast_index;
 126         u32 tid;
 127         u16 tcp_msdu_count;
 128         u16 tcp_ack_msdu_count;
 129         u16 udp_msdu_count;
 130         u16 other_msdu_count;
 131         u16 frame_control;
 132         u8 frame_control_info_valid;
 133         u8 data_sequence_control_info_valid;
 134         u16 first_data_seq_ctrl;
 135         u32 preamble_type;
 136         u16 ht_flags;
 137         u16 vht_flags;
 138         u16 he_flags;
 139         u8 rs_flags;
 140         u8 ldpc;
 141         u32 mpdu_cnt_fcs_ok;
 142         u32 mpdu_cnt_fcs_err;
 143         u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
 144         u32 mpdu_ok_byte_count;
 145         u32 mpdu_err_byte_count;
 146 };
 147
 148 #define HAL_MAX_UL_MU_USERS     37
 149
 150 struct hal_rx_mon_ppdu_info {
 151         u32 ppdu_id;
 152         u32 last_ppdu_id;
 153         u64 ppdu_ts;
 154         u32 num_mpdu_fcs_ok;
 155         u32 num_mpdu_fcs_err;
 156         u32 preamble_type;
 157         u32 mpdu_len;
 158         u16 chan_num;
 159         u16 freq;
 160         u16 tcp_msdu_count;
 161         u16 tcp_ack_msdu_count;
 162         u16 udp_msdu_count;
 163         u16 other_msdu_count;
 164         u16 peer_id;
 165         u8 rate;
 166         u8 mcs;
 167         u8 nss;
 168         u8 bw;
 169         u8 vht_flag_values1;
 170         u8 vht_flag_values2;
 171         u8 vht_flag_values3[4];
 172         u8 vht_flag_values4;
 173         u8 vht_flag_values5;
 174         u16 vht_flag_values6;
 175         u8 is_stbc;
 176         u8 gi;
 177         u8 sgi;
 178         u8 ldpc;
 179         u8 beamformed;
 180         u8 rssi_comb;
 181         u16 tid;
 182         u8 fc_valid;
 183         u16 ht_flags;
 184         u16 vht_flags;
 185         u16 he_flags;
 186         u16 he_mu_flags;
 187         u8 dcm;
 188         u8 ru_alloc;
 189         u8 reception_type;
 190         u64 tsft;
 191         u64 rx_duration;
 192         u16 frame_control;
 193         u32 ast_index;
 194         u8 rs_fcs_err;
 195         u8 rs_flags;
 196         u8 cck_flag;
 197         u8 ofdm_flag;
 198         u8 ulofdma_flag;
 199         u8 frame_control_info_valid;
 200         u16 he_per_user_1;
 201         u16 he_per_user_2;
 202         u8 he_per_user_position;
 203         u8 he_per_user_known;
 204         u16 he_flags1;
 205         u16 he_flags2;
 206         u8 he_RU[4];
 207         u16 he_data1;
 208         u16 he_data2;
 209         u16 he_data3;
 210         u16 he_data4;
 211         u16 he_data5;
 212         u16 he_data6;
 213         u32 ppdu_len;
 214         u32 prev_ppdu_id;
 215         u32 device_id;
 216         u16 first_data_seq_ctrl;
 217         u8 monitor_direct_used;
 218         u8 data_sequence_control_info_valid;
 219         u8 ltf_size;
 220         u8 rxpcu_filter_pass;
 221         s8 rssi_chain[8][8];
 222         u32 num_users;
 223         u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
 224         u8 addr1[ETH_ALEN];
 225         u8 addr2[ETH_ALEN];
 226         u8 addr3[ETH_ALEN];
 227         u8 addr4[ETH_ALEN];
 228         struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS];
 229         u8 userid;
 230         u16 ampdu_id[HAL_MAX_UL_MU_USERS];
 231         bool first_msdu_in_mpdu;
 232         bool is_ampdu;
 233         u8 medium_prot_type;
 234 };
 235
 236 #define HAL_RX_PPDU_START_INFO0_PPDU_ID                 GENMASK(15, 0)
 237 #define HAL_RX_PPDU_START_INFO1_CHAN_NUM                GENMASK(15, 0)
 238 #define HAL_RX_PPDU_START_INFO1_CHAN_FREQ               GENMASK(31, 16)
 239
 240 struct hal_rx_ppdu_start {
 241         __le32 info0;
 242         __le32 info1;
 243         __le32 ppdu_start_ts_31_0;
 244         __le32 ppdu_start_ts_63_32;
 245         __le32 rsvd[2];
 246 } __packed;
 247
 248 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR       GENMASK(26, 16)
 249
 250 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK        GENMASK(10, 0)
 251 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID               BIT(11)
 252 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID         BIT(12)
 253 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID          BIT(13)
 254 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE              GENMASK(24, 21)
 255
 256 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX              GENMASK(15, 0)
 257 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL             GENMASK(31, 16)
 258
 259 #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL               GENMASK(31, 16)
 260
 261 #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT           GENMASK(15, 0)
 262 #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT           GENMASK(31, 16)
 263
 264 #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT         GENMASK(15, 0)
 265 #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT       GENMASK(31, 16)
 266
 267 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP             GENMASK(15, 0)
 268 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP        GENMASK(31, 16)
 269
 270 #define HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT    GENMASK(24, 0)
 271 #define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT   GENMASK(24, 0)
 272
 273 struct hal_rx_ppdu_end_user_stats {
 274         __le32 rsvd0[2];
 275         __le32 info0;
 276         __le32 info1;
 277         __le32 info2;
 278         __le32 info3;
 279         __le32 ht_ctrl;
 280         __le32 rsvd1[2];
 281         __le32 info4;
 282         __le32 info5;
 283         __le32 usr_resp_ref;
 284         __le32 info6;
 285         __le32 rsvd3[4];
 286         __le32 info7;
 287         __le32 rsvd4;
 288         __le32 info8;
 289         __le32 rsvd5[2];
 290         __le32 usr_resp_ref_ext;
 291         __le32 rsvd6;
 292 } __packed;
 293
 294 struct hal_rx_ppdu_end_user_stats_ext {
 295         __le32 info0;
 296         __le32 info1;
 297         __le32 info2;
 298         __le32 info3;
 299         __le32 info4;
 300         __le32 info5;
 301         __le32 info6;
 302 } __packed;
 303
 304 #define HAL_RX_HT_SIG_INFO_INFO0_MCS            GENMASK(6, 0)
 305 #define HAL_RX_HT_SIG_INFO_INFO0_BW             BIT(7)
 306
 307 #define HAL_RX_HT_SIG_INFO_INFO1_STBC           GENMASK(5, 4)
 308 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING     BIT(6)
 309 #define HAL_RX_HT_SIG_INFO_INFO1_GI             BIT(7)
 310
 311 struct hal_rx_ht_sig_info {
 312         __le32 info0;
 313         __le32 info1;
 314 } __packed;
 315
 316 #define HAL_RX_LSIG_B_INFO_INFO0_RATE   GENMASK(3, 0)
 317 #define HAL_RX_LSIG_B_INFO_INFO0_LEN    GENMASK(15, 4)
 318
 319 struct hal_rx_lsig_b_info {
 320         __le32 info0;
 321 } __packed;
 322
 323 #define HAL_RX_LSIG_A_INFO_INFO0_RATE           GENMASK(3, 0)
 324 #define HAL_RX_LSIG_A_INFO_INFO0_LEN            GENMASK(16, 5)
 325 #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE       GENMASK(27, 24)
 326
 327 struct hal_rx_lsig_a_info {
 328         __le32 info0;
 329 } __packed;
 330
 331 #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW          GENMASK(1, 0)
 332 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC        BIT(3)
 333 #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID    GENMASK(9, 4)
 334 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS        GENMASK(21, 10)
 335
 336 #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING          GENMASK(1, 0)
 337 #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING        BIT(2)
 338 #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS                 GENMASK(7, 4)
 339 #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED          BIT(8)
 340
 341 struct hal_rx_vht_sig_a_info {
 342         __le32 info0;
 343         __le32 info1;
 344 } __packed;
 345
 346 enum hal_rx_vht_sig_a_gi_setting {
 347         HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
 348         HAL_RX_VHT_SIG_A_SHORT_GI = 1,
 349         HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
 350 };
 351
 352 #define HE_GI_0_8 0
 353 #define HE_GI_0_4 1
 354 #define HE_GI_1_6 2
 355 #define HE_GI_3_2 3
 356
 357 #define HE_LTF_1_X 0
 358 #define HE_LTF_2_X 1
 359 #define HE_LTF_4_X 2
 360
 361 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS      GENMASK(6, 3)
 362 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM               BIT(7)
 363 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW       GENMASK(20, 19)
 364 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE       GENMASK(22, 21)
 365 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS              GENMASK(25, 23)
 366 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR         GENMASK(13, 8)
 367 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE     GENMASK(18, 15)
 368 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND        BIT(0)
 369 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE       BIT(1)
 370 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG        BIT(2)
 371
 372 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION     GENMASK(6, 0)
 373 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING            BIT(7)
 374 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA        BIT(8)
 375 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC              BIT(9)
 376 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF              BIT(10)
 377 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR    GENMASK(12, 11)
 378 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM  BIT(13)
 379 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND       BIT(15)
 380
 381 struct hal_rx_he_sig_a_su_info {
 382         __le32 info0;
 383         __le32 info1;
 384 } __packed;
 385
 386 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG             BIT(1)
 387 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB         GENMASK(3, 1)
 388 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB         BIT(4)
 389 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR           GENMASK(10, 5)
 390 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE       GENMASK(14, 11)
 391 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW         GENMASK(17, 15)
 392 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB       GENMASK(21, 18)
 393 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB      BIT(22)
 394 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE         GENMASK(24, 23)
 395 #define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION  BIT(25)
 396
 397 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION       GENMASK(6, 0)
 398 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_CODING              BIT(7)
 399 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB        GENMASK(10, 8)
 400 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA          BIT(11)
 401 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC                BIT(12)
 402 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXBF                BIT(10)
 403 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR      GENMASK(14, 13)
 404 #define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM    BIT(15)
 405
 406 struct hal_rx_he_sig_a_mu_dl_info {
 407         __le32 info0;
 408         __le32 info1;
 409 } __packed;
 410
 411 #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION    GENMASK(7, 0)
 412
 413 struct hal_rx_he_sig_b1_mu_info {
 414         __le32 info0;
 415 } __packed;
 416
 417 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID           GENMASK(10, 0)
 418 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS          GENMASK(18, 15)
 419 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING       BIT(20)
 420 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS         GENMASK(31, 29)
 421
 422 struct hal_rx_he_sig_b2_mu_info {
 423         __le32 info0;
 424 } __packed;
 425
 426 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID        GENMASK(10, 0)
 427 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS      GENMASK(13, 11)
 428 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF      BIT(19)
 429 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS       GENMASK(18, 15)
 430 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM       BIT(19)
 431 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING    BIT(20)
 432
 433 struct hal_rx_he_sig_b2_ofdma_info {
 434         __le32 info0;
 435 } __packed;
 436
 437 enum hal_rx_ul_reception_type {
 438         HAL_RECEPTION_TYPE_ULOFMDA,
 439         HAL_RECEPTION_TYPE_ULMIMO,
 440         HAL_RECEPTION_TYPE_OTHER,
 441         HAL_RECEPTION_TYPE_FRAMELESS
 442 };
 443
 444 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RECEPTION   GENMASK(3, 0)
 445 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RX_BW       GENMASK(7, 5)
 446 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB   GENMASK(15, 8)
 447
 448 struct hal_rx_phyrx_rssi_legacy_info {
 449         __le32 info0;
 450         __le32 rsvd0[39];
 451         __le32 info1;
 452         __le32 rsvd1;
 453 } __packed;
 454
 455 #define HAL_RX_MPDU_START_INFO0_PPDU_ID                 GENMASK(31, 16)
 456 #define HAL_RX_MPDU_START_INFO1_PEERID                  GENMASK(31, 16)
 457 #define HAL_RX_MPDU_START_INFO2_MPDU_LEN                GENMASK(13, 0)
 458 struct hal_rx_mpdu_start {
 459         __le32 rsvd0[9];
 460         __le32 info0;
 461         __le32 info1;
 462         __le32 rsvd1[2];
 463         __le32 info2;
 464         __le32 rsvd2[16];
 465 } __packed;
 466
 467 #define HAL_RX_PPDU_END_DURATION        GENMASK(23, 0)
 468 struct hal_rx_ppdu_end_duration {
 469         __le32 rsvd0[9];
 470         __le32 info0;
 471         __le32 rsvd1[4];
 472 } __packed;
 473
 474 struct hal_rx_rxpcu_classification_overview {
 475         u32 rsvd0;
 476 } __packed;
 477
 478 struct hal_rx_msdu_desc_info {
 479         u32 msdu_flags;
 480         u16 msdu_len; /* 14 bits for length */
 481 };
 482
 483 #define HAL_RX_NUM_MSDU_DESC 6
 484 struct hal_rx_msdu_list {
 485         struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
 486         u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
 487         u8 rbm[HAL_RX_NUM_MSDU_DESC];
 488 };
 489
 490 #define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0         GENMASK(31, 0)
 491 #define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32        GENMASK(15, 0)
 492 #define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0         GENMASK(31, 16)
 493 #define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16        GENMASK(31, 0)
 494
 495 struct hal_rx_frame_bitmap_ack {
 496         __le32 reserved;
 497         __le32 info0;
 498         __le32 info1;
 499         __le32 info2;
 500         __le32 reserved1[10];
 501 } __packed;
 502
 503 #define HAL_RX_RESP_REQ_INFO0_PPDU_ID           GENMASK(15, 0)
 504 #define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE    BIT(16)
 505 #define HAL_RX_RESP_REQ_INFO1_DURATION          GENMASK(15, 0)
 506 #define HAL_RX_RESP_REQ_INFO1_RATE_MCS          GENMASK(24, 21)
 507 #define HAL_RX_RESP_REQ_INFO1_SGI               GENMASK(26, 25)
 508 #define HAL_RX_RESP_REQ_INFO1_STBC              BIT(27)
 509 #define HAL_RX_RESP_REQ_INFO1_LDPC              BIT(28)
 510 #define HAL_RX_RESP_REQ_INFO1_IS_AMPDU          BIT(29)
 511 #define HAL_RX_RESP_REQ_INFO2_NUM_USER          GENMASK(6, 0)
 512 #define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0        GENMASK(31, 0)
 513 #define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32       GENMASK(15, 0)
 514 #define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0        GENMASK(31, 16)
 515 #define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16       GENMASK(31, 0)
 516
 517 struct hal_rx_resp_req_info {
 518         __le32 info0;
 519         __le32 reserved[1];
 520         __le32 info1;
 521         __le32 info2;
 522         __le32 reserved1[2];
 523         __le32 info3;
 524         __le32 info4;
 525         __le32 info5;
 526         __le32 reserved2[5];
 527 } __packed;
 528
 529 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
 530 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
 531 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
 532 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
 533
 534 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID           BIT(30)
 535 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER             BIT(31)
 536 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS             GENMASK(2, 0)
 537 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS             GENMASK(6, 3)
 538 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC            BIT(7)
 539 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM             BIT(8)
 540 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START        GENMASK(15, 9)
 541 #define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE         GENMASK(18, 16)
 542
 543 /* HE Radiotap data1 Mask */
 544 #define HE_SU_FORMAT_TYPE 0x0000
 545 #define HE_EXT_SU_FORMAT_TYPE 0x0001
 546 #define HE_MU_FORMAT_TYPE  0x0002
 547 #define HE_TRIG_FORMAT_TYPE  0x0003
 548 #define HE_BEAM_CHANGE_KNOWN 0x0008
 549 #define HE_DL_UL_KNOWN 0x0010
 550 #define HE_MCS_KNOWN 0x0020
 551 #define HE_DCM_KNOWN 0x0040
 552 #define HE_CODING_KNOWN 0x0080
 553 #define HE_LDPC_EXTRA_SYMBOL_KNOWN 0x0100
 554 #define HE_STBC_KNOWN 0x0200
 555 #define HE_DATA_BW_RU_KNOWN 0x4000
 556 #define HE_DOPPLER_KNOWN 0x8000
 557 #define HE_BSS_COLOR_KNOWN 0x0004
 558
 559 /* HE Radiotap data2 Mask */
 560 #define HE_GI_KNOWN 0x0002
 561 #define HE_TXBF_KNOWN 0x0010
 562 #define HE_PE_DISAMBIGUITY_KNOWN 0x0020
 563 #define HE_TXOP_KNOWN 0x0040
 564 #define HE_LTF_SYMBOLS_KNOWN 0x0004
 565 #define HE_PRE_FEC_PADDING_KNOWN 0x0008
 566 #define HE_MIDABLE_PERIODICITY_KNOWN 0x0080
 567
 568 /* HE radiotap data3 shift values */
 569 #define HE_BEAM_CHANGE_SHIFT 6
 570 #define HE_DL_UL_SHIFT 7
 571 #define HE_TRANSMIT_MCS_SHIFT 8
 572 #define HE_DCM_SHIFT 12
 573 #define HE_CODING_SHIFT 13
 574 #define HE_LDPC_EXTRA_SYMBOL_SHIFT 14
 575 #define HE_STBC_SHIFT 15
 576
 577 /* HE radiotap data4 shift values */
 578 #define HE_STA_ID_SHIFT 4
 579
 580 /* HE radiotap data5 */
 581 #define HE_GI_SHIFT 4
 582 #define HE_LTF_SIZE_SHIFT 6
 583 #define HE_LTF_SYM_SHIFT 8
 584 #define HE_TXBF_SHIFT 14
 585 #define HE_PE_DISAMBIGUITY_SHIFT 15
 586 #define HE_PRE_FEC_PAD_SHIFT 12
 587
 588 /* HE radiotap data6 */
 589 #define HE_DOPPLER_SHIFT 4
 590 #define HE_TXOP_SHIFT 8
 591
 592 /* HE radiotap HE-MU flags1 */
 593 #define HE_SIG_B_MCS_KNOWN 0x0010
 594 #define HE_SIG_B_DCM_KNOWN 0x0040
 595 #define HE_SIG_B_SYM_NUM_KNOWN 0x8000
 596 #define HE_RU_0_KNOWN 0x0100
 597 #define HE_RU_1_KNOWN 0x0200
 598 #define HE_RU_2_KNOWN 0x0400
 599 #define HE_RU_3_KNOWN 0x0800
 600 #define HE_DCM_FLAG_1_SHIFT 5
 601 #define HE_SPATIAL_REUSE_MU_KNOWN 0x0100
 602 #define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN 0x4000
 603
 604 /* HE radiotap HE-MU flags2 */
 605 #define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT 3
 606 #define HE_BW_KNOWN 0x0004
 607 #define HE_NUM_SIG_B_SYMBOLS_SHIFT 4
 608 #define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN 0x0100
 609 #define HE_NUM_SIG_B_FLAG_2_SHIFT 9
 610 #define HE_LTF_FLAG_2_SYMBOLS_SHIFT 12
 611 #define HE_LTF_KNOWN 0x8000
 612
 613 /* HE radiotap per_user_1 */
 614 #define HE_STA_SPATIAL_SHIFT 11
 615 #define HE_TXBF_SHIFT 14
 616 #define HE_RESERVED_SET_TO_1_SHIFT 19
 617 #define HE_STA_CODING_SHIFT 20
 618
 619 /* HE radiotap per_user_2 */
 620 #define HE_STA_MCS_SHIFT 4
 621 #define HE_STA_DCM_SHIFT 5
 622
 623 /* HE radiotap per user known */
 624 #define HE_USER_FIELD_POSITION_KNOWN 0x01
 625 #define HE_STA_ID_PER_USER_KNOWN 0x02
 626 #define HE_STA_NSTS_KNOWN 0x04
 627 #define HE_STA_TX_BF_KNOWN 0x08
 628 #define HE_STA_SPATIAL_CONFIG_KNOWN 0x10
 629 #define HE_STA_MCS_KNOWN 0x20
 630 #define HE_STA_DCM_KNOWN 0x40
 631 #define HE_STA_CODING_KNOWN 0x80
 632
 633 #define HAL_RX_MPDU_ERR_FCS                     BIT(0)
 634 #define HAL_RX_MPDU_ERR_DECRYPT                 BIT(1)
 635 #define HAL_RX_MPDU_ERR_TKIP_MIC                BIT(2)
 636 #define HAL_RX_MPDU_ERR_AMSDU_ERR               BIT(3)
 637 #define HAL_RX_MPDU_ERR_OVERFLOW                BIT(4)
 638 #define HAL_RX_MPDU_ERR_MSDU_LEN                BIT(5)
 639 #define HAL_RX_MPDU_ERR_MPDU_LEN                BIT(6)
 640 #define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME       BIT(7)
 641
 642 static inline
 643 enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)
 644 {
 645         enum nl80211_he_ru_alloc ret;
 646
 647         switch (ru_tones) {
 648         case RU_52:
 649                 ret = NL80211_RATE_INFO_HE_RU_ALLOC_52;
 650                 break;
 651         case RU_106:
 652                 ret = NL80211_RATE_INFO_HE_RU_ALLOC_106;
 653                 break;
 654         case RU_242:
 655                 ret = NL80211_RATE_INFO_HE_RU_ALLOC_242;
 656                 break;
 657         case RU_484:
 658                 ret = NL80211_RATE_INFO_HE_RU_ALLOC_484;
 659                 break;
 660         case RU_996:
 661                 ret = NL80211_RATE_INFO_HE_RU_ALLOC_996;
 662                 break;
 663         case RU_26:
 664                 fallthrough;
 665         default:
 666                 ret = NL80211_RATE_INFO_HE_RU_ALLOC_26;
 667                 break;
 668         }
 669         return ret;
 670 }
 671
 672 void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab,
 673                                        struct hal_tlv_64_hdr *tlv,
 674                                        struct hal_reo_status *status);
 675 void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab,
 676                                        struct hal_tlv_64_hdr *tlv,
 677                                        struct hal_reo_status *status);
 678 void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab,
 679                                        struct hal_tlv_64_hdr *tlv,
 680                                        struct hal_reo_status *status);
 681 void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab,
 682                                        struct hal_tlv_64_hdr *tlv,
 683                                        struct hal_reo_status *status);
 684 void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab,
 685                                               struct hal_tlv_64_hdr *tlv,
 686                                               struct hal_reo_status *status);
 687 void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab,
 688                                                struct hal_tlv_64_hdr *tlv,
 689                                                struct hal_reo_status *status);
 690 void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab,
 691                                                struct hal_tlv_64_hdr *tlv,
 692                                                struct hal_reo_status *status);
 693 void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus,
 694                                       u32 *msdu_cookies,
 695                                       enum hal_rx_buf_return_buf_manager *rbm);
 696 void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab,
 697                                       struct hal_wbm_release_ring *dst_desc,
 698                                       struct hal_wbm_release_ring *src_desc,
 699                                       enum hal_wbm_rel_bm_act action);
 700 void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo,
 701                                      dma_addr_t paddr, u32 cookie, u8 manager);
 702 void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo,
 703                                      dma_addr_t *paddr,
 704                                      u32 *cookie, u8 *rbm);
 705 int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab,
 706                                   struct hal_reo_dest_ring *desc,
 707                                   dma_addr_t *paddr, u32 *desc_bank);
 708 int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc,
 709                                   struct hal_rx_wbm_rel_info *rel_info);
 710 void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab,
 711                                      struct ath12k_buffer_addr *buff_addr,
 712                                      dma_addr_t *paddr, u32 *cookie);
 713
 714 #endif