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accel/ivpu: Move recovery work to system_unbound_wq
[drm/drm-misc.git] / drivers / net / wireless / ath / ath9k / ar9003_phy.c
blob6274d1624261424cee157ee01e5465b95454bb72
1 /*
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/export.h>
18 #include "hw.h"
19 #include "ar9003_phy.h"
20 #include "ar9003_eeprom.h"
21
22 #define AR9300_OFDM_RATES 8
23 #define AR9300_HT_SS_RATES 8
24 #define AR9300_HT_DS_RATES 8
25 #define AR9300_HT_TS_RATES 8
26
27 #define AR9300_11NA_OFDM_SHIFT 0
28 #define AR9300_11NA_HT_SS_SHIFT 8
29 #define AR9300_11NA_HT_DS_SHIFT 16
30 #define AR9300_11NA_HT_TS_SHIFT 24
31
32 #define AR9300_11NG_OFDM_SHIFT 4
33 #define AR9300_11NG_HT_SS_SHIFT 12
34 #define AR9300_11NG_HT_DS_SHIFT 20
35 #define AR9300_11NG_HT_TS_SHIFT 28
36
37 static const int firstep_table[] =
38 /* level: 0 1 2 3 4 5 6 7 8 */
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
40
41 static const int cycpwrThr1_table[] =
42 /* level: 0 1 2 3 4 5 6 7 8 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
44
45 /*
46 * register values to turn OFDM weak signal detection OFF
47 */
48 static const int m1ThreshLow_off = 127;
49 static const int m2ThreshLow_off = 127;
50 static const int m1Thresh_off = 127;
51 static const int m2Thresh_off = 127;
52 static const int m2CountThr_off = 31;
53 static const int m2CountThrLow_off = 63;
54 static const int m1ThreshLowExt_off = 127;
55 static const int m2ThreshLowExt_off = 127;
56 static const int m1ThreshExt_off = 127;
57 static const int m2ThreshExt_off = 127;
58
59 static const u8 ofdm2pwr[] = {
60 ALL_TARGET_LEGACY_6_24,
61 ALL_TARGET_LEGACY_6_24,
62 ALL_TARGET_LEGACY_6_24,
63 ALL_TARGET_LEGACY_6_24,
64 ALL_TARGET_LEGACY_6_24,
65 ALL_TARGET_LEGACY_36,
66 ALL_TARGET_LEGACY_48,
67 ALL_TARGET_LEGACY_54
68 };
69
70 static const u8 mcs2pwr_ht20[] = {
71 ALL_TARGET_HT20_0_8_16,
72 ALL_TARGET_HT20_1_3_9_11_17_19,
73 ALL_TARGET_HT20_1_3_9_11_17_19,
74 ALL_TARGET_HT20_1_3_9_11_17_19,
75 ALL_TARGET_HT20_4,
76 ALL_TARGET_HT20_5,
77 ALL_TARGET_HT20_6,
78 ALL_TARGET_HT20_7,
79 ALL_TARGET_HT20_0_8_16,
80 ALL_TARGET_HT20_1_3_9_11_17_19,
81 ALL_TARGET_HT20_1_3_9_11_17_19,
82 ALL_TARGET_HT20_1_3_9_11_17_19,
83 ALL_TARGET_HT20_12,
84 ALL_TARGET_HT20_13,
85 ALL_TARGET_HT20_14,
86 ALL_TARGET_HT20_15,
87 ALL_TARGET_HT20_0_8_16,
88 ALL_TARGET_HT20_1_3_9_11_17_19,
89 ALL_TARGET_HT20_1_3_9_11_17_19,
90 ALL_TARGET_HT20_1_3_9_11_17_19,
91 ALL_TARGET_HT20_20,
92 ALL_TARGET_HT20_21,
93 ALL_TARGET_HT20_22,
94 ALL_TARGET_HT20_23
95 };
96
97 static const u8 mcs2pwr_ht40[] = {
98 ALL_TARGET_HT40_0_8_16,
99 ALL_TARGET_HT40_1_3_9_11_17_19,
100 ALL_TARGET_HT40_1_3_9_11_17_19,
101 ALL_TARGET_HT40_1_3_9_11_17_19,
102 ALL_TARGET_HT40_4,
103 ALL_TARGET_HT40_5,
104 ALL_TARGET_HT40_6,
105 ALL_TARGET_HT40_7,
106 ALL_TARGET_HT40_0_8_16,
107 ALL_TARGET_HT40_1_3_9_11_17_19,
108 ALL_TARGET_HT40_1_3_9_11_17_19,
109 ALL_TARGET_HT40_1_3_9_11_17_19,
110 ALL_TARGET_HT40_12,
111 ALL_TARGET_HT40_13,
112 ALL_TARGET_HT40_14,
113 ALL_TARGET_HT40_15,
114 ALL_TARGET_HT40_0_8_16,
115 ALL_TARGET_HT40_1_3_9_11_17_19,
116 ALL_TARGET_HT40_1_3_9_11_17_19,
117 ALL_TARGET_HT40_1_3_9_11_17_19,
118 ALL_TARGET_HT40_20,
119 ALL_TARGET_HT40_21,
120 ALL_TARGET_HT40_22,
121 ALL_TARGET_HT40_23,
122 };
123
124 /**
125 * ar9003_hw_set_channel - set channel on single-chip device
126 * @ah: atheros hardware structure
127 * @chan:
128 *
129 * This is the function to change channel on single-chip devices, that is
130 * for AR9300 family of chipsets.
131 *
132 * This function takes the channel value in MHz and sets
133 * hardware channel value. Assumes writes have been enabled to analog bus.
134 *
135 * Actual Expression,
136 *
137 * For 2GHz channel,
138 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
139 * (freq_ref = 40MHz)
140 *
141 * For 5GHz channel,
142 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
143 * (freq_ref = 40MHz/(24>>amodeRefSel))
144 *
145 * For 5GHz channels which are 5MHz spaced,
146 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
147 * (freq_ref = 40MHz)
148 */
149 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
150 {
151 u16 bMode, fracMode = 0, aModeRefSel = 0;
152 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0;
153 struct chan_centers centers;
154 int loadSynthChannel;
155
156 ath9k_hw_get_channel_centers(ah, chan, &centers);
157 freq = centers.synth_center;
158
159 if (freq < 4800) { /* 2 GHz, fractional mode */
160 if (AR_SREV_9330(ah) || AR_SREV_9485(ah) ||
161 AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
162 AR_SREV_9561(ah) || AR_SREV_9565(ah)) {
163 if (ah->is_clk_25mhz)
164 div = 75;
165 else
166 div = 120;
167
168 channelSel = (freq * 4) / div;
169 chan_frac = (((freq * 4) % div) * 0x20000) / div;
170 channelSel = (channelSel << 17) | chan_frac;
171 } else if (AR_SREV_9340(ah)) {
172 if (ah->is_clk_25mhz) {
173 channelSel = (freq * 2) / 75;
174 chan_frac = (((freq * 2) % 75) * 0x20000) / 75;
175 channelSel = (channelSel << 17) | chan_frac;
176 } else {
177 channelSel = CHANSEL_2G(freq) >> 1;
178 }
179 } else {
180 channelSel = CHANSEL_2G(freq);
181 }
182 /* Set to 2G mode */
183 bMode = 1;
184 } else {
185 if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) ||
186 AR_SREV_9531(ah) || AR_SREV_9561(ah)) &&
187 ah->is_clk_25mhz) {
188 channelSel = freq / 75;
189 chan_frac = ((freq % 75) * 0x20000) / 75;
190 channelSel = (channelSel << 17) | chan_frac;
191 } else {
192 channelSel = CHANSEL_5G(freq);
193 /* Doubler is ON, so, divide channelSel by 2. */
194 channelSel >>= 1;
195 }
196 /* Set to 5G mode */
197 bMode = 0;
198 }
199
200 /* Enable fractional mode for all channels */
201 fracMode = 1;
202 aModeRefSel = 0;
203 loadSynthChannel = 0;
204
205 reg32 = (bMode << 29);
206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
207
208 /* Enable Long shift Select for Synthesizer */
209 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
210 AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
211
212 /* Program Synth. setting */
213 reg32 = (channelSel << 2) | (fracMode << 30) |
214 (aModeRefSel << 28) | (loadSynthChannel << 31);
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
216
217 /* Toggle Load Synth channel bit */
218 loadSynthChannel = 1;
219 reg32 = (channelSel << 2) | (fracMode << 30) |
220 (aModeRefSel << 28) | (loadSynthChannel << 31);
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
222
223 ah->curchan = chan;
224
225 return 0;
226 }
227
228 /**
229 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
230 * @ah: atheros hardware structure
231 * @chan:
232 *
233 * For single-chip solutions. Converts to baseband spur frequency given the
234 * input channel frequency and compute register settings below.
235 *
236 * Spur mitigation for MRC CCK
237 */
238 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
239 struct ath9k_channel *chan)
240 {
241 static const u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
242 int cur_bb_spur, negative = 0, cck_spur_freq;
243 int i;
244 int range, max_spur_cnts, synth_freq;
245 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
246
247 /*
248 * Need to verify range +/- 10 MHz in control channel, otherwise spur
249 * is out-of-band and can be ignored.
250 */
251
252 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
253 AR_SREV_9550(ah) || AR_SREV_9561(ah)) {
254 if (spur_fbin_ptr[0] == 0) /* No spur */
255 return;
256 max_spur_cnts = 5;
257 if (IS_CHAN_HT40(chan)) {
258 range = 19;
259 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
260 AR_PHY_GC_DYN2040_PRI_CH) == 0)
261 synth_freq = chan->channel + 10;
262 else
263 synth_freq = chan->channel - 10;
264 } else {
265 range = 10;
266 synth_freq = chan->channel;
267 }
268 } else {
269 range = AR_SREV_9462(ah) ? 5 : 10;
270 max_spur_cnts = 4;
271 synth_freq = chan->channel;
272 }
273
274 for (i = 0; i < max_spur_cnts; i++) {
275 if (AR_SREV_9462(ah) && (i == 0 || i == 3))
276 continue;
277
278 negative = 0;
279 if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
280 AR_SREV_9550(ah) || AR_SREV_9561(ah))
281 cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
282 IS_CHAN_2GHZ(chan));
283 else
284 cur_bb_spur = spur_freq[i];
285
286 cur_bb_spur -= synth_freq;
287 if (cur_bb_spur < 0) {
288 negative = 1;
289 cur_bb_spur = -cur_bb_spur;
290 }
291 if (cur_bb_spur < range) {
292 cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
293
294 if (negative == 1)
295 cck_spur_freq = -cck_spur_freq;
296
297 cck_spur_freq = cck_spur_freq & 0xfffff;
298
299 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah),
300 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
301 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
302 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
303 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
304 AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
305 0x2);
306 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
307 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
308 0x1);
309 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
310 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
311 cck_spur_freq);
312
313 return;
314 }
315 }
316
317 REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL(ah),
318 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
319 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
320 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
321 REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
322 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
323 }
324
325 /* Clean all spur register fields */
326 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
327 {
328 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
329 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
330 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
331 AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
332 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
333 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
334 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
335 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
336 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
337 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
338 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
339 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
340 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
341 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
342 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
343 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
344 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
345 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
346
347 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
348 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
349 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
350 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
351 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
352 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
353 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
354 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
355 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
356 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
357 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
358 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
359 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
360 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
361 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
362 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
363 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
364 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
365 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
366 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
367 }
368
369 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
370 int freq_offset,
371 int spur_freq_sd,
372 int spur_delta_phase,
373 int spur_subchannel_sd,
374 int range,
375 int synth_freq)
376 {
377 int mask_index = 0;
378
379 /* OFDM Spur mitigation */
380 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
381 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
382 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
383 AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
384 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
385 AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
386 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
387 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
388 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
389 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
390
391 if (!(AR_SREV_9565(ah) && range == 10 && synth_freq == 2437))
392 REG_RMW_FIELD(ah, AR_PHY_TIMING11,
393 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
394
395 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
396 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
397 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
398 AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
399 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
400 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
401
402 if (!AR_SREV_9340(ah) &&
403 REG_READ_FIELD(ah, AR_PHY_MODE,
404 AR_PHY_MODE_DYNAMIC) == 0x1)
405 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
406 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
407
408 mask_index = (freq_offset << 4) / 5;
409 if (mask_index < 0)
410 mask_index = mask_index - 1;
411
412 mask_index = mask_index & 0x7f;
413
414 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
415 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
416 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
417 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
418 REG_RMW_FIELD(ah, AR_PHY_TIMING4,
419 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
420 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
421 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
422 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
423 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
424 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
425 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
426 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
427 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
428 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
429 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
430 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A(ah),
431 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
432 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
433 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
434 }
435
436 static void ar9003_hw_spur_ofdm_9565(struct ath_hw *ah,
437 int freq_offset)
438 {
439 int mask_index = 0;
440
441 mask_index = (freq_offset << 4) / 5;
442 if (mask_index < 0)
443 mask_index = mask_index - 1;
444
445 mask_index = mask_index & 0x7f;
446
447 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
448 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B,
449 mask_index);
450
451 /* A == B */
452 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B(ah),
453 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A,
454 mask_index);
455
456 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
457 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B,
458 mask_index);
459 REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
460 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe);
461 REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
462 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe);
463
464 /* A == B */
465 REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_B(ah),
466 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
467 }
468
469 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
470 struct ath9k_channel *chan,
471 int freq_offset,
472 int range,
473 int synth_freq)
474 {
475 int spur_freq_sd = 0;
476 int spur_subchannel_sd = 0;
477 int spur_delta_phase = 0;
478
479 if (IS_CHAN_HT40(chan)) {
480 if (freq_offset < 0) {
481 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
482 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
483 spur_subchannel_sd = 1;
484 else
485 spur_subchannel_sd = 0;
486
487 spur_freq_sd = ((freq_offset + 10) << 9) / 11;
488
489 } else {
490 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
491 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
492 spur_subchannel_sd = 0;
493 else
494 spur_subchannel_sd = 1;
495
496 spur_freq_sd = ((freq_offset - 10) << 9) / 11;
497
498 }
499
500 spur_delta_phase = (freq_offset << 17) / 5;
501
502 } else {
503 spur_subchannel_sd = 0;
504 spur_freq_sd = (freq_offset << 9) /11;
505 spur_delta_phase = (freq_offset << 18) / 5;
506 }
507
508 spur_freq_sd = spur_freq_sd & 0x3ff;
509 spur_delta_phase = spur_delta_phase & 0xfffff;
510
511 ar9003_hw_spur_ofdm(ah,
512 freq_offset,
513 spur_freq_sd,
514 spur_delta_phase,
515 spur_subchannel_sd,
516 range, synth_freq);
517 }
518
519 /* Spur mitigation for OFDM */
520 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
521 struct ath9k_channel *chan)
522 {
523 int synth_freq;
524 int range = 10;
525 int freq_offset = 0;
526 u8 *spur_fbin_ptr = ar9003_get_spur_chan_ptr(ah, IS_CHAN_2GHZ(chan));
527 unsigned int i;
528
529 if (spur_fbin_ptr[0] == 0)
530 return; /* No spur in the mode */
531
532 if (IS_CHAN_HT40(chan)) {
533 range = 19;
534 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
535 AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
536 synth_freq = chan->channel - 10;
537 else
538 synth_freq = chan->channel + 10;
539 } else {
540 range = 10;
541 synth_freq = chan->channel;
542 }
543
544 ar9003_hw_spur_ofdm_clear(ah);
545
546 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spur_fbin_ptr[i]; i++) {
547 freq_offset = ath9k_hw_fbin2freq(spur_fbin_ptr[i],
548 IS_CHAN_2GHZ(chan));
549 freq_offset -= synth_freq;
550 if (abs(freq_offset) < range) {
551 ar9003_hw_spur_ofdm_work(ah, chan, freq_offset,
552 range, synth_freq);
553
554 if (AR_SREV_9565(ah) && (i < 4)) {
555 freq_offset =
556 ath9k_hw_fbin2freq(spur_fbin_ptr[i + 1],
557 IS_CHAN_2GHZ(chan));
558 freq_offset -= synth_freq;
559 if (abs(freq_offset) < range)
560 ar9003_hw_spur_ofdm_9565(ah, freq_offset);
561 }
562
563 break;
564 }
565 }
566 }
567
568 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
569 struct ath9k_channel *chan)
570 {
571 if (!AR_SREV_9565(ah))
572 ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
573 ar9003_hw_spur_mitigate_ofdm(ah, chan);
574 }
575
576 static u32 ar9003_hw_compute_pll_control_soc(struct ath_hw *ah,
577 struct ath9k_channel *chan)
578 {
579 u32 pll;
580
581 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV);
582
583 if (chan && IS_CHAN_HALF_RATE(chan))
584 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL);
585 else if (chan && IS_CHAN_QUARTER_RATE(chan))
586 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL);
587
588 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT);
589
590 return pll;
591 }
592
593 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
594 struct ath9k_channel *chan)
595 {
596 u32 pll;
597
598 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
599
600 if (chan && IS_CHAN_HALF_RATE(chan))
601 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
602 else if (chan && IS_CHAN_QUARTER_RATE(chan))
603 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
604
605 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
606
607 return pll;
608 }
609
610 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
611 struct ath9k_channel *chan)
612 {
613 u32 phymode;
614 u32 enableDacFifo = 0;
615
616 enableDacFifo =
617 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
618
619 /* Enable 11n HT, 20 MHz */
620 phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
621
622 if (!AR_SREV_9561(ah))
623 phymode |= AR_PHY_GC_SINGLE_HT_LTF1;
624
625 /* Configure baseband for dynamic 20/40 operation */
626 if (IS_CHAN_HT40(chan)) {
627 phymode |= AR_PHY_GC_DYN2040_EN;
628 /* Configure control (primary) channel at +-10MHz */
629 if (IS_CHAN_HT40PLUS(chan))
630 phymode |= AR_PHY_GC_DYN2040_PRI_CH;
631
632 }
633
634 /* make sure we preserve INI settings */
635 phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
636 /* turn off Green Field detection for STA for now */
637 phymode &= ~AR_PHY_GC_GF_DETECT_EN;
638
639 REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
640
641 /* Configure MAC for 20/40 operation */
642 ath9k_hw_set11nmac2040(ah, chan);
643
644 /* global transmit timeout (25 TUs default)*/
645 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
646 /* carrier sense timeout */
647 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
648 }
649
650 static void ar9003_hw_init_bb(struct ath_hw *ah,
651 struct ath9k_channel *chan)
652 {
653 u32 synthDelay;
654
655 /*
656 * Wait for the frequency synth to settle (synth goes on
657 * via AR_PHY_ACTIVE_EN). Read the phy active delay register.
658 * Value is in 100ns increments.
659 */
660 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
661
662 /* Activate the PHY (includes baseband activate + synthesizer on) */
663 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
664 ath9k_hw_synth_delay(ah, chan, synthDelay);
665 }
666
667 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
668 {
669 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5)
670 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
671 AR_PHY_SWAP_ALT_CHAIN);
672
673 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
674 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
675
676 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7))
677 tx = 3;
678
679 REG_WRITE(ah, AR_SELFGEN_MASK, tx);
680 }
681
682 /*
683 * Override INI values with chip specific configuration.
684 */
685 static void ar9003_hw_override_ini(struct ath_hw *ah)
686 {
687 u32 val;
688
689 /*
690 * Set the RX_ABORT and RX_DIS and clear it only after
691 * RXE is set for MAC. This prevents frames with
692 * corrupted descriptor status.
693 */
694 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
695
696 /*
697 * For AR9280 and above, there is a new feature that allows
698 * Multicast search based on both MAC Address and Key ID. By default,
699 * this feature is enabled. But since the driver is not using this
700 * feature, we switch it off; otherwise multicast search based on
701 * MAC addr only will fail.
702 */
703 val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
704 val |= AR_AGG_WEP_ENABLE_FIX |
705 AR_AGG_WEP_ENABLE |
706 AR_PCU_MISC_MODE2_CFP_IGNORE;
707 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
708
709 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
710 REG_WRITE(ah, AR_GLB_SWREG_DISCONT_MODE,
711 AR_GLB_SWREG_DISCONT_EN_BT_WLAN);
712
713 if (REG_READ_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_0(ah),
714 AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL))
715 ah->enabled_cals |= TX_IQ_CAL;
716 else
717 ah->enabled_cals &= ~TX_IQ_CAL;
718
719 }
720
721 if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE)
722 ah->enabled_cals |= TX_CL_CAL;
723 else
724 ah->enabled_cals &= ~TX_CL_CAL;
725
726 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) ||
727 AR_SREV_9561(ah)) {
728 if (ah->is_clk_25mhz) {
729 REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x17c << 1);
730 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7);
731 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae);
732 } else {
733 REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x261 << 1);
734 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400);
735 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800);
736 }
737 udelay(100);
738 }
739 }
740
741 static void ar9003_hw_prog_ini(struct ath_hw *ah,
742 struct ar5416IniArray *iniArr,
743 int column)
744 {
745 unsigned int i, regWrites = 0;
746
747 /* New INI format: Array may be undefined (pre, core, post arrays) */
748 if (!iniArr->ia_array)
749 return;
750
751 /*
752 * New INI format: Pre, core, and post arrays for a given subsystem
753 * may be modal (> 2 columns) or non-modal (2 columns). Determine if
754 * the array is non-modal and force the column to 1.
755 */
756 if (column >= iniArr->ia_columns)
757 column = 1;
758
759 for (i = 0; i < iniArr->ia_rows; i++) {
760 u32 reg = INI_RA(iniArr, i, 0);
761 u32 val = INI_RA(iniArr, i, column);
762
763 REG_WRITE(ah, reg, val);
764
765 DO_DELAY(regWrites);
766 }
767 }
768
769 static u32 ar9550_hw_get_modes_txgain_index(struct ath_hw *ah,
770 struct ath9k_channel *chan)
771 {
772 u32 ret;
773
774 if (IS_CHAN_2GHZ(chan)) {
775 if (IS_CHAN_HT40(chan))
776 return 7;
777 else
778 return 8;
779 }
780
781 if (chan->channel <= 5350)
782 ret = 1;
783 else if ((chan->channel > 5350) && (chan->channel <= 5600))
784 ret = 3;
785 else
786 ret = 5;
787
788 if (IS_CHAN_HT40(chan))
789 ret++;
790
791 return ret;
792 }
793
794 static u32 ar9561_hw_get_modes_txgain_index(struct ath_hw *ah,
795 struct ath9k_channel *chan)
796 {
797 if (IS_CHAN_2GHZ(chan)) {
798 if (IS_CHAN_HT40(chan))
799 return 1;
800 else
801 return 2;
802 }
803
804 return 0;
805 }
806
807 static void ar9003_doubler_fix(struct ath_hw *ah)
808 {
809 if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9550(ah)) {
810 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2,
811 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
812 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
813 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2,
814 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
815 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
816 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2,
817 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
818 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0);
819
820 udelay(200);
821
822 REG_CLR_BIT(ah, AR_PHY_65NM_CH0_RXTX2,
823 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
824 REG_CLR_BIT(ah, AR_PHY_65NM_CH1_RXTX2,
825 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
826 REG_CLR_BIT(ah, AR_PHY_65NM_CH2_RXTX2,
827 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK);
828
829 udelay(1);
830
831 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX2,
832 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
833 REG_RMW_FIELD(ah, AR_PHY_65NM_CH1_RXTX2,
834 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
835 REG_RMW_FIELD(ah, AR_PHY_65NM_CH2_RXTX2,
836 AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK, 1);
837
838 udelay(200);
839
840 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH12,
841 AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf);
842
843 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0,
844 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
845 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
846 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0,
847 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
848 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
849 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0,
850 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK_S |
851 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S);
852 }
853 }
854
855 static int ar9003_hw_process_ini(struct ath_hw *ah,
856 struct ath9k_channel *chan)
857 {
858 unsigned int regWrites = 0, i;
859 u32 modesIndex;
860
861 if (IS_CHAN_5GHZ(chan))
862 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
863 else
864 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
865
866 /*
867 * SOC, MAC, BB, RADIO initvals.
868 */
869 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
870 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
871 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
872 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
873 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
874 if (i == ATH_INI_POST && AR_SREV_9462_20_OR_LATER(ah))
875 ar9003_hw_prog_ini(ah,
876 &ah->ini_radio_post_sys2ant,
877 modesIndex);
878 }
879
880 ar9003_doubler_fix(ah);
881
882 /*
883 * RXGAIN initvals.
884 */
885 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
886
887 if (AR_SREV_9462_20_OR_LATER(ah)) {
888 /*
889 * CUS217 mix LNA mode.
890 */
891 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
892 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
893 1, regWrites);
894 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
895 modesIndex, regWrites);
896 }
897
898 /*
899 * 5G-XLNA
900 */
901 if ((ar9003_hw_get_rx_gain_idx(ah) == 2) ||
902 (ar9003_hw_get_rx_gain_idx(ah) == 3)) {
903 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
904 modesIndex, regWrites);
905 }
906 }
907
908 if (AR_SREV_9550(ah) || AR_SREV_9561(ah))
909 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex,
910 regWrites);
911
912 if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0))
913 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna,
914 modesIndex, regWrites);
915 /*
916 * TXGAIN initvals.
917 */
918 if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
919 u32 modes_txgain_index = 1;
920
921 if (AR_SREV_9550(ah))
922 modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan);
923
924 if (AR_SREV_9561(ah))
925 modes_txgain_index =
926 ar9561_hw_get_modes_txgain_index(ah, chan);
927
928 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index,
929 regWrites);
930 } else {
931 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
932 }
933
934 /*
935 * For 5GHz channels requiring Fast Clock, apply
936 * different modal values.
937 */
938 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
939 REG_WRITE_ARRAY(&ah->iniModesFastClock,
940 modesIndex, regWrites);
941
942 /*
943 * Clock frequency initvals.
944 */
945 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
946
947 /*
948 * JAPAN regulatory.
949 */
950 if (chan->channel == 2484) {
951 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
952
953 if (AR_SREV_9531(ah))
954 REG_RMW_FIELD(ah, AR_PHY_FCAL_2_0,
955 AR_PHY_FLC_PWR_THRESH, 0);
956 }
957
958 ah->modes_index = modesIndex;
959 ar9003_hw_override_ini(ah);
960 ar9003_hw_set_channel_regs(ah, chan);
961 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
962 ath9k_hw_apply_txpower(ah, chan, false);
963
964 return 0;
965 }
966
967 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
968 struct ath9k_channel *chan)
969 {
970 u32 rfMode = 0;
971
972 if (chan == NULL)
973 return;
974
975 if (IS_CHAN_2GHZ(chan))
976 rfMode |= AR_PHY_MODE_DYNAMIC;
977 else
978 rfMode |= AR_PHY_MODE_OFDM;
979
980 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
981 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
982
983 if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
984 REG_RMW_FIELD(ah, AR_PHY_FRAME_CTL,
985 AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW, 3);
986
987 REG_WRITE(ah, AR_PHY_MODE, rfMode);
988 }
989
990 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
991 {
992 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
993 }
994
995 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
996 struct ath9k_channel *chan)
997 {
998 u32 coef_scaled, ds_coef_exp, ds_coef_man;
999 u32 clockMhzScaled = 0x64000000;
1000 struct chan_centers centers;
1001
1002 /*
1003 * half and quarter rate can divide the scaled clock by 2 or 4
1004 * scale for selected channel bandwidth
1005 */
1006 if (IS_CHAN_HALF_RATE(chan))
1007 clockMhzScaled = clockMhzScaled >> 1;
1008 else if (IS_CHAN_QUARTER_RATE(chan))
1009 clockMhzScaled = clockMhzScaled >> 2;
1010
1011 /*
1012 * ALGO -> coef = 1e8/fcarrier*fclock/40;
1013 * scaled coef to provide precision for this floating calculation
1014 */
1015 ath9k_hw_get_channel_centers(ah, chan, &centers);
1016 coef_scaled = clockMhzScaled / centers.synth_center;
1017
1018 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1019 &ds_coef_exp);
1020
1021 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1022 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1023 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1024 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1025
1026 /*
1027 * For Short GI,
1028 * scaled coeff is 9/10 that of normal coeff
1029 */
1030 coef_scaled = (9 * coef_scaled) / 10;
1031
1032 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1033 &ds_coef_exp);
1034
1035 /* for short gi */
1036 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1037 AR_PHY_SGI_DSC_MAN, ds_coef_man);
1038 REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
1039 AR_PHY_SGI_DSC_EXP, ds_coef_exp);
1040 }
1041
1042 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
1043 {
1044 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1045 return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1046 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
1047 }
1048
1049 /*
1050 * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
1051 * Read the phy active delay register. Value is in 100ns increments.
1052 */
1053 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
1054 {
1055 u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1056
1057 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay);
1058
1059 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1060 }
1061
1062 static bool ar9003_hw_ani_control(struct ath_hw *ah,
1063 enum ath9k_ani_cmd cmd, int param)
1064 {
1065 struct ath_common *common = ath9k_hw_common(ah);
1066 struct ath9k_channel *chan = ah->curchan;
1067 struct ar5416AniState *aniState = &ah->ani;
1068 int m1ThreshLow, m2ThreshLow;
1069 int m1Thresh, m2Thresh;
1070 int m2CountThr, m2CountThrLow;
1071 int m1ThreshLowExt, m2ThreshLowExt;
1072 int m1ThreshExt, m2ThreshExt;
1073 s32 value, value2;
1074
1075 switch (cmd & ah->ani_function) {
1076 case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1077 /*
1078 * on == 1 means ofdm weak signal detection is ON
1079 * on == 1 is the default, for less noise immunity
1080 *
1081 * on == 0 means ofdm weak signal detection is OFF
1082 * on == 0 means more noise imm
1083 */
1084 u32 on = param ? 1 : 0;
1085
1086 if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
1087 goto skip_ws_det;
1088
1089 m1ThreshLow = on ?
1090 aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1091 m2ThreshLow = on ?
1092 aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1093 m1Thresh = on ?
1094 aniState->iniDef.m1Thresh : m1Thresh_off;
1095 m2Thresh = on ?
1096 aniState->iniDef.m2Thresh : m2Thresh_off;
1097 m2CountThr = on ?
1098 aniState->iniDef.m2CountThr : m2CountThr_off;
1099 m2CountThrLow = on ?
1100 aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1101 m1ThreshLowExt = on ?
1102 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1103 m2ThreshLowExt = on ?
1104 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1105 m1ThreshExt = on ?
1106 aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1107 m2ThreshExt = on ?
1108 aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1109
1110 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1111 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1112 m1ThreshLow);
1113 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1114 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1115 m2ThreshLow);
1116 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1117 AR_PHY_SFCORR_M1_THRESH,
1118 m1Thresh);
1119 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1120 AR_PHY_SFCORR_M2_THRESH,
1121 m2Thresh);
1122 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1123 AR_PHY_SFCORR_M2COUNT_THR,
1124 m2CountThr);
1125 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1126 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1127 m2CountThrLow);
1128 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1129 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1130 m1ThreshLowExt);
1131 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1132 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1133 m2ThreshLowExt);
1134 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1135 AR_PHY_SFCORR_EXT_M1_THRESH,
1136 m1ThreshExt);
1137 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1138 AR_PHY_SFCORR_EXT_M2_THRESH,
1139 m2ThreshExt);
1140 skip_ws_det:
1141 if (on)
1142 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1143 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1144 else
1145 REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1146 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1147
1148 if (on != aniState->ofdmWeakSigDetect) {
1149 ath_dbg(common, ANI,
1150 "** ch %d: ofdm weak signal: %s=>%s\n",
1151 chan->channel,
1152 aniState->ofdmWeakSigDetect ?
1153 "on" : "off",
1154 on ? "on" : "off");
1155 if (on)
1156 ah->stats.ast_ani_ofdmon++;
1157 else
1158 ah->stats.ast_ani_ofdmoff++;
1159 aniState->ofdmWeakSigDetect = on;
1160 }
1161 break;
1162 }
1163 case ATH9K_ANI_FIRSTEP_LEVEL:{
1164 u32 level = param;
1165
1166 if (level >= ARRAY_SIZE(firstep_table)) {
1167 ath_dbg(common, ANI,
1168 "ATH9K_ANI_FIRSTEP_LEVEL: level out of range (%u > %zu)\n",
1169 level, ARRAY_SIZE(firstep_table));
1170 return false;
1171 }
1172
1173 /*
1174 * make register setting relative to default
1175 * from INI file & cap value
1176 */
1177 value = firstep_table[level] -
1178 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1179 aniState->iniDef.firstep;
1180 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1181 value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1182 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1183 value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1184 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1185 AR_PHY_FIND_SIG_FIRSTEP,
1186 value);
1187 /*
1188 * we need to set first step low register too
1189 * make register setting relative to default
1190 * from INI file & cap value
1191 */
1192 value2 = firstep_table[level] -
1193 firstep_table[ATH9K_ANI_FIRSTEP_LVL] +
1194 aniState->iniDef.firstepLow;
1195 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1196 value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1197 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1198 value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1199
1200 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1201 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW, value2);
1202
1203 if (level != aniState->firstepLevel) {
1204 ath_dbg(common, ANI,
1205 "** ch %d: level %d=>%d[def:%d] firstep[level]=%d ini=%d\n",
1206 chan->channel,
1207 aniState->firstepLevel,
1208 level,
1209 ATH9K_ANI_FIRSTEP_LVL,
1210 value,
1211 aniState->iniDef.firstep);
1212 ath_dbg(common, ANI,
1213 "** ch %d: level %d=>%d[def:%d] firstep_low[level]=%d ini=%d\n",
1214 chan->channel,
1215 aniState->firstepLevel,
1216 level,
1217 ATH9K_ANI_FIRSTEP_LVL,
1218 value2,
1219 aniState->iniDef.firstepLow);
1220 if (level > aniState->firstepLevel)
1221 ah->stats.ast_ani_stepup++;
1222 else if (level < aniState->firstepLevel)
1223 ah->stats.ast_ani_stepdown++;
1224 aniState->firstepLevel = level;
1225 }
1226 break;
1227 }
1228 case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1229 u32 level = param;
1230
1231 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1232 ath_dbg(common, ANI,
1233 "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level out of range (%u > %zu)\n",
1234 level, ARRAY_SIZE(cycpwrThr1_table));
1235 return false;
1236 }
1237 /*
1238 * make register setting relative to default
1239 * from INI file & cap value
1240 */
1241 value = cycpwrThr1_table[level] -
1242 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1243 aniState->iniDef.cycpwrThr1;
1244 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1245 value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1246 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1247 value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1248 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1249 AR_PHY_TIMING5_CYCPWR_THR1,
1250 value);
1251
1252 /*
1253 * set AR_PHY_EXT_CCA for extension channel
1254 * make register setting relative to default
1255 * from INI file & cap value
1256 */
1257 value2 = cycpwrThr1_table[level] -
1258 cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL] +
1259 aniState->iniDef.cycpwrThr1Ext;
1260 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1261 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1262 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1263 value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1264 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1265 AR_PHY_EXT_CYCPWR_THR1, value2);
1266
1267 if (level != aniState->spurImmunityLevel) {
1268 ath_dbg(common, ANI,
1269 "** ch %d: level %d=>%d[def:%d] cycpwrThr1[level]=%d ini=%d\n",
1270 chan->channel,
1271 aniState->spurImmunityLevel,
1272 level,
1273 ATH9K_ANI_SPUR_IMMUNE_LVL,
1274 value,
1275 aniState->iniDef.cycpwrThr1);
1276 ath_dbg(common, ANI,
1277 "** ch %d: level %d=>%d[def:%d] cycpwrThr1Ext[level]=%d ini=%d\n",
1278 chan->channel,
1279 aniState->spurImmunityLevel,
1280 level,
1281 ATH9K_ANI_SPUR_IMMUNE_LVL,
1282 value2,
1283 aniState->iniDef.cycpwrThr1Ext);
1284 if (level > aniState->spurImmunityLevel)
1285 ah->stats.ast_ani_spurup++;
1286 else if (level < aniState->spurImmunityLevel)
1287 ah->stats.ast_ani_spurdown++;
1288 aniState->spurImmunityLevel = level;
1289 }
1290 break;
1291 }
1292 case ATH9K_ANI_MRC_CCK:{
1293 /*
1294 * is_on == 1 means MRC CCK ON (default, less noise imm)
1295 * is_on == 0 means MRC CCK is OFF (more noise imm)
1296 */
1297 bool is_on = param ? 1 : 0;
1298
1299 if (ah->caps.rx_chainmask == 1)
1300 break;
1301
1302 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1303 AR_PHY_MRC_CCK_ENABLE, is_on);
1304 REG_RMW_FIELD(ah, AR_PHY_MRC_CCK_CTRL,
1305 AR_PHY_MRC_CCK_MUX_REG, is_on);
1306 if (is_on != aniState->mrcCCK) {
1307 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n",
1308 chan->channel,
1309 aniState->mrcCCK ? "on" : "off",
1310 is_on ? "on" : "off");
1311 if (is_on)
1312 ah->stats.ast_ani_ccklow++;
1313 else
1314 ah->stats.ast_ani_cckhigh++;
1315 aniState->mrcCCK = is_on;
1316 }
1317 break;
1318 }
1319 default:
1320 ath_dbg(common, ANI, "invalid cmd %u\n", cmd);
1321 return false;
1322 }
1323
1324 ath_dbg(common, ANI,
1325 "ANI parameters: SI=%d, ofdmWS=%s FS=%d MRCcck=%s listenTime=%d ofdmErrs=%d cckErrs=%d\n",
1326 aniState->spurImmunityLevel,
1327 aniState->ofdmWeakSigDetect ? "on" : "off",
1328 aniState->firstepLevel,
1329 aniState->mrcCCK ? "on" : "off",
1330 aniState->listenTime,
1331 aniState->ofdmPhyErrCount,
1332 aniState->cckPhyErrCount);
1333 return true;
1334 }
1335
1336 static void ar9003_hw_do_getnf(struct ath_hw *ah,
1337 int16_t nfarray[NUM_NF_READINGS])
1338 {
1339 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000
1340 #define AR_PHY_CH_MINCCA_PWR_S 20
1341 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000
1342 #define AR_PHY_CH_EXT_MINCCA_PWR_S 16
1343
1344 int16_t nf;
1345 int i;
1346
1347 for (i = 0; i < AR9300_MAX_CHAINS; i++) {
1348 if (ah->rxchainmask & BIT(i)) {
1349 nf = MS(REG_READ(ah, ah->nf_regs[i]),
1350 AR_PHY_CH_MINCCA_PWR);
1351 nfarray[i] = sign_extend32(nf, 8);
1352
1353 if (IS_CHAN_HT40(ah->curchan)) {
1354 u8 ext_idx = AR9300_MAX_CHAINS + i;
1355
1356 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]),
1357 AR_PHY_CH_EXT_MINCCA_PWR);
1358 nfarray[ext_idx] = sign_extend32(nf, 8);
1359 }
1360 }
1361 }
1362 }
1363
1364 static void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1365 {
1366 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1367 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1368 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ;
1369 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1370 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1371 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ;
1372
1373 if (AR_SREV_9330(ah))
1374 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ;
1375
1376 if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
1377 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ;
1378 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ;
1379 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ;
1380 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ;
1381 }
1382 }
1383
1384 /*
1385 * Initialize the ANI register values with default (ini) values.
1386 * This routine is called during a (full) hardware reset after
1387 * all the registers are initialised from the INI.
1388 */
1389 static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
1390 {
1391 struct ar5416AniState *aniState;
1392 struct ath_common *common = ath9k_hw_common(ah);
1393 struct ath9k_channel *chan = ah->curchan;
1394 struct ath9k_ani_default *iniDef;
1395 u32 val;
1396
1397 aniState = &ah->ani;
1398 iniDef = &aniState->iniDef;
1399
1400 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n",
1401 ah->hw_version.macVersion,
1402 ah->hw_version.macRev,
1403 ah->opmode,
1404 chan->channel);
1405
1406 val = REG_READ(ah, AR_PHY_SFCORR);
1407 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1408 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1409 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1410
1411 val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1412 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1413 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1414 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1415
1416 val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1417 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1418 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1419 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1420 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1421 iniDef->firstep = REG_READ_FIELD(ah,
1422 AR_PHY_FIND_SIG,
1423 AR_PHY_FIND_SIG_FIRSTEP);
1424 iniDef->firstepLow = REG_READ_FIELD(ah,
1425 AR_PHY_FIND_SIG_LOW,
1426 AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW);
1427 iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1428 AR_PHY_TIMING5,
1429 AR_PHY_TIMING5_CYCPWR_THR1);
1430 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1431 AR_PHY_EXT_CCA,
1432 AR_PHY_EXT_CYCPWR_THR1);
1433
1434 /* these levels just got reset to defaults by the INI */
1435 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL;
1436 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL;
1437 aniState->ofdmWeakSigDetect = true;
1438 aniState->mrcCCK = true;
1439 }
1440
1441 static void ar9003_hw_set_radar_params(struct ath_hw *ah,
1442 struct ath_hw_radar_conf *conf)
1443 {
1444 unsigned int regWrites = 0;
1445 u32 radar_0 = 0, radar_1;
1446
1447 if (!conf) {
1448 REG_CLR_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_ENA);
1449 return;
1450 }
1451
1452 radar_0 |= AR_PHY_RADAR_0_ENA | AR_PHY_RADAR_0_FFT_ENA;
1453 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR);
1454 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI);
1455 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT);
1456 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI);
1457 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND);
1458
1459 radar_1 = REG_READ(ah, AR_PHY_RADAR_1);
1460 radar_1 &= ~(AR_PHY_RADAR_1_MAXLEN | AR_PHY_RADAR_1_RELSTEP_THRESH |
1461 AR_PHY_RADAR_1_RELPWR_THRESH);
1462 radar_1 |= AR_PHY_RADAR_1_MAX_RRSSI;
1463 radar_1 |= AR_PHY_RADAR_1_BLOCK_CHECK;
1464 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN);
1465 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH);
1466 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH);
1467
1468 REG_WRITE(ah, AR_PHY_RADAR_0, radar_0);
1469 REG_WRITE(ah, AR_PHY_RADAR_1, radar_1);
1470 if (conf->ext_channel)
1471 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1472 else
1473 REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
1474
1475 if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
1476 REG_WRITE_ARRAY(&ah->ini_dfs,
1477 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
1478 }
1479 }
1480
1481 static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
1482 {
1483 struct ath_hw_radar_conf *conf = &ah->radar_conf;
1484
1485 conf->fir_power = -28;
1486 conf->radar_rssi = 0;
1487 conf->pulse_height = 10;
1488 conf->pulse_rssi = 15;
1489 conf->pulse_inband = 8;
1490 conf->pulse_maxlen = 255;
1491 conf->pulse_inband_step = 12;
1492 conf->radar_inband = 8;
1493 }
1494
1495 static void ar9003_hw_antdiv_comb_conf_get(struct ath_hw *ah,
1496 struct ath_hw_antcomb_conf *antconf)
1497 {
1498 u32 regval;
1499
1500 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1501 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >>
1502 AR_PHY_ANT_DIV_MAIN_LNACONF_S;
1503 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >>
1504 AR_PHY_ANT_DIV_ALT_LNACONF_S;
1505 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >>
1506 AR_PHY_ANT_FAST_DIV_BIAS_S;
1507
1508 if (AR_SREV_9330_11(ah)) {
1509 antconf->lna1_lna2_switch_delta = -1;
1510 antconf->lna1_lna2_delta = -9;
1511 antconf->div_group = 1;
1512 } else if (AR_SREV_9485(ah)) {
1513 antconf->lna1_lna2_switch_delta = -1;
1514 antconf->lna1_lna2_delta = -9;
1515 antconf->div_group = 2;
1516 } else if (AR_SREV_9565(ah)) {
1517 antconf->lna1_lna2_switch_delta = 3;
1518 antconf->lna1_lna2_delta = -9;
1519 antconf->div_group = 3;
1520 } else {
1521 antconf->lna1_lna2_switch_delta = -1;
1522 antconf->lna1_lna2_delta = -3;
1523 antconf->div_group = 0;
1524 }
1525 }
1526
1527 static void ar9003_hw_antdiv_comb_conf_set(struct ath_hw *ah,
1528 struct ath_hw_antcomb_conf *antconf)
1529 {
1530 u32 regval;
1531
1532 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1533 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1534 AR_PHY_ANT_DIV_ALT_LNACONF |
1535 AR_PHY_ANT_FAST_DIV_BIAS |
1536 AR_PHY_ANT_DIV_MAIN_GAINTB |
1537 AR_PHY_ANT_DIV_ALT_GAINTB);
1538 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S)
1539 & AR_PHY_ANT_DIV_MAIN_LNACONF);
1540 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S)
1541 & AR_PHY_ANT_DIV_ALT_LNACONF);
1542 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S)
1543 & AR_PHY_ANT_FAST_DIV_BIAS);
1544 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S)
1545 & AR_PHY_ANT_DIV_MAIN_GAINTB);
1546 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S)
1547 & AR_PHY_ANT_DIV_ALT_GAINTB);
1548
1549 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1550 }
1551
1552 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1553
1554 static void ar9003_hw_set_bt_ant_diversity(struct ath_hw *ah, bool enable)
1555 {
1556 struct ath9k_hw_capabilities *pCap = &ah->caps;
1557 u8 ant_div_ctl1;
1558 u32 regval;
1559
1560 if (!AR_SREV_9485(ah) && !AR_SREV_9565(ah))
1561 return;
1562
1563 if (AR_SREV_9485(ah)) {
1564 regval = ar9003_hw_ant_ctrl_common_2_get(ah,
1565 IS_CHAN_2GHZ(ah->curchan));
1566 if (enable) {
1567 regval &= ~AR_SWITCH_TABLE_COM2_ALL;
1568 regval |= ah->config.ant_ctrl_comm2g_switch_enable;
1569 }
1570 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2,
1571 AR_SWITCH_TABLE_COM2_ALL, regval);
1572 }
1573
1574 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
1575
1576 /*
1577 * Set MAIN/ALT LNA conf.
1578 * Set MAIN/ALT gain_tb.
1579 */
1580 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1581 regval &= (~AR_ANT_DIV_CTRL_ALL);
1582 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
1583 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1584
1585 if (AR_SREV_9485_11_OR_LATER(ah)) {
1586 /*
1587 * Enable LNA diversity.
1588 */
1589 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1590 regval &= ~AR_PHY_ANT_DIV_LNADIV;
1591 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S;
1592 if (enable)
1593 regval |= AR_ANT_DIV_ENABLE;
1594
1595 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1596
1597 /*
1598 * Enable fast antenna diversity.
1599 */
1600 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
1601 regval &= ~AR_FAST_DIV_ENABLE;
1602 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S;
1603 if (enable)
1604 regval |= AR_FAST_DIV_ENABLE;
1605
1606 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
1607
1608 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) {
1609 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1610 regval &= (~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1611 AR_PHY_ANT_DIV_ALT_LNACONF |
1612 AR_PHY_ANT_DIV_ALT_GAINTB |
1613 AR_PHY_ANT_DIV_MAIN_GAINTB));
1614 /*
1615 * Set MAIN to LNA1 and ALT to LNA2 at the
1616 * beginning.
1617 */
1618 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1619 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1620 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1621 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1622 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1623 }
1624 } else if (AR_SREV_9565(ah)) {
1625 if (enable) {
1626 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1627 AR_ANT_DIV_ENABLE);
1628 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1629 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1630 REG_SET_BIT(ah, AR_PHY_CCK_DETECT,
1631 AR_FAST_DIV_ENABLE);
1632 REG_SET_BIT(ah, AR_PHY_RESTART,
1633 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1634 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV,
1635 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1636 } else {
1637 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1638 AR_ANT_DIV_ENABLE);
1639 REG_CLR_BIT(ah, AR_PHY_MC_GAIN_CTRL,
1640 (1 << AR_PHY_ANT_SW_RX_PROT_S));
1641 REG_CLR_BIT(ah, AR_PHY_CCK_DETECT,
1642 AR_FAST_DIV_ENABLE);
1643 REG_CLR_BIT(ah, AR_PHY_RESTART,
1644 AR_PHY_RESTART_ENABLE_DIV_M2FLAG);
1645 REG_CLR_BIT(ah, AR_BTCOEX_WL_LNADIV,
1646 AR_BTCOEX_WL_LNADIV_FORCE_ON);
1647
1648 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
1649 regval &= ~(AR_PHY_ANT_DIV_MAIN_LNACONF |
1650 AR_PHY_ANT_DIV_ALT_LNACONF |
1651 AR_PHY_ANT_DIV_MAIN_GAINTB |
1652 AR_PHY_ANT_DIV_ALT_GAINTB);
1653 regval |= (ATH_ANT_DIV_COMB_LNA1 <<
1654 AR_PHY_ANT_DIV_MAIN_LNACONF_S);
1655 regval |= (ATH_ANT_DIV_COMB_LNA2 <<
1656 AR_PHY_ANT_DIV_ALT_LNACONF_S);
1657 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
1658 }
1659 }
1660 }
1661
1662 #endif
1663
1664 static int ar9003_hw_fast_chan_change(struct ath_hw *ah,
1665 struct ath9k_channel *chan,
1666 u8 *ini_reloaded)
1667 {
1668 unsigned int regWrites = 0;
1669 u32 modesIndex, txgain_index;
1670
1671 if (IS_CHAN_5GHZ(chan))
1672 modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
1673 else
1674 modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
1675
1676 txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex;
1677
1678 if (modesIndex == ah->modes_index) {
1679 *ini_reloaded = false;
1680 goto set_rfmode;
1681 }
1682
1683 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex);
1684 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex);
1685 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex);
1686 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex);
1687
1688 if (AR_SREV_9462_20_OR_LATER(ah))
1689 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
1690 modesIndex);
1691
1692 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites);
1693
1694 if (AR_SREV_9462_20_OR_LATER(ah)) {
1695 /*
1696 * CUS217 mix LNA mode.
1697 */
1698 if (ar9003_hw_get_rx_gain_idx(ah) == 2) {
1699 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core,
1700 1, regWrites);
1701 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble,
1702 modesIndex, regWrites);
1703 }
1704 }
1705
1706 /*
1707 * For 5GHz channels requiring Fast Clock, apply
1708 * different modal values.
1709 */
1710 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1711 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites);
1712
1713 if (AR_SREV_9565(ah))
1714 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites);
1715
1716 /*
1717 * JAPAN regulatory.
1718 */
1719 if (chan->channel == 2484)
1720 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1);
1721
1722 ah->modes_index = modesIndex;
1723 *ini_reloaded = true;
1724
1725 set_rfmode:
1726 ar9003_hw_set_rfmode(ah, chan);
1727 return 0;
1728 }
1729
1730 static void ar9003_hw_spectral_scan_config(struct ath_hw *ah,
1731 struct ath_spec_scan *param)
1732 {
1733 u8 count;
1734
1735 if (!param->enabled) {
1736 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1737 AR_PHY_SPECTRAL_SCAN_ENABLE);
1738 return;
1739 }
1740
1741 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA);
1742 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE);
1743
1744 /* on AR93xx and newer, count = 0 will make the chip send
1745 * spectral samples endlessly. Check if this really was intended,
1746 * and fix otherwise.
1747 */
1748 count = param->count;
1749 if (param->endless)
1750 count = 0;
1751 else if (param->count == 0)
1752 count = 1;
1753
1754 if (param->short_repeat)
1755 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1756 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1757 else
1758 REG_CLR_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1759 AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT);
1760
1761 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1762 AR_PHY_SPECTRAL_SCAN_COUNT, count);
1763 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1764 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period);
1765 REG_RMW_FIELD(ah, AR_PHY_SPECTRAL_SCAN,
1766 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period);
1767
1768 return;
1769 }
1770
1771 static void ar9003_hw_spectral_scan_trigger(struct ath_hw *ah)
1772 {
1773 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1774 AR_PHY_SPECTRAL_SCAN_ENABLE);
1775 /* Activate spectral scan */
1776 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN,
1777 AR_PHY_SPECTRAL_SCAN_ACTIVE);
1778 }
1779
1780 static void ar9003_hw_spectral_scan_wait(struct ath_hw *ah)
1781 {
1782 struct ath_common *common = ath9k_hw_common(ah);
1783
1784 /* Poll for spectral scan complete */
1785 if (!ath9k_hw_wait(ah, AR_PHY_SPECTRAL_SCAN,
1786 AR_PHY_SPECTRAL_SCAN_ACTIVE,
1787 0, AH_WAIT_TIMEOUT)) {
1788 ath_err(common, "spectral scan wait failed\n");
1789 return;
1790 }
1791 }
1792
1793 static void ar9003_hw_tx99_start(struct ath_hw *ah, u32 qnum)
1794 {
1795 REG_SET_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR);
1796 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1797 REG_WRITE(ah, AR_CR, AR_CR_RXD);
1798 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);
1799 REG_WRITE(ah, AR_D_GBL_IFS_SIFS, 20); /* 50 OK */
1800 REG_WRITE(ah, AR_D_GBL_IFS_EIFS, 20);
1801 REG_WRITE(ah, AR_TIME_OUT, 0x00000400);
1802 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);
1803 REG_SET_BIT(ah, AR_QMISC(qnum), AR_Q_MISC_DCU_EARLY_TERM_REQ);
1804 }
1805
1806 static void ar9003_hw_tx99_stop(struct ath_hw *ah)
1807 {
1808 REG_CLR_BIT(ah, AR_PHY_TEST(ah), PHY_AGC_CLR);
1809 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
1810 }
1811
1812 static void ar9003_hw_tx99_set_txpower(struct ath_hw *ah, u8 txpower)
1813 {
1814 static u8 p_pwr_array[ar9300RateSize] = { 0 };
1815 unsigned int i;
1816
1817 txpower = txpower <= MAX_RATE_POWER ? txpower : MAX_RATE_POWER;
1818 for (i = 0; i < ar9300RateSize; i++)
1819 p_pwr_array[i] = txpower;
1820
1821 ar9003_hw_tx_power_regwrite(ah, p_pwr_array);
1822 }
1823
1824 static void ar9003_hw_init_txpower_cck(struct ath_hw *ah, u8 *rate_array)
1825 {
1826 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1827 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L];
1828 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L],
1829 rate_array[ALL_TARGET_LEGACY_5S]);
1830 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L],
1831 rate_array[ALL_TARGET_LEGACY_11S]);
1832 }
1833
1834 static void ar9003_hw_init_txpower_ofdm(struct ath_hw *ah, u8 *rate_array,
1835 int offset)
1836 {
1837 int i, j;
1838
1839 for (i = offset; i < offset + AR9300_OFDM_RATES; i++) {
1840 /* OFDM rate to power table idx */
1841 j = ofdm2pwr[i - offset];
1842 ah->tx_power[i] = rate_array[j];
1843 }
1844 }
1845
1846 static void ar9003_hw_init_txpower_ht(struct ath_hw *ah, u8 *rate_array,
1847 int ss_offset, int ds_offset,
1848 int ts_offset, bool is_40)
1849 {
1850 int i, j, mcs_idx = 0;
1851 const u8 *mcs2pwr = (is_40) ? mcs2pwr_ht40 : mcs2pwr_ht20;
1852
1853 for (i = ss_offset; i < ss_offset + AR9300_HT_SS_RATES; i++) {
1854 j = mcs2pwr[mcs_idx];
1855 ah->tx_power[i] = rate_array[j];
1856 mcs_idx++;
1857 }
1858
1859 for (i = ds_offset; i < ds_offset + AR9300_HT_DS_RATES; i++) {
1860 j = mcs2pwr[mcs_idx];
1861 ah->tx_power[i] = rate_array[j];
1862 mcs_idx++;
1863 }
1864
1865 for (i = ts_offset; i < ts_offset + AR9300_HT_TS_RATES; i++) {
1866 j = mcs2pwr[mcs_idx];
1867 ah->tx_power[i] = rate_array[j];
1868 mcs_idx++;
1869 }
1870 }
1871
1872 static void ar9003_hw_init_txpower_stbc(struct ath_hw *ah, int ss_offset,
1873 int ds_offset, int ts_offset)
1874 {
1875 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset],
1876 AR9300_HT_SS_RATES);
1877 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset],
1878 AR9300_HT_DS_RATES);
1879 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset],
1880 AR9300_HT_TS_RATES);
1881 }
1882
1883 void ar9003_hw_init_rate_txpower(struct ath_hw *ah, u8 *rate_array,
1884 struct ath9k_channel *chan)
1885 {
1886 if (IS_CHAN_5GHZ(chan)) {
1887 ar9003_hw_init_txpower_ofdm(ah, rate_array,
1888 AR9300_11NA_OFDM_SHIFT);
1889 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1890 ar9003_hw_init_txpower_ht(ah, rate_array,
1891 AR9300_11NA_HT_SS_SHIFT,
1892 AR9300_11NA_HT_DS_SHIFT,
1893 AR9300_11NA_HT_TS_SHIFT,
1894 IS_CHAN_HT40(chan));
1895 ar9003_hw_init_txpower_stbc(ah,
1896 AR9300_11NA_HT_SS_SHIFT,
1897 AR9300_11NA_HT_DS_SHIFT,
1898 AR9300_11NA_HT_TS_SHIFT);
1899 }
1900 } else {
1901 ar9003_hw_init_txpower_cck(ah, rate_array);
1902 ar9003_hw_init_txpower_ofdm(ah, rate_array,
1903 AR9300_11NG_OFDM_SHIFT);
1904 if (IS_CHAN_HT20(chan) || IS_CHAN_HT40(chan)) {
1905 ar9003_hw_init_txpower_ht(ah, rate_array,
1906 AR9300_11NG_HT_SS_SHIFT,
1907 AR9300_11NG_HT_DS_SHIFT,
1908 AR9300_11NG_HT_TS_SHIFT,
1909 IS_CHAN_HT40(chan));
1910 ar9003_hw_init_txpower_stbc(ah,
1911 AR9300_11NG_HT_SS_SHIFT,
1912 AR9300_11NG_HT_DS_SHIFT,
1913 AR9300_11NG_HT_TS_SHIFT);
1914 }
1915 }
1916 }
1917
1918 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1919 {
1920 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1921 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
1922 static const u32 ar9300_cca_regs[6] = {
1923 AR_PHY_CCA_0,
1924 AR_PHY_CCA_1,
1925 AR_PHY_CCA_2,
1926 AR_PHY_EXT_CCA,
1927 AR_PHY_EXT_CCA_1,
1928 AR_PHY_EXT_CCA_2,
1929 };
1930
1931 priv_ops->rf_set_freq = ar9003_hw_set_channel;
1932 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1933
1934 if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1935 AR_SREV_9561(ah))
1936 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc;
1937 else
1938 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1939
1940 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1941 priv_ops->init_bb = ar9003_hw_init_bb;
1942 priv_ops->process_ini = ar9003_hw_process_ini;
1943 priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1944 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1945 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1946 priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1947 priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1948 priv_ops->ani_control = ar9003_hw_ani_control;
1949 priv_ops->do_getnf = ar9003_hw_do_getnf;
1950 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs;
1951 priv_ops->set_radar_params = ar9003_hw_set_radar_params;
1952 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change;
1953
1954 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get;
1955 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set;
1956 ops->spectral_scan_config = ar9003_hw_spectral_scan_config;
1957 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger;
1958 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait;
1959
1960 #ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
1961 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity;
1962 #endif
1963 ops->tx99_start = ar9003_hw_tx99_start;
1964 ops->tx99_stop = ar9003_hw_tx99_stop;
1965 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower;
1966
1967 ar9003_hw_set_nf_limits(ah);
1968 ar9003_hw_set_radar_conf(ah);
1969 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs));
1970 }
1971
1972 /*
1973 * Baseband Watchdog signatures:
1974 *
1975 * 0x04000539: BB hang when operating in HT40 DFS Channel.
1976 * Full chip reset is not required, but a recovery
1977 * mechanism is needed.
1978 *
1979 * 0x1300000a: Related to CAC deafness.
1980 * Chip reset is not required.
1981 *
1982 * 0x0400000a: Related to CAC deafness.
1983 * Full chip reset is required.
1984 *
1985 * 0x04000b09: RX state machine gets into an illegal state
1986 * when a packet with unsupported rate is received.
1987 * Full chip reset is required and PHY_RESTART has
1988 * to be disabled.
1989 *
1990 * 0x04000409: Packet stuck on receive.
1991 * Full chip reset is required for all chips except
1992 * AR9340, AR9531 and AR9561.
1993 */
1994
1995 /*
1996 * ar9003_hw_bb_watchdog_check(): Returns true if a chip reset is required.
1997 */
1998 bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah)
1999 {
2000 u32 val;
2001
2002 switch(ah->bb_watchdog_last_status) {
2003 case 0x04000539:
2004 val = REG_READ(ah, AR_PHY_RADAR_0);
2005 val &= (~AR_PHY_RADAR_0_FIRPWR);
2006 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR);
2007 REG_WRITE(ah, AR_PHY_RADAR_0, val);
2008 udelay(1);
2009 val = REG_READ(ah, AR_PHY_RADAR_0);
2010 val &= ~AR_PHY_RADAR_0_FIRPWR;
2011 val |= SM(AR9300_DFS_FIRPWR, AR_PHY_RADAR_0_FIRPWR);
2012 REG_WRITE(ah, AR_PHY_RADAR_0, val);
2013
2014 return false;
2015 case 0x1300000a:
2016 return false;
2017 case 0x0400000a:
2018 case 0x04000b09:
2019 return true;
2020 case 0x04000409:
2021 if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah))
2022 return false;
2023 else
2024 return true;
2025 default:
2026 /*
2027 * For any other unknown signatures, do a
2028 * full chip reset.
2029 */
2030 return true;
2031 }
2032 }
2033 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_check);
2034
2035 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah)
2036 {
2037 struct ath_common *common = ath9k_hw_common(ah);
2038 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms;
2039 u32 val, idle_count;
2040
2041 if (!idle_tmo_ms) {
2042 /* disable IRQ, disable chip-reset for BB panic */
2043 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2044 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) &
2045 ~(AR_PHY_WATCHDOG_RST_ENABLE |
2046 AR_PHY_WATCHDOG_IRQ_ENABLE));
2047
2048 /* disable watchdog in non-IDLE mode, disable in IDLE mode */
2049 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2050 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1) &
2051 ~(AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2052 AR_PHY_WATCHDOG_IDLE_ENABLE));
2053
2054 ath_dbg(common, RESET, "Disabled BB Watchdog\n");
2055 return;
2056 }
2057
2058 /* enable IRQ, disable chip-reset for BB watchdog */
2059 val = REG_READ(ah, AR_PHY_WATCHDOG_CTL_2) & AR_PHY_WATCHDOG_CNTL2_MASK;
2060 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_2,
2061 (val | AR_PHY_WATCHDOG_IRQ_ENABLE) &
2062 ~AR_PHY_WATCHDOG_RST_ENABLE);
2063
2064 /* bound limit to 10 secs */
2065 if (idle_tmo_ms > 10000)
2066 idle_tmo_ms = 10000;
2067
2068 /*
2069 * The time unit for watchdog event is 2^15 44/88MHz cycles.
2070 *
2071 * For HT20 we have a time unit of 2^15/44 MHz = .74 ms per tick
2072 * For HT40 we have a time unit of 2^15/88 MHz = .37 ms per tick
2073 *
2074 * Given we use fast clock now in 5 GHz, these time units should
2075 * be common for both 2 GHz and 5 GHz.
2076 */
2077 idle_count = (100 * idle_tmo_ms) / 74;
2078 if (ah->curchan && IS_CHAN_HT40(ah->curchan))
2079 idle_count = (100 * idle_tmo_ms) / 37;
2080
2081 /*
2082 * enable watchdog in non-IDLE mode, disable in IDLE mode,
2083 * set idle time-out.
2084 */
2085 REG_WRITE(ah, AR_PHY_WATCHDOG_CTL_1,
2086 AR_PHY_WATCHDOG_NON_IDLE_ENABLE |
2087 AR_PHY_WATCHDOG_IDLE_MASK |
2088 (AR_PHY_WATCHDOG_NON_IDLE_MASK & (idle_count << 2)));
2089
2090 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n",
2091 idle_tmo_ms);
2092 }
2093
2094 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah)
2095 {
2096 /*
2097 * we want to avoid printing in ISR context so we save the
2098 * watchdog status to be printed later in bottom half context.
2099 */
2100 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS);
2101
2102 /*
2103 * the watchdog timer should reset on status read but to be sure
2104 * sure we write 0 to the watchdog status bit.
2105 */
2106 REG_WRITE(ah, AR_PHY_WATCHDOG_STATUS,
2107 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR);
2108 }
2109
2110 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah)
2111 {
2112 struct ath_common *common = ath9k_hw_common(ah);
2113 u32 status;
2114
2115 if (likely(!(common->debug_mask & ATH_DBG_RESET)))
2116 return;
2117
2118 status = ah->bb_watchdog_last_status;
2119 ath_dbg(common, RESET,
2120 "\n==== BB update: BB status=0x%08x ====\n", status);
2121 ath_dbg(common, RESET,
2122 "** BB state: wd=%u det=%u rdar=%u rOFDM=%d rCCK=%u tOFDM=%u tCCK=%u agc=%u src=%u **\n",
2123 MS(status, AR_PHY_WATCHDOG_INFO),
2124 MS(status, AR_PHY_WATCHDOG_DET_HANG),
2125 MS(status, AR_PHY_WATCHDOG_RADAR_SM),
2126 MS(status, AR_PHY_WATCHDOG_RX_OFDM_SM),
2127 MS(status, AR_PHY_WATCHDOG_RX_CCK_SM),
2128 MS(status, AR_PHY_WATCHDOG_TX_OFDM_SM),
2129 MS(status, AR_PHY_WATCHDOG_TX_CCK_SM),
2130 MS(status, AR_PHY_WATCHDOG_AGC_SM),
2131 MS(status, AR_PHY_WATCHDOG_SRCH_SM));
2132
2133 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n",
2134 REG_READ(ah, AR_PHY_WATCHDOG_CTL_1),
2135 REG_READ(ah, AR_PHY_WATCHDOG_CTL_2));
2136 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n",
2137 REG_READ(ah, AR_PHY_GEN_CTRL));
2138
2139 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles)
2140 if (common->cc_survey.cycles)
2141 ath_dbg(common, RESET,
2142 "** BB busy times: rx_clear=%d%%, rx_frame=%d%%, tx_frame=%d%% **\n",
2143 PCT(rx_busy), PCT(rx_frame), PCT(tx_frame));
2144
2145 ath_dbg(common, RESET, "==== BB update: done ====\n\n");
2146 }
2147 EXPORT_SYMBOL(ar9003_hw_bb_watchdog_dbg_info);
2148
2149 void ar9003_hw_disable_phy_restart(struct ath_hw *ah)
2150 {
2151 u8 result;
2152 u32 val;
2153
2154 /* While receiving unsupported rate frame rx state machine
2155 * gets into a state 0xb and if phy_restart happens in that
2156 * state, BB would go hang. If RXSM is in 0xb state after
2157 * first bb panic, ensure to disable the phy_restart.
2158 */
2159 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM);
2160
2161 if ((result == 0xb) || ah->bb_hang_rx_ofdm) {
2162 ah->bb_hang_rx_ofdm = true;
2163 val = REG_READ(ah, AR_PHY_RESTART);
2164 val &= ~AR_PHY_RESTART_ENA;
2165 REG_WRITE(ah, AR_PHY_RESTART, val);
2166 }
2167 }
2168 EXPORT_SYMBOL(ar9003_hw_disable_phy_restart);
Kernel DRM miscellaneous fixes and cross-tree changes