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drm/rockchip: Don't change hdmi reference clock rate
[drm/drm-misc.git] / drivers / net / wireless / intel / ipw2x00 / ipw2200.h
blob19310fd0d8eb33054dccfeccc5a3fafe5a32a94c
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /******************************************************************************
3
4 Copyright(c) 2003 - 2006 Intel Corporation. All rights reserved.
5
6
7 Contact Information:
8 Intel Linux Wireless <ilw@linux.intel.com>
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
10
11 ******************************************************************************/
12
13 #ifndef __ipw2200_h__
14 #define __ipw2200_h__
15
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/interrupt.h>
19 #include <linux/mutex.h>
20
21 #include <linux/pci.h>
22 #include <linux/netdevice.h>
23 #include <linux/ethtool.h>
24 #include <linux/skbuff.h>
25 #include <linux/etherdevice.h>
26 #include <linux/delay.h>
27 #include <linux/random.h>
28 #include <linux/dma-mapping.h>
29
30 #include <linux/firmware.h>
31 #include <linux/wireless.h>
32 #include <linux/jiffies.h>
33 #include <asm/io.h>
34 #include <net/ieee80211_radiotap.h>
35
36 #define DRV_NAME "ipw2200"
37
38 #include <linux/workqueue.h>
39
40 #include "libipw.h"
41
42 /* Authentication and Association States */
43 enum connection_manager_assoc_states {
44 CMAS_INIT = 0,
45 CMAS_TX_AUTH_SEQ_1,
46 CMAS_RX_AUTH_SEQ_2,
47 CMAS_AUTH_SEQ_1_PASS,
48 CMAS_AUTH_SEQ_1_FAIL,
49 CMAS_TX_AUTH_SEQ_3,
50 CMAS_RX_AUTH_SEQ_4,
51 CMAS_AUTH_SEQ_2_PASS,
52 CMAS_AUTH_SEQ_2_FAIL,
53 CMAS_AUTHENTICATED,
54 CMAS_TX_ASSOC,
55 CMAS_RX_ASSOC_RESP,
56 CMAS_ASSOCIATED,
57 CMAS_LAST
58 };
59
60 #define IPW_WAIT (1<<0)
61 #define IPW_QUIET (1<<1)
62 #define IPW_ROAMING (1<<2)
63
64 #define IPW_POWER_MODE_CAM 0x00 //(always on)
65 #define IPW_POWER_INDEX_1 0x01
66 #define IPW_POWER_INDEX_2 0x02
67 #define IPW_POWER_INDEX_3 0x03
68 #define IPW_POWER_INDEX_4 0x04
69 #define IPW_POWER_INDEX_5 0x05
70 #define IPW_POWER_AC 0x06
71 #define IPW_POWER_BATTERY 0x07
72 #define IPW_POWER_LIMIT 0x07
73 #define IPW_POWER_MASK 0x0F
74 #define IPW_POWER_ENABLED 0x10
75 #define IPW_POWER_LEVEL(x) ((x) & IPW_POWER_MASK)
76
77 #define IPW_CMD_HOST_COMPLETE 2
78 #define IPW_CMD_POWER_DOWN 4
79 #define IPW_CMD_SYSTEM_CONFIG 6
80 #define IPW_CMD_MULTICAST_ADDRESS 7
81 #define IPW_CMD_SSID 8
82 #define IPW_CMD_ADAPTER_ADDRESS 11
83 #define IPW_CMD_PORT_TYPE 12
84 #define IPW_CMD_RTS_THRESHOLD 15
85 #define IPW_CMD_FRAG_THRESHOLD 16
86 #define IPW_CMD_POWER_MODE 17
87 #define IPW_CMD_WEP_KEY 18
88 #define IPW_CMD_TGI_TX_KEY 19
89 #define IPW_CMD_SCAN_REQUEST 20
90 #define IPW_CMD_ASSOCIATE 21
91 #define IPW_CMD_SUPPORTED_RATES 22
92 #define IPW_CMD_SCAN_ABORT 23
93 #define IPW_CMD_TX_FLUSH 24
94 #define IPW_CMD_QOS_PARAMETERS 25
95 #define IPW_CMD_SCAN_REQUEST_EXT 26
96 #define IPW_CMD_DINO_CONFIG 30
97 #define IPW_CMD_RSN_CAPABILITIES 31
98 #define IPW_CMD_RX_KEY 32
99 #define IPW_CMD_CARD_DISABLE 33
100 #define IPW_CMD_SEED_NUMBER 34
101 #define IPW_CMD_TX_POWER 35
102 #define IPW_CMD_COUNTRY_INFO 36
103 #define IPW_CMD_AIRONET_INFO 37
104 #define IPW_CMD_AP_TX_POWER 38
105 #define IPW_CMD_CCKM_INFO 39
106 #define IPW_CMD_CCX_VER_INFO 40
107 #define IPW_CMD_SET_CALIBRATION 41
108 #define IPW_CMD_SENSITIVITY_CALIB 42
109 #define IPW_CMD_RETRY_LIMIT 51
110 #define IPW_CMD_IPW_PRE_POWER_DOWN 58
111 #define IPW_CMD_VAP_BEACON_TEMPLATE 60
112 #define IPW_CMD_VAP_DTIM_PERIOD 61
113 #define IPW_CMD_EXT_SUPPORTED_RATES 62
114 #define IPW_CMD_VAP_LOCAL_TX_PWR_CONSTRAINT 63
115 #define IPW_CMD_VAP_QUIET_INTERVALS 64
116 #define IPW_CMD_VAP_CHANNEL_SWITCH 65
117 #define IPW_CMD_VAP_MANDATORY_CHANNELS 66
118 #define IPW_CMD_VAP_CELL_PWR_LIMIT 67
119 #define IPW_CMD_VAP_CF_PARAM_SET 68
120 #define IPW_CMD_VAP_SET_BEACONING_STATE 69
121 #define IPW_CMD_MEASUREMENT 80
122 #define IPW_CMD_POWER_CAPABILITY 81
123 #define IPW_CMD_SUPPORTED_CHANNELS 82
124 #define IPW_CMD_TPC_REPORT 83
125 #define IPW_CMD_WME_INFO 84
126 #define IPW_CMD_PRODUCTION_COMMAND 85
127 #define IPW_CMD_LINKSYS_EOU_INFO 90
128
129 #define RFD_SIZE 4
130 #define NUM_TFD_CHUNKS 6
131
132 #define TX_QUEUE_SIZE 32
133 #define RX_QUEUE_SIZE 32
134
135 #define DINO_CMD_WEP_KEY 0x08
136 #define DINO_CMD_TX 0x0B
137 #define DCT_ANTENNA_A 0x01
138 #define DCT_ANTENNA_B 0x02
139
140 #define IPW_A_MODE 0
141 #define IPW_B_MODE 1
142 #define IPW_G_MODE 2
143
144 /*
145 * TX Queue Flag Definitions
146 */
147
148 /* tx wep key definition */
149 #define DCT_WEP_KEY_NOT_IMMIDIATE 0x00
150 #define DCT_WEP_KEY_64Bit 0x40
151 #define DCT_WEP_KEY_128Bit 0x80
152 #define DCT_WEP_KEY_128bitIV 0xC0
153 #define DCT_WEP_KEY_SIZE_MASK 0xC0
154
155 #define DCT_WEP_KEY_INDEX_MASK 0x0F
156 #define DCT_WEP_INDEX_USE_IMMEDIATE 0x20
157
158 /* abort attempt if mgmt frame is rx'd */
159 #define DCT_FLAG_ABORT_MGMT 0x01
160
161 /* require CTS */
162 #define DCT_FLAG_CTS_REQUIRED 0x02
163
164 /* use short preamble */
165 #define DCT_FLAG_LONG_PREAMBLE 0x00
166 #define DCT_FLAG_SHORT_PREAMBLE 0x04
167
168 /* RTS/CTS first */
169 #define DCT_FLAG_RTS_REQD 0x08
170
171 /* dont calculate duration field */
172 #define DCT_FLAG_DUR_SET 0x10
173
174 /* even if MAC WEP set (allows pre-encrypt) */
175 #define DCT_FLAG_NO_WEP 0x20
176
177 /* overwrite TSF field */
178 #define DCT_FLAG_TSF_REQD 0x40
179
180 /* ACK rx is expected to follow */
181 #define DCT_FLAG_ACK_REQD 0x80
182
183 /* TX flags extension */
184 #define DCT_FLAG_EXT_MODE_CCK 0x01
185 #define DCT_FLAG_EXT_MODE_OFDM 0x00
186
187 #define DCT_FLAG_EXT_SECURITY_WEP 0x00
188 #define DCT_FLAG_EXT_SECURITY_NO DCT_FLAG_EXT_SECURITY_WEP
189 #define DCT_FLAG_EXT_SECURITY_CKIP 0x04
190 #define DCT_FLAG_EXT_SECURITY_CCM 0x08
191 #define DCT_FLAG_EXT_SECURITY_TKIP 0x0C
192 #define DCT_FLAG_EXT_SECURITY_MASK 0x0C
193
194 #define DCT_FLAG_EXT_QOS_ENABLED 0x10
195
196 #define DCT_FLAG_EXT_HC_NO_SIFS_PIFS 0x00
197 #define DCT_FLAG_EXT_HC_SIFS 0x20
198 #define DCT_FLAG_EXT_HC_PIFS 0x40
199
200 #define TX_RX_TYPE_MASK 0xFF
201 #define TX_FRAME_TYPE 0x00
202 #define TX_HOST_COMMAND_TYPE 0x01
203 #define RX_FRAME_TYPE 0x09
204 #define RX_HOST_NOTIFICATION_TYPE 0x03
205 #define RX_HOST_CMD_RESPONSE_TYPE 0x04
206 #define RX_TX_FRAME_RESPONSE_TYPE 0x05
207 #define TFD_NEED_IRQ_MASK 0x04
208
209 #define HOST_CMD_DINO_CONFIG 30
210
211 #define HOST_NOTIFICATION_STATUS_ASSOCIATED 10
212 #define HOST_NOTIFICATION_STATUS_AUTHENTICATE 11
213 #define HOST_NOTIFICATION_STATUS_SCAN_CHANNEL_RESULT 12
214 #define HOST_NOTIFICATION_STATUS_SCAN_COMPLETED 13
215 #define HOST_NOTIFICATION_STATUS_FRAG_LENGTH 14
216 #define HOST_NOTIFICATION_STATUS_LINK_DETERIORATION 15
217 #define HOST_NOTIFICATION_DINO_CONFIG_RESPONSE 16
218 #define HOST_NOTIFICATION_STATUS_BEACON_STATE 17
219 #define HOST_NOTIFICATION_STATUS_TGI_TX_KEY 18
220 #define HOST_NOTIFICATION_TX_STATUS 19
221 #define HOST_NOTIFICATION_CALIB_KEEP_RESULTS 20
222 #define HOST_NOTIFICATION_MEASUREMENT_STARTED 21
223 #define HOST_NOTIFICATION_MEASUREMENT_ENDED 22
224 #define HOST_NOTIFICATION_CHANNEL_SWITCHED 23
225 #define HOST_NOTIFICATION_RX_DURING_QUIET_PERIOD 24
226 #define HOST_NOTIFICATION_NOISE_STATS 25
227 #define HOST_NOTIFICATION_S36_MEASUREMENT_ACCEPTED 30
228 #define HOST_NOTIFICATION_S36_MEASUREMENT_REFUSED 31
229
230 #define HOST_NOTIFICATION_STATUS_BEACON_MISSING 1
231 #define IPW_MB_SCAN_CANCEL_THRESHOLD 3
232 #define IPW_MB_ROAMING_THRESHOLD_MIN 1
233 #define IPW_MB_ROAMING_THRESHOLD_DEFAULT 8
234 #define IPW_MB_ROAMING_THRESHOLD_MAX 30
235 #define IPW_MB_DISASSOCIATE_THRESHOLD_DEFAULT 3*IPW_MB_ROAMING_THRESHOLD_DEFAULT
236 #define IPW_REAL_RATE_RX_PACKET_THRESHOLD 300
237
238 #define MACADRR_BYTE_LEN 6
239
240 #define DCR_TYPE_AP 0x01
241 #define DCR_TYPE_WLAP 0x02
242 #define DCR_TYPE_MU_ESS 0x03
243 #define DCR_TYPE_MU_IBSS 0x04
244 #define DCR_TYPE_MU_PIBSS 0x05
245 #define DCR_TYPE_SNIFFER 0x06
246 #define DCR_TYPE_MU_BSS DCR_TYPE_MU_ESS
247
248 /* QoS definitions */
249
250 #define CW_MIN_OFDM 15
251 #define CW_MAX_OFDM 1023
252 #define CW_MIN_CCK 31
253 #define CW_MAX_CCK 1023
254
255 #define QOS_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
256 #define QOS_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
257 #define QOS_TX2_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)
258 #define QOS_TX3_CW_MIN_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/4 - 1)
259
260 #define QOS_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
261 #define QOS_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
262 #define QOS_TX2_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)
263 #define QOS_TX3_CW_MIN_CCK cpu_to_le16((CW_MIN_CCK + 1)/4 - 1)
264
265 #define QOS_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
266 #define QOS_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
267 #define QOS_TX2_CW_MAX_OFDM cpu_to_le16(CW_MIN_OFDM)
268 #define QOS_TX3_CW_MAX_OFDM cpu_to_le16((CW_MIN_OFDM + 1)/2 - 1)
269
270 #define QOS_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
271 #define QOS_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
272 #define QOS_TX2_CW_MAX_CCK cpu_to_le16(CW_MIN_CCK)
273 #define QOS_TX3_CW_MAX_CCK cpu_to_le16((CW_MIN_CCK + 1)/2 - 1)
274
275 #define QOS_TX0_AIFS (3 - QOS_AIFSN_MIN_VALUE)
276 #define QOS_TX1_AIFS (7 - QOS_AIFSN_MIN_VALUE)
277 #define QOS_TX2_AIFS (2 - QOS_AIFSN_MIN_VALUE)
278 #define QOS_TX3_AIFS (2 - QOS_AIFSN_MIN_VALUE)
279
280 #define QOS_TX0_ACM 0
281 #define QOS_TX1_ACM 0
282 #define QOS_TX2_ACM 0
283 #define QOS_TX3_ACM 0
284
285 #define QOS_TX0_TXOP_LIMIT_CCK 0
286 #define QOS_TX1_TXOP_LIMIT_CCK 0
287 #define QOS_TX2_TXOP_LIMIT_CCK cpu_to_le16(6016)
288 #define QOS_TX3_TXOP_LIMIT_CCK cpu_to_le16(3264)
289
290 #define QOS_TX0_TXOP_LIMIT_OFDM 0
291 #define QOS_TX1_TXOP_LIMIT_OFDM 0
292 #define QOS_TX2_TXOP_LIMIT_OFDM cpu_to_le16(3008)
293 #define QOS_TX3_TXOP_LIMIT_OFDM cpu_to_le16(1504)
294
295 #define DEF_TX0_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
296 #define DEF_TX1_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
297 #define DEF_TX2_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
298 #define DEF_TX3_CW_MIN_OFDM cpu_to_le16(CW_MIN_OFDM)
299
300 #define DEF_TX0_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
301 #define DEF_TX1_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
302 #define DEF_TX2_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
303 #define DEF_TX3_CW_MIN_CCK cpu_to_le16(CW_MIN_CCK)
304
305 #define DEF_TX0_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
306 #define DEF_TX1_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
307 #define DEF_TX2_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
308 #define DEF_TX3_CW_MAX_OFDM cpu_to_le16(CW_MAX_OFDM)
309
310 #define DEF_TX0_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
311 #define DEF_TX1_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
312 #define DEF_TX2_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
313 #define DEF_TX3_CW_MAX_CCK cpu_to_le16(CW_MAX_CCK)
314
315 #define DEF_TX0_AIFS 0
316 #define DEF_TX1_AIFS 0
317 #define DEF_TX2_AIFS 0
318 #define DEF_TX3_AIFS 0
319
320 #define DEF_TX0_ACM 0
321 #define DEF_TX1_ACM 0
322 #define DEF_TX2_ACM 0
323 #define DEF_TX3_ACM 0
324
325 #define DEF_TX0_TXOP_LIMIT_CCK 0
326 #define DEF_TX1_TXOP_LIMIT_CCK 0
327 #define DEF_TX2_TXOP_LIMIT_CCK 0
328 #define DEF_TX3_TXOP_LIMIT_CCK 0
329
330 #define DEF_TX0_TXOP_LIMIT_OFDM 0
331 #define DEF_TX1_TXOP_LIMIT_OFDM 0
332 #define DEF_TX2_TXOP_LIMIT_OFDM 0
333 #define DEF_TX3_TXOP_LIMIT_OFDM 0
334
335 #define QOS_QOS_SETS 3
336 #define QOS_PARAM_SET_ACTIVE 0
337 #define QOS_PARAM_SET_DEF_CCK 1
338 #define QOS_PARAM_SET_DEF_OFDM 2
339
340 #define CTRL_QOS_NO_ACK (0x0020)
341
342 #define IPW_TX_QUEUE_1 1
343 #define IPW_TX_QUEUE_2 2
344 #define IPW_TX_QUEUE_3 3
345 #define IPW_TX_QUEUE_4 4
346
347 /* QoS sturctures */
348 struct ipw_qos_info {
349 int qos_enable;
350 struct libipw_qos_parameters *def_qos_parm_OFDM;
351 struct libipw_qos_parameters *def_qos_parm_CCK;
352 u32 burst_duration_CCK;
353 u32 burst_duration_OFDM;
354 u16 qos_no_ack_mask;
355 int burst_enable;
356 };
357
358 /**************************************************************/
359 /**
360 * Generic queue structure
361 *
362 * Contains common data for Rx and Tx queues
363 */
364 struct clx2_queue {
365 int n_bd; /**< number of BDs in this queue */
366 int first_empty; /**< 1-st empty entry (index) */
367 int last_used; /**< last used entry (index) */
368 u32 reg_w; /**< 'write' reg (queue head), addr in domain 1 */
369 u32 reg_r; /**< 'read' reg (queue tail), addr in domain 1 */
370 dma_addr_t dma_addr; /**< physical addr for BD's */
371 int low_mark; /**< low watermark, resume queue if free space more than this */
372 int high_mark; /**< high watermark, stop queue if free space less than this */
373 } __packed; /* XXX */
374
375 struct machdr32 {
376 __le16 frame_ctl;
377 __le16 duration; // watch out for endians!
378 u8 addr1[MACADRR_BYTE_LEN];
379 u8 addr2[MACADRR_BYTE_LEN];
380 u8 addr3[MACADRR_BYTE_LEN];
381 __le16 seq_ctrl; // more endians!
382 u8 addr4[MACADRR_BYTE_LEN];
383 __le16 qos_ctrl;
384 } __packed;
385
386 struct machdr30 {
387 __le16 frame_ctl;
388 __le16 duration; // watch out for endians!
389 u8 addr1[MACADRR_BYTE_LEN];
390 u8 addr2[MACADRR_BYTE_LEN];
391 u8 addr3[MACADRR_BYTE_LEN];
392 __le16 seq_ctrl; // more endians!
393 u8 addr4[MACADRR_BYTE_LEN];
394 } __packed;
395
396 struct machdr26 {
397 __le16 frame_ctl;
398 __le16 duration; // watch out for endians!
399 u8 addr1[MACADRR_BYTE_LEN];
400 u8 addr2[MACADRR_BYTE_LEN];
401 u8 addr3[MACADRR_BYTE_LEN];
402 __le16 seq_ctrl; // more endians!
403 __le16 qos_ctrl;
404 } __packed;
405
406 struct machdr24 {
407 __le16 frame_ctl;
408 __le16 duration; // watch out for endians!
409 u8 addr1[MACADRR_BYTE_LEN];
410 u8 addr2[MACADRR_BYTE_LEN];
411 u8 addr3[MACADRR_BYTE_LEN];
412 __le16 seq_ctrl; // more endians!
413 } __packed;
414
415 // TX TFD with 32 byte MAC Header
416 struct tx_tfd_32 {
417 struct machdr32 mchdr; // 32
418 __le32 uivplaceholder[2]; // 8
419 } __packed;
420
421 // TX TFD with 30 byte MAC Header
422 struct tx_tfd_30 {
423 struct machdr30 mchdr; // 30
424 u8 reserved[2]; // 2
425 __le32 uivplaceholder[2]; // 8
426 } __packed;
427
428 // tx tfd with 26 byte mac header
429 struct tx_tfd_26 {
430 struct machdr26 mchdr; // 26
431 u8 reserved1[2]; // 2
432 __le32 uivplaceholder[2]; // 8
433 u8 reserved2[4]; // 4
434 } __packed;
435
436 // tx tfd with 24 byte mac header
437 struct tx_tfd_24 {
438 struct machdr24 mchdr; // 24
439 __le32 uivplaceholder[2]; // 8
440 u8 reserved[8]; // 8
441 } __packed;
442
443 #define DCT_WEP_KEY_FIELD_LENGTH 16
444
445 struct tfd_command {
446 u8 index;
447 u8 length;
448 __le16 reserved;
449 u8 payload[];
450 } __packed;
451
452 struct tfd_data {
453 /* Header */
454 __le32 work_area_ptr;
455 u8 station_number; /* 0 for BSS */
456 u8 reserved1;
457 __le16 reserved2;
458
459 /* Tx Parameters */
460 u8 cmd_id;
461 u8 seq_num;
462 __le16 len;
463 u8 priority;
464 u8 tx_flags;
465 u8 tx_flags_ext;
466 u8 key_index;
467 u8 wepkey[DCT_WEP_KEY_FIELD_LENGTH];
468 u8 rate;
469 u8 antenna;
470 __le16 next_packet_duration;
471 __le16 next_frag_len;
472 __le16 back_off_counter; //////txop;
473 u8 retrylimit;
474 __le16 cwcurrent;
475 u8 reserved3;
476
477 /* 802.11 MAC Header */
478 union {
479 struct tx_tfd_24 tfd_24;
480 struct tx_tfd_26 tfd_26;
481 struct tx_tfd_30 tfd_30;
482 struct tx_tfd_32 tfd_32;
483 } tfd;
484
485 /* Payload DMA info */
486 __le32 num_chunks;
487 __le32 chunk_ptr[NUM_TFD_CHUNKS];
488 __le16 chunk_len[NUM_TFD_CHUNKS];
489 } __packed;
490
491 struct txrx_control_flags {
492 u8 message_type;
493 u8 rx_seq_num;
494 u8 control_bits;
495 u8 reserved;
496 } __packed;
497
498 #define TFD_SIZE 128
499 #define TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH (TFD_SIZE - sizeof(struct txrx_control_flags))
500
501 struct tfd_frame {
502 struct txrx_control_flags control_flags;
503 union {
504 struct tfd_data data;
505 struct tfd_command cmd;
506 u8 raw[TFD_CMD_IMMEDIATE_PAYLOAD_LENGTH];
507 } u;
508 } __packed;
509
510 typedef void destructor_func(const void *);
511
512 /**
513 * Tx Queue for DMA. Queue consists of circular buffer of
514 * BD's and required locking structures.
515 */
516 struct clx2_tx_queue {
517 struct clx2_queue q;
518 struct tfd_frame *bd;
519 struct libipw_txb **txb;
520 };
521
522 /*
523 * RX related structures and functions
524 */
525 #define RX_FREE_BUFFERS 32
526 #define RX_LOW_WATERMARK 8
527
528 #define SUP_RATE_11A_MAX_NUM_CHANNELS 8
529 #define SUP_RATE_11B_MAX_NUM_CHANNELS 4
530 #define SUP_RATE_11G_MAX_NUM_CHANNELS 12
531
532 // Used for passing to driver number of successes and failures per rate
533 struct rate_histogram {
534 union {
535 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
536 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
537 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
538 } success;
539 union {
540 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
541 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
542 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
543 } failed;
544 } __packed;
545
546 /* statistics command response */
547 struct ipw_cmd_stats {
548 u8 cmd_id;
549 u8 seq_num;
550 __le16 good_sfd;
551 __le16 bad_plcp;
552 __le16 wrong_bssid;
553 __le16 valid_mpdu;
554 __le16 bad_mac_header;
555 __le16 reserved_frame_types;
556 __le16 rx_ina;
557 __le16 bad_crc32;
558 __le16 invalid_cts;
559 __le16 invalid_acks;
560 __le16 long_distance_ina_fina;
561 __le16 dsp_silence_unreachable;
562 __le16 accumulated_rssi;
563 __le16 rx_ovfl_frame_tossed;
564 __le16 rssi_silence_threshold;
565 __le16 rx_ovfl_frame_supplied;
566 __le16 last_rx_frame_signal;
567 __le16 last_rx_frame_noise;
568 __le16 rx_autodetec_no_ofdm;
569 __le16 rx_autodetec_no_barker;
570 __le16 reserved;
571 } __packed;
572
573 struct notif_channel_result {
574 u8 channel_num;
575 struct ipw_cmd_stats stats;
576 u8 uReserved;
577 } __packed;
578
579 #define SCAN_COMPLETED_STATUS_COMPLETE 1
580 #define SCAN_COMPLETED_STATUS_ABORTED 2
581
582 struct notif_scan_complete {
583 u8 scan_type;
584 u8 num_channels;
585 u8 status;
586 u8 reserved;
587 } __packed;
588
589 struct notif_frag_length {
590 __le16 frag_length;
591 __le16 reserved;
592 } __packed;
593
594 struct notif_beacon_state {
595 __le32 state;
596 __le32 number;
597 } __packed;
598
599 struct notif_tgi_tx_key {
600 u8 key_state;
601 u8 security_type;
602 u8 station_index;
603 u8 reserved;
604 } __packed;
605
606 #define SILENCE_OVER_THRESH (1)
607 #define SILENCE_UNDER_THRESH (2)
608
609 struct notif_link_deterioration {
610 struct ipw_cmd_stats stats;
611 u8 rate;
612 u8 modulation;
613 struct rate_histogram histogram;
614 u8 silence_notification_type; /* SILENCE_OVER/UNDER_THRESH */
615 __le16 silence_count;
616 } __packed;
617
618 struct notif_association {
619 u8 state;
620 } __packed;
621
622 struct notif_authenticate {
623 u8 state;
624 struct machdr24 addr;
625 __le16 status;
626 } __packed;
627
628 struct notif_calibration {
629 u8 data[104];
630 } __packed;
631
632 struct notif_noise {
633 __le32 value;
634 } __packed;
635
636 struct ipw_rx_notification {
637 u8 reserved[8];
638 u8 subtype;
639 u8 flags;
640 __le16 size;
641 union {
642 struct notif_association assoc;
643 struct notif_authenticate auth;
644 struct notif_channel_result channel_result;
645 struct notif_scan_complete scan_complete;
646 struct notif_frag_length frag_len;
647 struct notif_beacon_state beacon_state;
648 struct notif_tgi_tx_key tgi_tx_key;
649 struct notif_link_deterioration link_deterioration;
650 struct notif_calibration calibration;
651 struct notif_noise noise;
652 DECLARE_FLEX_ARRAY(u8, raw);
653 } u;
654 } __packed;
655
656 struct ipw_rx_frame {
657 __le32 reserved1;
658 u8 parent_tsf[4]; // fw_use[0] is boolean for OUR_TSF_IS_GREATER
659 u8 received_channel; // The channel that this frame was received on.
660 // Note that for .11b this does not have to be
661 // the same as the channel that it was sent.
662 // Filled by LMAC
663 u8 frameStatus;
664 u8 rate;
665 u8 rssi;
666 u8 agc;
667 u8 rssi_dbm;
668 __le16 signal;
669 __le16 noise;
670 u8 antennaAndPhy;
671 u8 control; // control bit should be on in bg
672 u8 rtscts_rate; // rate of rts or cts (in rts cts sequence rate
673 // is identical)
674 u8 rtscts_seen; // 0x1 RTS seen ; 0x2 CTS seen
675 __le16 length;
676 u8 data[];
677 } __packed;
678
679 struct ipw_rx_header {
680 u8 message_type;
681 u8 rx_seq_num;
682 u8 control_bits;
683 u8 reserved;
684 } __packed;
685
686 struct ipw_rx_packet {
687 struct ipw_rx_header header;
688 union {
689 struct ipw_rx_frame frame;
690 struct ipw_rx_notification notification;
691 } u;
692 } __packed;
693
694 #define IPW_RX_NOTIFICATION_SIZE sizeof(struct ipw_rx_header) + 12
695 #define IPW_RX_FRAME_SIZE (unsigned int)(sizeof(struct ipw_rx_header) + \
696 sizeof(struct ipw_rx_frame))
697
698 struct ipw_rx_mem_buffer {
699 dma_addr_t dma_addr;
700 struct sk_buff *skb;
701 struct list_head list;
702 }; /* Not transferred over network, so not __packed */
703
704 struct ipw_rx_queue {
705 struct ipw_rx_mem_buffer pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
706 struct ipw_rx_mem_buffer *queue[RX_QUEUE_SIZE];
707 u32 processed; /* Internal index to last handled Rx packet */
708 u32 read; /* Shared index to newest available Rx buffer */
709 u32 write; /* Shared index to oldest written Rx packet */
710 u32 free_count; /* Number of pre-allocated buffers in rx_free */
711 /* Each of these lists is used as a FIFO for ipw_rx_mem_buffers */
712 struct list_head rx_free; /* Own an SKBs */
713 struct list_head rx_used; /* No SKB allocated */
714 spinlock_t lock;
715 }; /* Not transferred over network, so not __packed */
716
717 struct alive_command_responce {
718 u8 alive_command;
719 u8 sequence_number;
720 __le16 software_revision;
721 u8 device_identifier;
722 u8 reserved1[5];
723 __le16 reserved2;
724 __le16 reserved3;
725 __le16 clock_settle_time;
726 __le16 powerup_settle_time;
727 __le16 reserved4;
728 u8 time_stamp[5]; /* month, day, year, hours, minutes */
729 u8 ucode_valid;
730 } __packed;
731
732 #define IPW_MAX_RATES 12
733
734 struct ipw_rates {
735 u8 num_rates;
736 u8 rates[IPW_MAX_RATES];
737 } __packed;
738
739 struct command_block {
740 unsigned int control;
741 u32 source_addr;
742 u32 dest_addr;
743 unsigned int status;
744 } __packed;
745
746 #define CB_NUMBER_OF_ELEMENTS_SMALL 64
747 struct fw_image_desc {
748 unsigned long last_cb_index;
749 unsigned long current_cb_index;
750 struct command_block cb_list[CB_NUMBER_OF_ELEMENTS_SMALL];
751 void *v_addr;
752 unsigned long p_addr;
753 unsigned long len;
754 };
755
756 struct ipw_sys_config {
757 u8 bt_coexistence;
758 u8 reserved1;
759 u8 answer_broadcast_ssid_probe;
760 u8 accept_all_data_frames;
761 u8 accept_non_directed_frames;
762 u8 exclude_unicast_unencrypted;
763 u8 disable_unicast_decryption;
764 u8 exclude_multicast_unencrypted;
765 u8 disable_multicast_decryption;
766 u8 antenna_diversity;
767 u8 pass_crc_to_host;
768 u8 dot11g_auto_detection;
769 u8 enable_cts_to_self;
770 u8 enable_multicast_filtering;
771 u8 bt_coexist_collision_thr;
772 u8 silence_threshold;
773 u8 accept_all_mgmt_bcpr;
774 u8 accept_all_mgmt_frames;
775 u8 pass_noise_stats_to_host;
776 u8 reserved3;
777 } __packed;
778
779 struct ipw_multicast_addr {
780 u8 num_of_multicast_addresses;
781 u8 reserved[3];
782 u8 mac1[6];
783 u8 mac2[6];
784 u8 mac3[6];
785 u8 mac4[6];
786 } __packed;
787
788 #define DCW_WEP_KEY_INDEX_MASK 0x03 /* bits [0:1] */
789 #define DCW_WEP_KEY_SEC_TYPE_MASK 0x30 /* bits [4:5] */
790
791 #define DCW_WEP_KEY_SEC_TYPE_WEP 0x00
792 #define DCW_WEP_KEY_SEC_TYPE_CCM 0x20
793 #define DCW_WEP_KEY_SEC_TYPE_TKIP 0x30
794
795 #define DCW_WEP_KEY_INVALID_SIZE 0x00 /* 0 = Invalid key */
796 #define DCW_WEP_KEY64Bit_SIZE 0x05 /* 64-bit encryption */
797 #define DCW_WEP_KEY128Bit_SIZE 0x0D /* 128-bit encryption */
798 #define DCW_CCM_KEY128Bit_SIZE 0x10 /* 128-bit key */
799 //#define DCW_WEP_KEY128BitIV_SIZE 0x10 /* 128-bit key and 128-bit IV */
800
801 struct ipw_wep_key {
802 u8 cmd_id;
803 u8 seq_num;
804 u8 key_index;
805 u8 key_size;
806 u8 key[16];
807 } __packed;
808
809 struct ipw_tgi_tx_key {
810 u8 key_id;
811 u8 security_type;
812 u8 station_index;
813 u8 flags;
814 u8 key[16];
815 __le32 tx_counter[2];
816 } __packed;
817
818 #define IPW_SCAN_CHANNELS 54
819
820 struct ipw_scan_request {
821 u8 scan_type;
822 __le16 dwell_time;
823 u8 channels_list[IPW_SCAN_CHANNELS];
824 u8 channels_reserved[3];
825 } __packed;
826
827 enum {
828 IPW_SCAN_PASSIVE_TILL_FIRST_BEACON_SCAN = 0,
829 IPW_SCAN_PASSIVE_FULL_DWELL_SCAN,
830 IPW_SCAN_ACTIVE_DIRECT_SCAN,
831 IPW_SCAN_ACTIVE_BROADCAST_SCAN,
832 IPW_SCAN_ACTIVE_BROADCAST_AND_DIRECT_SCAN,
833 IPW_SCAN_TYPES
834 };
835
836 struct ipw_scan_request_ext {
837 __le32 full_scan_index;
838 u8 channels_list[IPW_SCAN_CHANNELS];
839 u8 scan_type[IPW_SCAN_CHANNELS / 2];
840 u8 reserved;
841 __le16 dwell_time[IPW_SCAN_TYPES];
842 } __packed;
843
844 static inline u8 ipw_get_scan_type(struct ipw_scan_request_ext *scan, u8 index)
845 {
846 if (index % 2)
847 return scan->scan_type[index / 2] & 0x0F;
848 else
849 return (scan->scan_type[index / 2] & 0xF0) >> 4;
850 }
851
852 static inline void ipw_set_scan_type(struct ipw_scan_request_ext *scan,
853 u8 index, u8 scan_type)
854 {
855 if (index % 2)
856 scan->scan_type[index / 2] =
857 (scan->scan_type[index / 2] & 0xF0) | (scan_type & 0x0F);
858 else
859 scan->scan_type[index / 2] =
860 (scan->scan_type[index / 2] & 0x0F) |
861 ((scan_type & 0x0F) << 4);
862 }
863
864 struct ipw_associate {
865 u8 channel;
866 #ifdef __LITTLE_ENDIAN_BITFIELD
867 u8 auth_type:4, auth_key:4;
868 #else
869 u8 auth_key:4, auth_type:4;
870 #endif
871 u8 assoc_type;
872 u8 reserved;
873 __le16 policy_support;
874 u8 preamble_length;
875 u8 ieee_mode;
876 u8 bssid[ETH_ALEN];
877 __le32 assoc_tsf_msw;
878 __le32 assoc_tsf_lsw;
879 __le16 capability;
880 __le16 listen_interval;
881 __le16 beacon_interval;
882 u8 dest[ETH_ALEN];
883 __le16 atim_window;
884 u8 smr;
885 u8 reserved1;
886 __le16 reserved2;
887 } __packed;
888
889 struct ipw_supported_rates {
890 u8 ieee_mode;
891 u8 num_rates;
892 u8 purpose;
893 u8 reserved;
894 u8 supported_rates[IPW_MAX_RATES];
895 } __packed;
896
897 struct ipw_rts_threshold {
898 __le16 rts_threshold;
899 __le16 reserved;
900 } __packed;
901
902 struct ipw_frag_threshold {
903 __le16 frag_threshold;
904 __le16 reserved;
905 } __packed;
906
907 struct ipw_retry_limit {
908 u8 short_retry_limit;
909 u8 long_retry_limit;
910 __le16 reserved;
911 } __packed;
912
913 struct ipw_dino_config {
914 __le32 dino_config_addr;
915 __le16 dino_config_size;
916 u8 dino_response;
917 u8 reserved;
918 } __packed;
919
920 struct ipw_aironet_info {
921 u8 id;
922 u8 length;
923 __le16 reserved;
924 } __packed;
925
926 struct ipw_rx_key {
927 u8 station_index;
928 u8 key_type;
929 u8 key_id;
930 u8 key_flag;
931 u8 key[16];
932 u8 station_address[6];
933 u8 key_index;
934 u8 reserved;
935 } __packed;
936
937 struct ipw_country_channel_info {
938 u8 first_channel;
939 u8 no_channels;
940 s8 max_tx_power;
941 } __packed;
942
943 struct ipw_country_info {
944 u8 id;
945 u8 length;
946 u8 country_str[IEEE80211_COUNTRY_STRING_LEN];
947 struct ipw_country_channel_info groups[7];
948 } __packed;
949
950 struct ipw_channel_tx_power {
951 u8 channel_number;
952 s8 tx_power;
953 } __packed;
954
955 #define SCAN_ASSOCIATED_INTERVAL (HZ)
956 #define SCAN_INTERVAL (HZ / 10)
957 #define MAX_A_CHANNELS 37
958 #define MAX_B_CHANNELS 14
959
960 struct ipw_tx_power {
961 u8 num_channels;
962 u8 ieee_mode;
963 struct ipw_channel_tx_power channels_tx_power[MAX_A_CHANNELS];
964 } __packed;
965
966 struct ipw_rsn_capabilities {
967 u8 id;
968 u8 length;
969 __le16 version;
970 } __packed;
971
972 struct ipw_sensitivity_calib {
973 __le16 beacon_rssi_raw;
974 __le16 reserved;
975 } __packed;
976
977 /**
978 * Host command structure.
979 *
980 * On input, the following fields should be filled:
981 * - cmd
982 * - len
983 * - status_len
984 * - param (if needed)
985 *
986 * On output,
987 * - \a status contains status;
988 * - \a param filled with status parameters.
989 */
990 struct ipw_cmd { /* XXX */
991 u32 cmd; /**< Host command */
992 u32 status;/**< Status */
993 u32 status_len;
994 /**< How many 32 bit parameters in the status */
995 u32 len; /**< incoming parameters length, bytes */
996 /**
997 * command parameters.
998 * There should be enough space for incoming and
999 * outcoming parameters.
1000 * Incoming parameters listed 1-st, followed by outcoming params.
1001 * nParams=(len+3)/4+status_len
1002 */
1003 u32 param[];
1004 } __packed;
1005
1006 #define STATUS_HCMD_ACTIVE (1<<0) /**< host command in progress */
1007
1008 #define STATUS_INT_ENABLED (1<<1)
1009 #define STATUS_RF_KILL_HW (1<<2)
1010 #define STATUS_RF_KILL_SW (1<<3)
1011 #define STATUS_RF_KILL_MASK (STATUS_RF_KILL_HW | STATUS_RF_KILL_SW)
1012
1013 #define STATUS_INIT (1<<5)
1014 #define STATUS_AUTH (1<<6)
1015 #define STATUS_ASSOCIATED (1<<7)
1016 #define STATUS_STATE_MASK (STATUS_INIT | STATUS_AUTH | STATUS_ASSOCIATED)
1017
1018 #define STATUS_ASSOCIATING (1<<8)
1019 #define STATUS_DISASSOCIATING (1<<9)
1020 #define STATUS_ROAMING (1<<10)
1021 #define STATUS_EXIT_PENDING (1<<11)
1022 #define STATUS_DISASSOC_PENDING (1<<12)
1023 #define STATUS_STATE_PENDING (1<<13)
1024
1025 #define STATUS_DIRECT_SCAN_PENDING (1<<19)
1026 #define STATUS_SCAN_PENDING (1<<20)
1027 #define STATUS_SCANNING (1<<21)
1028 #define STATUS_SCAN_ABORTING (1<<22)
1029 #define STATUS_SCAN_FORCED (1<<23)
1030
1031 #define STATUS_LED_LINK_ON (1<<24)
1032 #define STATUS_LED_ACT_ON (1<<25)
1033
1034 #define STATUS_INDIRECT_BYTE (1<<28) /* sysfs entry configured for access */
1035 #define STATUS_INDIRECT_DWORD (1<<29) /* sysfs entry configured for access */
1036 #define STATUS_DIRECT_DWORD (1<<30) /* sysfs entry configured for access */
1037
1038 #define STATUS_SECURITY_UPDATED (1<<31) /* Security sync needed */
1039
1040 #define CFG_STATIC_CHANNEL (1<<0) /* Restrict assoc. to single channel */
1041 #define CFG_STATIC_ESSID (1<<1) /* Restrict assoc. to single SSID */
1042 #define CFG_STATIC_BSSID (1<<2) /* Restrict assoc. to single BSSID */
1043 #define CFG_CUSTOM_MAC (1<<3)
1044 #define CFG_PREAMBLE_LONG (1<<4)
1045 #define CFG_ADHOC_PERSIST (1<<5)
1046 #define CFG_ASSOCIATE (1<<6)
1047 #define CFG_FIXED_RATE (1<<7)
1048 #define CFG_ADHOC_CREATE (1<<8)
1049 #define CFG_NO_LED (1<<9)
1050 #define CFG_BACKGROUND_SCAN (1<<10)
1051 #define CFG_SPEED_SCAN (1<<11)
1052 #define CFG_NET_STATS (1<<12)
1053
1054 #define CAP_SHARED_KEY (1<<0) /* Off = OPEN */
1055 #define CAP_PRIVACY_ON (1<<1) /* Off = No privacy */
1056
1057 #define MAX_STATIONS 32
1058 #define IPW_INVALID_STATION (0xff)
1059
1060 struct ipw_station_entry {
1061 u8 mac_addr[ETH_ALEN];
1062 u8 reserved;
1063 u8 support_mode;
1064 };
1065
1066 #define AVG_ENTRIES 8
1067 struct average {
1068 s16 entries[AVG_ENTRIES];
1069 u8 pos;
1070 u8 init;
1071 s32 sum;
1072 };
1073
1074 #define MAX_SPEED_SCAN 100
1075 #define IPW_IBSS_MAC_HASH_SIZE 31
1076
1077 struct ipw_ibss_seq {
1078 u8 mac[ETH_ALEN];
1079 u16 seq_num;
1080 u16 frag_num;
1081 unsigned long packet_time;
1082 struct list_head list;
1083 };
1084
1085 struct ipw_error_elem { /* XXX */
1086 u32 desc;
1087 u32 time;
1088 u32 blink1;
1089 u32 blink2;
1090 u32 link1;
1091 u32 link2;
1092 u32 data;
1093 };
1094
1095 struct ipw_event { /* XXX */
1096 u32 event;
1097 u32 time;
1098 u32 data;
1099 } __packed;
1100
1101 struct ipw_fw_error { /* XXX */
1102 unsigned long jiffies;
1103 u32 status;
1104 u32 config;
1105 u32 elem_len;
1106 u32 log_len;
1107 struct ipw_event *log;
1108 struct ipw_error_elem elem[];
1109 } __packed;
1110
1111 #ifdef CONFIG_IPW2200_PROMISCUOUS
1112
1113 enum ipw_prom_filter {
1114 IPW_PROM_CTL_HEADER_ONLY = (1 << 0),
1115 IPW_PROM_MGMT_HEADER_ONLY = (1 << 1),
1116 IPW_PROM_DATA_HEADER_ONLY = (1 << 2),
1117 IPW_PROM_ALL_HEADER_ONLY = 0xf, /* bits 0..3 */
1118 IPW_PROM_NO_TX = (1 << 4),
1119 IPW_PROM_NO_RX = (1 << 5),
1120 IPW_PROM_NO_CTL = (1 << 6),
1121 IPW_PROM_NO_MGMT = (1 << 7),
1122 IPW_PROM_NO_DATA = (1 << 8),
1123 };
1124
1125 struct ipw_priv;
1126 struct ipw_prom_priv {
1127 struct ipw_priv *priv;
1128 struct libipw_device *ieee;
1129 enum ipw_prom_filter filter;
1130 int tx_packets;
1131 int rx_packets;
1132 };
1133 #endif
1134
1135 #if defined(CONFIG_IPW2200_RADIOTAP) || defined(CONFIG_IPW2200_PROMISCUOUS)
1136 /* Magic struct that slots into the radiotap header -- no reason
1137 * to build this manually element by element, we can write it much
1138 * more efficiently than we can parse it. ORDER MATTERS HERE
1139 *
1140 * When sent to us via the simulated Rx interface in sysfs, the entire
1141 * structure is provided regardless of any bits unset.
1142 */
1143 struct ipw_rt_hdr {
1144 struct ieee80211_radiotap_header_fixed rt_hdr;
1145 u64 rt_tsf; /* TSF */ /* XXX */
1146 u8 rt_flags; /* radiotap packet flags */
1147 u8 rt_rate; /* rate in 500kb/s */
1148 __le16 rt_channel; /* channel in mhz */
1149 __le16 rt_chbitmask; /* channel bitfield */
1150 s8 rt_dbmsignal; /* signal in dbM, kluged to signed */
1151 s8 rt_dbmnoise;
1152 u8 rt_antenna; /* antenna number */
1153 u8 payload[]; /* payload... */
1154 } __packed;
1155 #endif
1156
1157 struct ipw_priv {
1158 /* ieee device used by generic ieee processing code */
1159 struct libipw_device *ieee;
1160
1161 spinlock_t lock;
1162 spinlock_t irq_lock;
1163 struct mutex mutex;
1164
1165 /* basic pci-network driver stuff */
1166 struct pci_dev *pci_dev;
1167 struct net_device *net_dev;
1168
1169 #ifdef CONFIG_IPW2200_PROMISCUOUS
1170 /* Promiscuous mode */
1171 struct ipw_prom_priv *prom_priv;
1172 struct net_device *prom_net_dev;
1173 #endif
1174
1175 /* pci hardware address support */
1176 void __iomem *hw_base;
1177 unsigned long hw_len;
1178
1179 struct fw_image_desc sram_desc;
1180
1181 /* result of ucode download */
1182 struct alive_command_responce dino_alive;
1183
1184 wait_queue_head_t wait_command_queue;
1185 wait_queue_head_t wait_state;
1186
1187 /* Rx and Tx DMA processing queues */
1188 struct ipw_rx_queue *rxq;
1189 struct clx2_tx_queue txq_cmd;
1190 struct clx2_tx_queue txq[4];
1191 u32 status;
1192 u32 config;
1193 u32 capability;
1194
1195 struct average average_missed_beacons;
1196 s16 exp_avg_rssi;
1197 s16 exp_avg_noise;
1198 u32 port_type;
1199 int rx_bufs_min; /**< minimum number of bufs in Rx queue */
1200 int rx_pend_max; /**< maximum pending buffers for one IRQ */
1201 u32 hcmd_seq; /**< sequence number for hcmd */
1202 u32 disassociate_threshold;
1203 u32 roaming_threshold;
1204
1205 struct ipw_associate assoc_request;
1206 struct libipw_network *assoc_network;
1207
1208 unsigned long ts_scan_abort;
1209 struct ipw_supported_rates rates;
1210 struct ipw_rates phy[3]; /**< PHY restrictions, per band */
1211 struct ipw_rates supp; /**< software defined */
1212 struct ipw_rates extended; /**< use for corresp. IE, AP only */
1213
1214 struct notif_link_deterioration last_link_deterioration; /** for statistics */
1215 struct ipw_cmd *hcmd; /**< host command currently executed */
1216
1217 wait_queue_head_t hcmd_wq; /**< host command waits for execution */
1218 u32 tsf_bcn[2]; /**< TSF from latest beacon */
1219
1220 struct notif_calibration calib; /**< last calibration */
1221
1222 /* ordinal interface with firmware */
1223 u32 table0_addr;
1224 u32 table0_len;
1225 u32 table1_addr;
1226 u32 table1_len;
1227 u32 table2_addr;
1228 u32 table2_len;
1229
1230 /* context information */
1231 u8 essid[IW_ESSID_MAX_SIZE];
1232 u8 essid_len;
1233 u8 nick[IW_ESSID_MAX_SIZE];
1234 u16 rates_mask;
1235 u8 channel;
1236 struct ipw_sys_config sys_config;
1237 u32 power_mode;
1238 u8 bssid[ETH_ALEN];
1239 u16 rts_threshold;
1240 u8 mac_addr[ETH_ALEN];
1241 u8 num_stations;
1242 u8 stations[MAX_STATIONS][ETH_ALEN];
1243 u8 short_retry_limit;
1244 u8 long_retry_limit;
1245
1246 u32 notif_missed_beacons;
1247
1248 /* Statistics and counters normalized with each association */
1249 u32 last_missed_beacons;
1250 u32 last_tx_packets;
1251 u32 last_rx_packets;
1252 u32 last_tx_failures;
1253 u32 last_rx_err;
1254 u32 last_rate;
1255
1256 u32 missed_adhoc_beacons;
1257 u32 missed_beacons;
1258 u32 rx_packets;
1259 u32 tx_packets;
1260 u32 quality;
1261
1262 u8 speed_scan[MAX_SPEED_SCAN];
1263 u8 speed_scan_pos;
1264
1265 u16 last_seq_num;
1266 u16 last_frag_num;
1267 unsigned long last_packet_time;
1268 struct list_head ibss_mac_hash[IPW_IBSS_MAC_HASH_SIZE];
1269
1270 /* eeprom */
1271 u8 eeprom[0x100]; /* 256 bytes of eeprom */
1272 u8 country[4];
1273 int eeprom_delay;
1274
1275 struct iw_statistics wstats;
1276
1277 int user_requested_scan;
1278 u8 direct_scan_ssid[IW_ESSID_MAX_SIZE];
1279 u8 direct_scan_ssid_len;
1280
1281 struct delayed_work adhoc_check;
1282 struct work_struct associate;
1283 struct work_struct disassociate;
1284 struct work_struct system_config;
1285 struct work_struct rx_replenish;
1286 struct delayed_work request_scan;
1287 struct delayed_work request_direct_scan;
1288 struct delayed_work request_passive_scan;
1289 struct delayed_work scan_event;
1290 struct work_struct adapter_restart;
1291 struct delayed_work rf_kill;
1292 struct work_struct up;
1293 struct work_struct down;
1294 struct delayed_work gather_stats;
1295 struct work_struct abort_scan;
1296 struct work_struct roam;
1297 struct delayed_work scan_check;
1298 struct work_struct link_up;
1299 struct work_struct link_down;
1300
1301 struct tasklet_struct irq_tasklet;
1302
1303 /* LED related variables and work_struct */
1304 u8 nic_type;
1305 u32 led_activity_on;
1306 u32 led_activity_off;
1307 u32 led_association_on;
1308 u32 led_association_off;
1309 u32 led_ofdm_on;
1310 u32 led_ofdm_off;
1311
1312 struct delayed_work led_link_on;
1313 struct delayed_work led_link_off;
1314 struct delayed_work led_act_off;
1315 struct work_struct merge_networks;
1316
1317 struct ipw_cmd_log *cmdlog;
1318 int cmdlog_len;
1319 int cmdlog_pos;
1320
1321 #define IPW_2200BG 1
1322 #define IPW_2915ABG 2
1323 u8 adapter;
1324
1325 s8 tx_power;
1326
1327 /* Track time in suspend using CLOCK_BOOTTIME */
1328 time64_t suspend_at;
1329 time64_t suspend_time;
1330
1331 #ifdef CONFIG_PM
1332 u32 pm_state[16];
1333 #endif
1334
1335 struct ipw_fw_error *error;
1336
1337 /* network state */
1338
1339 /* Used to pass the current INTA value from ISR to Tasklet */
1340 u32 isr_inta;
1341
1342 /* QoS */
1343 struct ipw_qos_info qos_data;
1344 struct work_struct qos_activate;
1345 /*********************************/
1346
1347 /* debugging info */
1348 u32 indirect_dword;
1349 u32 direct_dword;
1350 u32 indirect_byte;
1351 }; /*ipw_priv */
1352
1353 /* debug macros */
1354
1355 /* Debug and printf string expansion helpers for printing bitfields */
1356 #define BIT_FMT8 "%c%c%c%c-%c%c%c%c"
1357 #define BIT_FMT16 BIT_FMT8 ":" BIT_FMT8
1358 #define BIT_FMT32 BIT_FMT16 " " BIT_FMT16
1359
1360 #define BITC(x,y) (((x>>y)&1)?'1':'0')
1361 #define BIT_ARG8(x) \
1362 BITC(x,7),BITC(x,6),BITC(x,5),BITC(x,4),\
1363 BITC(x,3),BITC(x,2),BITC(x,1),BITC(x,0)
1364
1365 #define BIT_ARG16(x) \
1366 BITC(x,15),BITC(x,14),BITC(x,13),BITC(x,12),\
1367 BITC(x,11),BITC(x,10),BITC(x,9),BITC(x,8),\
1368 BIT_ARG8(x)
1369
1370 #define BIT_ARG32(x) \
1371 BITC(x,31),BITC(x,30),BITC(x,29),BITC(x,28),\
1372 BITC(x,27),BITC(x,26),BITC(x,25),BITC(x,24),\
1373 BITC(x,23),BITC(x,22),BITC(x,21),BITC(x,20),\
1374 BITC(x,19),BITC(x,18),BITC(x,17),BITC(x,16),\
1375 BIT_ARG16(x)
1376
1377
1378 #define IPW_DEBUG(level, fmt, args...) \
1379 do { if (ipw_debug_level & (level)) \
1380 printk(KERN_DEBUG DRV_NAME": %s " fmt, __func__ , ## args); } while (0)
1381
1382 #ifdef CONFIG_IPW2200_DEBUG
1383 #define IPW_LL_DEBUG(level, fmt, args...) \
1384 do { if (ipw_debug_level & (level)) \
1385 printk(KERN_DEBUG DRV_NAME": %s " fmt, __func__ , ## args); } while (0)
1386 #else
1387 #define IPW_LL_DEBUG(level, fmt, args...) do {} while (0)
1388 #endif /* CONFIG_IPW2200_DEBUG */
1389
1390 /*
1391 * To use the debug system;
1392 *
1393 * If you are defining a new debug classification, simply add it to the #define
1394 * list here in the form of:
1395 *
1396 * #define IPW_DL_xxxx VALUE
1397 *
1398 * shifting value to the left one bit from the previous entry. xxxx should be
1399 * the name of the classification (for example, WEP)
1400 *
1401 * You then need to either add a IPW_xxxx_DEBUG() macro definition for your
1402 * classification, or use IPW_DEBUG(IPW_DL_xxxx, ...) whenever you want
1403 * to send output to that classification.
1404 *
1405 * To add your debug level to the list of levels seen when you perform
1406 *
1407 * % cat /proc/net/ipw/debug_level
1408 *
1409 * you simply need to add your entry to the ipw_debug_levels array.
1410 *
1411 * If you do not see debug_level in /proc/net/ipw then you do not have
1412 * CONFIG_IPW2200_DEBUG defined in your kernel configuration
1413 *
1414 */
1415
1416 #define IPW_DL_ERROR (1<<0)
1417 #define IPW_DL_WARNING (1<<1)
1418 #define IPW_DL_INFO (1<<2)
1419 #define IPW_DL_WX (1<<3)
1420 #define IPW_DL_HOST_COMMAND (1<<5)
1421 #define IPW_DL_STATE (1<<6)
1422
1423 #define IPW_DL_NOTIF (1<<10)
1424 #define IPW_DL_SCAN (1<<11)
1425 #define IPW_DL_ASSOC (1<<12)
1426 #define IPW_DL_DROP (1<<13)
1427 #define IPW_DL_IOCTL (1<<14)
1428
1429 #define IPW_DL_MANAGE (1<<15)
1430 #define IPW_DL_FW (1<<16)
1431 #define IPW_DL_RF_KILL (1<<17)
1432 #define IPW_DL_FW_ERRORS (1<<18)
1433
1434 #define IPW_DL_LED (1<<19)
1435
1436 #define IPW_DL_ORD (1<<20)
1437
1438 #define IPW_DL_FRAG (1<<21)
1439 #define IPW_DL_WEP (1<<22)
1440 #define IPW_DL_TX (1<<23)
1441 #define IPW_DL_RX (1<<24)
1442 #define IPW_DL_ISR (1<<25)
1443 #define IPW_DL_FW_INFO (1<<26)
1444 #define IPW_DL_IO (1<<27)
1445 #define IPW_DL_TRACE (1<<28)
1446
1447 #define IPW_DL_STATS (1<<29)
1448 #define IPW_DL_MERGE (1<<30)
1449 #define IPW_DL_QOS (1<<31)
1450
1451 #define IPW_ERROR(f, a...) printk(KERN_ERR DRV_NAME ": " f, ## a)
1452 #define IPW_WARNING(f, a...) printk(KERN_WARNING DRV_NAME ": " f, ## a)
1453 #define IPW_DEBUG_INFO(f, a...) IPW_DEBUG(IPW_DL_INFO, f, ## a)
1454
1455 #define IPW_DEBUG_WX(f, a...) IPW_DEBUG(IPW_DL_WX, f, ## a)
1456 #define IPW_DEBUG_SCAN(f, a...) IPW_DEBUG(IPW_DL_SCAN, f, ## a)
1457 #define IPW_DEBUG_TRACE(f, a...) IPW_LL_DEBUG(IPW_DL_TRACE, f, ## a)
1458 #define IPW_DEBUG_RX(f, a...) IPW_LL_DEBUG(IPW_DL_RX, f, ## a)
1459 #define IPW_DEBUG_TX(f, a...) IPW_LL_DEBUG(IPW_DL_TX, f, ## a)
1460 #define IPW_DEBUG_ISR(f, a...) IPW_LL_DEBUG(IPW_DL_ISR, f, ## a)
1461 #define IPW_DEBUG_MANAGEMENT(f, a...) IPW_DEBUG(IPW_DL_MANAGE, f, ## a)
1462 #define IPW_DEBUG_LED(f, a...) IPW_LL_DEBUG(IPW_DL_LED, f, ## a)
1463 #define IPW_DEBUG_WEP(f, a...) IPW_LL_DEBUG(IPW_DL_WEP, f, ## a)
1464 #define IPW_DEBUG_HC(f, a...) IPW_LL_DEBUG(IPW_DL_HOST_COMMAND, f, ## a)
1465 #define IPW_DEBUG_FRAG(f, a...) IPW_LL_DEBUG(IPW_DL_FRAG, f, ## a)
1466 #define IPW_DEBUG_FW(f, a...) IPW_LL_DEBUG(IPW_DL_FW, f, ## a)
1467 #define IPW_DEBUG_RF_KILL(f, a...) IPW_DEBUG(IPW_DL_RF_KILL, f, ## a)
1468 #define IPW_DEBUG_DROP(f, a...) IPW_DEBUG(IPW_DL_DROP, f, ## a)
1469 #define IPW_DEBUG_IO(f, a...) IPW_LL_DEBUG(IPW_DL_IO, f, ## a)
1470 #define IPW_DEBUG_ORD(f, a...) IPW_LL_DEBUG(IPW_DL_ORD, f, ## a)
1471 #define IPW_DEBUG_FW_INFO(f, a...) IPW_LL_DEBUG(IPW_DL_FW_INFO, f, ## a)
1472 #define IPW_DEBUG_NOTIF(f, a...) IPW_DEBUG(IPW_DL_NOTIF, f, ## a)
1473 #define IPW_DEBUG_STATE(f, a...) IPW_DEBUG(IPW_DL_STATE | IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1474 #define IPW_DEBUG_ASSOC(f, a...) IPW_DEBUG(IPW_DL_ASSOC | IPW_DL_INFO, f, ## a)
1475 #define IPW_DEBUG_STATS(f, a...) IPW_LL_DEBUG(IPW_DL_STATS, f, ## a)
1476 #define IPW_DEBUG_MERGE(f, a...) IPW_LL_DEBUG(IPW_DL_MERGE, f, ## a)
1477 #define IPW_DEBUG_QOS(f, a...) IPW_LL_DEBUG(IPW_DL_QOS, f, ## a)
1478
1479 #include <linux/ctype.h>
1480
1481 /*
1482 * Register bit definitions
1483 */
1484
1485 #define IPW_INTA_RW 0x00000008
1486 #define IPW_INTA_MASK_R 0x0000000C
1487 #define IPW_INDIRECT_ADDR 0x00000010
1488 #define IPW_INDIRECT_DATA 0x00000014
1489 #define IPW_AUTOINC_ADDR 0x00000018
1490 #define IPW_AUTOINC_DATA 0x0000001C
1491 #define IPW_RESET_REG 0x00000020
1492 #define IPW_GP_CNTRL_RW 0x00000024
1493
1494 #define IPW_READ_INT_REGISTER 0xFF4
1495
1496 #define IPW_GP_CNTRL_BIT_INIT_DONE 0x00000004
1497
1498 #define IPW_REGISTER_DOMAIN1_END 0x00001000
1499 #define IPW_SRAM_READ_INT_REGISTER 0x00000ff4
1500
1501 #define IPW_SHARED_LOWER_BOUND 0x00000200
1502 #define IPW_INTERRUPT_AREA_LOWER_BOUND 0x00000f80
1503
1504 #define IPW_NIC_SRAM_LOWER_BOUND 0x00000000
1505 #define IPW_NIC_SRAM_UPPER_BOUND 0x00030000
1506
1507 #define IPW_BIT_INT_HOST_SRAM_READ_INT_REGISTER (1 << 29)
1508 #define IPW_GP_CNTRL_BIT_CLOCK_READY 0x00000001
1509 #define IPW_GP_CNTRL_BIT_HOST_ALLOWS_STANDBY 0x00000002
1510
1511 /*
1512 * RESET Register Bit Indexes
1513 */
1514 #define CBD_RESET_REG_PRINCETON_RESET (1<<0)
1515 #define IPW_START_STANDBY (1<<2)
1516 #define IPW_ACTIVITY_LED (1<<4)
1517 #define IPW_ASSOCIATED_LED (1<<5)
1518 #define IPW_OFDM_LED (1<<6)
1519 #define IPW_RESET_REG_SW_RESET (1<<7)
1520 #define IPW_RESET_REG_MASTER_DISABLED (1<<8)
1521 #define IPW_RESET_REG_STOP_MASTER (1<<9)
1522 #define IPW_GATE_ODMA (1<<25)
1523 #define IPW_GATE_IDMA (1<<26)
1524 #define IPW_ARC_KESHET_CONFIG (1<<27)
1525 #define IPW_GATE_ADMA (1<<29)
1526
1527 #define IPW_CSR_CIS_UPPER_BOUND 0x00000200
1528 #define IPW_DOMAIN_0_END 0x1000
1529 #define CLX_MEM_BAR_SIZE 0x1000
1530
1531 /* Dino/baseband control registers bits */
1532
1533 #define DINO_ENABLE_SYSTEM 0x80 /* 1 = baseband processor on, 0 = reset */
1534 #define DINO_ENABLE_CS 0x40 /* 1 = enable ucode load */
1535 #define DINO_RXFIFO_DATA 0x01 /* 1 = data available */
1536 #define IPW_BASEBAND_CONTROL_STATUS 0X00200000
1537 #define IPW_BASEBAND_TX_FIFO_WRITE 0X00200004
1538 #define IPW_BASEBAND_RX_FIFO_READ 0X00200004
1539 #define IPW_BASEBAND_CONTROL_STORE 0X00200010
1540
1541 #define IPW_INTERNAL_CMD_EVENT 0X00300004
1542 #define IPW_BASEBAND_POWER_DOWN 0x00000001
1543
1544 #define IPW_MEM_HALT_AND_RESET 0x003000e0
1545
1546 /* defgroup bits_halt_reset MEM_HALT_AND_RESET register bits */
1547 #define IPW_BIT_HALT_RESET_ON 0x80000000
1548 #define IPW_BIT_HALT_RESET_OFF 0x00000000
1549
1550 #define CB_LAST_VALID 0x20000000
1551 #define CB_INT_ENABLED 0x40000000
1552 #define CB_VALID 0x80000000
1553 #define CB_SRC_LE 0x08000000
1554 #define CB_DEST_LE 0x04000000
1555 #define CB_SRC_AUTOINC 0x00800000
1556 #define CB_SRC_IO_GATED 0x00400000
1557 #define CB_DEST_AUTOINC 0x00080000
1558 #define CB_SRC_SIZE_LONG 0x00200000
1559 #define CB_DEST_SIZE_LONG 0x00020000
1560
1561 /* DMA DEFINES */
1562
1563 #define DMA_CONTROL_SMALL_CB_CONST_VALUE 0x00540000
1564 #define DMA_CB_STOP_AND_ABORT 0x00000C00
1565 #define DMA_CB_START 0x00000100
1566
1567 #define IPW_SHARED_SRAM_SIZE 0x00030000
1568 #define IPW_SHARED_SRAM_DMA_CONTROL 0x00027000
1569 #define CB_MAX_LENGTH 0x1FFF
1570
1571 #define IPW_HOST_EEPROM_DATA_SRAM_SIZE 0xA18
1572 #define IPW_EEPROM_IMAGE_SIZE 0x100
1573
1574 /* DMA defs */
1575 #define IPW_DMA_I_CURRENT_CB 0x003000D0
1576 #define IPW_DMA_O_CURRENT_CB 0x003000D4
1577 #define IPW_DMA_I_DMA_CONTROL 0x003000A4
1578 #define IPW_DMA_I_CB_BASE 0x003000A0
1579
1580 #define IPW_TX_CMD_QUEUE_BD_BASE 0x00000200
1581 #define IPW_TX_CMD_QUEUE_BD_SIZE 0x00000204
1582 #define IPW_TX_QUEUE_0_BD_BASE 0x00000208
1583 #define IPW_TX_QUEUE_0_BD_SIZE (0x0000020C)
1584 #define IPW_TX_QUEUE_1_BD_BASE 0x00000210
1585 #define IPW_TX_QUEUE_1_BD_SIZE 0x00000214
1586 #define IPW_TX_QUEUE_2_BD_BASE 0x00000218
1587 #define IPW_TX_QUEUE_2_BD_SIZE (0x0000021C)
1588 #define IPW_TX_QUEUE_3_BD_BASE 0x00000220
1589 #define IPW_TX_QUEUE_3_BD_SIZE 0x00000224
1590 #define IPW_RX_BD_BASE 0x00000240
1591 #define IPW_RX_BD_SIZE 0x00000244
1592 #define IPW_RFDS_TABLE_LOWER 0x00000500
1593
1594 #define IPW_TX_CMD_QUEUE_READ_INDEX 0x00000280
1595 #define IPW_TX_QUEUE_0_READ_INDEX 0x00000284
1596 #define IPW_TX_QUEUE_1_READ_INDEX 0x00000288
1597 #define IPW_TX_QUEUE_2_READ_INDEX (0x0000028C)
1598 #define IPW_TX_QUEUE_3_READ_INDEX 0x00000290
1599 #define IPW_RX_READ_INDEX (0x000002A0)
1600
1601 #define IPW_TX_CMD_QUEUE_WRITE_INDEX (0x00000F80)
1602 #define IPW_TX_QUEUE_0_WRITE_INDEX (0x00000F84)
1603 #define IPW_TX_QUEUE_1_WRITE_INDEX (0x00000F88)
1604 #define IPW_TX_QUEUE_2_WRITE_INDEX (0x00000F8C)
1605 #define IPW_TX_QUEUE_3_WRITE_INDEX (0x00000F90)
1606 #define IPW_RX_WRITE_INDEX (0x00000FA0)
1607
1608 /*
1609 * EEPROM Related Definitions
1610 */
1611
1612 #define IPW_EEPROM_DATA_SRAM_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x814)
1613 #define IPW_EEPROM_DATA_SRAM_SIZE (IPW_SHARED_LOWER_BOUND + 0x818)
1614 #define IPW_EEPROM_LOAD_DISABLE (IPW_SHARED_LOWER_BOUND + 0x81C)
1615 #define IPW_EEPROM_DATA (IPW_SHARED_LOWER_BOUND + 0x820)
1616 #define IPW_EEPROM_UPPER_ADDRESS (IPW_SHARED_LOWER_BOUND + 0x9E0)
1617
1618 #define IPW_STATION_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0xA0C)
1619 #define IPW_STATION_TABLE_UPPER (IPW_SHARED_LOWER_BOUND + 0xB0C)
1620 #define IPW_REQUEST_ATIM (IPW_SHARED_LOWER_BOUND + 0xB0C)
1621 #define IPW_ATIM_SENT (IPW_SHARED_LOWER_BOUND + 0xB10)
1622 #define IPW_WHO_IS_AWAKE (IPW_SHARED_LOWER_BOUND + 0xB14)
1623 #define IPW_DURING_ATIM_WINDOW (IPW_SHARED_LOWER_BOUND + 0xB18)
1624
1625 #define MSB 1
1626 #define LSB 0
1627 #define WORD_TO_BYTE(_word) ((_word) * sizeof(u16))
1628
1629 #define GET_EEPROM_ADDR(_wordoffset,_byteoffset) \
1630 ( WORD_TO_BYTE(_wordoffset) + (_byteoffset) )
1631
1632 /* EEPROM access by BYTE */
1633 #define EEPROM_PME_CAPABILITY (GET_EEPROM_ADDR(0x09,MSB)) /* 1 byte */
1634 #define EEPROM_MAC_ADDRESS (GET_EEPROM_ADDR(0x21,LSB)) /* 6 byte */
1635 #define EEPROM_VERSION (GET_EEPROM_ADDR(0x24,MSB)) /* 1 byte */
1636 #define EEPROM_NIC_TYPE (GET_EEPROM_ADDR(0x25,LSB)) /* 1 byte */
1637 #define EEPROM_SKU_CAPABILITY (GET_EEPROM_ADDR(0x25,MSB)) /* 1 byte */
1638 #define EEPROM_COUNTRY_CODE (GET_EEPROM_ADDR(0x26,LSB)) /* 3 bytes */
1639 #define EEPROM_IBSS_CHANNELS_BG (GET_EEPROM_ADDR(0x28,LSB)) /* 2 bytes */
1640 #define EEPROM_IBSS_CHANNELS_A (GET_EEPROM_ADDR(0x29,MSB)) /* 5 bytes */
1641 #define EEPROM_BSS_CHANNELS_BG (GET_EEPROM_ADDR(0x2c,LSB)) /* 2 bytes */
1642 #define EEPROM_HW_VERSION (GET_EEPROM_ADDR(0x72,LSB)) /* 2 bytes */
1643
1644 /* NIC type as found in the one byte EEPROM_NIC_TYPE offset */
1645 #define EEPROM_NIC_TYPE_0 0
1646 #define EEPROM_NIC_TYPE_1 1
1647 #define EEPROM_NIC_TYPE_2 2
1648 #define EEPROM_NIC_TYPE_3 3
1649 #define EEPROM_NIC_TYPE_4 4
1650
1651 /* Bluetooth Coexistence capabilities as found in EEPROM_SKU_CAPABILITY */
1652 #define EEPROM_SKU_CAP_BT_CHANNEL_SIG 0x01 /* we can tell BT our channel # */
1653 #define EEPROM_SKU_CAP_BT_PRIORITY 0x02 /* BT can take priority over us */
1654 #define EEPROM_SKU_CAP_BT_OOB 0x04 /* we can signal BT out-of-band */
1655
1656 #define FW_MEM_REG_LOWER_BOUND 0x00300000
1657 #define FW_MEM_REG_EEPROM_ACCESS (FW_MEM_REG_LOWER_BOUND + 0x40)
1658 #define IPW_EVENT_REG (FW_MEM_REG_LOWER_BOUND + 0x04)
1659 #define EEPROM_BIT_SK (1<<0)
1660 #define EEPROM_BIT_CS (1<<1)
1661 #define EEPROM_BIT_DI (1<<2)
1662 #define EEPROM_BIT_DO (1<<4)
1663
1664 #define EEPROM_CMD_READ 0x2
1665
1666 /* Interrupts masks */
1667 #define IPW_INTA_NONE 0x00000000
1668
1669 #define IPW_INTA_BIT_RX_TRANSFER 0x00000002
1670 #define IPW_INTA_BIT_STATUS_CHANGE 0x00000010
1671 #define IPW_INTA_BIT_BEACON_PERIOD_EXPIRED 0x00000020
1672
1673 //Inta Bits for CF
1674 #define IPW_INTA_BIT_TX_CMD_QUEUE 0x00000800
1675 #define IPW_INTA_BIT_TX_QUEUE_1 0x00001000
1676 #define IPW_INTA_BIT_TX_QUEUE_2 0x00002000
1677 #define IPW_INTA_BIT_TX_QUEUE_3 0x00004000
1678 #define IPW_INTA_BIT_TX_QUEUE_4 0x00008000
1679
1680 #define IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE 0x00010000
1681
1682 #define IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN 0x00100000
1683 #define IPW_INTA_BIT_POWER_DOWN 0x00200000
1684
1685 #define IPW_INTA_BIT_FW_INITIALIZATION_DONE 0x01000000
1686 #define IPW_INTA_BIT_FW_CARD_DISABLE_PHY_OFF_DONE 0x02000000
1687 #define IPW_INTA_BIT_RF_KILL_DONE 0x04000000
1688 #define IPW_INTA_BIT_FATAL_ERROR 0x40000000
1689 #define IPW_INTA_BIT_PARITY_ERROR 0x80000000
1690
1691 /* Interrupts enabled at init time. */
1692 #define IPW_INTA_MASK_ALL \
1693 (IPW_INTA_BIT_TX_QUEUE_1 | \
1694 IPW_INTA_BIT_TX_QUEUE_2 | \
1695 IPW_INTA_BIT_TX_QUEUE_3 | \
1696 IPW_INTA_BIT_TX_QUEUE_4 | \
1697 IPW_INTA_BIT_TX_CMD_QUEUE | \
1698 IPW_INTA_BIT_RX_TRANSFER | \
1699 IPW_INTA_BIT_FATAL_ERROR | \
1700 IPW_INTA_BIT_PARITY_ERROR | \
1701 IPW_INTA_BIT_STATUS_CHANGE | \
1702 IPW_INTA_BIT_FW_INITIALIZATION_DONE | \
1703 IPW_INTA_BIT_BEACON_PERIOD_EXPIRED | \
1704 IPW_INTA_BIT_SLAVE_MODE_HOST_CMD_DONE | \
1705 IPW_INTA_BIT_PREPARE_FOR_POWER_DOWN | \
1706 IPW_INTA_BIT_POWER_DOWN | \
1707 IPW_INTA_BIT_RF_KILL_DONE )
1708
1709 /* FW event log definitions */
1710 #define EVENT_ELEM_SIZE (3 * sizeof(u32))
1711 #define EVENT_START_OFFSET (1 * sizeof(u32) + 2 * sizeof(u16))
1712
1713 /* FW error log definitions */
1714 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1715 #define ERROR_START_OFFSET (1 * sizeof(u32))
1716
1717 /* TX power level (dbm) */
1718 #define IPW_TX_POWER_MIN -12
1719 #define IPW_TX_POWER_MAX 20
1720 #define IPW_TX_POWER_DEFAULT IPW_TX_POWER_MAX
1721
1722 enum {
1723 IPW_FW_ERROR_OK = 0,
1724 IPW_FW_ERROR_FAIL,
1725 IPW_FW_ERROR_MEMORY_UNDERFLOW,
1726 IPW_FW_ERROR_MEMORY_OVERFLOW,
1727 IPW_FW_ERROR_BAD_PARAM,
1728 IPW_FW_ERROR_BAD_CHECKSUM,
1729 IPW_FW_ERROR_NMI_INTERRUPT,
1730 IPW_FW_ERROR_BAD_DATABASE,
1731 IPW_FW_ERROR_ALLOC_FAIL,
1732 IPW_FW_ERROR_DMA_UNDERRUN,
1733 IPW_FW_ERROR_DMA_STATUS,
1734 IPW_FW_ERROR_DINO_ERROR,
1735 IPW_FW_ERROR_EEPROM_ERROR,
1736 IPW_FW_ERROR_SYSASSERT,
1737 IPW_FW_ERROR_FATAL_ERROR
1738 };
1739
1740 #define AUTH_OPEN 0
1741 #define AUTH_SHARED_KEY 1
1742 #define AUTH_LEAP 2
1743 #define AUTH_IGNORE 3
1744
1745 #define HC_ASSOCIATE 0
1746 #define HC_REASSOCIATE 1
1747 #define HC_DISASSOCIATE 2
1748 #define HC_IBSS_START 3
1749 #define HC_IBSS_RECONF 4
1750 #define HC_DISASSOC_QUIET 5
1751
1752 #define HC_QOS_SUPPORT_ASSOC cpu_to_le16(0x01)
1753
1754 #define IPW_RATE_CAPABILITIES 1
1755 #define IPW_RATE_CONNECT 0
1756
1757 /*
1758 * Rate values and masks
1759 */
1760 #define IPW_TX_RATE_1MB 0x0A
1761 #define IPW_TX_RATE_2MB 0x14
1762 #define IPW_TX_RATE_5MB 0x37
1763 #define IPW_TX_RATE_6MB 0x0D
1764 #define IPW_TX_RATE_9MB 0x0F
1765 #define IPW_TX_RATE_11MB 0x6E
1766 #define IPW_TX_RATE_12MB 0x05
1767 #define IPW_TX_RATE_18MB 0x07
1768 #define IPW_TX_RATE_24MB 0x09
1769 #define IPW_TX_RATE_36MB 0x0B
1770 #define IPW_TX_RATE_48MB 0x01
1771 #define IPW_TX_RATE_54MB 0x03
1772
1773 #define IPW_ORD_TABLE_ID_MASK 0x0000FF00
1774 #define IPW_ORD_TABLE_VALUE_MASK 0x000000FF
1775
1776 #define IPW_ORD_TABLE_0_MASK 0x0000F000
1777 #define IPW_ORD_TABLE_1_MASK 0x0000F100
1778 #define IPW_ORD_TABLE_2_MASK 0x0000F200
1779 #define IPW_ORD_TABLE_3_MASK 0x0000F300
1780 #define IPW_ORD_TABLE_4_MASK 0x0000F400
1781 #define IPW_ORD_TABLE_5_MASK 0x0000F500
1782 #define IPW_ORD_TABLE_6_MASK 0x0000F600
1783 #define IPW_ORD_TABLE_7_MASK 0x0000F700
1784
1785 /*
1786 * Table 0 Entries (all entries are 32 bits)
1787 */
1788 enum {
1789 IPW_ORD_STAT_TX_CURR_RATE = IPW_ORD_TABLE_0_MASK + 1,
1790 IPW_ORD_STAT_FRAG_TRESHOLD,
1791 IPW_ORD_STAT_RTS_THRESHOLD,
1792 IPW_ORD_STAT_TX_HOST_REQUESTS,
1793 IPW_ORD_STAT_TX_HOST_COMPLETE,
1794 IPW_ORD_STAT_TX_DIR_DATA,
1795 IPW_ORD_STAT_TX_DIR_DATA_B_1,
1796 IPW_ORD_STAT_TX_DIR_DATA_B_2,
1797 IPW_ORD_STAT_TX_DIR_DATA_B_5_5,
1798 IPW_ORD_STAT_TX_DIR_DATA_B_11,
1799 /* Hole */
1800
1801 IPW_ORD_STAT_TX_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 19,
1802 IPW_ORD_STAT_TX_DIR_DATA_G_2,
1803 IPW_ORD_STAT_TX_DIR_DATA_G_5_5,
1804 IPW_ORD_STAT_TX_DIR_DATA_G_6,
1805 IPW_ORD_STAT_TX_DIR_DATA_G_9,
1806 IPW_ORD_STAT_TX_DIR_DATA_G_11,
1807 IPW_ORD_STAT_TX_DIR_DATA_G_12,
1808 IPW_ORD_STAT_TX_DIR_DATA_G_18,
1809 IPW_ORD_STAT_TX_DIR_DATA_G_24,
1810 IPW_ORD_STAT_TX_DIR_DATA_G_36,
1811 IPW_ORD_STAT_TX_DIR_DATA_G_48,
1812 IPW_ORD_STAT_TX_DIR_DATA_G_54,
1813 IPW_ORD_STAT_TX_NON_DIR_DATA,
1814 IPW_ORD_STAT_TX_NON_DIR_DATA_B_1,
1815 IPW_ORD_STAT_TX_NON_DIR_DATA_B_2,
1816 IPW_ORD_STAT_TX_NON_DIR_DATA_B_5_5,
1817 IPW_ORD_STAT_TX_NON_DIR_DATA_B_11,
1818 /* Hole */
1819
1820 IPW_ORD_STAT_TX_NON_DIR_DATA_G_1 = IPW_ORD_TABLE_0_MASK + 44,
1821 IPW_ORD_STAT_TX_NON_DIR_DATA_G_2,
1822 IPW_ORD_STAT_TX_NON_DIR_DATA_G_5_5,
1823 IPW_ORD_STAT_TX_NON_DIR_DATA_G_6,
1824 IPW_ORD_STAT_TX_NON_DIR_DATA_G_9,
1825 IPW_ORD_STAT_TX_NON_DIR_DATA_G_11,
1826 IPW_ORD_STAT_TX_NON_DIR_DATA_G_12,
1827 IPW_ORD_STAT_TX_NON_DIR_DATA_G_18,
1828 IPW_ORD_STAT_TX_NON_DIR_DATA_G_24,
1829 IPW_ORD_STAT_TX_NON_DIR_DATA_G_36,
1830 IPW_ORD_STAT_TX_NON_DIR_DATA_G_48,
1831 IPW_ORD_STAT_TX_NON_DIR_DATA_G_54,
1832 IPW_ORD_STAT_TX_RETRY,
1833 IPW_ORD_STAT_TX_FAILURE,
1834 IPW_ORD_STAT_RX_ERR_CRC,
1835 IPW_ORD_STAT_RX_ERR_ICV,
1836 IPW_ORD_STAT_RX_NO_BUFFER,
1837 IPW_ORD_STAT_FULL_SCANS,
1838 IPW_ORD_STAT_PARTIAL_SCANS,
1839 IPW_ORD_STAT_TGH_ABORTED_SCANS,
1840 IPW_ORD_STAT_TX_TOTAL_BYTES,
1841 IPW_ORD_STAT_CURR_RSSI_RAW,
1842 IPW_ORD_STAT_RX_BEACON,
1843 IPW_ORD_STAT_MISSED_BEACONS,
1844 IPW_ORD_TABLE_0_LAST
1845 };
1846
1847 #define IPW_RSSI_TO_DBM 112
1848
1849 /* Table 1 Entries
1850 */
1851 enum {
1852 IPW_ORD_TABLE_1_LAST = IPW_ORD_TABLE_1_MASK | 1,
1853 };
1854
1855 /*
1856 * Table 2 Entries
1857 *
1858 * FW_VERSION: 16 byte string
1859 * FW_DATE: 16 byte string (only 14 bytes used)
1860 * UCODE_VERSION: 4 byte version code
1861 * UCODE_DATE: 5 bytes code code
1862 * ADDAPTER_MAC: 6 byte MAC address
1863 * RTC: 4 byte clock
1864 */
1865 enum {
1866 IPW_ORD_STAT_FW_VERSION = IPW_ORD_TABLE_2_MASK | 1,
1867 IPW_ORD_STAT_FW_DATE,
1868 IPW_ORD_STAT_UCODE_VERSION,
1869 IPW_ORD_STAT_UCODE_DATE,
1870 IPW_ORD_STAT_ADAPTER_MAC,
1871 IPW_ORD_STAT_RTC,
1872 IPW_ORD_TABLE_2_LAST
1873 };
1874
1875 /* Table 3 */
1876 enum {
1877 IPW_ORD_STAT_TX_PACKET = IPW_ORD_TABLE_3_MASK | 0,
1878 IPW_ORD_STAT_TX_PACKET_FAILURE,
1879 IPW_ORD_STAT_TX_PACKET_SUCCESS,
1880 IPW_ORD_STAT_TX_PACKET_ABORTED,
1881 IPW_ORD_TABLE_3_LAST
1882 };
1883
1884 /* Table 4 */
1885 enum {
1886 IPW_ORD_TABLE_4_LAST = IPW_ORD_TABLE_4_MASK
1887 };
1888
1889 /* Table 5 */
1890 enum {
1891 IPW_ORD_STAT_AVAILABLE_AP_COUNT = IPW_ORD_TABLE_5_MASK,
1892 IPW_ORD_STAT_AP_ASSNS,
1893 IPW_ORD_STAT_ROAM,
1894 IPW_ORD_STAT_ROAM_CAUSE_MISSED_BEACONS,
1895 IPW_ORD_STAT_ROAM_CAUSE_UNASSOC,
1896 IPW_ORD_STAT_ROAM_CAUSE_RSSI,
1897 IPW_ORD_STAT_ROAM_CAUSE_LINK_QUALITY,
1898 IPW_ORD_STAT_ROAM_CAUSE_AP_LOAD_BALANCE,
1899 IPW_ORD_STAT_ROAM_CAUSE_AP_NO_TX,
1900 IPW_ORD_STAT_LINK_UP,
1901 IPW_ORD_STAT_LINK_DOWN,
1902 IPW_ORD_ANTENNA_DIVERSITY,
1903 IPW_ORD_CURR_FREQ,
1904 IPW_ORD_TABLE_5_LAST
1905 };
1906
1907 /* Table 6 */
1908 enum {
1909 IPW_ORD_COUNTRY_CODE = IPW_ORD_TABLE_6_MASK,
1910 IPW_ORD_CURR_BSSID,
1911 IPW_ORD_CURR_SSID,
1912 IPW_ORD_TABLE_6_LAST
1913 };
1914
1915 /* Table 7 */
1916 enum {
1917 IPW_ORD_STAT_PERCENT_MISSED_BEACONS = IPW_ORD_TABLE_7_MASK,
1918 IPW_ORD_STAT_PERCENT_TX_RETRIES,
1919 IPW_ORD_STAT_PERCENT_LINK_QUALITY,
1920 IPW_ORD_STAT_CURR_RSSI_DBM,
1921 IPW_ORD_TABLE_7_LAST
1922 };
1923
1924 #define IPW_ERROR_LOG (IPW_SHARED_LOWER_BOUND + 0x410)
1925 #define IPW_EVENT_LOG (IPW_SHARED_LOWER_BOUND + 0x414)
1926 #define IPW_ORDINALS_TABLE_LOWER (IPW_SHARED_LOWER_BOUND + 0x500)
1927 #define IPW_ORDINALS_TABLE_0 (IPW_SHARED_LOWER_BOUND + 0x180)
1928 #define IPW_ORDINALS_TABLE_1 (IPW_SHARED_LOWER_BOUND + 0x184)
1929 #define IPW_ORDINALS_TABLE_2 (IPW_SHARED_LOWER_BOUND + 0x188)
1930 #define IPW_MEM_FIXED_OVERRIDE (IPW_SHARED_LOWER_BOUND + 0x41C)
1931
1932 struct ipw_fixed_rate {
1933 __le16 tx_rates;
1934 __le16 reserved;
1935 } __packed;
1936
1937 #define IPW_INDIRECT_ADDR_MASK (~0x3ul)
1938
1939 struct host_cmd {
1940 u8 cmd;
1941 u8 len;
1942 u16 reserved;
1943 const u32 *param;
1944 } __packed; /* XXX */
1945
1946 struct cmdlog_host_cmd {
1947 u8 cmd;
1948 u8 len;
1949 __le16 reserved;
1950 char param[124];
1951 } __packed;
1952
1953 struct ipw_cmd_log {
1954 unsigned long jiffies;
1955 int retcode;
1956 struct cmdlog_host_cmd cmd;
1957 };
1958
1959 /* SysConfig command parameters ... */
1960 /* bt_coexistence param */
1961 #define CFG_BT_COEXISTENCE_SIGNAL_CHNL 0x01 /* tell BT our chnl # */
1962 #define CFG_BT_COEXISTENCE_DEFER 0x02 /* defer our Tx if BT traffic */
1963 #define CFG_BT_COEXISTENCE_KILL 0x04 /* kill our Tx if BT traffic */
1964 #define CFG_BT_COEXISTENCE_WME_OVER_BT 0x08 /* multimedia extensions */
1965 #define CFG_BT_COEXISTENCE_OOB 0x10 /* signal BT via out-of-band */
1966
1967 /* clear-to-send to self param */
1968 #define CFG_CTS_TO_ITSELF_ENABLED_MIN 0x00
1969 #define CFG_CTS_TO_ITSELF_ENABLED_MAX 0x01
1970 #define CFG_CTS_TO_ITSELF_ENABLED_DEF CFG_CTS_TO_ITSELF_ENABLED_MIN
1971
1972 /* Antenna diversity param (h/w can select best antenna, based on signal) */
1973 #define CFG_SYS_ANTENNA_BOTH 0x00 /* NIC selects best antenna */
1974 #define CFG_SYS_ANTENNA_A 0x01 /* force antenna A */
1975 #define CFG_SYS_ANTENNA_B 0x03 /* force antenna B */
1976 #define CFG_SYS_ANTENNA_SLOW_DIV 0x02 /* consider background noise */
1977
1978 #define IPW_MAX_CONFIG_RETRIES 10
1979
1980 #endif /* __ipw2200_h__ */
Kernel DRM miscellaneous fixes and cross-tree changes