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drm/panel: panel-himax-hx83102: support for csot-pna957qt1-1 MIPI-DSI panel
[drm/drm-misc.git] / drivers / net / wireless / intel / iwlwifi / iwl-nvm-parse.c
blob9f7e013252febc58c768405cba61b18478b08c81
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /*
3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
6 */
7 #include <linux/types.h>
8 #include <linux/slab.h>
9 #include <linux/export.h>
10 #include <linux/etherdevice.h>
11 #include <linux/pci.h>
12 #include <linux/firmware.h>
13
14 #include "iwl-drv.h"
15 #include "iwl-modparams.h"
16 #include "iwl-nvm-parse.h"
17 #include "iwl-prph.h"
18 #include "iwl-io.h"
19 #include "iwl-csr.h"
20 #include "fw/acpi.h"
21 #include "fw/api/nvm-reg.h"
22 #include "fw/api/commands.h"
23 #include "fw/api/cmdhdr.h"
24 #include "fw/img.h"
25 #include "mei/iwl-mei.h"
26
27 /* NVM offsets (in words) definitions */
28 enum nvm_offsets {
29 /* NVM HW-Section offset (in words) definitions */
30 SUBSYSTEM_ID = 0x0A,
31 HW_ADDR = 0x15,
32
33 /* NVM SW-Section offset (in words) definitions */
34 NVM_SW_SECTION = 0x1C0,
35 NVM_VERSION = 0,
36 RADIO_CFG = 1,
37 SKU = 2,
38 N_HW_ADDRS = 3,
39 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
40
41 /* NVM REGULATORY -Section offset (in words) definitions */
42 NVM_CHANNELS_SDP = 0,
43 };
44
45 enum ext_nvm_offsets {
46 /* NVM HW-Section offset (in words) definitions */
47
48 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
49
50 /* NVM SW-Section offset (in words) definitions */
51 NVM_VERSION_EXT_NVM = 0,
52 N_HW_ADDRS_FAMILY_8000 = 3,
53
54 /* NVM PHY_SKU-Section offset (in words) definitions */
55 RADIO_CFG_FAMILY_EXT_NVM = 0,
56 SKU_FAMILY_8000 = 2,
57
58 /* NVM REGULATORY -Section offset (in words) definitions */
59 NVM_CHANNELS_EXTENDED = 0,
60 NVM_LAR_OFFSET_OLD = 0x4C7,
61 NVM_LAR_OFFSET = 0x507,
62 NVM_LAR_ENABLED = 0x7,
63 };
64
65 /* SKU Capabilities (actual values from NVM definition) */
66 enum nvm_sku_bits {
67 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
68 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
69 NVM_SKU_CAP_11N_ENABLE = BIT(2),
70 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
71 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
72 };
73
74 /*
75 * These are the channel numbers in the order that they are stored in the NVM
76 */
77 static const u16 iwl_nvm_channels[] = {
78 /* 2.4 GHz */
79 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
80 /* 5 GHz */
81 36, 40, 44, 48, 52, 56, 60, 64,
82 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
83 149, 153, 157, 161, 165
84 };
85
86 static const u16 iwl_ext_nvm_channels[] = {
87 /* 2.4 GHz */
88 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
89 /* 5 GHz */
90 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
91 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
92 149, 153, 157, 161, 165, 169, 173, 177, 181
93 };
94
95 static const u16 iwl_uhb_nvm_channels[] = {
96 /* 2.4 GHz */
97 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
98 /* 5 GHz */
99 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
100 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
101 149, 153, 157, 161, 165, 169, 173, 177, 181,
102 /* 6-7 GHz */
103 1, 5, 9, 13, 17, 21, 25, 29, 33, 37, 41, 45, 49, 53, 57, 61, 65, 69,
104 73, 77, 81, 85, 89, 93, 97, 101, 105, 109, 113, 117, 121, 125, 129,
105 133, 137, 141, 145, 149, 153, 157, 161, 165, 169, 173, 177, 181, 185,
106 189, 193, 197, 201, 205, 209, 213, 217, 221, 225, 229, 233
107 };
108
109 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
110 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
111 #define IWL_NVM_NUM_CHANNELS_UHB ARRAY_SIZE(iwl_uhb_nvm_channels)
112 #define NUM_2GHZ_CHANNELS 14
113 #define NUM_5GHZ_CHANNELS 37
114 #define FIRST_2GHZ_HT_MINUS 5
115 #define LAST_2GHZ_HT_PLUS 9
116 #define N_HW_ADDR_MASK 0xF
117
118 /* rate data (static) */
119 static struct ieee80211_rate iwl_cfg80211_rates[] = {
120 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
121 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
122 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
123 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
124 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
125 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
126 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
127 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
128 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
129 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
130 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
131 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
132 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
133 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
134 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
135 };
136 #define RATES_24_OFFS 0
137 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
138 #define RATES_52_OFFS 4
139 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
140
141 /**
142 * enum iwl_nvm_channel_flags - channel flags in NVM
143 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
144 * @NVM_CHANNEL_IBSS: usable as an IBSS channel and deprecated
145 * when %IWL_NVM_SBANDS_FLAGS_LAR enabled.
146 * @NVM_CHANNEL_ACTIVE: active scanning allowed and allows IBSS
147 * when %IWL_NVM_SBANDS_FLAGS_LAR enabled.
148 * @NVM_CHANNEL_RADAR: radar detection required
149 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
150 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
151 * on same channel on 2.4 or same UNII band on 5.2
152 * @NVM_CHANNEL_UNIFORM: uniform spreading required
153 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
154 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
155 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
156 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
157 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
158 * @NVM_CHANNEL_VLP: client support connection to UHB VLP AP
159 * @NVM_CHANNEL_AFC: client support connection to UHB AFC AP
160 */
161 enum iwl_nvm_channel_flags {
162 NVM_CHANNEL_VALID = BIT(0),
163 NVM_CHANNEL_IBSS = BIT(1),
164 NVM_CHANNEL_ACTIVE = BIT(3),
165 NVM_CHANNEL_RADAR = BIT(4),
166 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
167 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
168 NVM_CHANNEL_UNIFORM = BIT(7),
169 NVM_CHANNEL_20MHZ = BIT(8),
170 NVM_CHANNEL_40MHZ = BIT(9),
171 NVM_CHANNEL_80MHZ = BIT(10),
172 NVM_CHANNEL_160MHZ = BIT(11),
173 NVM_CHANNEL_DC_HIGH = BIT(12),
174 NVM_CHANNEL_VLP = BIT(13),
175 NVM_CHANNEL_AFC = BIT(14),
176 };
177
178 /**
179 * enum iwl_reg_capa_flags_v1 - global flags applied for the whole regulatory
180 * domain.
181 * @REG_CAPA_V1_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
182 * 2.4Ghz band is allowed.
183 * @REG_CAPA_V1_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
184 * 5Ghz band is allowed.
185 * @REG_CAPA_V1_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
186 * for this regulatory domain (valid only in 5Ghz).
187 * @REG_CAPA_V1_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
188 * for this regulatory domain (valid only in 5Ghz).
189 * @REG_CAPA_V1_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
190 * @REG_CAPA_V1_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
191 * @REG_CAPA_V1_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
192 * for this regulatory domain (valid only in 5Ghz).
193 * @REG_CAPA_V1_DC_HIGH_ENABLED: DC HIGH allowed.
194 * @REG_CAPA_V1_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
195 */
196 enum iwl_reg_capa_flags_v1 {
197 REG_CAPA_V1_BF_CCD_LOW_BAND = BIT(0),
198 REG_CAPA_V1_BF_CCD_HIGH_BAND = BIT(1),
199 REG_CAPA_V1_160MHZ_ALLOWED = BIT(2),
200 REG_CAPA_V1_80MHZ_ALLOWED = BIT(3),
201 REG_CAPA_V1_MCS_8_ALLOWED = BIT(4),
202 REG_CAPA_V1_MCS_9_ALLOWED = BIT(5),
203 REG_CAPA_V1_40MHZ_FORBIDDEN = BIT(7),
204 REG_CAPA_V1_DC_HIGH_ENABLED = BIT(9),
205 REG_CAPA_V1_11AX_DISABLED = BIT(10),
206 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_1 */
207
208 /**
209 * enum iwl_reg_capa_flags_v2 - global flags applied for the whole regulatory
210 * domain (version 2).
211 * @REG_CAPA_V2_STRADDLE_DISABLED: Straddle channels (144, 142, 138) are
212 * disabled.
213 * @REG_CAPA_V2_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
214 * 2.4Ghz band is allowed.
215 * @REG_CAPA_V2_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
216 * 5Ghz band is allowed.
217 * @REG_CAPA_V2_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
218 * for this regulatory domain (valid only in 5Ghz).
219 * @REG_CAPA_V2_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
220 * for this regulatory domain (valid only in 5Ghz).
221 * @REG_CAPA_V2_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
222 * @REG_CAPA_V2_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
223 * @REG_CAPA_V2_WEATHER_DISABLED: Weather radar channels (120, 124, 128, 118,
224 * 126, 122) are disabled.
225 * @REG_CAPA_V2_40MHZ_ALLOWED: 11n channel with a width of 40Mhz is allowed
226 * for this regulatory domain (uvalid only in 5Ghz).
227 * @REG_CAPA_V2_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
228 */
229 enum iwl_reg_capa_flags_v2 {
230 REG_CAPA_V2_STRADDLE_DISABLED = BIT(0),
231 REG_CAPA_V2_BF_CCD_LOW_BAND = BIT(1),
232 REG_CAPA_V2_BF_CCD_HIGH_BAND = BIT(2),
233 REG_CAPA_V2_160MHZ_ALLOWED = BIT(3),
234 REG_CAPA_V2_80MHZ_ALLOWED = BIT(4),
235 REG_CAPA_V2_MCS_8_ALLOWED = BIT(5),
236 REG_CAPA_V2_MCS_9_ALLOWED = BIT(6),
237 REG_CAPA_V2_WEATHER_DISABLED = BIT(7),
238 REG_CAPA_V2_40MHZ_ALLOWED = BIT(8),
239 REG_CAPA_V2_11AX_DISABLED = BIT(10),
240 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_2 */
241
242 /**
243 * enum iwl_reg_capa_flags_v4 - global flags applied for the whole regulatory
244 * domain.
245 * @REG_CAPA_V4_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
246 * for this regulatory domain (valid only in 5Ghz).
247 * @REG_CAPA_V4_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
248 * for this regulatory domain (valid only in 5Ghz).
249 * @REG_CAPA_V4_MCS_12_ALLOWED: 11ac with MCS 12 is allowed.
250 * @REG_CAPA_V4_MCS_13_ALLOWED: 11ac with MCS 13 is allowed.
251 * @REG_CAPA_V4_11BE_DISABLED: 11be is forbidden for this regulatory domain.
252 * @REG_CAPA_V4_11AX_DISABLED: 11ax is forbidden for this regulatory domain.
253 * @REG_CAPA_V4_320MHZ_ALLOWED: 11be channel with a width of 320Mhz is allowed
254 * for this regulatory domain (valid only in 5GHz).
255 */
256 enum iwl_reg_capa_flags_v4 {
257 REG_CAPA_V4_160MHZ_ALLOWED = BIT(3),
258 REG_CAPA_V4_80MHZ_ALLOWED = BIT(4),
259 REG_CAPA_V4_MCS_12_ALLOWED = BIT(5),
260 REG_CAPA_V4_MCS_13_ALLOWED = BIT(6),
261 REG_CAPA_V4_11BE_DISABLED = BIT(8),
262 REG_CAPA_V4_11AX_DISABLED = BIT(13),
263 REG_CAPA_V4_320MHZ_ALLOWED = BIT(16),
264 }; /* GEO_CHANNEL_CAPABILITIES_API_S_VER_4 */
265
266 /*
267 * API v2 for reg_capa_flags is relevant from version 6 and onwards of the
268 * MCC update command response.
269 */
270 #define REG_CAPA_V2_RESP_VER 6
271
272 /* API v4 for reg_capa_flags is relevant from version 8 and onwards of the
273 * MCC update command response.
274 */
275 #define REG_CAPA_V4_RESP_VER 8
276
277 /**
278 * struct iwl_reg_capa - struct for global regulatory capabilities, Used for
279 * handling the different APIs of reg_capa_flags.
280 *
281 * @allow_40mhz: 11n channel with a width of 40Mhz is allowed
282 * for this regulatory domain.
283 * @allow_80mhz: 11ac channel with a width of 80Mhz is allowed
284 * for this regulatory domain (valid only in 5 and 6 Ghz).
285 * @allow_160mhz: 11ac channel with a width of 160Mhz is allowed
286 * for this regulatory domain (valid only in 5 and 6 Ghz).
287 * @allow_320mhz: 11be channel with a width of 320Mhz is allowed
288 * for this regulatory domain (valid only in 6 Ghz).
289 * @disable_11ax: 11ax is forbidden for this regulatory domain.
290 * @disable_11be: 11be is forbidden for this regulatory domain.
291 */
292 struct iwl_reg_capa {
293 bool allow_40mhz;
294 bool allow_80mhz;
295 bool allow_160mhz;
296 bool allow_320mhz;
297 bool disable_11ax;
298 bool disable_11be;
299 };
300
301 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
302 int chan, u32 flags)
303 {
304 #define CHECK_AND_PRINT_I(x) \
305 ((flags & NVM_CHANNEL_##x) ? " " #x : "")
306
307 if (!(flags & NVM_CHANNEL_VALID)) {
308 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
309 chan, flags);
310 return;
311 }
312
313 /* Note: already can print up to 101 characters, 110 is the limit! */
314 IWL_DEBUG_DEV(dev, level,
315 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
316 chan, flags,
317 CHECK_AND_PRINT_I(VALID),
318 CHECK_AND_PRINT_I(IBSS),
319 CHECK_AND_PRINT_I(ACTIVE),
320 CHECK_AND_PRINT_I(RADAR),
321 CHECK_AND_PRINT_I(INDOOR_ONLY),
322 CHECK_AND_PRINT_I(GO_CONCURRENT),
323 CHECK_AND_PRINT_I(UNIFORM),
324 CHECK_AND_PRINT_I(20MHZ),
325 CHECK_AND_PRINT_I(40MHZ),
326 CHECK_AND_PRINT_I(80MHZ),
327 CHECK_AND_PRINT_I(160MHZ),
328 CHECK_AND_PRINT_I(DC_HIGH),
329 CHECK_AND_PRINT_I(VLP),
330 CHECK_AND_PRINT_I(AFC));
331 #undef CHECK_AND_PRINT_I
332 }
333
334 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, enum nl80211_band band,
335 u32 nvm_flags, const struct iwl_cfg *cfg)
336 {
337 u32 flags = IEEE80211_CHAN_NO_HT40;
338
339 if (band == NL80211_BAND_2GHZ && (nvm_flags & NVM_CHANNEL_40MHZ)) {
340 if (ch_num <= LAST_2GHZ_HT_PLUS)
341 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
342 if (ch_num >= FIRST_2GHZ_HT_MINUS)
343 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
344 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
345 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
346 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
347 else
348 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
349 }
350 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
351 flags |= IEEE80211_CHAN_NO_80MHZ;
352 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
353 flags |= IEEE80211_CHAN_NO_160MHZ;
354
355 if (!(nvm_flags & NVM_CHANNEL_IBSS))
356 flags |= IEEE80211_CHAN_NO_IR;
357
358 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
359 flags |= IEEE80211_CHAN_NO_IR;
360
361 if (nvm_flags & NVM_CHANNEL_RADAR)
362 flags |= IEEE80211_CHAN_RADAR;
363
364 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
365 flags |= IEEE80211_CHAN_INDOOR_ONLY;
366
367 /* Set the GO concurrent flag only in case that NO_IR is set.
368 * Otherwise it is meaningless
369 */
370 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
371 (flags & IEEE80211_CHAN_NO_IR))
372 flags |= IEEE80211_CHAN_IR_CONCURRENT;
373
374 /* Set the AP type for the UHB case. */
375 if (nvm_flags & NVM_CHANNEL_VLP)
376 flags |= IEEE80211_CHAN_ALLOW_6GHZ_VLP_AP;
377 else
378 flags |= IEEE80211_CHAN_NO_6GHZ_VLP_CLIENT;
379 if (!(nvm_flags & NVM_CHANNEL_AFC))
380 flags |= IEEE80211_CHAN_NO_6GHZ_AFC_CLIENT;
381
382 return flags;
383 }
384
385 static enum nl80211_band iwl_nl80211_band_from_channel_idx(int ch_idx)
386 {
387 if (ch_idx >= NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS) {
388 return NL80211_BAND_6GHZ;
389 }
390
391 if (ch_idx >= NUM_2GHZ_CHANNELS)
392 return NL80211_BAND_5GHZ;
393 return NL80211_BAND_2GHZ;
394 }
395
396 static int iwl_init_channel_map(struct iwl_trans *trans,
397 const struct iwl_fw *fw,
398 struct iwl_nvm_data *data,
399 const void * const nvm_ch_flags,
400 u32 sbands_flags, bool v4)
401 {
402 const struct iwl_cfg *cfg = trans->cfg;
403 struct device *dev = trans->dev;
404 int ch_idx;
405 int n_channels = 0;
406 struct ieee80211_channel *channel;
407 u32 ch_flags;
408 int num_of_ch;
409 const u16 *nvm_chan;
410
411 if (cfg->uhb_supported) {
412 num_of_ch = IWL_NVM_NUM_CHANNELS_UHB;
413 nvm_chan = iwl_uhb_nvm_channels;
414 } else if (cfg->nvm_type == IWL_NVM_EXT) {
415 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
416 nvm_chan = iwl_ext_nvm_channels;
417 } else {
418 num_of_ch = IWL_NVM_NUM_CHANNELS;
419 nvm_chan = iwl_nvm_channels;
420 }
421
422 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
423 enum nl80211_band band =
424 iwl_nl80211_band_from_channel_idx(ch_idx);
425
426 if (v4)
427 ch_flags =
428 __le32_to_cpup((const __le32 *)nvm_ch_flags + ch_idx);
429 else
430 ch_flags =
431 __le16_to_cpup((const __le16 *)nvm_ch_flags + ch_idx);
432
433 if (band == NL80211_BAND_5GHZ &&
434 !data->sku_cap_band_52ghz_enable)
435 continue;
436
437 /* workaround to disable wide channels in 5GHz */
438 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
439 band == NL80211_BAND_5GHZ) {
440 ch_flags &= ~(NVM_CHANNEL_40MHZ |
441 NVM_CHANNEL_80MHZ |
442 NVM_CHANNEL_160MHZ);
443 }
444
445 if (ch_flags & NVM_CHANNEL_160MHZ)
446 data->vht160_supported = true;
447
448 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
449 !(ch_flags & NVM_CHANNEL_VALID)) {
450 /*
451 * Channels might become valid later if lar is
452 * supported, hence we still want to add them to
453 * the list of supported channels to cfg80211.
454 */
455 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
456 nvm_chan[ch_idx], ch_flags);
457 continue;
458 }
459
460 channel = &data->channels[n_channels];
461 n_channels++;
462
463 channel->hw_value = nvm_chan[ch_idx];
464 channel->band = band;
465 channel->center_freq =
466 ieee80211_channel_to_frequency(
467 channel->hw_value, channel->band);
468
469 /* Initialize regulatory-based run-time data */
470
471 /*
472 * Default value - highest tx power value. max_power
473 * is not used in mvm, and is used for backwards compatibility
474 */
475 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
476
477 /* don't put limitations in case we're using LAR */
478 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
479 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
480 ch_idx, band,
481 ch_flags, cfg);
482 else
483 channel->flags = 0;
484
485 if (fw_has_capa(&fw->ucode_capa,
486 IWL_UCODE_TLV_CAPA_MONITOR_PASSIVE_CHANS))
487 channel->flags |= IEEE80211_CHAN_CAN_MONITOR;
488
489 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
490 channel->hw_value, ch_flags);
491 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
492 channel->hw_value, channel->max_power);
493 }
494
495 return n_channels;
496 }
497
498 static void iwl_init_vht_hw_capab(struct iwl_trans *trans,
499 struct iwl_nvm_data *data,
500 struct ieee80211_sta_vht_cap *vht_cap,
501 u8 tx_chains, u8 rx_chains)
502 {
503 const struct iwl_cfg *cfg = trans->cfg;
504 int num_rx_ants = num_of_ant(rx_chains);
505 int num_tx_ants = num_of_ant(tx_chains);
506
507 vht_cap->vht_supported = true;
508
509 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
510 IEEE80211_VHT_CAP_RXSTBC_1 |
511 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
512 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
513 IEEE80211_VHT_MAX_AMPDU_1024K <<
514 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
515
516 if (!trans->cfg->ht_params->stbc)
517 vht_cap->cap &= ~IEEE80211_VHT_CAP_RXSTBC_MASK;
518
519 if (data->vht160_supported)
520 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
521 IEEE80211_VHT_CAP_SHORT_GI_160;
522
523 if (cfg->vht_mu_mimo_supported)
524 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
525
526 if (cfg->ht_params->ldpc)
527 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
528
529 if (data->sku_cap_mimo_disabled) {
530 num_rx_ants = 1;
531 num_tx_ants = 1;
532 }
533
534 if (trans->cfg->ht_params->stbc && num_tx_ants > 1)
535 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
536 else
537 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
538
539 switch (iwlwifi_mod_params.amsdu_size) {
540 case IWL_AMSDU_DEF:
541 if (trans->trans_cfg->mq_rx_supported)
542 vht_cap->cap |=
543 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
544 else
545 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
546 break;
547 case IWL_AMSDU_2K:
548 if (trans->trans_cfg->mq_rx_supported)
549 vht_cap->cap |=
550 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
551 else
552 WARN(1, "RB size of 2K is not supported by this device\n");
553 break;
554 case IWL_AMSDU_4K:
555 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
556 break;
557 case IWL_AMSDU_8K:
558 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
559 break;
560 case IWL_AMSDU_12K:
561 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
562 break;
563 default:
564 break;
565 }
566
567 vht_cap->vht_mcs.rx_mcs_map =
568 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
569 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
570 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
571 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
572 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
573 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
574 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
575 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
576
577 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
578 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
579 /* this works because NOT_SUPPORTED == 3 */
580 vht_cap->vht_mcs.rx_mcs_map |=
581 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
582 }
583
584 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
585
586 vht_cap->vht_mcs.tx_highest |=
587 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
588 }
589
590 static const u8 iwl_vendor_caps[] = {
591 0xdd, /* vendor element */
592 0x06, /* length */
593 0x00, 0x17, 0x35, /* Intel OUI */
594 0x08, /* type (Intel Capabilities) */
595 /* followed by 16 bits of capabilities */
596 #define IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE BIT(0)
597 IWL_VENDOR_CAP_IMPROVED_BF_FDBK_HE,
598 0x00
599 };
600
601 static const struct ieee80211_sband_iftype_data iwl_he_eht_capa[] = {
602 {
603 .types_mask = BIT(NL80211_IFTYPE_STATION) |
604 BIT(NL80211_IFTYPE_P2P_CLIENT),
605 .he_cap = {
606 .has_he = true,
607 .he_cap_elem = {
608 .mac_cap_info[0] =
609 IEEE80211_HE_MAC_CAP0_HTC_HE,
610 .mac_cap_info[1] =
611 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
612 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
613 .mac_cap_info[2] =
614 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP,
615 .mac_cap_info[3] =
616 IEEE80211_HE_MAC_CAP3_OMI_CONTROL |
617 IEEE80211_HE_MAC_CAP3_RX_CTRL_FRAME_TO_MULTIBSS,
618 .mac_cap_info[4] =
619 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU |
620 IEEE80211_HE_MAC_CAP4_MULTI_TID_AGG_TX_QOS_B39,
621 .mac_cap_info[5] =
622 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B40 |
623 IEEE80211_HE_MAC_CAP5_MULTI_TID_AGG_TX_QOS_B41 |
624 IEEE80211_HE_MAC_CAP5_UL_2x996_TONE_RU |
625 IEEE80211_HE_MAC_CAP5_HE_DYNAMIC_SM_PS |
626 IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX,
627 .phy_cap_info[1] =
628 IEEE80211_HE_PHY_CAP1_PREAMBLE_PUNC_RX_MASK |
629 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
630 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
631 .phy_cap_info[2] =
632 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
633 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ,
634 .phy_cap_info[3] =
635 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK |
636 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
637 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK |
638 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
639 .phy_cap_info[4] =
640 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
641 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
642 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
643 .phy_cap_info[6] =
644 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
645 IEEE80211_HE_PHY_CAP6_TRIG_MU_BEAMFORMING_PARTIAL_BW_FB |
646 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
647 .phy_cap_info[7] =
648 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
649 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
650 .phy_cap_info[8] =
651 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
652 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
653 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
654 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU |
655 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
656 .phy_cap_info[9] =
657 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
658 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
659 (IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED <<
660 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS),
661 .phy_cap_info[10] =
662 IEEE80211_HE_PHY_CAP10_HE_MU_M1RU_MAX_LTF,
663 },
664 /*
665 * Set default Tx/Rx HE MCS NSS Support field.
666 * Indicate support for up to 2 spatial streams and all
667 * MCS, without any special cases
668 */
669 .he_mcs_nss_supp = {
670 .rx_mcs_80 = cpu_to_le16(0xfffa),
671 .tx_mcs_80 = cpu_to_le16(0xfffa),
672 .rx_mcs_160 = cpu_to_le16(0xfffa),
673 .tx_mcs_160 = cpu_to_le16(0xfffa),
674 .rx_mcs_80p80 = cpu_to_le16(0xffff),
675 .tx_mcs_80p80 = cpu_to_le16(0xffff),
676 },
677 /*
678 * Set default PPE thresholds, with PPET16 set to 0,
679 * PPET8 set to 7
680 */
681 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
682 },
683 .eht_cap = {
684 .has_eht = true,
685 .eht_cap_elem = {
686 .mac_cap_info[0] =
687 IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
688 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
689 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2 |
690 IEEE80211_EHT_MAC_CAP0_SCS_TRAFFIC_DESC,
691 .phy_cap_info[0] =
692 IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ |
693 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
694 IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO |
695 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE |
696 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK,
697 .phy_cap_info[1] =
698 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK |
699 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK,
700 .phy_cap_info[3] =
701 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
702 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
703 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
704 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
705 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
706 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK |
707 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK,
708
709 .phy_cap_info[4] =
710 IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO |
711 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
712 IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI,
713 .phy_cap_info[5] =
714 FIELD_PREP_CONST(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK,
715 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US) |
716 IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK |
717 IEEE80211_EHT_PHY_CAP5_TX_LESS_242_TONE_RU_SUPP |
718 IEEE80211_EHT_PHY_CAP5_RX_LESS_242_TONE_RU_SUPP,
719 .phy_cap_info[6] =
720 IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK |
721 IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP,
722 .phy_cap_info[8] =
723 IEEE80211_EHT_PHY_CAP8_RX_1024QAM_WIDER_BW_DL_OFDMA |
724 IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA,
725 },
726
727 /* For all MCS and bandwidth, set 2 NSS for both Tx and
728 * Rx - note we don't set the only_20mhz, but due to this
729 * being a union, it gets set correctly anyway.
730 */
731 .eht_mcs_nss_supp = {
732 .bw._80 = {
733 .rx_tx_mcs9_max_nss = 0x22,
734 .rx_tx_mcs11_max_nss = 0x22,
735 .rx_tx_mcs13_max_nss = 0x22,
736 },
737 .bw._160 = {
738 .rx_tx_mcs9_max_nss = 0x22,
739 .rx_tx_mcs11_max_nss = 0x22,
740 .rx_tx_mcs13_max_nss = 0x22,
741 },
742 .bw._320 = {
743 .rx_tx_mcs9_max_nss = 0x22,
744 .rx_tx_mcs11_max_nss = 0x22,
745 .rx_tx_mcs13_max_nss = 0x22,
746 },
747 },
748
749 /*
750 * PPE thresholds for NSS = 2, and RU index bitmap set
751 * to 0xc.
752 * Note: just for stating what we want, not present in
753 * the transmitted data due to not including
754 * IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT.
755 */
756 .eht_ppe_thres = {0xc1, 0x0e, 0xe0 }
757 },
758 },
759 {
760 .types_mask = BIT(NL80211_IFTYPE_AP) |
761 BIT(NL80211_IFTYPE_P2P_GO),
762 .he_cap = {
763 .has_he = true,
764 .he_cap_elem = {
765 .mac_cap_info[0] =
766 IEEE80211_HE_MAC_CAP0_HTC_HE,
767 .mac_cap_info[1] =
768 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_RX_QOS_8,
769 .mac_cap_info[3] =
770 IEEE80211_HE_MAC_CAP3_OMI_CONTROL,
771 .phy_cap_info[1] =
772 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD,
773 .phy_cap_info[2] =
774 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
775 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US,
776 .phy_cap_info[3] =
777 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK |
778 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
779 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK |
780 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
781 .phy_cap_info[6] =
782 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
783 .phy_cap_info[7] =
784 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI,
785 .phy_cap_info[8] =
786 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
787 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_242,
788 .phy_cap_info[9] =
789 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_RESERVED
790 << IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_POS,
791 },
792 /*
793 * Set default Tx/Rx HE MCS NSS Support field.
794 * Indicate support for up to 2 spatial streams and all
795 * MCS, without any special cases
796 */
797 .he_mcs_nss_supp = {
798 .rx_mcs_80 = cpu_to_le16(0xfffa),
799 .tx_mcs_80 = cpu_to_le16(0xfffa),
800 .rx_mcs_160 = cpu_to_le16(0xfffa),
801 .tx_mcs_160 = cpu_to_le16(0xfffa),
802 .rx_mcs_80p80 = cpu_to_le16(0xffff),
803 .tx_mcs_80p80 = cpu_to_le16(0xffff),
804 },
805 /*
806 * Set default PPE thresholds, with PPET16 set to 0,
807 * PPET8 set to 7
808 */
809 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
810 },
811 .eht_cap = {
812 .has_eht = true,
813 .eht_cap_elem = {
814 .mac_cap_info[0] =
815 IEEE80211_EHT_MAC_CAP0_OM_CONTROL |
816 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
817 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2,
818 .phy_cap_info[0] =
819 IEEE80211_EHT_PHY_CAP0_242_TONE_RU_GT20MHZ |
820 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI,
821 .phy_cap_info[5] =
822 FIELD_PREP_CONST(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK,
823 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US),
824 },
825
826 /* For all MCS and bandwidth, set 2 NSS for both Tx and
827 * Rx - note we don't set the only_20mhz, but due to this
828 * being a union, it gets set correctly anyway.
829 */
830 .eht_mcs_nss_supp = {
831 .bw._80 = {
832 .rx_tx_mcs9_max_nss = 0x22,
833 .rx_tx_mcs11_max_nss = 0x22,
834 .rx_tx_mcs13_max_nss = 0x22,
835 },
836 .bw._160 = {
837 .rx_tx_mcs9_max_nss = 0x22,
838 .rx_tx_mcs11_max_nss = 0x22,
839 .rx_tx_mcs13_max_nss = 0x22,
840 },
841 .bw._320 = {
842 .rx_tx_mcs9_max_nss = 0x22,
843 .rx_tx_mcs11_max_nss = 0x22,
844 .rx_tx_mcs13_max_nss = 0x22,
845 },
846 },
847
848 /*
849 * PPE thresholds for NSS = 2, and RU index bitmap set
850 * to 0xc.
851 * Note: just for stating what we want, not present in
852 * the transmitted data due to not including
853 * IEEE80211_EHT_PHY_CAP5_PPE_THRESHOLD_PRESENT.
854 */
855 .eht_ppe_thres = {0xc1, 0x0e, 0xe0 }
856 },
857 },
858 };
859
860 static void iwl_init_he_6ghz_capa(struct iwl_trans *trans,
861 struct iwl_nvm_data *data,
862 struct ieee80211_supported_band *sband,
863 u8 tx_chains, u8 rx_chains)
864 {
865 struct ieee80211_sta_ht_cap ht_cap;
866 struct ieee80211_sta_vht_cap vht_cap = {};
867 struct ieee80211_sband_iftype_data *iftype_data;
868 u16 he_6ghz_capa = 0;
869 u32 exp;
870 int i;
871
872 if (sband->band != NL80211_BAND_6GHZ)
873 return;
874
875 /* grab HT/VHT capabilities and calculate HE 6 GHz capabilities */
876 iwl_init_ht_hw_capab(trans, data, &ht_cap, NL80211_BAND_5GHZ,
877 tx_chains, rx_chains);
878 WARN_ON(!ht_cap.ht_supported);
879 iwl_init_vht_hw_capab(trans, data, &vht_cap, tx_chains, rx_chains);
880 WARN_ON(!vht_cap.vht_supported);
881
882 he_6ghz_capa |=
883 u16_encode_bits(ht_cap.ampdu_density,
884 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START);
885 exp = u32_get_bits(vht_cap.cap,
886 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK);
887 he_6ghz_capa |=
888 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP);
889 exp = u32_get_bits(vht_cap.cap, IEEE80211_VHT_CAP_MAX_MPDU_MASK);
890 he_6ghz_capa |=
891 u16_encode_bits(exp, IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
892 /* we don't support extended_ht_cap_info anywhere, so no RD_RESPONDER */
893 if (vht_cap.cap & IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN)
894 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_TX_ANTPAT_CONS;
895 if (vht_cap.cap & IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN)
896 he_6ghz_capa |= IEEE80211_HE_6GHZ_CAP_RX_ANTPAT_CONS;
897
898 IWL_DEBUG_EEPROM(trans->dev, "he_6ghz_capa=0x%x\n", he_6ghz_capa);
899
900 /* we know it's writable - we set it before ourselves */
901 iftype_data = (void *)(uintptr_t)sband->iftype_data;
902 for (i = 0; i < sband->n_iftype_data; i++)
903 iftype_data[i].he_6ghz_capa.capa = cpu_to_le16(he_6ghz_capa);
904 }
905
906 static void
907 iwl_nvm_fixup_sband_iftd(struct iwl_trans *trans,
908 struct iwl_nvm_data *data,
909 struct ieee80211_supported_band *sband,
910 struct ieee80211_sband_iftype_data *iftype_data,
911 u8 tx_chains, u8 rx_chains,
912 const struct iwl_fw *fw)
913 {
914 bool is_ap = iftype_data->types_mask & (BIT(NL80211_IFTYPE_AP) |
915 BIT(NL80211_IFTYPE_P2P_GO));
916 bool no_320;
917
918 no_320 = (!trans->trans_cfg->integrated &&
919 trans->pcie_link_speed < PCI_EXP_LNKSTA_CLS_8_0GB) ||
920 trans->reduced_cap_sku;
921
922 if (!data->sku_cap_11be_enable || iwlwifi_mod_params.disable_11be)
923 iftype_data->eht_cap.has_eht = false;
924
925 /* Advertise an A-MPDU exponent extension based on
926 * operating band
927 */
928 if (sband->band == NL80211_BAND_6GHZ && iftype_data->eht_cap.has_eht)
929 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
930 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
931 else if (sband->band != NL80211_BAND_2GHZ)
932 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
933 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_1;
934 else
935 iftype_data->he_cap.he_cap_elem.mac_cap_info[3] |=
936 IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_3;
937
938 switch (sband->band) {
939 case NL80211_BAND_2GHZ:
940 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
941 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
942 iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] |=
943 u8_encode_bits(IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_11454,
944 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
945 break;
946 case NL80211_BAND_6GHZ:
947 if (!no_320) {
948 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[0] |=
949 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
950 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[1] |=
951 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK;
952 }
953 fallthrough;
954 case NL80211_BAND_5GHZ:
955 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] |=
956 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
957 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
958 break;
959 default:
960 WARN_ON(1);
961 break;
962 }
963
964 if ((tx_chains & rx_chains) == ANT_AB) {
965 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |=
966 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ;
967 iftype_data->he_cap.he_cap_elem.phy_cap_info[5] |=
968 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
969 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2;
970 if (!is_ap) {
971 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
972 IEEE80211_HE_PHY_CAP7_MAX_NC_2;
973
974 if (iftype_data->eht_cap.has_eht) {
975 /*
976 * Set the number of sounding dimensions for each
977 * bandwidth to 1 to indicate the maximal supported
978 * value of TXVECTOR parameter NUM_STS of 2
979 */
980 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] |= 0x49;
981
982 /*
983 * Set the MAX NC to 1 to indicate sounding feedback of
984 * 2 supported by the beamfomee.
985 */
986 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] |= 0x10;
987 }
988 }
989 } else {
990 struct ieee80211_he_mcs_nss_supp *he_mcs_nss_supp =
991 &iftype_data->he_cap.he_mcs_nss_supp;
992
993 if (iftype_data->eht_cap.has_eht) {
994 struct ieee80211_eht_mcs_nss_supp *mcs_nss =
995 &iftype_data->eht_cap.eht_mcs_nss_supp;
996
997 memset(mcs_nss, 0x11, sizeof(*mcs_nss));
998 }
999
1000 if (!is_ap) {
1001 /* If not 2x2, we need to indicate 1x1 in the
1002 * Midamble RX Max NSTS - but not for AP mode
1003 */
1004 iftype_data->he_cap.he_cap_elem.phy_cap_info[1] &=
1005 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_TX_MAX_NSTS;
1006 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
1007 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_TX_MAX_NSTS;
1008 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] |=
1009 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
1010 }
1011
1012 he_mcs_nss_supp->rx_mcs_80 |=
1013 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1014 he_mcs_nss_supp->tx_mcs_80 |=
1015 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1016 he_mcs_nss_supp->rx_mcs_160 |=
1017 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1018 he_mcs_nss_supp->tx_mcs_160 |=
1019 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1020 he_mcs_nss_supp->rx_mcs_80p80 |=
1021 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1022 he_mcs_nss_supp->tx_mcs_80p80 |=
1023 cpu_to_le16(IEEE80211_HE_MCS_NOT_SUPPORTED << 2);
1024 }
1025
1026 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210 && !is_ap)
1027 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] |=
1028 IEEE80211_HE_PHY_CAP2_UL_MU_FULL_MU_MIMO;
1029
1030 switch (CSR_HW_RFID_TYPE(trans->hw_rf_id)) {
1031 case IWL_CFG_RF_TYPE_GF:
1032 case IWL_CFG_RF_TYPE_FM:
1033 case IWL_CFG_RF_TYPE_WH:
1034 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
1035 IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
1036 if (!is_ap)
1037 iftype_data->he_cap.he_cap_elem.phy_cap_info[9] |=
1038 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU;
1039 break;
1040 }
1041
1042 if (CSR_HW_REV_TYPE(trans->hw_rev) == IWL_CFG_MAC_TYPE_GL &&
1043 iftype_data->eht_cap.has_eht) {
1044 iftype_data->eht_cap.eht_cap_elem.mac_cap_info[0] &=
1045 ~(IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE1 |
1046 IEEE80211_EHT_MAC_CAP0_TRIG_TXOP_SHARING_MODE2);
1047 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[3] &=
1048 ~(IEEE80211_EHT_PHY_CAP0_PARTIAL_BW_UL_MU_MIMO |
1049 IEEE80211_EHT_PHY_CAP3_NG_16_SU_FEEDBACK |
1050 IEEE80211_EHT_PHY_CAP3_NG_16_MU_FEEDBACK |
1051 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
1052 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
1053 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK |
1054 IEEE80211_EHT_PHY_CAP3_TRIG_CQI_FDBK);
1055 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[4] &=
1056 ~(IEEE80211_EHT_PHY_CAP4_PART_BW_DL_MU_MIMO |
1057 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP);
1058 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] &=
1059 ~IEEE80211_EHT_PHY_CAP5_NON_TRIG_CQI_FEEDBACK;
1060 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[6] &=
1061 ~(IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK |
1062 IEEE80211_EHT_PHY_CAP6_EHT_DUP_6GHZ_SUPP);
1063 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[5] |=
1064 IEEE80211_EHT_PHY_CAP5_SUPP_EXTRA_EHT_LTF;
1065 }
1066
1067 if (fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_BROADCAST_TWT))
1068 iftype_data->he_cap.he_cap_elem.mac_cap_info[2] |=
1069 IEEE80211_HE_MAC_CAP2_BCAST_TWT;
1070
1071 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 &&
1072 !is_ap) {
1073 iftype_data->vendor_elems.data = iwl_vendor_caps;
1074 iftype_data->vendor_elems.len = ARRAY_SIZE(iwl_vendor_caps);
1075 }
1076
1077 if (!trans->cfg->ht_params->stbc) {
1078 iftype_data->he_cap.he_cap_elem.phy_cap_info[2] &=
1079 ~IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ;
1080 iftype_data->he_cap.he_cap_elem.phy_cap_info[7] &=
1081 ~IEEE80211_HE_PHY_CAP7_STBC_RX_ABOVE_80MHZ;
1082 }
1083
1084 if (trans->step_urm) {
1085 iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs11_max_nss = 0;
1086 iftype_data->eht_cap.eht_mcs_nss_supp.bw._320.rx_tx_mcs13_max_nss = 0;
1087 }
1088
1089 if (trans->no_160)
1090 iftype_data->he_cap.he_cap_elem.phy_cap_info[0] &=
1091 ~IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
1092
1093 if (trans->reduced_cap_sku) {
1094 memset(&iftype_data->eht_cap.eht_mcs_nss_supp.bw._320, 0,
1095 sizeof(iftype_data->eht_cap.eht_mcs_nss_supp.bw._320));
1096 iftype_data->eht_cap.eht_mcs_nss_supp.bw._80.rx_tx_mcs13_max_nss = 0;
1097 iftype_data->eht_cap.eht_mcs_nss_supp.bw._160.rx_tx_mcs13_max_nss = 0;
1098 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[8] &=
1099 ~IEEE80211_EHT_PHY_CAP8_RX_4096QAM_WIDER_BW_DL_OFDMA;
1100 iftype_data->eht_cap.eht_cap_elem.phy_cap_info[2] &=
1101 ~IEEE80211_EHT_PHY_CAP2_SOUNDING_DIM_320MHZ_MASK;
1102 }
1103 }
1104
1105 static void iwl_init_he_hw_capab(struct iwl_trans *trans,
1106 struct iwl_nvm_data *data,
1107 struct ieee80211_supported_band *sband,
1108 u8 tx_chains, u8 rx_chains,
1109 const struct iwl_fw *fw)
1110 {
1111 struct ieee80211_sband_iftype_data *iftype_data;
1112 int i;
1113
1114 BUILD_BUG_ON(sizeof(data->iftd.low) != sizeof(iwl_he_eht_capa));
1115 BUILD_BUG_ON(sizeof(data->iftd.high) != sizeof(iwl_he_eht_capa));
1116 BUILD_BUG_ON(sizeof(data->iftd.uhb) != sizeof(iwl_he_eht_capa));
1117
1118 switch (sband->band) {
1119 case NL80211_BAND_2GHZ:
1120 iftype_data = data->iftd.low;
1121 break;
1122 case NL80211_BAND_5GHZ:
1123 iftype_data = data->iftd.high;
1124 break;
1125 case NL80211_BAND_6GHZ:
1126 iftype_data = data->iftd.uhb;
1127 break;
1128 default:
1129 WARN_ON(1);
1130 return;
1131 }
1132
1133 memcpy(iftype_data, iwl_he_eht_capa, sizeof(iwl_he_eht_capa));
1134
1135 _ieee80211_set_sband_iftype_data(sband, iftype_data,
1136 ARRAY_SIZE(iwl_he_eht_capa));
1137
1138 for (i = 0; i < sband->n_iftype_data; i++)
1139 iwl_nvm_fixup_sband_iftd(trans, data, sband, &iftype_data[i],
1140 tx_chains, rx_chains, fw);
1141
1142 iwl_init_he_6ghz_capa(trans, data, sband, tx_chains, rx_chains);
1143 }
1144
1145 void iwl_reinit_cab(struct iwl_trans *trans, struct iwl_nvm_data *data,
1146 u8 tx_chains, u8 rx_chains, const struct iwl_fw *fw)
1147 {
1148 struct ieee80211_supported_band *sband;
1149
1150 sband = &data->bands[NL80211_BAND_2GHZ];
1151 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
1152 tx_chains, rx_chains);
1153
1154 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1155 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1156 fw);
1157
1158 sband = &data->bands[NL80211_BAND_5GHZ];
1159 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
1160 tx_chains, rx_chains);
1161 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
1162 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
1163 tx_chains, rx_chains);
1164
1165 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1166 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1167 fw);
1168
1169 sband = &data->bands[NL80211_BAND_6GHZ];
1170 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1171 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1172 fw);
1173 }
1174 IWL_EXPORT_SYMBOL(iwl_reinit_cab);
1175
1176 static void iwl_init_sbands(struct iwl_trans *trans,
1177 struct iwl_nvm_data *data,
1178 const void *nvm_ch_flags, u8 tx_chains,
1179 u8 rx_chains, u32 sbands_flags, bool v4,
1180 const struct iwl_fw *fw)
1181 {
1182 struct device *dev = trans->dev;
1183 int n_channels;
1184 int n_used = 0;
1185 struct ieee80211_supported_band *sband;
1186
1187 n_channels = iwl_init_channel_map(trans, fw, data, nvm_ch_flags,
1188 sbands_flags, v4);
1189 sband = &data->bands[NL80211_BAND_2GHZ];
1190 sband->band = NL80211_BAND_2GHZ;
1191 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
1192 sband->n_bitrates = N_RATES_24;
1193 n_used += iwl_init_sband_channels(data, sband, n_channels,
1194 NL80211_BAND_2GHZ);
1195 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ,
1196 tx_chains, rx_chains);
1197
1198 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1199 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1200 fw);
1201
1202 sband = &data->bands[NL80211_BAND_5GHZ];
1203 sband->band = NL80211_BAND_5GHZ;
1204 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
1205 sband->n_bitrates = N_RATES_52;
1206 n_used += iwl_init_sband_channels(data, sband, n_channels,
1207 NL80211_BAND_5GHZ);
1208 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ,
1209 tx_chains, rx_chains);
1210 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
1211 iwl_init_vht_hw_capab(trans, data, &sband->vht_cap,
1212 tx_chains, rx_chains);
1213
1214 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1215 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1216 fw);
1217
1218 /* 6GHz band. */
1219 sband = &data->bands[NL80211_BAND_6GHZ];
1220 sband->band = NL80211_BAND_6GHZ;
1221 /* use the same rates as 5GHz band */
1222 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
1223 sband->n_bitrates = N_RATES_52;
1224 n_used += iwl_init_sband_channels(data, sband, n_channels,
1225 NL80211_BAND_6GHZ);
1226
1227 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
1228 iwl_init_he_hw_capab(trans, data, sband, tx_chains, rx_chains,
1229 fw);
1230 else
1231 sband->n_channels = 0;
1232 if (n_channels != n_used)
1233 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
1234 n_used, n_channels);
1235 }
1236
1237 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
1238 const __le16 *phy_sku)
1239 {
1240 if (cfg->nvm_type != IWL_NVM_EXT)
1241 return le16_to_cpup(nvm_sw + SKU);
1242
1243 return le32_to_cpup((const __le32 *)(phy_sku + SKU_FAMILY_8000));
1244 }
1245
1246 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
1247 {
1248 if (cfg->nvm_type != IWL_NVM_EXT)
1249 return le16_to_cpup(nvm_sw + NVM_VERSION);
1250 else
1251 return le32_to_cpup((const __le32 *)(nvm_sw +
1252 NVM_VERSION_EXT_NVM));
1253 }
1254
1255 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
1256 const __le16 *phy_sku)
1257 {
1258 if (cfg->nvm_type != IWL_NVM_EXT)
1259 return le16_to_cpup(nvm_sw + RADIO_CFG);
1260
1261 return le32_to_cpup((const __le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
1262
1263 }
1264
1265 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
1266 {
1267 int n_hw_addr;
1268
1269 if (cfg->nvm_type != IWL_NVM_EXT)
1270 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
1271
1272 n_hw_addr = le32_to_cpup((const __le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
1273
1274 return n_hw_addr & N_HW_ADDR_MASK;
1275 }
1276
1277 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
1278 struct iwl_nvm_data *data,
1279 u32 radio_cfg)
1280 {
1281 if (cfg->nvm_type != IWL_NVM_EXT) {
1282 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
1283 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
1284 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
1285 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
1286 return;
1287 }
1288
1289 /* set the radio configuration for family 8000 */
1290 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
1291 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
1292 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
1293 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
1294 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
1295 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
1296 }
1297
1298 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
1299 {
1300 const u8 *hw_addr;
1301
1302 hw_addr = (const u8 *)&mac_addr0;
1303 dest[0] = hw_addr[3];
1304 dest[1] = hw_addr[2];
1305 dest[2] = hw_addr[1];
1306 dest[3] = hw_addr[0];
1307
1308 hw_addr = (const u8 *)&mac_addr1;
1309 dest[4] = hw_addr[1];
1310 dest[5] = hw_addr[0];
1311 }
1312
1313 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
1314 struct iwl_nvm_data *data)
1315 {
1316 __le32 mac_addr0 = cpu_to_le32(iwl_read32(trans,
1317 CSR_MAC_ADDR0_STRAP(trans)));
1318 __le32 mac_addr1 = cpu_to_le32(iwl_read32(trans,
1319 CSR_MAC_ADDR1_STRAP(trans)));
1320
1321 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1322 /*
1323 * If the OEM fused a valid address, use it instead of the one in the
1324 * OTP
1325 */
1326 if (is_valid_ether_addr(data->hw_addr))
1327 return;
1328
1329 mac_addr0 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR0_OTP(trans)));
1330 mac_addr1 = cpu_to_le32(iwl_read32(trans, CSR_MAC_ADDR1_OTP(trans)));
1331
1332 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1333 }
1334
1335 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
1336 const struct iwl_cfg *cfg,
1337 struct iwl_nvm_data *data,
1338 const __le16 *mac_override,
1339 const __be16 *nvm_hw)
1340 {
1341 const u8 *hw_addr;
1342
1343 if (mac_override) {
1344 static const u8 reserved_mac[] = {
1345 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
1346 };
1347
1348 hw_addr = (const u8 *)(mac_override +
1349 MAC_ADDRESS_OVERRIDE_EXT_NVM);
1350
1351 /*
1352 * Store the MAC address from MAO section.
1353 * No byte swapping is required in MAO section
1354 */
1355 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
1356
1357 /*
1358 * Force the use of the OTP MAC address in case of reserved MAC
1359 * address in the NVM, or if address is given but invalid.
1360 */
1361 if (is_valid_ether_addr(data->hw_addr) &&
1362 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
1363 return;
1364
1365 IWL_ERR(trans,
1366 "mac address from nvm override section is not valid\n");
1367 }
1368
1369 if (nvm_hw) {
1370 /* read the mac address from WFMP registers */
1371 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
1372 WFMP_MAC_ADDR_0));
1373 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
1374 WFMP_MAC_ADDR_1));
1375
1376 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
1377
1378 return;
1379 }
1380
1381 IWL_ERR(trans, "mac address is not found\n");
1382 }
1383
1384 static int iwl_set_hw_address(struct iwl_trans *trans,
1385 const struct iwl_cfg *cfg,
1386 struct iwl_nvm_data *data, const __be16 *nvm_hw,
1387 const __le16 *mac_override)
1388 {
1389 if (cfg->mac_addr_from_csr) {
1390 iwl_set_hw_address_from_csr(trans, data);
1391 } else if (cfg->nvm_type != IWL_NVM_EXT) {
1392 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
1393
1394 /* The byte order is little endian 16 bit, meaning 214365 */
1395 data->hw_addr[0] = hw_addr[1];
1396 data->hw_addr[1] = hw_addr[0];
1397 data->hw_addr[2] = hw_addr[3];
1398 data->hw_addr[3] = hw_addr[2];
1399 data->hw_addr[4] = hw_addr[5];
1400 data->hw_addr[5] = hw_addr[4];
1401 } else {
1402 iwl_set_hw_address_family_8000(trans, cfg, data,
1403 mac_override, nvm_hw);
1404 }
1405
1406 if (!is_valid_ether_addr(data->hw_addr)) {
1407 IWL_ERR(trans, "no valid mac address was found\n");
1408 return -EINVAL;
1409 }
1410
1411 if (!trans->csme_own)
1412 IWL_INFO(trans, "base HW address: %pM, OTP minor version: 0x%x\n",
1413 data->hw_addr, iwl_read_prph(trans, REG_OTP_MINOR));
1414
1415 return 0;
1416 }
1417
1418 static bool
1419 iwl_nvm_no_wide_in_5ghz(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1420 const __be16 *nvm_hw)
1421 {
1422 /*
1423 * Workaround a bug in Indonesia SKUs where the regulatory in
1424 * some 7000-family OTPs erroneously allow wide channels in
1425 * 5GHz. To check for Indonesia, we take the SKU value from
1426 * bits 1-4 in the subsystem ID and check if it is either 5 or
1427 * 9. In those cases, we need to force-disable wide channels
1428 * in 5GHz otherwise the FW will throw a sysassert when we try
1429 * to use them.
1430 */
1431 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) {
1432 /*
1433 * Unlike the other sections in the NVM, the hw
1434 * section uses big-endian.
1435 */
1436 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
1437 u8 sku = (subsystem_id & 0x1e) >> 1;
1438
1439 if (sku == 5 || sku == 9) {
1440 IWL_DEBUG_EEPROM(trans->dev,
1441 "disabling wide channels in 5GHz (0x%0x %d)\n",
1442 subsystem_id, sku);
1443 return true;
1444 }
1445 }
1446
1447 return false;
1448 }
1449
1450 struct iwl_nvm_data *
1451 iwl_parse_mei_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1452 const struct iwl_mei_nvm *mei_nvm,
1453 const struct iwl_fw *fw, u8 tx_ant, u8 rx_ant)
1454 {
1455 struct iwl_nvm_data *data;
1456 u32 sbands_flags = 0;
1457 u8 rx_chains = fw->valid_rx_ant;
1458 u8 tx_chains = fw->valid_rx_ant;
1459
1460 if (cfg->uhb_supported)
1461 data = kzalloc(struct_size(data, channels,
1462 IWL_NVM_NUM_CHANNELS_UHB),
1463 GFP_KERNEL);
1464 else
1465 data = kzalloc(struct_size(data, channels,
1466 IWL_NVM_NUM_CHANNELS_EXT),
1467 GFP_KERNEL);
1468 if (!data)
1469 return NULL;
1470
1471 BUILD_BUG_ON(ARRAY_SIZE(mei_nvm->channels) !=
1472 IWL_NVM_NUM_CHANNELS_UHB);
1473 data->nvm_version = mei_nvm->nvm_version;
1474
1475 iwl_set_radio_cfg(cfg, data, mei_nvm->radio_cfg);
1476 if (data->valid_tx_ant)
1477 tx_chains &= data->valid_tx_ant;
1478 if (data->valid_rx_ant)
1479 rx_chains &= data->valid_rx_ant;
1480 if (tx_ant)
1481 tx_chains &= tx_ant;
1482 if (rx_ant)
1483 rx_chains &= rx_ant;
1484
1485 data->sku_cap_mimo_disabled = false;
1486 data->sku_cap_band_24ghz_enable = true;
1487 data->sku_cap_band_52ghz_enable = true;
1488 data->sku_cap_11n_enable =
1489 !(iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL);
1490 data->sku_cap_11ac_enable = true;
1491 data->sku_cap_11ax_enable =
1492 mei_nvm->caps & MEI_NVM_CAPS_11AX_SUPPORT;
1493
1494 data->lar_enabled = mei_nvm->caps & MEI_NVM_CAPS_LARI_SUPPORT;
1495
1496 data->n_hw_addrs = mei_nvm->n_hw_addrs;
1497 /* If no valid mac address was found - bail out */
1498 if (iwl_set_hw_address(trans, cfg, data, NULL, NULL)) {
1499 kfree(data);
1500 return NULL;
1501 }
1502
1503 if (data->lar_enabled &&
1504 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1505 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1506
1507 iwl_init_sbands(trans, data, mei_nvm->channels, tx_chains, rx_chains,
1508 sbands_flags, true, fw);
1509
1510 return data;
1511 }
1512 IWL_EXPORT_SYMBOL(iwl_parse_mei_nvm_data);
1513
1514 struct iwl_nvm_data *
1515 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
1516 const struct iwl_fw *fw,
1517 const __be16 *nvm_hw, const __le16 *nvm_sw,
1518 const __le16 *nvm_calib, const __le16 *regulatory,
1519 const __le16 *mac_override, const __le16 *phy_sku,
1520 u8 tx_chains, u8 rx_chains)
1521 {
1522 struct iwl_nvm_data *data;
1523 bool lar_enabled;
1524 u32 sku, radio_cfg;
1525 u32 sbands_flags = 0;
1526 u16 lar_config;
1527 const __le16 *ch_section;
1528
1529 if (cfg->uhb_supported)
1530 data = kzalloc(struct_size(data, channels,
1531 IWL_NVM_NUM_CHANNELS_UHB),
1532 GFP_KERNEL);
1533 else if (cfg->nvm_type != IWL_NVM_EXT)
1534 data = kzalloc(struct_size(data, channels,
1535 IWL_NVM_NUM_CHANNELS),
1536 GFP_KERNEL);
1537 else
1538 data = kzalloc(struct_size(data, channels,
1539 IWL_NVM_NUM_CHANNELS_EXT),
1540 GFP_KERNEL);
1541 if (!data)
1542 return NULL;
1543
1544 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
1545
1546 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
1547 iwl_set_radio_cfg(cfg, data, radio_cfg);
1548 if (data->valid_tx_ant)
1549 tx_chains &= data->valid_tx_ant;
1550 if (data->valid_rx_ant)
1551 rx_chains &= data->valid_rx_ant;
1552
1553 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
1554 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
1555 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
1556 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
1557 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
1558 data->sku_cap_11n_enable = false;
1559 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
1560 (sku & NVM_SKU_CAP_11AC_ENABLE);
1561 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
1562
1563 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
1564
1565 if (cfg->nvm_type != IWL_NVM_EXT) {
1566 /* Checking for required sections */
1567 if (!nvm_calib) {
1568 IWL_ERR(trans,
1569 "Can't parse empty Calib NVM sections\n");
1570 kfree(data);
1571 return NULL;
1572 }
1573
1574 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
1575 &regulatory[NVM_CHANNELS_SDP] :
1576 &nvm_sw[NVM_CHANNELS];
1577
1578 lar_enabled = true;
1579 } else {
1580 u16 lar_offset = data->nvm_version < 0xE39 ?
1581 NVM_LAR_OFFSET_OLD :
1582 NVM_LAR_OFFSET;
1583
1584 lar_config = le16_to_cpup(regulatory + lar_offset);
1585 data->lar_enabled = !!(lar_config &
1586 NVM_LAR_ENABLED);
1587 lar_enabled = data->lar_enabled;
1588 ch_section = &regulatory[NVM_CHANNELS_EXTENDED];
1589 }
1590
1591 /* If no valid mac address was found - bail out */
1592 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
1593 kfree(data);
1594 return NULL;
1595 }
1596
1597 if (lar_enabled &&
1598 fw_has_capa(&fw->ucode_capa, IWL_UCODE_TLV_CAPA_LAR_SUPPORT))
1599 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1600
1601 if (iwl_nvm_no_wide_in_5ghz(trans, cfg, nvm_hw))
1602 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
1603
1604 iwl_init_sbands(trans, data, ch_section, tx_chains, rx_chains,
1605 sbands_flags, false, fw);
1606 data->calib_version = 255;
1607
1608 return data;
1609 }
1610 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
1611
1612 static u32 iwl_nvm_get_regdom_bw_flags(const u16 *nvm_chan,
1613 int ch_idx, u16 nvm_flags,
1614 struct iwl_reg_capa reg_capa,
1615 const struct iwl_cfg *cfg)
1616 {
1617 u32 flags = NL80211_RRF_NO_HT40;
1618
1619 if (ch_idx < NUM_2GHZ_CHANNELS &&
1620 (nvm_flags & NVM_CHANNEL_40MHZ)) {
1621 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
1622 flags &= ~NL80211_RRF_NO_HT40PLUS;
1623 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
1624 flags &= ~NL80211_RRF_NO_HT40MINUS;
1625 } else if (ch_idx < NUM_2GHZ_CHANNELS + NUM_5GHZ_CHANNELS &&
1626 nvm_flags & NVM_CHANNEL_40MHZ) {
1627 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
1628 flags &= ~NL80211_RRF_NO_HT40PLUS;
1629 else
1630 flags &= ~NL80211_RRF_NO_HT40MINUS;
1631 } else if (nvm_flags & NVM_CHANNEL_40MHZ) {
1632 flags &= ~NL80211_RRF_NO_HT40PLUS;
1633 flags &= ~NL80211_RRF_NO_HT40MINUS;
1634 }
1635
1636 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
1637 flags |= NL80211_RRF_NO_80MHZ;
1638 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
1639 flags |= NL80211_RRF_NO_160MHZ;
1640
1641 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
1642 flags |= NL80211_RRF_NO_IR;
1643
1644 if (nvm_flags & NVM_CHANNEL_RADAR)
1645 flags |= NL80211_RRF_DFS;
1646
1647 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
1648 flags |= NL80211_RRF_NO_OUTDOOR;
1649
1650 /* Set the GO concurrent flag only in case that NO_IR is set.
1651 * Otherwise it is meaningless
1652 */
1653 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT)) {
1654 if (flags & NL80211_RRF_NO_IR)
1655 flags |= NL80211_RRF_GO_CONCURRENT;
1656 if (flags & NL80211_RRF_DFS) {
1657 flags |= NL80211_RRF_DFS_CONCURRENT;
1658 /* Our device doesn't set active bit for DFS channels
1659 * however, once marked as DFS no-ir is not needed.
1660 */
1661 flags &= ~NL80211_RRF_NO_IR;
1662 }
1663 }
1664
1665 /* Set the AP type for the UHB case. */
1666 if (nvm_flags & NVM_CHANNEL_VLP)
1667 flags |= NL80211_RRF_ALLOW_6GHZ_VLP_AP;
1668 else
1669 flags |= NL80211_RRF_NO_6GHZ_VLP_CLIENT;
1670
1671 if (!(nvm_flags & NVM_CHANNEL_AFC))
1672 flags |= NL80211_RRF_NO_6GHZ_AFC_CLIENT;
1673
1674 /*
1675 * reg_capa is per regulatory domain so apply it for every channel
1676 */
1677 if (ch_idx >= NUM_2GHZ_CHANNELS) {
1678 if (!reg_capa.allow_40mhz)
1679 flags |= NL80211_RRF_NO_HT40;
1680
1681 if (!reg_capa.allow_80mhz)
1682 flags |= NL80211_RRF_NO_80MHZ;
1683
1684 if (!reg_capa.allow_160mhz)
1685 flags |= NL80211_RRF_NO_160MHZ;
1686
1687 if (!reg_capa.allow_320mhz)
1688 flags |= NL80211_RRF_NO_320MHZ;
1689 }
1690
1691 if (reg_capa.disable_11ax)
1692 flags |= NL80211_RRF_NO_HE;
1693
1694 if (reg_capa.disable_11be)
1695 flags |= NL80211_RRF_NO_EHT;
1696
1697 return flags;
1698 }
1699
1700 static struct iwl_reg_capa iwl_get_reg_capa(u32 flags, u8 resp_ver)
1701 {
1702 struct iwl_reg_capa reg_capa = {};
1703
1704 if (resp_ver >= REG_CAPA_V4_RESP_VER) {
1705 reg_capa.allow_40mhz = true;
1706 reg_capa.allow_80mhz = flags & REG_CAPA_V4_80MHZ_ALLOWED;
1707 reg_capa.allow_160mhz = flags & REG_CAPA_V4_160MHZ_ALLOWED;
1708 reg_capa.allow_320mhz = flags & REG_CAPA_V4_320MHZ_ALLOWED;
1709 reg_capa.disable_11ax = flags & REG_CAPA_V4_11AX_DISABLED;
1710 reg_capa.disable_11be = flags & REG_CAPA_V4_11BE_DISABLED;
1711 } else if (resp_ver >= REG_CAPA_V2_RESP_VER) {
1712 reg_capa.allow_40mhz = flags & REG_CAPA_V2_40MHZ_ALLOWED;
1713 reg_capa.allow_80mhz = flags & REG_CAPA_V2_80MHZ_ALLOWED;
1714 reg_capa.allow_160mhz = flags & REG_CAPA_V2_160MHZ_ALLOWED;
1715 reg_capa.disable_11ax = flags & REG_CAPA_V2_11AX_DISABLED;
1716 } else {
1717 reg_capa.allow_40mhz = !(flags & REG_CAPA_V1_40MHZ_FORBIDDEN);
1718 reg_capa.allow_80mhz = flags & REG_CAPA_V1_80MHZ_ALLOWED;
1719 reg_capa.allow_160mhz = flags & REG_CAPA_V1_160MHZ_ALLOWED;
1720 reg_capa.disable_11ax = flags & REG_CAPA_V1_11AX_DISABLED;
1721 }
1722 return reg_capa;
1723 }
1724
1725 struct ieee80211_regdomain *
1726 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1727 int num_of_ch, __le32 *channels, u16 fw_mcc,
1728 u16 geo_info, u32 cap, u8 resp_ver)
1729 {
1730 int ch_idx;
1731 u16 ch_flags;
1732 u32 reg_rule_flags, prev_reg_rule_flags = 0;
1733 const u16 *nvm_chan;
1734 struct ieee80211_regdomain *regd, *copy_rd;
1735 struct ieee80211_reg_rule *rule;
1736 int center_freq, prev_center_freq = 0;
1737 int valid_rules = 0;
1738 bool new_rule;
1739 int max_num_ch;
1740 struct iwl_reg_capa reg_capa;
1741
1742 if (cfg->uhb_supported) {
1743 max_num_ch = IWL_NVM_NUM_CHANNELS_UHB;
1744 nvm_chan = iwl_uhb_nvm_channels;
1745 } else if (cfg->nvm_type == IWL_NVM_EXT) {
1746 max_num_ch = IWL_NVM_NUM_CHANNELS_EXT;
1747 nvm_chan = iwl_ext_nvm_channels;
1748 } else {
1749 max_num_ch = IWL_NVM_NUM_CHANNELS;
1750 nvm_chan = iwl_nvm_channels;
1751 }
1752
1753 if (num_of_ch > max_num_ch) {
1754 IWL_DEBUG_DEV(dev, IWL_DL_LAR,
1755 "Num of channels (%d) is greater than expected. Truncating to %d\n",
1756 num_of_ch, max_num_ch);
1757 num_of_ch = max_num_ch;
1758 }
1759
1760 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1761 return ERR_PTR(-EINVAL);
1762
1763 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1764 num_of_ch);
1765
1766 /* build a regdomain rule for every valid channel */
1767 regd = kzalloc(struct_size(regd, reg_rules, num_of_ch), GFP_KERNEL);
1768 if (!regd)
1769 return ERR_PTR(-ENOMEM);
1770
1771 /* set alpha2 from FW. */
1772 regd->alpha2[0] = fw_mcc >> 8;
1773 regd->alpha2[1] = fw_mcc & 0xff;
1774
1775 /* parse regulatory capability flags */
1776 reg_capa = iwl_get_reg_capa(cap, resp_ver);
1777
1778 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1779 enum nl80211_band band =
1780 iwl_nl80211_band_from_channel_idx(ch_idx);
1781
1782 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1783 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1784 band);
1785 new_rule = false;
1786
1787 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1788 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1789 nvm_chan[ch_idx], ch_flags);
1790 continue;
1791 }
1792
1793 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1794 ch_flags, reg_capa,
1795 cfg);
1796
1797 /* we can't continue the same rule */
1798 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1799 center_freq - prev_center_freq > 20) {
1800 valid_rules++;
1801 new_rule = true;
1802 }
1803
1804 rule = &regd->reg_rules[valid_rules - 1];
1805
1806 if (new_rule)
1807 rule->freq_range.start_freq_khz =
1808 MHZ_TO_KHZ(center_freq - 10);
1809
1810 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1811
1812 /* this doesn't matter - not used by FW */
1813 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1814 rule->power_rule.max_eirp =
1815 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1816
1817 rule->flags = reg_rule_flags;
1818
1819 /* rely on auto-calculation to merge BW of contiguous chans */
1820 rule->flags |= NL80211_RRF_AUTO_BW;
1821 rule->freq_range.max_bandwidth_khz = 0;
1822
1823 prev_center_freq = center_freq;
1824 prev_reg_rule_flags = reg_rule_flags;
1825
1826 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1827 nvm_chan[ch_idx], ch_flags);
1828
1829 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1830 band == NL80211_BAND_2GHZ)
1831 continue;
1832
1833 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1834 }
1835
1836 /*
1837 * Certain firmware versions might report no valid channels
1838 * if booted in RF-kill, i.e. not all calibrations etc. are
1839 * running. We'll get out of this situation later when the
1840 * rfkill is removed and we update the regdomain again, but
1841 * since cfg80211 doesn't accept an empty regdomain, add a
1842 * dummy (unusable) rule here in this case so we can init.
1843 */
1844 if (!valid_rules) {
1845 valid_rules = 1;
1846 rule = &regd->reg_rules[valid_rules - 1];
1847 rule->freq_range.start_freq_khz = MHZ_TO_KHZ(2412);
1848 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(2413);
1849 rule->freq_range.max_bandwidth_khz = MHZ_TO_KHZ(1);
1850 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1851 rule->power_rule.max_eirp =
1852 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1853 }
1854
1855 regd->n_reg_rules = valid_rules;
1856
1857 /*
1858 * Narrow down regdom for unused regulatory rules to prevent hole
1859 * between reg rules to wmm rules.
1860 */
1861 copy_rd = kmemdup(regd, struct_size(regd, reg_rules, valid_rules),
1862 GFP_KERNEL);
1863 if (!copy_rd)
1864 copy_rd = ERR_PTR(-ENOMEM);
1865
1866 kfree(regd);
1867 return copy_rd;
1868 }
1869 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1870
1871 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58
1872 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
1873 #define MAX_NVM_FILE_LEN 16384
1874
1875 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1876 unsigned int len)
1877 {
1878 #define IWL_4165_DEVICE_ID 0x5501
1879 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1880
1881 if (section == NVM_SECTION_TYPE_PHY_SKU &&
1882 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1883 (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1884 /* OTP 0x52 bug work around: it's a 1x1 device */
1885 data[3] = ANT_B | (ANT_B << 4);
1886 }
1887 IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1888
1889 /*
1890 * Reads external NVM from a file into mvm->nvm_sections
1891 *
1892 * HOW TO CREATE THE NVM FILE FORMAT:
1893 * ------------------------------
1894 * 1. create hex file, format:
1895 * 3800 -> header
1896 * 0000 -> header
1897 * 5a40 -> data
1898 *
1899 * rev - 6 bit (word1)
1900 * len - 10 bit (word1)
1901 * id - 4 bit (word2)
1902 * rsv - 12 bit (word2)
1903 *
1904 * 2. flip 8bits with 8 bits per line to get the right NVM file format
1905 *
1906 * 3. create binary file from the hex file
1907 *
1908 * 4. save as "iNVM_xxx.bin" under /lib/firmware
1909 */
1910 int iwl_read_external_nvm(struct iwl_trans *trans,
1911 const char *nvm_file_name,
1912 struct iwl_nvm_section *nvm_sections)
1913 {
1914 int ret, section_size;
1915 u16 section_id;
1916 const struct firmware *fw_entry;
1917 const struct {
1918 __le16 word1;
1919 __le16 word2;
1920 u8 data[];
1921 } *file_sec;
1922 const u8 *eof;
1923 u8 *temp;
1924 int max_section_size;
1925 const __le32 *dword_buff;
1926
1927 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1928 #define NVM_WORD2_ID(x) (x >> 12)
1929 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1930 #define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1931 #define NVM_HEADER_0 (0x2A504C54)
1932 #define NVM_HEADER_1 (0x4E564D2A)
1933 #define NVM_HEADER_SIZE (4 * sizeof(u32))
1934
1935 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1936
1937 /* Maximal size depends on NVM version */
1938 if (trans->cfg->nvm_type != IWL_NVM_EXT)
1939 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1940 else
1941 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1942
1943 /*
1944 * Obtain NVM image via request_firmware. Since we already used
1945 * request_firmware_nowait() for the firmware binary load and only
1946 * get here after that we assume the NVM request can be satisfied
1947 * synchronously.
1948 */
1949 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1950 if (ret) {
1951 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1952 nvm_file_name, ret);
1953 return ret;
1954 }
1955
1956 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1957 nvm_file_name, fw_entry->size);
1958
1959 if (fw_entry->size > MAX_NVM_FILE_LEN) {
1960 IWL_ERR(trans, "NVM file too large\n");
1961 ret = -EINVAL;
1962 goto out;
1963 }
1964
1965 eof = fw_entry->data + fw_entry->size;
1966 dword_buff = (const __le32 *)fw_entry->data;
1967
1968 /* some NVM file will contain a header.
1969 * The header is identified by 2 dwords header as follow:
1970 * dword[0] = 0x2A504C54
1971 * dword[1] = 0x4E564D2A
1972 *
1973 * This header must be skipped when providing the NVM data to the FW.
1974 */
1975 if (fw_entry->size > NVM_HEADER_SIZE &&
1976 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1977 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1978 file_sec = (const void *)(fw_entry->data + NVM_HEADER_SIZE);
1979 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1980 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1981 le32_to_cpu(dword_buff[3]));
1982
1983 /* nvm file validation, dword_buff[2] holds the file version */
1984 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1985 trans->hw_rev_step == SILICON_C_STEP &&
1986 le32_to_cpu(dword_buff[2]) < 0xE4A) {
1987 ret = -EFAULT;
1988 goto out;
1989 }
1990 } else {
1991 file_sec = (const void *)fw_entry->data;
1992 }
1993
1994 while (true) {
1995 if (file_sec->data > eof) {
1996 IWL_ERR(trans,
1997 "ERROR - NVM file too short for section header\n");
1998 ret = -EINVAL;
1999 break;
2000 }
2001
2002 /* check for EOF marker */
2003 if (!file_sec->word1 && !file_sec->word2) {
2004 ret = 0;
2005 break;
2006 }
2007
2008 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
2009 section_size =
2010 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
2011 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
2012 } else {
2013 section_size = 2 * EXT_NVM_WORD2_LEN(
2014 le16_to_cpu(file_sec->word2));
2015 section_id = EXT_NVM_WORD1_ID(
2016 le16_to_cpu(file_sec->word1));
2017 }
2018
2019 if (section_size > max_section_size) {
2020 IWL_ERR(trans, "ERROR - section too large (%d)\n",
2021 section_size);
2022 ret = -EINVAL;
2023 break;
2024 }
2025
2026 if (!section_size) {
2027 IWL_ERR(trans, "ERROR - section empty\n");
2028 ret = -EINVAL;
2029 break;
2030 }
2031
2032 if (file_sec->data + section_size > eof) {
2033 IWL_ERR(trans,
2034 "ERROR - NVM file too short for section (%d bytes)\n",
2035 section_size);
2036 ret = -EINVAL;
2037 break;
2038 }
2039
2040 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
2041 "Invalid NVM section ID %d\n", section_id)) {
2042 ret = -EINVAL;
2043 break;
2044 }
2045
2046 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
2047 if (!temp) {
2048 ret = -ENOMEM;
2049 break;
2050 }
2051
2052 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
2053
2054 kfree(nvm_sections[section_id].data);
2055 nvm_sections[section_id].data = temp;
2056 nvm_sections[section_id].length = section_size;
2057
2058 /* advance to the next section */
2059 file_sec = (const void *)(file_sec->data + section_size);
2060 }
2061 out:
2062 release_firmware(fw_entry);
2063 return ret;
2064 }
2065 IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
2066
2067 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
2068 const struct iwl_fw *fw,
2069 u8 set_tx_ant, u8 set_rx_ant)
2070 {
2071 struct iwl_nvm_get_info cmd = {};
2072 struct iwl_nvm_data *nvm;
2073 struct iwl_host_cmd hcmd = {
2074 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
2075 .data = { &cmd, },
2076 .len = { sizeof(cmd) },
2077 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
2078 };
2079 int ret;
2080 bool empty_otp;
2081 u32 mac_flags;
2082 u32 sbands_flags = 0;
2083 u8 tx_ant;
2084 u8 rx_ant;
2085
2086 /*
2087 * All the values in iwl_nvm_get_info_rsp v4 are the same as
2088 * in v3, except for the channel profile part of the
2089 * regulatory. So we can just access the new struct, with the
2090 * exception of the latter.
2091 */
2092 struct iwl_nvm_get_info_rsp *rsp;
2093 struct iwl_nvm_get_info_rsp_v3 *rsp_v3;
2094 bool v4 = fw_has_api(&fw->ucode_capa,
2095 IWL_UCODE_TLV_API_REGULATORY_NVM_INFO);
2096 size_t rsp_size = v4 ? sizeof(*rsp) : sizeof(*rsp_v3);
2097 void *channel_profile;
2098
2099 ret = iwl_trans_send_cmd(trans, &hcmd);
2100 if (ret)
2101 return ERR_PTR(ret);
2102
2103 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != rsp_size,
2104 "Invalid payload len in NVM response from FW %d",
2105 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
2106 ret = -EINVAL;
2107 goto out;
2108 }
2109
2110 rsp = (void *)hcmd.resp_pkt->data;
2111 empty_otp = !!(le32_to_cpu(rsp->general.flags) &
2112 NVM_GENERAL_FLAGS_EMPTY_OTP);
2113 if (empty_otp)
2114 IWL_INFO(trans, "OTP is empty\n");
2115
2116 nvm = kzalloc(struct_size(nvm, channels, IWL_NUM_CHANNELS), GFP_KERNEL);
2117 if (!nvm) {
2118 ret = -ENOMEM;
2119 goto out;
2120 }
2121
2122 iwl_set_hw_address_from_csr(trans, nvm);
2123 /* TODO: if platform NVM has MAC address - override it here */
2124
2125 if (!is_valid_ether_addr(nvm->hw_addr)) {
2126 IWL_ERR(trans, "no valid mac address was found\n");
2127 ret = -EINVAL;
2128 goto err_free;
2129 }
2130
2131 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
2132
2133 /* Initialize general data */
2134 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
2135 nvm->n_hw_addrs = rsp->general.n_hw_addrs;
2136 if (nvm->n_hw_addrs == 0)
2137 IWL_WARN(trans,
2138 "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
2139 empty_otp);
2140
2141 /* Initialize MAC sku data */
2142 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
2143 nvm->sku_cap_11ac_enable =
2144 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
2145 nvm->sku_cap_11n_enable =
2146 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
2147 nvm->sku_cap_11ax_enable =
2148 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
2149 nvm->sku_cap_band_24ghz_enable =
2150 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
2151 nvm->sku_cap_band_52ghz_enable =
2152 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
2153 nvm->sku_cap_mimo_disabled =
2154 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
2155 if (CSR_HW_RFID_TYPE(trans->hw_rf_id) >= IWL_CFG_RF_TYPE_FM)
2156 nvm->sku_cap_11be_enable = true;
2157
2158 /* Initialize PHY sku data */
2159 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
2160 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
2161
2162 if (le32_to_cpu(rsp->regulatory.lar_enabled) &&
2163 fw_has_capa(&fw->ucode_capa,
2164 IWL_UCODE_TLV_CAPA_LAR_SUPPORT)) {
2165 nvm->lar_enabled = true;
2166 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
2167 }
2168
2169 rsp_v3 = (void *)rsp;
2170 channel_profile = v4 ? (void *)rsp->regulatory.channel_profile :
2171 (void *)rsp_v3->regulatory.channel_profile;
2172
2173 tx_ant = nvm->valid_tx_ant & fw->valid_tx_ant;
2174 rx_ant = nvm->valid_rx_ant & fw->valid_rx_ant;
2175
2176 if (set_tx_ant)
2177 tx_ant &= set_tx_ant;
2178 if (set_rx_ant)
2179 rx_ant &= set_rx_ant;
2180
2181 iwl_init_sbands(trans, nvm, channel_profile, tx_ant, rx_ant,
2182 sbands_flags, v4, fw);
2183
2184 iwl_free_resp(&hcmd);
2185 return nvm;
2186
2187 err_free:
2188 kfree(nvm);
2189 out:
2190 iwl_free_resp(&hcmd);
2191 return ERR_PTR(ret);
2192 }
2193 IWL_EXPORT_SYMBOL(iwl_get_nvm);
Kernel DRM miscellaneous fixes and cross-tree changes