drivers/net/wireless/mediatek/mt76/mt7615/mcu.h

   1 /* SPDX-License-Identifier: ISC */
   2 /* Copyright (C) 2019 MediaTek Inc. */
   3
   4 #ifndef __MT7615_MCU_H
   5 #define __MT7615_MCU_H
   6
   7 #include "../mt76_connac_mcu.h"
   8
   9 struct mt7615_mcu_txd {
  10         __le32 txd[8];
  11
  12         __le16 len;
  13         __le16 pq_id;
  14
  15         u8 cid;
  16         u8 pkt_type;
  17         u8 set_query; /* FW don't care */
  18         u8 seq;
  19
  20         u8 uc_d2b0_rev;
  21         u8 ext_cid;
  22         u8 s2d_index;
  23         u8 ext_cid_ack;
  24
  25         u32 reserved[5];
  26 } __packed __aligned(4);
  27
  28 /**
  29  * struct mt7615_uni_txd - mcu command descriptor for firmware v3
  30  * @txd: hardware descriptor
  31  * @len: total length not including txd
  32  * @cid: command identifier
  33  * @pkt_type: must be 0xa0 (cmd packet by long format)
  34  * @frag_n: fragment number
  35  * @seq: sequence number
  36  * @checksum: 0 mean there is no checksum
  37  * @s2d_index: index for command source and destination
  38  *  Definition              | value | note
  39  *  CMD_S2D_IDX_H2N         | 0x00  | command from HOST to WM
  40  *  CMD_S2D_IDX_C2N         | 0x01  | command from WA to WM
  41  *  CMD_S2D_IDX_H2C         | 0x02  | command from HOST to WA
  42  *  CMD_S2D_IDX_H2N_AND_H2C | 0x03  | command from HOST to WA and WM
  43  *
  44  * @option: command option
  45  *  BIT[0]: UNI_CMD_OPT_BIT_ACK
  46  *          set to 1 to request a fw reply
  47  *          if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY
  48  *          is set, mcu firmware will send response event EID = 0x01
  49  *          (UNI_EVENT_ID_CMD_RESULT) to the host.
  50  *  BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD
  51  *          0: original command
  52  *          1: unified command
  53  *  BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY
  54  *          0: QUERY command
  55  *          1: SET command
  56  */
  57 struct mt7615_uni_txd {
  58         __le32 txd[8];
  59
  60         /* DW1 */
  61         __le16 len;
  62         __le16 cid;
  63
  64         /* DW2 */
  65         u8 reserved;
  66         u8 pkt_type;
  67         u8 frag_n;
  68         u8 seq;
  69
  70         /* DW3 */
  71         __le16 checksum;
  72         u8 s2d_index;
  73         u8 option;
  74
  75         /* DW4 */
  76         u8 reserved2[4];
  77 } __packed __aligned(4);
  78
  79 enum {
  80     MT_SKU_CCK_1_2 = 0,
  81     MT_SKU_CCK_55_11,
  82     MT_SKU_OFDM_6_9,
  83     MT_SKU_OFDM_12_18,
  84     MT_SKU_OFDM_24_36,
  85     MT_SKU_OFDM_48,
  86     MT_SKU_OFDM_54,
  87     MT_SKU_HT20_0_8,
  88     MT_SKU_HT20_32,
  89     MT_SKU_HT20_1_2_9_10,
  90     MT_SKU_HT20_3_4_11_12,
  91     MT_SKU_HT20_5_13,
  92     MT_SKU_HT20_6_14,
  93     MT_SKU_HT20_7_15,
  94     MT_SKU_HT40_0_8,
  95     MT_SKU_HT40_32,
  96     MT_SKU_HT40_1_2_9_10,
  97     MT_SKU_HT40_3_4_11_12,
  98     MT_SKU_HT40_5_13,
  99     MT_SKU_HT40_6_14,
 100     MT_SKU_HT40_7_15,
 101     MT_SKU_VHT20_0,
 102     MT_SKU_VHT20_1_2,
 103     MT_SKU_VHT20_3_4,
 104     MT_SKU_VHT20_5_6,
 105     MT_SKU_VHT20_7,
 106     MT_SKU_VHT20_8,
 107     MT_SKU_VHT20_9,
 108     MT_SKU_VHT40_0,
 109     MT_SKU_VHT40_1_2,
 110     MT_SKU_VHT40_3_4,
 111     MT_SKU_VHT40_5_6,
 112     MT_SKU_VHT40_7,
 113     MT_SKU_VHT40_8,
 114     MT_SKU_VHT40_9,
 115     MT_SKU_VHT80_0,
 116     MT_SKU_VHT80_1_2,
 117     MT_SKU_VHT80_3_4,
 118     MT_SKU_VHT80_5_6,
 119     MT_SKU_VHT80_7,
 120     MT_SKU_VHT80_8,
 121     MT_SKU_VHT80_9,
 122     MT_SKU_VHT160_0,
 123     MT_SKU_VHT160_1_2,
 124     MT_SKU_VHT160_3_4,
 125     MT_SKU_VHT160_5_6,
 126     MT_SKU_VHT160_7,
 127     MT_SKU_VHT160_8,
 128     MT_SKU_VHT160_9,
 129     MT_SKU_1SS_DELTA,
 130     MT_SKU_2SS_DELTA,
 131     MT_SKU_3SS_DELTA,
 132     MT_SKU_4SS_DELTA,
 133 };
 134
 135 struct mt7615_mcu_rxd {
 136         __le32 rxd[4];
 137
 138         __le16 len;
 139         __le16 pkt_type_id;
 140
 141         u8 eid;
 142         u8 seq;
 143         __le16 __rsv;
 144
 145         u8 ext_eid;
 146         u8 __rsv1[2];
 147         u8 s2d_index;
 148 };
 149
 150 struct mt7615_mcu_csa_notify {
 151         struct mt7615_mcu_rxd rxd;
 152
 153         u8 omac_idx;
 154         u8 csa_count;
 155         u8 rsv[2];
 156 } __packed;
 157
 158 struct mt7615_mcu_rdd_report {
 159         struct mt7615_mcu_rxd rxd;
 160
 161         u8 band_idx;
 162         u8 long_detected;
 163         u8 constant_prf_detected;
 164         u8 staggered_prf_detected;
 165         u8 radar_type_idx;
 166         u8 periodic_pulse_num;
 167         u8 long_pulse_num;
 168         u8 hw_pulse_num;
 169
 170         u8 out_lpn;
 171         u8 out_spn;
 172         u8 out_crpn;
 173         u8 out_crpw;
 174         u8 out_crbn;
 175         u8 out_stgpn;
 176         u8 out_stgpw;
 177
 178         u8 _rsv[2];
 179
 180         __le32 out_pri_const;
 181         __le32 out_pri_stg[3];
 182
 183         struct {
 184                 __le32 start;
 185                 __le16 pulse_width;
 186                 __le16 pulse_power;
 187         } long_pulse[32];
 188
 189         struct {
 190                 __le32 start;
 191                 __le16 pulse_width;
 192                 __le16 pulse_power;
 193         } periodic_pulse[32];
 194
 195         struct {
 196                 __le32 start;
 197                 __le16 pulse_width;
 198                 __le16 pulse_power;
 199                 u8 sc_pass;
 200                 u8 sw_reset;
 201         } hw_pulse[32];
 202 };
 203
 204 enum {
 205         MCU_ATE_SET_FREQ_OFFSET = 0xa,
 206         MCU_ATE_SET_TX_POWER_CONTROL = 0x15,
 207 };
 208
 209 struct mt7615_roc_tlv {
 210         u8 bss_idx;
 211         u8 token;
 212         u8 active;
 213         u8 primary_chan;
 214         u8 sco;
 215         u8 band;
 216         u8 width;       /* To support 80/160MHz bandwidth */
 217         u8 freq_seg1;   /* To support 80/160MHz bandwidth */
 218         u8 freq_seg2;   /* To support 80/160MHz bandwidth */
 219         u8 req_type;
 220         u8 dbdc_band;
 221         u8 rsv0;
 222         __le32 max_interval;    /* ms */
 223         u8 rsv1[8];
 224 } __packed;
 225
 226 enum {
 227         FW_STATE_PWR_ON = 1,
 228         FW_STATE_N9_RDY = 2,
 229 };
 230
 231 enum {
 232         DBDC_TYPE_WMM,
 233         DBDC_TYPE_MGMT,
 234         DBDC_TYPE_BSS,
 235         DBDC_TYPE_MBSS,
 236         DBDC_TYPE_REPEATER,
 237         DBDC_TYPE_MU,
 238         DBDC_TYPE_BF,
 239         DBDC_TYPE_PTA,
 240         __DBDC_TYPE_MAX,
 241 };
 242
 243 #endif