1 /* SPDX-License-Identifier: ISC */
2 /* Copyright (C) 2020 MediaTek Inc. */
7 #include "../mt76_connac2_mac.h"
9 #define MT_TX_FREE_VER GENMASK(18, 16)
10 #define MT_TX_FREE_MSDU_CNT_V0 GENMASK(6, 0)
11 /* 0: success, others: dropped */
12 #define MT_TX_FREE_COUNT GENMASK(12, 0)
13 #define MT_TX_FREE_COUNT_V3 GENMASK(27, 24)
14 #define MT_TX_FREE_STAT GENMASK(14, 13)
15 #define MT_TX_FREE_STAT_V3 GENMASK(29, 28)
16 #define MT_TX_FREE_MPDU_HEADER BIT(15)
17 #define MT_TX_FREE_MPDU_HEADER_V3 BIT(30)
18 #define MT_TX_FREE_MSDU_ID_V3 GENMASK(14, 0)
20 #define MT_TXS5_F0_FINAL_MPDU BIT(31)
21 #define MT_TXS5_F0_QOS BIT(30)
22 #define MT_TXS5_F0_TX_COUNT GENMASK(29, 25)
23 #define MT_TXS5_F0_FRONT_TIME GENMASK(24, 0)
24 #define MT_TXS5_F1_MPDU_TX_COUNT GENMASK(31, 24)
25 #define MT_TXS5_F1_MPDU_TX_BYTES GENMASK(23, 0)
27 #define MT_TXS6_F0_NOISE_3 GENMASK(31, 24)
28 #define MT_TXS6_F0_NOISE_2 GENMASK(23, 16)
29 #define MT_TXS6_F0_NOISE_1 GENMASK(15, 8)
30 #define MT_TXS6_F0_NOISE_0 GENMASK(7, 0)
31 #define MT_TXS6_F1_MPDU_FAIL_COUNT GENMASK(31, 24)
32 #define MT_TXS6_F1_MPDU_FAIL_BYTES GENMASK(23, 0)
34 #define MT_TXS7_F0_RCPI_3 GENMASK(31, 24)
35 #define MT_TXS7_F0_RCPI_2 GENMASK(23, 16)
36 #define MT_TXS7_F0_RCPI_1 GENMASK(15, 8)
37 #define MT_TXS7_F0_RCPI_0 GENMASK(7, 0)
38 #define MT_TXS7_F1_MPDU_RETRY_COUNT GENMASK(31, 24)
39 #define MT_TXS7_F1_MPDU_RETRY_BYTES GENMASK(23, 0)
41 struct mt7915_dfs_pulse
{
42 u32 max_width
; /* us */
43 int max_pwr
; /* dbm */
44 int min_pwr
; /* dbm */
45 u32 min_stgr_pri
; /* us */
46 u32 max_stgr_pri
; /* us */
47 u32 min_cr_pri
; /* us */
48 u32 max_cr_pri
; /* us */
51 struct mt7915_dfs_pattern
{
70 struct mt7915_dfs_radar_spec
{
71 struct mt7915_dfs_pulse pulse_th
;
72 struct mt7915_dfs_pattern radar_pattern
[16];