drivers/net/wireless/silabs/wfx/hwio.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Low-level I/O functions.
   4  *
   5  * Copyright (c) 2017-2020, Silicon Laboratories, Inc.
   6  * Copyright (c) 2010, ST-Ericsson
   7  */
   8 #ifndef WFX_HWIO_H
   9 #define WFX_HWIO_H
  10
  11 #include <linux/types.h>
  12
  13 struct wfx_dev;
  14
  15 /* Caution: in the functions below, 'buf' will used with a DMA. So, it must be kmalloc'd (do not use
  16  * stack allocated buffers). In doubt, enable CONFIG_DEBUG_SG to detect badly located buffer.
  17  */
  18 int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t buf_len);
  19 int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t buf_len);
  20
  21 int wfx_sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
  22 int wfx_sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
  23
  24 int wfx_ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
  25 int wfx_ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
  26
  27 int wfx_sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
  28 int wfx_sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
  29
  30 int wfx_ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
  31 int wfx_ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
  32
  33 #define CFG_ERR_SPI_FRAME          0x00000001 /* only with SPI */
  34 #define CFG_ERR_SDIO_BUF_MISMATCH  0x00000001 /* only with SDIO */
  35 #define CFG_ERR_BUF_UNDERRUN       0x00000002
  36 #define CFG_ERR_DATA_IN_TOO_LARGE  0x00000004
  37 #define CFG_ERR_HOST_NO_OUT_QUEUE  0x00000008
  38 #define CFG_ERR_BUF_OVERRUN        0x00000010
  39 #define CFG_ERR_DATA_OUT_TOO_LARGE 0x00000020
  40 #define CFG_ERR_HOST_NO_IN_QUEUE   0x00000040
  41 #define CFG_ERR_HOST_CRC_MISS      0x00000080 /* only with SDIO */
  42 #define CFG_SPI_IGNORE_CS          0x00000080 /* only with SPI */
  43 #define CFG_BYTE_ORDER_MASK        0x00000300 /* only writable with SPI */
  44 #define     CFG_BYTE_ORDER_BADC    0x00000000
  45 #define     CFG_BYTE_ORDER_DCBA    0x00000100
  46 #define     CFG_BYTE_ORDER_ABCD    0x00000200 /* SDIO always use this value */
  47 #define CFG_DIRECT_ACCESS_MODE     0x00000400
  48 #define CFG_PREFETCH_AHB           0x00000800
  49 #define CFG_DISABLE_CPU_CLK        0x00001000
  50 #define CFG_PREFETCH_SRAM          0x00002000
  51 #define CFG_CPU_RESET              0x00004000
  52 #define CFG_SDIO_DISABLE_IRQ       0x00008000 /* only with SDIO */
  53 #define CFG_IRQ_ENABLE_DATA        0x00010000
  54 #define CFG_IRQ_ENABLE_WRDY        0x00020000
  55 #define CFG_CLK_RISE_EDGE          0x00040000
  56 #define CFG_SDIO_DISABLE_CRC_CHK   0x00080000 /* only with SDIO */
  57 #define CFG_RESERVED               0x00F00000
  58 #define CFG_DEVICE_ID_MAJOR        0x07000000
  59 #define CFG_DEVICE_ID_RESERVED     0x78000000
  60 #define CFG_DEVICE_ID_TYPE         0x80000000
  61 int wfx_config_reg_read(struct wfx_dev *wdev, u32 *val);
  62 int wfx_config_reg_write(struct wfx_dev *wdev, u32 val);
  63 int wfx_config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
  64
  65 #define CTRL_NEXT_LEN_MASK   0x00000FFF
  66 #define CTRL_WLAN_WAKEUP     0x00001000
  67 #define CTRL_WLAN_READY      0x00002000
  68 int wfx_control_reg_read(struct wfx_dev *wdev, u32 *val);
  69 int wfx_control_reg_write(struct wfx_dev *wdev, u32 val);
  70 int wfx_control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
  71
  72 #define IGPR_RW          0x80000000
  73 #define IGPR_INDEX       0x7F000000
  74 #define IGPR_VALUE       0x00FFFFFF
  75 int wfx_igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val);
  76 int wfx_igpr_reg_write(struct wfx_dev *wdev, int index, u32 val);
  77
  78 #endif