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drm: add modifiers for MediaTek tiled formats
[drm/drm-misc.git] / drivers / pci / controller / dwc / pcie-qcom.c
blobdc102d8bd58c69b7da7ff1073cbf12de9e0b8896
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm PCIe root complex driver
4 *
5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 * Copyright 2015 Linaro Limited.
7 *
8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/crc8.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/interconnect.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/iopoll.h>
20 #include <linux/kernel.h>
21 #include <linux/limits.h>
22 #include <linux/init.h>
23 #include <linux/of.h>
24 #include <linux/pci.h>
25 #include <linux/pm_opp.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/platform_device.h>
28 #include <linux/phy/pcie.h>
29 #include <linux/phy/phy.h>
30 #include <linux/regulator/consumer.h>
31 #include <linux/reset.h>
32 #include <linux/slab.h>
33 #include <linux/types.h>
34 #include <linux/units.h>
35
36 #include "../../pci.h"
37 #include "pcie-designware.h"
38 #include "pcie-qcom-common.h"
39
40 /* PARF registers */
41 #define PARF_SYS_CTRL 0x00
42 #define PARF_PM_CTRL 0x20
43 #define PARF_PCS_DEEMPH 0x34
44 #define PARF_PCS_SWING 0x38
45 #define PARF_PHY_CTRL 0x40
46 #define PARF_PHY_REFCLK 0x4c
47 #define PARF_CONFIG_BITS 0x50
48 #define PARF_DBI_BASE_ADDR 0x168
49 #define PARF_SLV_ADDR_SPACE_SIZE 0x16c
50 #define PARF_MHI_CLOCK_RESET_CTRL 0x174
51 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x178
52 #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8
53 #define PARF_Q2A_FLUSH 0x1ac
54 #define PARF_LTSSM 0x1b0
55 #define PARF_INT_ALL_STATUS 0x224
56 #define PARF_INT_ALL_CLEAR 0x228
57 #define PARF_INT_ALL_MASK 0x22c
58 #define PARF_SID_OFFSET 0x234
59 #define PARF_BDF_TRANSLATE_CFG 0x24c
60 #define PARF_DBI_BASE_ADDR_V2 0x350
61 #define PARF_DBI_BASE_ADDR_V2_HI 0x354
62 #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358
63 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c
64 #define PARF_NO_SNOOP_OVERIDE 0x3d4
65 #define PARF_ATU_BASE_ADDR 0x634
66 #define PARF_ATU_BASE_ADDR_HI 0x638
67 #define PARF_DEVICE_TYPE 0x1000
68 #define PARF_BDF_TO_SID_TABLE_N 0x2000
69 #define PARF_BDF_TO_SID_CFG 0x2c00
70
71 /* ELBI registers */
72 #define ELBI_SYS_CTRL 0x04
73
74 /* DBI registers */
75 #define AXI_MSTR_RESP_COMP_CTRL0 0x818
76 #define AXI_MSTR_RESP_COMP_CTRL1 0x81c
77
78 /* MHI registers */
79 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
80 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
81 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
82 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
83 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
84
85 /* PARF_SYS_CTRL register fields */
86 #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29)
87 #define MST_WAKEUP_EN BIT(13)
88 #define SLV_WAKEUP_EN BIT(12)
89 #define MSTR_ACLK_CGC_DIS BIT(10)
90 #define SLV_ACLK_CGC_DIS BIT(9)
91 #define CORE_CLK_CGC_DIS BIT(6)
92 #define AUX_PWR_DET BIT(4)
93 #define L23_CLK_RMV_DIS BIT(2)
94 #define L1_CLK_RMV_DIS BIT(1)
95
96 /* PARF_PM_CTRL register fields */
97 #define REQ_NOT_ENTR_L1 BIT(5)
98
99 /* PARF_PCS_DEEMPH register fields */
100 #define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x)
101 #define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x)
102 #define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x)
103
104 /* PARF_PCS_SWING register fields */
105 #define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x)
106 #define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x)
107
108 /* PARF_PHY_CTRL register fields */
109 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16)
110 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x)
111 #define PHY_TEST_PWR_DOWN BIT(0)
112
113 /* PARF_PHY_REFCLK register fields */
114 #define PHY_REFCLK_SSP_EN BIT(16)
115 #define PHY_REFCLK_USE_PAD BIT(12)
116
117 /* PARF_CONFIG_BITS register fields */
118 #define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x)
119
120 /* PARF_SLV_ADDR_SPACE_SIZE register value */
121 #define SLV_ADDR_SPACE_SZ 0x80000000
122
123 /* PARF_MHI_CLOCK_RESET_CTRL register fields */
124 #define AHB_CLK_EN BIT(0)
125 #define MSTR_AXI_CLK_EN BIT(1)
126 #define BYPASS BIT(4)
127
128 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
129 #define EN BIT(31)
130
131 /* PARF_LTSSM register fields */
132 #define LTSSM_EN BIT(8)
133
134 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
135 #define PARF_INT_ALL_LINK_UP BIT(13)
136 #define PARF_INT_MSI_DEV_0_7 GENMASK(30, 23)
137
138 /* PARF_NO_SNOOP_OVERIDE register fields */
139 #define WR_NO_SNOOP_OVERIDE_EN BIT(1)
140 #define RD_NO_SNOOP_OVERIDE_EN BIT(3)
141
142 /* PARF_DEVICE_TYPE register fields */
143 #define DEVICE_TYPE_RC 0x4
144
145 /* PARF_BDF_TO_SID_CFG fields */
146 #define BDF_TO_SID_BYPASS BIT(0)
147
148 /* ELBI_SYS_CTRL register fields */
149 #define ELBI_SYS_CTRL_LT_ENABLE BIT(0)
150
151 /* AXI_MSTR_RESP_COMP_CTRL0 register fields */
152 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4
153 #define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5
154
155 /* AXI_MSTR_RESP_COMP_CTRL1 register fields */
156 #define CFG_BRIDGE_SB_INIT BIT(0)
157
158 /* PCI_EXP_SLTCAP register fields */
159 #define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250)
160 #define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1)
161 #define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \
162 PCI_EXP_SLTCAP_PCP | \
163 PCI_EXP_SLTCAP_MRLSP | \
164 PCI_EXP_SLTCAP_AIP | \
165 PCI_EXP_SLTCAP_PIP | \
166 PCI_EXP_SLTCAP_HPS | \
167 PCI_EXP_SLTCAP_EIP | \
168 PCIE_CAP_SLOT_POWER_LIMIT_VAL | \
169 PCIE_CAP_SLOT_POWER_LIMIT_SCALE)
170
171 #define PERST_DELAY_US 1000
172
173 #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0))
174
175 #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
176 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))
177
178 struct qcom_pcie_resources_1_0_0 {
179 struct clk_bulk_data *clks;
180 int num_clks;
181 struct reset_control *core;
182 struct regulator *vdda;
183 };
184
185 #define QCOM_PCIE_2_1_0_MAX_RESETS 6
186 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3
187 struct qcom_pcie_resources_2_1_0 {
188 struct clk_bulk_data *clks;
189 int num_clks;
190 struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS];
191 int num_resets;
192 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY];
193 };
194
195 #define QCOM_PCIE_2_3_2_MAX_SUPPLY 2
196 struct qcom_pcie_resources_2_3_2 {
197 struct clk_bulk_data *clks;
198 int num_clks;
199 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY];
200 };
201
202 #define QCOM_PCIE_2_3_3_MAX_RESETS 7
203 struct qcom_pcie_resources_2_3_3 {
204 struct clk_bulk_data *clks;
205 int num_clks;
206 struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS];
207 };
208
209 #define QCOM_PCIE_2_4_0_MAX_RESETS 12
210 struct qcom_pcie_resources_2_4_0 {
211 struct clk_bulk_data *clks;
212 int num_clks;
213 struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS];
214 int num_resets;
215 };
216
217 #define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2
218 struct qcom_pcie_resources_2_7_0 {
219 struct clk_bulk_data *clks;
220 int num_clks;
221 struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES];
222 struct reset_control *rst;
223 };
224
225 struct qcom_pcie_resources_2_9_0 {
226 struct clk_bulk_data *clks;
227 int num_clks;
228 struct reset_control *rst;
229 };
230
231 union qcom_pcie_resources {
232 struct qcom_pcie_resources_1_0_0 v1_0_0;
233 struct qcom_pcie_resources_2_1_0 v2_1_0;
234 struct qcom_pcie_resources_2_3_2 v2_3_2;
235 struct qcom_pcie_resources_2_3_3 v2_3_3;
236 struct qcom_pcie_resources_2_4_0 v2_4_0;
237 struct qcom_pcie_resources_2_7_0 v2_7_0;
238 struct qcom_pcie_resources_2_9_0 v2_9_0;
239 };
240
241 struct qcom_pcie;
242
243 struct qcom_pcie_ops {
244 int (*get_resources)(struct qcom_pcie *pcie);
245 int (*init)(struct qcom_pcie *pcie);
246 int (*post_init)(struct qcom_pcie *pcie);
247 void (*host_post_init)(struct qcom_pcie *pcie);
248 void (*deinit)(struct qcom_pcie *pcie);
249 void (*ltssm_enable)(struct qcom_pcie *pcie);
250 int (*config_sid)(struct qcom_pcie *pcie);
251 };
252
253 /**
254 * struct qcom_pcie_cfg - Per SoC config struct
255 * @ops: qcom PCIe ops structure
256 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache
257 * snooping
258 */
259 struct qcom_pcie_cfg {
260 const struct qcom_pcie_ops *ops;
261 bool override_no_snoop;
262 bool no_l0s;
263 };
264
265 struct qcom_pcie {
266 struct dw_pcie *pci;
267 void __iomem *parf; /* DT parf */
268 void __iomem *elbi; /* DT elbi */
269 void __iomem *mhi;
270 union qcom_pcie_resources res;
271 struct phy *phy;
272 struct gpio_desc *reset;
273 struct icc_path *icc_mem;
274 struct icc_path *icc_cpu;
275 const struct qcom_pcie_cfg *cfg;
276 struct dentry *debugfs;
277 bool suspended;
278 bool use_pm_opp;
279 };
280
281 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
282
283 static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
284 {
285 gpiod_set_value_cansleep(pcie->reset, 1);
286 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
287 }
288
289 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
290 {
291 /* Ensure that PERST has been asserted for at least 100 ms */
292 msleep(100);
293 gpiod_set_value_cansleep(pcie->reset, 0);
294 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
295 }
296
297 static int qcom_pcie_start_link(struct dw_pcie *pci)
298 {
299 struct qcom_pcie *pcie = to_qcom_pcie(pci);
300
301 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) {
302 qcom_pcie_common_set_16gt_equalization(pci);
303 qcom_pcie_common_set_16gt_lane_margining(pci);
304 }
305
306 /* Enable Link Training state machine */
307 if (pcie->cfg->ops->ltssm_enable)
308 pcie->cfg->ops->ltssm_enable(pcie);
309
310 return 0;
311 }
312
313 static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci)
314 {
315 struct qcom_pcie *pcie = to_qcom_pcie(pci);
316 u16 offset;
317 u32 val;
318
319 if (!pcie->cfg->no_l0s)
320 return;
321
322 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
323
324 dw_pcie_dbi_ro_wr_en(pci);
325
326 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
327 val &= ~PCI_EXP_LNKCAP_ASPM_L0S;
328 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
329
330 dw_pcie_dbi_ro_wr_dis(pci);
331 }
332
333 static void qcom_pcie_clear_hpc(struct dw_pcie *pci)
334 {
335 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
336 u32 val;
337
338 dw_pcie_dbi_ro_wr_en(pci);
339
340 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP);
341 val &= ~PCI_EXP_SLTCAP_HPC;
342 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP);
343
344 dw_pcie_dbi_ro_wr_dis(pci);
345 }
346
347 static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie)
348 {
349 struct dw_pcie *pci = pcie->pci;
350
351 if (pci->dbi_phys_addr) {
352 /*
353 * PARF_DBI_BASE_ADDR register is in CPU domain and require to
354 * be programmed with CPU physical address.
355 */
356 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +
357 PARF_DBI_BASE_ADDR);
358 writel(SLV_ADDR_SPACE_SZ, pcie->parf +
359 PARF_SLV_ADDR_SPACE_SIZE);
360 }
361 }
362
363 static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie)
364 {
365 struct dw_pcie *pci = pcie->pci;
366
367 if (pci->dbi_phys_addr) {
368 /*
369 * PARF_DBI_BASE_ADDR_V2 and PARF_ATU_BASE_ADDR registers are
370 * in CPU domain and require to be programmed with CPU
371 * physical addresses.
372 */
373 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +
374 PARF_DBI_BASE_ADDR_V2);
375 writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf +
376 PARF_DBI_BASE_ADDR_V2_HI);
377
378 if (pci->atu_phys_addr) {
379 writel(lower_32_bits(pci->atu_phys_addr), pcie->parf +
380 PARF_ATU_BASE_ADDR);
381 writel(upper_32_bits(pci->atu_phys_addr), pcie->parf +
382 PARF_ATU_BASE_ADDR_HI);
383 }
384
385 writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2);
386 writel(SLV_ADDR_SPACE_SZ, pcie->parf +
387 PARF_SLV_ADDR_SPACE_SIZE_V2_HI);
388 }
389 }
390
391 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie)
392 {
393 u32 val;
394
395 /* enable link training */
396 val = readl(pcie->elbi + ELBI_SYS_CTRL);
397 val |= ELBI_SYS_CTRL_LT_ENABLE;
398 writel(val, pcie->elbi + ELBI_SYS_CTRL);
399 }
400
401 static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie)
402 {
403 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
404 struct dw_pcie *pci = pcie->pci;
405 struct device *dev = pci->dev;
406 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064");
407 int ret;
408
409 res->supplies[0].supply = "vdda";
410 res->supplies[1].supply = "vdda_phy";
411 res->supplies[2].supply = "vdda_refclk";
412 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
413 res->supplies);
414 if (ret)
415 return ret;
416
417 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
418 if (res->num_clks < 0) {
419 dev_err(dev, "Failed to get clocks\n");
420 return res->num_clks;
421 }
422
423 res->resets[0].id = "pci";
424 res->resets[1].id = "axi";
425 res->resets[2].id = "ahb";
426 res->resets[3].id = "por";
427 res->resets[4].id = "phy";
428 res->resets[5].id = "ext";
429
430 /* ext is optional on APQ8016 */
431 res->num_resets = is_apq ? 5 : 6;
432 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets);
433 if (ret < 0)
434 return ret;
435
436 return 0;
437 }
438
439 static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie)
440 {
441 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
442
443 clk_bulk_disable_unprepare(res->num_clks, res->clks);
444 reset_control_bulk_assert(res->num_resets, res->resets);
445
446 writel(1, pcie->parf + PARF_PHY_CTRL);
447
448 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
449 }
450
451 static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie)
452 {
453 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
454 struct dw_pcie *pci = pcie->pci;
455 struct device *dev = pci->dev;
456 int ret;
457
458 /* reset the PCIe interface as uboot can leave it undefined state */
459 ret = reset_control_bulk_assert(res->num_resets, res->resets);
460 if (ret < 0) {
461 dev_err(dev, "cannot assert resets\n");
462 return ret;
463 }
464
465 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
466 if (ret < 0) {
467 dev_err(dev, "cannot enable regulators\n");
468 return ret;
469 }
470
471 ret = reset_control_bulk_deassert(res->num_resets, res->resets);
472 if (ret < 0) {
473 dev_err(dev, "cannot deassert resets\n");
474 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
475 return ret;
476 }
477
478 return 0;
479 }
480
481 static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie)
482 {
483 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
484 struct dw_pcie *pci = pcie->pci;
485 struct device *dev = pci->dev;
486 struct device_node *node = dev->of_node;
487 u32 val;
488 int ret;
489
490 /* enable PCIe clocks and resets */
491 val = readl(pcie->parf + PARF_PHY_CTRL);
492 val &= ~PHY_TEST_PWR_DOWN;
493 writel(val, pcie->parf + PARF_PHY_CTRL);
494
495 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
496 if (ret)
497 return ret;
498
499 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") ||
500 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) {
501 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) |
502 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) |
503 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34),
504 pcie->parf + PARF_PCS_DEEMPH);
505 writel(PCS_SWING_TX_SWING_FULL(120) |
506 PCS_SWING_TX_SWING_LOW(120),
507 pcie->parf + PARF_PCS_SWING);
508 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);
509 }
510
511 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
512 /* set TX termination offset */
513 val = readl(pcie->parf + PARF_PHY_CTRL);
514 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
515 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
516 writel(val, pcie->parf + PARF_PHY_CTRL);
517 }
518
519 /* enable external reference clock */
520 val = readl(pcie->parf + PARF_PHY_REFCLK);
521 /* USE_PAD is required only for ipq806x */
522 if (!of_device_is_compatible(node, "qcom,pcie-apq8064"))
523 val &= ~PHY_REFCLK_USE_PAD;
524 val |= PHY_REFCLK_SSP_EN;
525 writel(val, pcie->parf + PARF_PHY_REFCLK);
526
527 /* wait for clock acquisition */
528 usleep_range(1000, 1500);
529
530 /* Set the Max TLP size to 2K, instead of using default of 4K */
531 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K,
532 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0);
533 writel(CFG_BRIDGE_SB_INIT,
534 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1);
535
536 qcom_pcie_clear_hpc(pcie->pci);
537
538 return 0;
539 }
540
541 static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie)
542 {
543 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
544 struct dw_pcie *pci = pcie->pci;
545 struct device *dev = pci->dev;
546
547 res->vdda = devm_regulator_get(dev, "vdda");
548 if (IS_ERR(res->vdda))
549 return PTR_ERR(res->vdda);
550
551 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
552 if (res->num_clks < 0) {
553 dev_err(dev, "Failed to get clocks\n");
554 return res->num_clks;
555 }
556
557 res->core = devm_reset_control_get_exclusive(dev, "core");
558 return PTR_ERR_OR_ZERO(res->core);
559 }
560
561 static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie)
562 {
563 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
564
565 reset_control_assert(res->core);
566 clk_bulk_disable_unprepare(res->num_clks, res->clks);
567 regulator_disable(res->vdda);
568 }
569
570 static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie)
571 {
572 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0;
573 struct dw_pcie *pci = pcie->pci;
574 struct device *dev = pci->dev;
575 int ret;
576
577 ret = reset_control_deassert(res->core);
578 if (ret) {
579 dev_err(dev, "cannot deassert core reset\n");
580 return ret;
581 }
582
583 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
584 if (ret) {
585 dev_err(dev, "cannot prepare/enable clocks\n");
586 goto err_assert_reset;
587 }
588
589 ret = regulator_enable(res->vdda);
590 if (ret) {
591 dev_err(dev, "cannot enable vdda regulator\n");
592 goto err_disable_clks;
593 }
594
595 return 0;
596
597 err_disable_clks:
598 clk_bulk_disable_unprepare(res->num_clks, res->clks);
599 err_assert_reset:
600 reset_control_assert(res->core);
601
602 return ret;
603 }
604
605 static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie)
606 {
607 qcom_pcie_configure_dbi_base(pcie);
608
609 if (IS_ENABLED(CONFIG_PCI_MSI)) {
610 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
611
612 val |= EN;
613 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
614 }
615
616 qcom_pcie_clear_hpc(pcie->pci);
617
618 return 0;
619 }
620
621 static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie)
622 {
623 u32 val;
624
625 /* enable link training */
626 val = readl(pcie->parf + PARF_LTSSM);
627 val |= LTSSM_EN;
628 writel(val, pcie->parf + PARF_LTSSM);
629 }
630
631 static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie)
632 {
633 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
634 struct dw_pcie *pci = pcie->pci;
635 struct device *dev = pci->dev;
636 int ret;
637
638 res->supplies[0].supply = "vdda";
639 res->supplies[1].supply = "vddpe-3v3";
640 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
641 res->supplies);
642 if (ret)
643 return ret;
644
645 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
646 if (res->num_clks < 0) {
647 dev_err(dev, "Failed to get clocks\n");
648 return res->num_clks;
649 }
650
651 return 0;
652 }
653
654 static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie)
655 {
656 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
657
658 clk_bulk_disable_unprepare(res->num_clks, res->clks);
659 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
660 }
661
662 static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie)
663 {
664 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2;
665 struct dw_pcie *pci = pcie->pci;
666 struct device *dev = pci->dev;
667 int ret;
668
669 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
670 if (ret < 0) {
671 dev_err(dev, "cannot enable regulators\n");
672 return ret;
673 }
674
675 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
676 if (ret) {
677 dev_err(dev, "cannot prepare/enable clocks\n");
678 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
679 return ret;
680 }
681
682 return 0;
683 }
684
685 static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie)
686 {
687 u32 val;
688
689 /* enable PCIe clocks and resets */
690 val = readl(pcie->parf + PARF_PHY_CTRL);
691 val &= ~PHY_TEST_PWR_DOWN;
692 writel(val, pcie->parf + PARF_PHY_CTRL);
693
694 qcom_pcie_configure_dbi_base(pcie);
695
696 /* MAC PHY_POWERDOWN MUX DISABLE */
697 val = readl(pcie->parf + PARF_SYS_CTRL);
698 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
699 writel(val, pcie->parf + PARF_SYS_CTRL);
700
701 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
702 val |= BYPASS;
703 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
704
705 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
706 val |= EN;
707 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
708
709 qcom_pcie_clear_hpc(pcie->pci);
710
711 return 0;
712 }
713
714 static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie)
715 {
716 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
717 struct dw_pcie *pci = pcie->pci;
718 struct device *dev = pci->dev;
719 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019");
720 int ret;
721
722 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
723 if (res->num_clks < 0) {
724 dev_err(dev, "Failed to get clocks\n");
725 return res->num_clks;
726 }
727
728 res->resets[0].id = "axi_m";
729 res->resets[1].id = "axi_s";
730 res->resets[2].id = "axi_m_sticky";
731 res->resets[3].id = "pipe_sticky";
732 res->resets[4].id = "pwr";
733 res->resets[5].id = "ahb";
734 res->resets[6].id = "pipe";
735 res->resets[7].id = "axi_m_vmid";
736 res->resets[8].id = "axi_s_xpu";
737 res->resets[9].id = "parf";
738 res->resets[10].id = "phy";
739 res->resets[11].id = "phy_ahb";
740
741 res->num_resets = is_ipq ? 12 : 6;
742
743 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets);
744 if (ret < 0)
745 return ret;
746
747 return 0;
748 }
749
750 static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie)
751 {
752 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
753
754 reset_control_bulk_assert(res->num_resets, res->resets);
755 clk_bulk_disable_unprepare(res->num_clks, res->clks);
756 }
757
758 static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie)
759 {
760 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0;
761 struct dw_pcie *pci = pcie->pci;
762 struct device *dev = pci->dev;
763 int ret;
764
765 ret = reset_control_bulk_assert(res->num_resets, res->resets);
766 if (ret < 0) {
767 dev_err(dev, "cannot assert resets\n");
768 return ret;
769 }
770
771 usleep_range(10000, 12000);
772
773 ret = reset_control_bulk_deassert(res->num_resets, res->resets);
774 if (ret < 0) {
775 dev_err(dev, "cannot deassert resets\n");
776 return ret;
777 }
778
779 usleep_range(10000, 12000);
780
781 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
782 if (ret) {
783 reset_control_bulk_assert(res->num_resets, res->resets);
784 return ret;
785 }
786
787 return 0;
788 }
789
790 static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie)
791 {
792 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
793 struct dw_pcie *pci = pcie->pci;
794 struct device *dev = pci->dev;
795 int ret;
796
797 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
798 if (res->num_clks < 0) {
799 dev_err(dev, "Failed to get clocks\n");
800 return res->num_clks;
801 }
802
803 res->rst[0].id = "axi_m";
804 res->rst[1].id = "axi_s";
805 res->rst[2].id = "pipe";
806 res->rst[3].id = "axi_m_sticky";
807 res->rst[4].id = "sticky";
808 res->rst[5].id = "ahb";
809 res->rst[6].id = "sleep";
810
811 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst);
812 if (ret < 0)
813 return ret;
814
815 return 0;
816 }
817
818 static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie)
819 {
820 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
821
822 clk_bulk_disable_unprepare(res->num_clks, res->clks);
823 }
824
825 static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
826 {
827 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
828 struct dw_pcie *pci = pcie->pci;
829 struct device *dev = pci->dev;
830 int ret;
831
832 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst);
833 if (ret < 0) {
834 dev_err(dev, "cannot assert resets\n");
835 return ret;
836 }
837
838 usleep_range(2000, 2500);
839
840 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst);
841 if (ret < 0) {
842 dev_err(dev, "cannot deassert resets\n");
843 return ret;
844 }
845
846 /*
847 * Don't have a way to see if the reset has completed.
848 * Wait for some time.
849 */
850 usleep_range(2000, 2500);
851
852 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
853 if (ret) {
854 dev_err(dev, "cannot prepare/enable clocks\n");
855 goto err_assert_resets;
856 }
857
858 return 0;
859
860 err_assert_resets:
861 /*
862 * Not checking for failure, will anyway return
863 * the original failure in 'ret'.
864 */
865 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst);
866
867 return ret;
868 }
869
870 static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie)
871 {
872 struct dw_pcie *pci = pcie->pci;
873 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
874 u32 val;
875
876 val = readl(pcie->parf + PARF_PHY_CTRL);
877 val &= ~PHY_TEST_PWR_DOWN;
878 writel(val, pcie->parf + PARF_PHY_CTRL);
879
880 qcom_pcie_configure_dbi_atu_base(pcie);
881
882 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS
883 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
884 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
885 pcie->parf + PARF_SYS_CTRL);
886 writel(0, pcie->parf + PARF_Q2A_FLUSH);
887
888 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
889
890 dw_pcie_dbi_ro_wr_en(pci);
891
892 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
893
894 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
895 val &= ~PCI_EXP_LNKCAP_ASPMS;
896 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
897
898 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
899 PCI_EXP_DEVCTL2);
900
901 dw_pcie_dbi_ro_wr_dis(pci);
902
903 return 0;
904 }
905
906 static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie)
907 {
908 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
909 struct dw_pcie *pci = pcie->pci;
910 struct device *dev = pci->dev;
911 int ret;
912
913 res->rst = devm_reset_control_array_get_exclusive(dev);
914 if (IS_ERR(res->rst))
915 return PTR_ERR(res->rst);
916
917 res->supplies[0].supply = "vdda";
918 res->supplies[1].supply = "vddpe-3v3";
919 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies),
920 res->supplies);
921 if (ret)
922 return ret;
923
924 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
925 if (res->num_clks < 0) {
926 dev_err(dev, "Failed to get clocks\n");
927 return res->num_clks;
928 }
929
930 return 0;
931 }
932
933 static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie)
934 {
935 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
936 struct dw_pcie *pci = pcie->pci;
937 struct device *dev = pci->dev;
938 u32 val;
939 int ret;
940
941 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies);
942 if (ret < 0) {
943 dev_err(dev, "cannot enable regulators\n");
944 return ret;
945 }
946
947 ret = clk_bulk_prepare_enable(res->num_clks, res->clks);
948 if (ret < 0)
949 goto err_disable_regulators;
950
951 ret = reset_control_assert(res->rst);
952 if (ret) {
953 dev_err(dev, "reset assert failed (%d)\n", ret);
954 goto err_disable_clocks;
955 }
956
957 usleep_range(1000, 1500);
958
959 ret = reset_control_deassert(res->rst);
960 if (ret) {
961 dev_err(dev, "reset deassert failed (%d)\n", ret);
962 goto err_disable_clocks;
963 }
964
965 /* Wait for reset to complete, required on SM8450 */
966 usleep_range(1000, 1500);
967
968 /* configure PCIe to RC mode */
969 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
970
971 /* enable PCIe clocks and resets */
972 val = readl(pcie->parf + PARF_PHY_CTRL);
973 val &= ~PHY_TEST_PWR_DOWN;
974 writel(val, pcie->parf + PARF_PHY_CTRL);
975
976 qcom_pcie_configure_dbi_atu_base(pcie);
977
978 /* MAC PHY_POWERDOWN MUX DISABLE */
979 val = readl(pcie->parf + PARF_SYS_CTRL);
980 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN;
981 writel(val, pcie->parf + PARF_SYS_CTRL);
982
983 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
984 val |= BYPASS;
985 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
986
987 /* Enable L1 and L1SS */
988 val = readl(pcie->parf + PARF_PM_CTRL);
989 val &= ~REQ_NOT_ENTR_L1;
990 writel(val, pcie->parf + PARF_PM_CTRL);
991
992 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
993 val |= EN;
994 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);
995
996 return 0;
997 err_disable_clocks:
998 clk_bulk_disable_unprepare(res->num_clks, res->clks);
999 err_disable_regulators:
1000 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1001
1002 return ret;
1003 }
1004
1005 static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie)
1006 {
1007 const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg;
1008
1009 if (pcie_cfg->override_no_snoop)
1010 writel(WR_NO_SNOOP_OVERIDE_EN | RD_NO_SNOOP_OVERIDE_EN,
1011 pcie->parf + PARF_NO_SNOOP_OVERIDE);
1012
1013 qcom_pcie_clear_aspm_l0s(pcie->pci);
1014 qcom_pcie_clear_hpc(pcie->pci);
1015
1016 return 0;
1017 }
1018
1019 static int qcom_pcie_enable_aspm(struct pci_dev *pdev, void *userdata)
1020 {
1021 /*
1022 * Downstream devices need to be in D0 state before enabling PCI PM
1023 * substates.
1024 */
1025 pci_set_power_state_locked(pdev, PCI_D0);
1026 pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL);
1027
1028 return 0;
1029 }
1030
1031 static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie)
1032 {
1033 struct dw_pcie_rp *pp = &pcie->pci->pp;
1034
1035 pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL);
1036 }
1037
1038 static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie)
1039 {
1040 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0;
1041
1042 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1043
1044 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
1045 }
1046
1047 static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie)
1048 {
1049 /* iommu map structure */
1050 struct {
1051 u32 bdf;
1052 u32 phandle;
1053 u32 smmu_sid;
1054 u32 smmu_sid_len;
1055 } *map;
1056 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;
1057 struct device *dev = pcie->pci->dev;
1058 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE];
1059 int i, nr_map, size = 0;
1060 u32 smmu_sid_base;
1061 u32 val;
1062
1063 of_get_property(dev->of_node, "iommu-map", &size);
1064 if (!size)
1065 return 0;
1066
1067 /* Enable BDF to SID translation by disabling bypass mode (default) */
1068 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);
1069 val &= ~BDF_TO_SID_BYPASS;
1070 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);
1071
1072 map = kzalloc(size, GFP_KERNEL);
1073 if (!map)
1074 return -ENOMEM;
1075
1076 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map,
1077 size / sizeof(u32));
1078
1079 nr_map = size / (sizeof(*map));
1080
1081 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL);
1082
1083 /* Registers need to be zero out first */
1084 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32));
1085
1086 /* Extract the SMMU SID base from the first entry of iommu-map */
1087 smmu_sid_base = map[0].smmu_sid;
1088
1089 /* Look for an available entry to hold the mapping */
1090 for (i = 0; i < nr_map; i++) {
1091 __be16 bdf_be = cpu_to_be16(map[i].bdf);
1092 u32 val;
1093 u8 hash;
1094
1095 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 0);
1096
1097 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1098
1099 /* If the register is already populated, look for next available entry */
1100 while (val) {
1101 u8 current_hash = hash++;
1102 u8 next_mask = 0xff;
1103
1104 /* If NEXT field is NULL then update it with next hash */
1105 if (!(val & next_mask)) {
1106 val |= (u32)hash;
1107 writel(val, bdf_to_sid_base + current_hash * sizeof(u32));
1108 }
1109
1110 val = readl(bdf_to_sid_base + hash * sizeof(u32));
1111 }
1112
1113 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */
1114 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0;
1115 writel(val, bdf_to_sid_base + hash * sizeof(u32));
1116 }
1117
1118 kfree(map);
1119
1120 return 0;
1121 }
1122
1123 static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie)
1124 {
1125 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1126 struct dw_pcie *pci = pcie->pci;
1127 struct device *dev = pci->dev;
1128
1129 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks);
1130 if (res->num_clks < 0) {
1131 dev_err(dev, "Failed to get clocks\n");
1132 return res->num_clks;
1133 }
1134
1135 res->rst = devm_reset_control_array_get_exclusive(dev);
1136 if (IS_ERR(res->rst))
1137 return PTR_ERR(res->rst);
1138
1139 return 0;
1140 }
1141
1142 static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie)
1143 {
1144 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1145
1146 clk_bulk_disable_unprepare(res->num_clks, res->clks);
1147 }
1148
1149 static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie)
1150 {
1151 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0;
1152 struct device *dev = pcie->pci->dev;
1153 int ret;
1154
1155 ret = reset_control_assert(res->rst);
1156 if (ret) {
1157 dev_err(dev, "reset assert failed (%d)\n", ret);
1158 return ret;
1159 }
1160
1161 /*
1162 * Delay periods before and after reset deassert are working values
1163 * from downstream Codeaurora kernel
1164 */
1165 usleep_range(2000, 2500);
1166
1167 ret = reset_control_deassert(res->rst);
1168 if (ret) {
1169 dev_err(dev, "reset deassert failed (%d)\n", ret);
1170 return ret;
1171 }
1172
1173 usleep_range(2000, 2500);
1174
1175 return clk_bulk_prepare_enable(res->num_clks, res->clks);
1176 }
1177
1178 static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie)
1179 {
1180 struct dw_pcie *pci = pcie->pci;
1181 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1182 u32 val;
1183 int i;
1184
1185 val = readl(pcie->parf + PARF_PHY_CTRL);
1186 val &= ~PHY_TEST_PWR_DOWN;
1187 writel(val, pcie->parf + PARF_PHY_CTRL);
1188
1189 qcom_pcie_configure_dbi_atu_base(pcie);
1190
1191 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);
1192 writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN,
1193 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);
1194 writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS |
1195 GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL,
1196 pci->dbi_base + GEN3_RELATED_OFF);
1197
1198 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS |
1199 SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS |
1200 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS,
1201 pcie->parf + PARF_SYS_CTRL);
1202
1203 writel(0, pcie->parf + PARF_Q2A_FLUSH);
1204
1205 dw_pcie_dbi_ro_wr_en(pci);
1206
1207 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
1208
1209 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
1210 val &= ~PCI_EXP_LNKCAP_ASPMS;
1211 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
1212
1213 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
1214 PCI_EXP_DEVCTL2);
1215
1216 dw_pcie_dbi_ro_wr_dis(pci);
1217
1218 for (i = 0; i < 256; i++)
1219 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));
1220
1221 return 0;
1222 }
1223
1224 static int qcom_pcie_link_up(struct dw_pcie *pci)
1225 {
1226 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1227 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1228
1229 return !!(val & PCI_EXP_LNKSTA_DLLLA);
1230 }
1231
1232 static int qcom_pcie_host_init(struct dw_pcie_rp *pp)
1233 {
1234 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1235 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1236 int ret;
1237
1238 qcom_ep_reset_assert(pcie);
1239
1240 ret = pcie->cfg->ops->init(pcie);
1241 if (ret)
1242 return ret;
1243
1244 ret = phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC);
1245 if (ret)
1246 goto err_deinit;
1247
1248 ret = phy_power_on(pcie->phy);
1249 if (ret)
1250 goto err_deinit;
1251
1252 if (pcie->cfg->ops->post_init) {
1253 ret = pcie->cfg->ops->post_init(pcie);
1254 if (ret)
1255 goto err_disable_phy;
1256 }
1257
1258 qcom_ep_reset_deassert(pcie);
1259
1260 if (pcie->cfg->ops->config_sid) {
1261 ret = pcie->cfg->ops->config_sid(pcie);
1262 if (ret)
1263 goto err_assert_reset;
1264 }
1265
1266 return 0;
1267
1268 err_assert_reset:
1269 qcom_ep_reset_assert(pcie);
1270 err_disable_phy:
1271 phy_power_off(pcie->phy);
1272 err_deinit:
1273 pcie->cfg->ops->deinit(pcie);
1274
1275 return ret;
1276 }
1277
1278 static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp)
1279 {
1280 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1281 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1282
1283 qcom_ep_reset_assert(pcie);
1284 phy_power_off(pcie->phy);
1285 pcie->cfg->ops->deinit(pcie);
1286 }
1287
1288 static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp)
1289 {
1290 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1291 struct qcom_pcie *pcie = to_qcom_pcie(pci);
1292
1293 if (pcie->cfg->ops->host_post_init)
1294 pcie->cfg->ops->host_post_init(pcie);
1295 }
1296
1297 static const struct dw_pcie_host_ops qcom_pcie_dw_ops = {
1298 .init = qcom_pcie_host_init,
1299 .deinit = qcom_pcie_host_deinit,
1300 .post_init = qcom_pcie_host_post_init,
1301 };
1302
1303 /* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */
1304 static const struct qcom_pcie_ops ops_2_1_0 = {
1305 .get_resources = qcom_pcie_get_resources_2_1_0,
1306 .init = qcom_pcie_init_2_1_0,
1307 .post_init = qcom_pcie_post_init_2_1_0,
1308 .deinit = qcom_pcie_deinit_2_1_0,
1309 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1310 };
1311
1312 /* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */
1313 static const struct qcom_pcie_ops ops_1_0_0 = {
1314 .get_resources = qcom_pcie_get_resources_1_0_0,
1315 .init = qcom_pcie_init_1_0_0,
1316 .post_init = qcom_pcie_post_init_1_0_0,
1317 .deinit = qcom_pcie_deinit_1_0_0,
1318 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable,
1319 };
1320
1321 /* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */
1322 static const struct qcom_pcie_ops ops_2_3_2 = {
1323 .get_resources = qcom_pcie_get_resources_2_3_2,
1324 .init = qcom_pcie_init_2_3_2,
1325 .post_init = qcom_pcie_post_init_2_3_2,
1326 .deinit = qcom_pcie_deinit_2_3_2,
1327 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1328 };
1329
1330 /* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */
1331 static const struct qcom_pcie_ops ops_2_4_0 = {
1332 .get_resources = qcom_pcie_get_resources_2_4_0,
1333 .init = qcom_pcie_init_2_4_0,
1334 .post_init = qcom_pcie_post_init_2_3_2,
1335 .deinit = qcom_pcie_deinit_2_4_0,
1336 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1337 };
1338
1339 /* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */
1340 static const struct qcom_pcie_ops ops_2_3_3 = {
1341 .get_resources = qcom_pcie_get_resources_2_3_3,
1342 .init = qcom_pcie_init_2_3_3,
1343 .post_init = qcom_pcie_post_init_2_3_3,
1344 .deinit = qcom_pcie_deinit_2_3_3,
1345 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1346 };
1347
1348 /* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */
1349 static const struct qcom_pcie_ops ops_2_7_0 = {
1350 .get_resources = qcom_pcie_get_resources_2_7_0,
1351 .init = qcom_pcie_init_2_7_0,
1352 .post_init = qcom_pcie_post_init_2_7_0,
1353 .deinit = qcom_pcie_deinit_2_7_0,
1354 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1355 };
1356
1357 /* Qcom IP rev.: 1.9.0 */
1358 static const struct qcom_pcie_ops ops_1_9_0 = {
1359 .get_resources = qcom_pcie_get_resources_2_7_0,
1360 .init = qcom_pcie_init_2_7_0,
1361 .post_init = qcom_pcie_post_init_2_7_0,
1362 .host_post_init = qcom_pcie_host_post_init_2_7_0,
1363 .deinit = qcom_pcie_deinit_2_7_0,
1364 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1365 .config_sid = qcom_pcie_config_sid_1_9_0,
1366 };
1367
1368 /* Qcom IP rev.: 1.21.0 Synopsys IP rev.: 5.60a */
1369 static const struct qcom_pcie_ops ops_1_21_0 = {
1370 .get_resources = qcom_pcie_get_resources_2_7_0,
1371 .init = qcom_pcie_init_2_7_0,
1372 .post_init = qcom_pcie_post_init_2_7_0,
1373 .host_post_init = qcom_pcie_host_post_init_2_7_0,
1374 .deinit = qcom_pcie_deinit_2_7_0,
1375 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1376 };
1377
1378 /* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */
1379 static const struct qcom_pcie_ops ops_2_9_0 = {
1380 .get_resources = qcom_pcie_get_resources_2_9_0,
1381 .init = qcom_pcie_init_2_9_0,
1382 .post_init = qcom_pcie_post_init_2_9_0,
1383 .deinit = qcom_pcie_deinit_2_9_0,
1384 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable,
1385 };
1386
1387 static const struct qcom_pcie_cfg cfg_1_0_0 = {
1388 .ops = &ops_1_0_0,
1389 };
1390
1391 static const struct qcom_pcie_cfg cfg_1_9_0 = {
1392 .ops = &ops_1_9_0,
1393 };
1394
1395 static const struct qcom_pcie_cfg cfg_1_34_0 = {
1396 .ops = &ops_1_9_0,
1397 .override_no_snoop = true,
1398 };
1399
1400 static const struct qcom_pcie_cfg cfg_2_1_0 = {
1401 .ops = &ops_2_1_0,
1402 };
1403
1404 static const struct qcom_pcie_cfg cfg_2_3_2 = {
1405 .ops = &ops_2_3_2,
1406 };
1407
1408 static const struct qcom_pcie_cfg cfg_2_3_3 = {
1409 .ops = &ops_2_3_3,
1410 };
1411
1412 static const struct qcom_pcie_cfg cfg_2_4_0 = {
1413 .ops = &ops_2_4_0,
1414 };
1415
1416 static const struct qcom_pcie_cfg cfg_2_7_0 = {
1417 .ops = &ops_2_7_0,
1418 };
1419
1420 static const struct qcom_pcie_cfg cfg_2_9_0 = {
1421 .ops = &ops_2_9_0,
1422 };
1423
1424 static const struct qcom_pcie_cfg cfg_sc8280xp = {
1425 .ops = &ops_1_21_0,
1426 .no_l0s = true,
1427 };
1428
1429 static const struct dw_pcie_ops dw_pcie_ops = {
1430 .link_up = qcom_pcie_link_up,
1431 .start_link = qcom_pcie_start_link,
1432 };
1433
1434 static int qcom_pcie_icc_init(struct qcom_pcie *pcie)
1435 {
1436 struct dw_pcie *pci = pcie->pci;
1437 int ret;
1438
1439 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem");
1440 if (IS_ERR(pcie->icc_mem))
1441 return PTR_ERR(pcie->icc_mem);
1442
1443 pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie");
1444 if (IS_ERR(pcie->icc_cpu))
1445 return PTR_ERR(pcie->icc_cpu);
1446 /*
1447 * Some Qualcomm platforms require interconnect bandwidth constraints
1448 * to be set before enabling interconnect clocks.
1449 *
1450 * Set an initial peak bandwidth corresponding to single-lane Gen 1
1451 * for the pcie-mem path.
1452 */
1453 ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
1454 if (ret) {
1455 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
1456 ret);
1457 return ret;
1458 }
1459
1460 /*
1461 * Since the CPU-PCIe path is only used for activities like register
1462 * access of the host controller and endpoint Config/BAR space access,
1463 * HW team has recommended to use a minimal bandwidth of 1KBps just to
1464 * keep the path active.
1465 */
1466 ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1));
1467 if (ret) {
1468 dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n",
1469 ret);
1470 icc_set_bw(pcie->icc_mem, 0, 0);
1471 return ret;
1472 }
1473
1474 return 0;
1475 }
1476
1477 static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie)
1478 {
1479 u32 offset, status, width, speed;
1480 struct dw_pcie *pci = pcie->pci;
1481 unsigned long freq_kbps;
1482 struct dev_pm_opp *opp;
1483 int ret, freq_mbps;
1484
1485 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
1486 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
1487
1488 /* Only update constraints if link is up. */
1489 if (!(status & PCI_EXP_LNKSTA_DLLLA))
1490 return;
1491
1492 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
1493 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
1494
1495 if (pcie->icc_mem) {
1496 ret = icc_set_bw(pcie->icc_mem, 0,
1497 width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
1498 if (ret) {
1499 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
1500 ret);
1501 }
1502 } else if (pcie->use_pm_opp) {
1503 freq_mbps = pcie_dev_speed_mbps(pcie_link_speed[speed]);
1504 if (freq_mbps < 0)
1505 return;
1506
1507 freq_kbps = freq_mbps * KILO;
1508 opp = dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width,
1509 true);
1510 if (!IS_ERR(opp)) {
1511 ret = dev_pm_opp_set_opp(pci->dev, opp);
1512 if (ret)
1513 dev_err(pci->dev, "Failed to set OPP for freq (%lu): %d\n",
1514 freq_kbps * width, ret);
1515 dev_pm_opp_put(opp);
1516 }
1517 }
1518 }
1519
1520 static int qcom_pcie_link_transition_count(struct seq_file *s, void *data)
1521 {
1522 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private);
1523
1524 seq_printf(s, "L0s transition count: %u\n",
1525 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
1526
1527 seq_printf(s, "L1 transition count: %u\n",
1528 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
1529
1530 seq_printf(s, "L1.1 transition count: %u\n",
1531 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
1532
1533 seq_printf(s, "L1.2 transition count: %u\n",
1534 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
1535
1536 seq_printf(s, "L2 transition count: %u\n",
1537 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
1538
1539 return 0;
1540 }
1541
1542 static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie)
1543 {
1544 struct dw_pcie *pci = pcie->pci;
1545 struct device *dev = pci->dev;
1546 char *name;
1547
1548 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
1549 if (!name)
1550 return;
1551
1552 pcie->debugfs = debugfs_create_dir(name, NULL);
1553 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs,
1554 qcom_pcie_link_transition_count);
1555 }
1556
1557 static irqreturn_t qcom_pcie_global_irq_thread(int irq, void *data)
1558 {
1559 struct qcom_pcie *pcie = data;
1560 struct dw_pcie_rp *pp = &pcie->pci->pp;
1561 struct device *dev = pcie->pci->dev;
1562 u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS);
1563
1564 writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR);
1565
1566 if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
1567 dev_dbg(dev, "Received Link up event. Starting enumeration!\n");
1568 /* Rescan the bus to enumerate endpoint devices */
1569 pci_lock_rescan_remove();
1570 pci_rescan_bus(pp->bridge->bus);
1571 pci_unlock_rescan_remove();
1572 } else {
1573 dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n",
1574 status);
1575 }
1576
1577 return IRQ_HANDLED;
1578 }
1579
1580 static int qcom_pcie_probe(struct platform_device *pdev)
1581 {
1582 const struct qcom_pcie_cfg *pcie_cfg;
1583 unsigned long max_freq = ULONG_MAX;
1584 struct device *dev = &pdev->dev;
1585 struct dev_pm_opp *opp;
1586 struct qcom_pcie *pcie;
1587 struct dw_pcie_rp *pp;
1588 struct resource *res;
1589 struct dw_pcie *pci;
1590 int ret, irq;
1591 char *name;
1592
1593 pcie_cfg = of_device_get_match_data(dev);
1594 if (!pcie_cfg || !pcie_cfg->ops) {
1595 dev_err(dev, "Invalid platform data\n");
1596 return -EINVAL;
1597 }
1598
1599 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
1600 if (!pcie)
1601 return -ENOMEM;
1602
1603 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
1604 if (!pci)
1605 return -ENOMEM;
1606
1607 pm_runtime_enable(dev);
1608 ret = pm_runtime_get_sync(dev);
1609 if (ret < 0)
1610 goto err_pm_runtime_put;
1611
1612 pci->dev = dev;
1613 pci->ops = &dw_pcie_ops;
1614 pp = &pci->pp;
1615
1616 pcie->pci = pci;
1617
1618 pcie->cfg = pcie_cfg;
1619
1620 pcie->reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH);
1621 if (IS_ERR(pcie->reset)) {
1622 ret = PTR_ERR(pcie->reset);
1623 goto err_pm_runtime_put;
1624 }
1625
1626 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
1627 if (IS_ERR(pcie->parf)) {
1628 ret = PTR_ERR(pcie->parf);
1629 goto err_pm_runtime_put;
1630 }
1631
1632 pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
1633 if (IS_ERR(pcie->elbi)) {
1634 ret = PTR_ERR(pcie->elbi);
1635 goto err_pm_runtime_put;
1636 }
1637
1638 /* MHI region is optional */
1639 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mhi");
1640 if (res) {
1641 pcie->mhi = devm_ioremap_resource(dev, res);
1642 if (IS_ERR(pcie->mhi)) {
1643 ret = PTR_ERR(pcie->mhi);
1644 goto err_pm_runtime_put;
1645 }
1646 }
1647
1648 pcie->phy = devm_phy_optional_get(dev, "pciephy");
1649 if (IS_ERR(pcie->phy)) {
1650 ret = PTR_ERR(pcie->phy);
1651 goto err_pm_runtime_put;
1652 }
1653
1654 /* OPP table is optional */
1655 ret = devm_pm_opp_of_add_table(dev);
1656 if (ret && ret != -ENODEV) {
1657 dev_err_probe(dev, ret, "Failed to add OPP table\n");
1658 goto err_pm_runtime_put;
1659 }
1660
1661 /*
1662 * Before the PCIe link is initialized, vote for highest OPP in the OPP
1663 * table, so that we are voting for maximum voltage corner for the
1664 * link to come up in maximum supported speed. At the end of the
1665 * probe(), OPP will be updated using qcom_pcie_icc_opp_update().
1666 */
1667 if (!ret) {
1668 opp = dev_pm_opp_find_freq_floor(dev, &max_freq);
1669 if (IS_ERR(opp)) {
1670 ret = PTR_ERR(opp);
1671 dev_err_probe(pci->dev, ret,
1672 "Unable to find max freq OPP\n");
1673 goto err_pm_runtime_put;
1674 } else {
1675 ret = dev_pm_opp_set_opp(dev, opp);
1676 }
1677
1678 dev_pm_opp_put(opp);
1679 if (ret) {
1680 dev_err_probe(pci->dev, ret,
1681 "Failed to set OPP for freq %lu\n",
1682 max_freq);
1683 goto err_pm_runtime_put;
1684 }
1685
1686 pcie->use_pm_opp = true;
1687 } else {
1688 /* Skip ICC init if OPP is supported as it is handled by OPP */
1689 ret = qcom_pcie_icc_init(pcie);
1690 if (ret)
1691 goto err_pm_runtime_put;
1692 }
1693
1694 ret = pcie->cfg->ops->get_resources(pcie);
1695 if (ret)
1696 goto err_pm_runtime_put;
1697
1698 pp->ops = &qcom_pcie_dw_ops;
1699
1700 ret = phy_init(pcie->phy);
1701 if (ret)
1702 goto err_pm_runtime_put;
1703
1704 platform_set_drvdata(pdev, pcie);
1705
1706 ret = dw_pcie_host_init(pp);
1707 if (ret) {
1708 dev_err(dev, "cannot initialize host\n");
1709 goto err_phy_exit;
1710 }
1711
1712 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_global_irq%d",
1713 pci_domain_nr(pp->bridge->bus));
1714 if (!name) {
1715 ret = -ENOMEM;
1716 goto err_host_deinit;
1717 }
1718
1719 irq = platform_get_irq_byname_optional(pdev, "global");
1720 if (irq > 0) {
1721 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1722 qcom_pcie_global_irq_thread,
1723 IRQF_ONESHOT, name, pcie);
1724 if (ret) {
1725 dev_err_probe(&pdev->dev, ret,
1726 "Failed to request Global IRQ\n");
1727 goto err_host_deinit;
1728 }
1729
1730 writel_relaxed(PARF_INT_ALL_LINK_UP | PARF_INT_MSI_DEV_0_7,
1731 pcie->parf + PARF_INT_ALL_MASK);
1732 }
1733
1734 qcom_pcie_icc_opp_update(pcie);
1735
1736 if (pcie->mhi)
1737 qcom_pcie_init_debugfs(pcie);
1738
1739 return 0;
1740
1741 err_host_deinit:
1742 dw_pcie_host_deinit(pp);
1743 err_phy_exit:
1744 phy_exit(pcie->phy);
1745 err_pm_runtime_put:
1746 pm_runtime_put(dev);
1747 pm_runtime_disable(dev);
1748
1749 return ret;
1750 }
1751
1752 static int qcom_pcie_suspend_noirq(struct device *dev)
1753 {
1754 struct qcom_pcie *pcie = dev_get_drvdata(dev);
1755 int ret = 0;
1756
1757 /*
1758 * Set minimum bandwidth required to keep data path functional during
1759 * suspend.
1760 */
1761 if (pcie->icc_mem) {
1762 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1));
1763 if (ret) {
1764 dev_err(dev,
1765 "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n",
1766 ret);
1767 return ret;
1768 }
1769 }
1770
1771 /*
1772 * Turn OFF the resources only for controllers without active PCIe
1773 * devices. For controllers with active devices, the resources are kept
1774 * ON and the link is expected to be in L0/L1 (sub)states.
1775 *
1776 * Turning OFF the resources for controllers with active PCIe devices
1777 * will trigger access violation during the end of the suspend cycle,
1778 * as kernel tries to access the PCIe devices config space for masking
1779 * MSIs.
1780 *
1781 * Also, it is not desirable to put the link into L2/L3 state as that
1782 * implies VDD supply will be removed and the devices may go into
1783 * powerdown state. This will affect the lifetime of the storage devices
1784 * like NVMe.
1785 */
1786 if (!dw_pcie_link_up(pcie->pci)) {
1787 qcom_pcie_host_deinit(&pcie->pci->pp);
1788 pcie->suspended = true;
1789 }
1790
1791 /*
1792 * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM.
1793 * Because on some platforms, DBI access can happen very late during the
1794 * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC
1795 * error.
1796 */
1797 if (pm_suspend_target_state != PM_SUSPEND_MEM) {
1798 ret = icc_disable(pcie->icc_cpu);
1799 if (ret)
1800 dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret);
1801
1802 if (pcie->use_pm_opp)
1803 dev_pm_opp_set_opp(pcie->pci->dev, NULL);
1804 }
1805 return ret;
1806 }
1807
1808 static int qcom_pcie_resume_noirq(struct device *dev)
1809 {
1810 struct qcom_pcie *pcie = dev_get_drvdata(dev);
1811 int ret;
1812
1813 if (pm_suspend_target_state != PM_SUSPEND_MEM) {
1814 ret = icc_enable(pcie->icc_cpu);
1815 if (ret) {
1816 dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret);
1817 return ret;
1818 }
1819 }
1820
1821 if (pcie->suspended) {
1822 ret = qcom_pcie_host_init(&pcie->pci->pp);
1823 if (ret)
1824 return ret;
1825
1826 pcie->suspended = false;
1827 }
1828
1829 qcom_pcie_icc_opp_update(pcie);
1830
1831 return 0;
1832 }
1833
1834 static const struct of_device_id qcom_pcie_match[] = {
1835 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 },
1836 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 },
1837 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 },
1838 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 },
1839 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 },
1840 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 },
1841 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 },
1842 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 },
1843 { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 },
1844 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 },
1845 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 },
1846 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp },
1847 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0},
1848 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 },
1849 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 },
1850 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp },
1851 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 },
1852 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 },
1853 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 },
1854 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 },
1855 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 },
1856 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 },
1857 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 },
1858 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 },
1859 { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp },
1860 { }
1861 };
1862
1863 static void qcom_fixup_class(struct pci_dev *dev)
1864 {
1865 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL;
1866 }
1867 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class);
1868 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class);
1869 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class);
1870 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class);
1871 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class);
1872 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class);
1873 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class);
1874
1875 static const struct dev_pm_ops qcom_pcie_pm_ops = {
1876 NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_suspend_noirq, qcom_pcie_resume_noirq)
1877 };
1878
1879 static struct platform_driver qcom_pcie_driver = {
1880 .probe = qcom_pcie_probe,
1881 .driver = {
1882 .name = "qcom-pcie",
1883 .suppress_bind_attrs = true,
1884 .of_match_table = qcom_pcie_match,
1885 .pm = &qcom_pcie_pm_ops,
1886 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1887 },
1888 };
1889 builtin_platform_driver(qcom_pcie_driver);
Kernel DRM miscellaneous fixes and cross-tree changes