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drm/tidss: Fix typos
[drm/drm-misc.git] / drivers / pci / pci.h
blob2e40fc63ba31595b4f11723cb6b117e036c74ba2
1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef DRIVERS_PCI_H
3 #define DRIVERS_PCI_H
4
5 #include <linux/pci.h>
6
7 /* Number of possible devfns: 0.0 to 1f.7 inclusive */
8 #define MAX_NR_DEVFNS 256
9
10 #define PCI_FIND_CAP_TTL 48
11
12 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13
14 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000
15
16 /*
17 * Power stable to PERST# inactive.
18 *
19 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
20 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol
21 * "T_PVPERL".
22 */
23 #define PCIE_T_PVPERL_MS 100
24
25 /*
26 * REFCLK stable before PERST# inactive.
27 *
28 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express
29 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol
30 * "T_PERST-CLK".
31 */
32 #define PCIE_T_PERST_CLK_US 100
33
34 /*
35 * End of conventional reset (PERST# de-asserted) to first configuration
36 * request (device able to respond with a "Request Retry Status" completion),
37 * from PCIe r6.0, sec 6.6.1.
38 */
39 #define PCIE_T_RRS_READY_MS 100
40
41 /*
42 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization>
43 * Recommends 1ms to 10ms timeout to check L2 ready.
44 */
45 #define PCIE_PME_TO_L2_TIMEOUT_US 10000
46
47 /*
48 * PCIe r6.0, sec 6.6.1 <Conventional Reset>
49 *
50 * - "With a Downstream Port that does not support Link speeds greater
51 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit
52 * from a Conventional Reset before sending a Configuration Request to
53 * the device immediately below that Port."
54 *
55 * - "With a Downstream Port that supports Link speeds greater than
56 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training
57 * completes before sending a Configuration Request to the device
58 * immediately below that Port."
59 */
60 #define PCIE_RESET_CONFIG_DEVICE_WAIT_MS 100
61
62 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
63 #define PCIE_MSG_TYPE_R_RC 0
64 #define PCIE_MSG_TYPE_R_ADDR 1
65 #define PCIE_MSG_TYPE_R_ID 2
66 #define PCIE_MSG_TYPE_R_BC 3
67 #define PCIE_MSG_TYPE_R_LOCAL 4
68 #define PCIE_MSG_TYPE_R_GATHER 5
69
70 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */
71 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19
72
73 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */
74 #define PCIE_MSG_CODE_ASSERT_INTA 0x20
75 #define PCIE_MSG_CODE_ASSERT_INTB 0x21
76 #define PCIE_MSG_CODE_ASSERT_INTC 0x22
77 #define PCIE_MSG_CODE_ASSERT_INTD 0x23
78 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24
79 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25
80 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26
81 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27
82
83 extern const unsigned char pcie_link_speed[];
84 extern bool pci_early_dump;
85
86 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
87 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev);
88 bool pcie_cap_has_rtctl(const struct pci_dev *dev);
89
90 /* Functions internal to the PCI core code */
91
92 #ifdef CONFIG_DMI
93 extern const struct attribute_group pci_dev_smbios_attr_group;
94 #endif
95
96 enum pci_mmap_api {
97 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
98 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
99 };
100 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
101 enum pci_mmap_api mmap_api);
102
103 bool pci_reset_supported(struct pci_dev *dev);
104 void pci_init_reset_methods(struct pci_dev *dev);
105 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
106 int pci_bus_error_reset(struct pci_dev *dev);
107 int __pci_reset_bus(struct pci_bus *bus);
108
109 struct pci_cap_saved_data {
110 u16 cap_nr;
111 bool cap_extended;
112 unsigned int size;
113 u32 data[];
114 };
115
116 struct pci_cap_saved_state {
117 struct hlist_node next;
118 struct pci_cap_saved_data cap;
119 };
120
121 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
122 void pci_free_cap_save_buffers(struct pci_dev *dev);
123 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
124 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
125 u16 cap, unsigned int size);
126 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
127 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
128 u16 cap);
129
130 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */
131 #define PCI_PM_D3HOT_WAIT 10 /* msec */
132 #define PCI_PM_D3COLD_WAIT 100 /* msec */
133
134 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
135 void pci_refresh_power_state(struct pci_dev *dev);
136 int pci_power_up(struct pci_dev *dev);
137 void pci_disable_enabled_device(struct pci_dev *dev);
138 int pci_finish_runtime_suspend(struct pci_dev *dev);
139 void pcie_clear_device_status(struct pci_dev *dev);
140 void pcie_clear_root_pme_status(struct pci_dev *dev);
141 bool pci_check_pme_status(struct pci_dev *dev);
142 void pci_pme_wakeup_bus(struct pci_bus *bus);
143 void pci_pme_restore(struct pci_dev *dev);
144 bool pci_dev_need_resume(struct pci_dev *dev);
145 void pci_dev_adjust_pme(struct pci_dev *dev);
146 void pci_dev_complete_resume(struct pci_dev *pci_dev);
147 void pci_config_pm_runtime_get(struct pci_dev *dev);
148 void pci_config_pm_runtime_put(struct pci_dev *dev);
149 void pci_pm_init(struct pci_dev *dev);
150 void pci_ea_init(struct pci_dev *dev);
151 void pci_msi_init(struct pci_dev *dev);
152 void pci_msix_init(struct pci_dev *dev);
153 bool pci_bridge_d3_possible(struct pci_dev *dev);
154 void pci_bridge_d3_update(struct pci_dev *dev);
155 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type);
156
157 static inline bool pci_bus_rrs_vendor_id(u32 l)
158 {
159 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG;
160 }
161
162 static inline void pci_wakeup_event(struct pci_dev *dev)
163 {
164 /* Wait 100 ms before the system can be put into a sleep state. */
165 pm_wakeup_event(&dev->dev, 100);
166 }
167
168 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
169 {
170 return !!(pci_dev->subordinate);
171 }
172
173 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
174 {
175 /*
176 * Currently we allow normal PCI devices and PCI bridges transition
177 * into D3 if their bridge_d3 is set.
178 */
179 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
180 }
181
182 static inline bool pcie_downstream_port(const struct pci_dev *dev)
183 {
184 int type = pci_pcie_type(dev);
185
186 return type == PCI_EXP_TYPE_ROOT_PORT ||
187 type == PCI_EXP_TYPE_DOWNSTREAM ||
188 type == PCI_EXP_TYPE_PCIE_BRIDGE;
189 }
190
191 void pci_vpd_init(struct pci_dev *dev);
192 extern const struct attribute_group pci_dev_vpd_attr_group;
193
194 /* PCI Virtual Channel */
195 int pci_save_vc_state(struct pci_dev *dev);
196 void pci_restore_vc_state(struct pci_dev *dev);
197 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
198
199 /* PCI /proc functions */
200 #ifdef CONFIG_PROC_FS
201 int pci_proc_attach_device(struct pci_dev *dev);
202 int pci_proc_detach_device(struct pci_dev *dev);
203 int pci_proc_detach_bus(struct pci_bus *bus);
204 #else
205 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
206 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
207 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
208 #endif
209
210 /* Functions for PCI Hotplug drivers to use */
211 int pci_hp_add_bridge(struct pci_dev *dev);
212
213 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY)
214 void pci_create_legacy_files(struct pci_bus *bus);
215 void pci_remove_legacy_files(struct pci_bus *bus);
216 #else
217 static inline void pci_create_legacy_files(struct pci_bus *bus) { }
218 static inline void pci_remove_legacy_files(struct pci_bus *bus) { }
219 #endif
220
221 /* Lock for read/write access to pci device and bus lists */
222 extern struct rw_semaphore pci_bus_sem;
223 extern struct mutex pci_slot_mutex;
224
225 extern raw_spinlock_t pci_lock;
226
227 extern unsigned int pci_pm_d3hot_delay;
228
229 #ifdef CONFIG_PCI_MSI
230 void pci_no_msi(void);
231 #else
232 static inline void pci_no_msi(void) { }
233 #endif
234
235 void pci_realloc_get_opt(char *);
236
237 static inline int pci_no_d1d2(struct pci_dev *dev)
238 {
239 unsigned int parent_dstates = 0;
240
241 if (dev->bus->self)
242 parent_dstates = dev->bus->self->no_d1d2;
243 return (dev->no_d1d2 || parent_dstates);
244
245 }
246
247 #ifdef CONFIG_SYSFS
248 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
249 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
250 extern const struct attribute_group *pci_dev_groups[];
251 extern const struct attribute_group *pci_dev_attr_groups[];
252 extern const struct attribute_group *pcibus_groups[];
253 extern const struct attribute_group *pci_bus_groups[];
254 #else
255 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; }
256 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { }
257 #define pci_dev_groups NULL
258 #define pci_dev_attr_groups NULL
259 #define pcibus_groups NULL
260 #define pci_bus_groups NULL
261 #endif
262
263 extern unsigned long pci_hotplug_io_size;
264 extern unsigned long pci_hotplug_mmio_size;
265 extern unsigned long pci_hotplug_mmio_pref_size;
266 extern unsigned long pci_hotplug_bus_size;
267
268 /**
269 * pci_match_one_device - Tell if a PCI device structure has a matching
270 * PCI device id structure
271 * @id: single PCI device id structure to match
272 * @dev: the PCI device structure to match against
273 *
274 * Returns the matching pci_device_id structure or %NULL if there is no match.
275 */
276 static inline const struct pci_device_id *
277 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
278 {
279 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
280 (id->device == PCI_ANY_ID || id->device == dev->device) &&
281 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
282 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
283 !((id->class ^ dev->class) & id->class_mask))
284 return id;
285 return NULL;
286 }
287
288 /* PCI slot sysfs helper code */
289 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
290
291 extern struct kset *pci_slots_kset;
292
293 struct pci_slot_attribute {
294 struct attribute attr;
295 ssize_t (*show)(struct pci_slot *, char *);
296 ssize_t (*store)(struct pci_slot *, const char *, size_t);
297 };
298 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
299
300 enum pci_bar_type {
301 pci_bar_unknown, /* Standard PCI BAR probe */
302 pci_bar_io, /* An I/O port BAR */
303 pci_bar_mem32, /* A 32-bit memory BAR */
304 pci_bar_mem64, /* A 64-bit memory BAR */
305 };
306
307 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
308 void pci_put_host_bridge_device(struct device *dev);
309
310 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
311 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
312 int rrs_timeout);
313 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
314 int rrs_timeout);
315 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout);
316
317 int pci_setup_device(struct pci_dev *dev);
318 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
319 struct resource *res, unsigned int reg);
320 void pci_configure_ari(struct pci_dev *dev);
321 void __pci_bus_size_bridges(struct pci_bus *bus,
322 struct list_head *realloc_head);
323 void __pci_bus_assign_resources(const struct pci_bus *bus,
324 struct list_head *realloc_head,
325 struct list_head *fail_head);
326 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
327 void pci_walk_bus_locked(struct pci_bus *top,
328 int (*cb)(struct pci_dev *, void *),
329 void *userdata);
330
331 const char *pci_resource_name(struct pci_dev *dev, unsigned int i);
332
333 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
334 void pci_disable_bridge_window(struct pci_dev *dev);
335 struct pci_bus *pci_bus_get(struct pci_bus *bus);
336 void pci_bus_put(struct pci_bus *bus);
337
338 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \
339 ({ \
340 ((lnkcap) == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
341 (lnkcap) == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
342 (lnkcap) == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
343 (lnkcap) == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
344 (lnkcap) == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
345 (lnkcap) == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
346 PCI_SPEED_UNKNOWN); \
347 })
348
349 /* PCIe link information from Link Capabilities 2 */
350 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
351 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \
352 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
353 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
354 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
355 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
356 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
357 PCI_SPEED_UNKNOWN)
358
359 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \
360 ((lnkctl2) == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \
361 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \
362 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \
363 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \
364 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \
365 (lnkctl2) == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \
366 PCI_SPEED_UNKNOWN)
367
368 /* PCIe speed to Mb/s reduced by encoding overhead */
369 #define PCIE_SPEED2MBS_ENC(speed) \
370 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \
371 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
372 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
373 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
374 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
375 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
376 0)
377
378 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed)
379 {
380 switch (speed) {
381 case PCIE_SPEED_2_5GT:
382 return 2500;
383 case PCIE_SPEED_5_0GT:
384 return 5000;
385 case PCIE_SPEED_8_0GT:
386 return 8000;
387 case PCIE_SPEED_16_0GT:
388 return 16000;
389 case PCIE_SPEED_32_0GT:
390 return 32000;
391 case PCIE_SPEED_64_0GT:
392 return 64000;
393 default:
394 break;
395 }
396
397 return -EINVAL;
398 }
399
400 u8 pcie_get_supported_speeds(struct pci_dev *dev);
401 const char *pci_speed_string(enum pci_bus_speed speed);
402 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
403 void pcie_report_downtraining(struct pci_dev *dev);
404
405 static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
406 {
407 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
408 }
409 void pcie_update_link_speed(struct pci_bus *bus);
410
411 /* Single Root I/O Virtualization */
412 struct pci_sriov {
413 int pos; /* Capability position */
414 int nres; /* Number of resources */
415 u32 cap; /* SR-IOV Capabilities */
416 u16 ctrl; /* SR-IOV Control */
417 u16 total_VFs; /* Total VFs associated with the PF */
418 u16 initial_VFs; /* Initial VFs associated with the PF */
419 u16 num_VFs; /* Number of VFs available */
420 u16 offset; /* First VF Routing ID offset */
421 u16 stride; /* Following VF stride */
422 u16 vf_device; /* VF device ID */
423 u32 pgsz; /* Page size for BAR alignment */
424 u8 link; /* Function Dependency Link */
425 u8 max_VF_buses; /* Max buses consumed by VFs */
426 u16 driver_max_VFs; /* Max num VFs driver supports */
427 struct pci_dev *dev; /* Lowest numbered PF */
428 struct pci_dev *self; /* This PF */
429 u32 class; /* VF device */
430 u8 hdr_type; /* VF header type */
431 u16 subsystem_vendor; /* VF subsystem vendor */
432 u16 subsystem_device; /* VF subsystem device */
433 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
434 bool drivers_autoprobe; /* Auto probing of VFs by driver */
435 };
436
437 #ifdef CONFIG_PCI_DOE
438 void pci_doe_init(struct pci_dev *pdev);
439 void pci_doe_destroy(struct pci_dev *pdev);
440 void pci_doe_disconnected(struct pci_dev *pdev);
441 #else
442 static inline void pci_doe_init(struct pci_dev *pdev) { }
443 static inline void pci_doe_destroy(struct pci_dev *pdev) { }
444 static inline void pci_doe_disconnected(struct pci_dev *pdev) { }
445 #endif
446
447 #ifdef CONFIG_PCI_NPEM
448 void pci_npem_create(struct pci_dev *dev);
449 void pci_npem_remove(struct pci_dev *dev);
450 #else
451 static inline void pci_npem_create(struct pci_dev *dev) { }
452 static inline void pci_npem_remove(struct pci_dev *dev) { }
453 #endif
454
455 /**
456 * pci_dev_set_io_state - Set the new error state if possible.
457 *
458 * @dev: PCI device to set new error_state
459 * @new: the state we want dev to be in
460 *
461 * If the device is experiencing perm_failure, it has to remain in that state.
462 * Any other transition is allowed.
463 *
464 * Returns true if state has been changed to the requested state.
465 */
466 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
467 pci_channel_state_t new)
468 {
469 pci_channel_state_t old;
470
471 switch (new) {
472 case pci_channel_io_perm_failure:
473 xchg(&dev->error_state, pci_channel_io_perm_failure);
474 return true;
475 case pci_channel_io_frozen:
476 old = cmpxchg(&dev->error_state, pci_channel_io_normal,
477 pci_channel_io_frozen);
478 return old != pci_channel_io_perm_failure;
479 case pci_channel_io_normal:
480 old = cmpxchg(&dev->error_state, pci_channel_io_frozen,
481 pci_channel_io_normal);
482 return old != pci_channel_io_perm_failure;
483 default:
484 return false;
485 }
486 }
487
488 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
489 {
490 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
491 pci_doe_disconnected(dev);
492
493 return 0;
494 }
495
496 /* pci_dev priv_flags */
497 #define PCI_DEV_ADDED 0
498 #define PCI_DPC_RECOVERED 1
499 #define PCI_DPC_RECOVERING 2
500 #define PCI_DEV_REMOVED 3
501
502 static inline void pci_dev_assign_added(struct pci_dev *dev)
503 {
504 smp_mb__before_atomic();
505 set_bit(PCI_DEV_ADDED, &dev->priv_flags);
506 smp_mb__after_atomic();
507 }
508
509 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev)
510 {
511 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags);
512 }
513
514 static inline bool pci_dev_is_added(const struct pci_dev *dev)
515 {
516 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
517 }
518
519 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev)
520 {
521 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags);
522 }
523
524 #ifdef CONFIG_PCIEAER
525 #include <linux/aer.h>
526
527 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
528
529 struct aer_err_info {
530 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
531 int error_dev_num;
532
533 unsigned int id:16;
534
535 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
536 unsigned int __pad1:5;
537 unsigned int multi_error_valid:1;
538
539 unsigned int first_error:5;
540 unsigned int __pad2:2;
541 unsigned int tlp_header_valid:1;
542
543 unsigned int status; /* COR/UNCOR Error Status */
544 unsigned int mask; /* COR/UNCOR Error Mask */
545 struct pcie_tlp_log tlp; /* TLP Header */
546 };
547
548 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
549 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
550 #endif /* CONFIG_PCIEAER */
551
552 #ifdef CONFIG_PCIEPORTBUS
553 /* Cached RCEC Endpoint Association */
554 struct rcec_ea {
555 u8 nextbusn;
556 u8 lastbusn;
557 u32 bitmap;
558 };
559 #endif
560
561 #ifdef CONFIG_PCIE_DPC
562 void pci_save_dpc_state(struct pci_dev *dev);
563 void pci_restore_dpc_state(struct pci_dev *dev);
564 void pci_dpc_init(struct pci_dev *pdev);
565 void dpc_process_error(struct pci_dev *pdev);
566 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
567 bool pci_dpc_recovered(struct pci_dev *pdev);
568 #else
569 static inline void pci_save_dpc_state(struct pci_dev *dev) { }
570 static inline void pci_restore_dpc_state(struct pci_dev *dev) { }
571 static inline void pci_dpc_init(struct pci_dev *pdev) { }
572 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; }
573 #endif
574
575 #ifdef CONFIG_PCIEPORTBUS
576 void pci_rcec_init(struct pci_dev *dev);
577 void pci_rcec_exit(struct pci_dev *dev);
578 void pcie_link_rcec(struct pci_dev *rcec);
579 void pcie_walk_rcec(struct pci_dev *rcec,
580 int (*cb)(struct pci_dev *, void *),
581 void *userdata);
582 #else
583 static inline void pci_rcec_init(struct pci_dev *dev) { }
584 static inline void pci_rcec_exit(struct pci_dev *dev) { }
585 static inline void pcie_link_rcec(struct pci_dev *rcec) { }
586 static inline void pcie_walk_rcec(struct pci_dev *rcec,
587 int (*cb)(struct pci_dev *, void *),
588 void *userdata) { }
589 #endif
590
591 #ifdef CONFIG_PCI_ATS
592 /* Address Translation Service */
593 void pci_ats_init(struct pci_dev *dev);
594 void pci_restore_ats_state(struct pci_dev *dev);
595 #else
596 static inline void pci_ats_init(struct pci_dev *d) { }
597 static inline void pci_restore_ats_state(struct pci_dev *dev) { }
598 #endif /* CONFIG_PCI_ATS */
599
600 #ifdef CONFIG_PCI_PRI
601 void pci_pri_init(struct pci_dev *dev);
602 void pci_restore_pri_state(struct pci_dev *pdev);
603 #else
604 static inline void pci_pri_init(struct pci_dev *dev) { }
605 static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
606 #endif
607
608 #ifdef CONFIG_PCI_PASID
609 void pci_pasid_init(struct pci_dev *dev);
610 void pci_restore_pasid_state(struct pci_dev *pdev);
611 #else
612 static inline void pci_pasid_init(struct pci_dev *dev) { }
613 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
614 #endif
615
616 #ifdef CONFIG_PCI_IOV
617 int pci_iov_init(struct pci_dev *dev);
618 void pci_iov_release(struct pci_dev *dev);
619 void pci_iov_remove(struct pci_dev *dev);
620 void pci_iov_update_resource(struct pci_dev *dev, int resno);
621 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
622 void pci_restore_iov_state(struct pci_dev *dev);
623 int pci_iov_bus_range(struct pci_bus *bus);
624 extern const struct attribute_group sriov_pf_dev_attr_group;
625 extern const struct attribute_group sriov_vf_dev_attr_group;
626 #else
627 static inline int pci_iov_init(struct pci_dev *dev)
628 {
629 return -ENODEV;
630 }
631 static inline void pci_iov_release(struct pci_dev *dev) { }
632 static inline void pci_iov_remove(struct pci_dev *dev) { }
633 static inline void pci_restore_iov_state(struct pci_dev *dev) { }
634 static inline int pci_iov_bus_range(struct pci_bus *bus)
635 {
636 return 0;
637 }
638
639 #endif /* CONFIG_PCI_IOV */
640
641 #ifdef CONFIG_PCIE_TPH
642 void pci_restore_tph_state(struct pci_dev *dev);
643 void pci_save_tph_state(struct pci_dev *dev);
644 void pci_no_tph(void);
645 void pci_tph_init(struct pci_dev *dev);
646 #else
647 static inline void pci_restore_tph_state(struct pci_dev *dev) { }
648 static inline void pci_save_tph_state(struct pci_dev *dev) { }
649 static inline void pci_no_tph(void) { }
650 static inline void pci_tph_init(struct pci_dev *dev) { }
651 #endif
652
653 #ifdef CONFIG_PCIE_PTM
654 void pci_ptm_init(struct pci_dev *dev);
655 void pci_save_ptm_state(struct pci_dev *dev);
656 void pci_restore_ptm_state(struct pci_dev *dev);
657 void pci_suspend_ptm(struct pci_dev *dev);
658 void pci_resume_ptm(struct pci_dev *dev);
659 #else
660 static inline void pci_ptm_init(struct pci_dev *dev) { }
661 static inline void pci_save_ptm_state(struct pci_dev *dev) { }
662 static inline void pci_restore_ptm_state(struct pci_dev *dev) { }
663 static inline void pci_suspend_ptm(struct pci_dev *dev) { }
664 static inline void pci_resume_ptm(struct pci_dev *dev) { }
665 #endif
666
667 unsigned long pci_cardbus_resource_alignment(struct resource *);
668
669 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
670 struct resource *res)
671 {
672 #ifdef CONFIG_PCI_IOV
673 int resno = res - dev->resource;
674
675 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
676 return pci_sriov_resource_alignment(dev, resno);
677 #endif
678 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
679 return pci_cardbus_resource_alignment(res);
680 return resource_alignment(res);
681 }
682
683 void pci_acs_init(struct pci_dev *dev);
684 #ifdef CONFIG_PCI_QUIRKS
685 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
686 int pci_dev_specific_enable_acs(struct pci_dev *dev);
687 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
688 int pcie_failed_link_retrain(struct pci_dev *dev);
689 #else
690 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
691 u16 acs_flags)
692 {
693 return -ENOTTY;
694 }
695 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
696 {
697 return -ENOTTY;
698 }
699 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
700 {
701 return -ENOTTY;
702 }
703 static inline int pcie_failed_link_retrain(struct pci_dev *dev)
704 {
705 return -ENOTTY;
706 }
707 #endif
708
709 /* PCI error reporting and recovery */
710 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
711 pci_channel_state_t state,
712 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev));
713
714 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
715 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt);
716
717 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */
718 void pci_save_ltr_state(struct pci_dev *dev);
719 void pci_restore_ltr_state(struct pci_dev *dev);
720 void pci_configure_aspm_l1ss(struct pci_dev *dev);
721 void pci_save_aspm_l1ss_state(struct pci_dev *dev);
722 void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
723
724 #ifdef CONFIG_PCIEASPM
725 void pcie_aspm_init_link_state(struct pci_dev *pdev);
726 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
727 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked);
728 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
729 void pci_configure_ltr(struct pci_dev *pdev);
730 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev);
731 #else
732 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
733 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
734 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { }
735 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
736 static inline void pci_configure_ltr(struct pci_dev *pdev) { }
737 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { }
738 #endif
739
740 #ifdef CONFIG_PCIE_ECRC
741 void pcie_set_ecrc_checking(struct pci_dev *dev);
742 void pcie_ecrc_get_policy(char *str);
743 #else
744 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
745 static inline void pcie_ecrc_get_policy(char *str) { }
746 #endif
747
748 #ifdef CONFIG_PCIEPORTBUS
749 void pcie_reset_lbms_count(struct pci_dev *port);
750 int pcie_lbms_count(struct pci_dev *port, unsigned long *val);
751 #else
752 static inline void pcie_reset_lbms_count(struct pci_dev *port) {}
753 static inline int pcie_lbms_count(struct pci_dev *port, unsigned long *val)
754 {
755 return -EOPNOTSUPP;
756 }
757 #endif
758
759 struct pci_dev_reset_methods {
760 u16 vendor;
761 u16 device;
762 int (*reset)(struct pci_dev *dev, bool probe);
763 };
764
765 struct pci_reset_fn_method {
766 int (*reset_fn)(struct pci_dev *pdev, bool probe);
767 char *name;
768 };
769
770 #ifdef CONFIG_PCI_QUIRKS
771 int pci_dev_specific_reset(struct pci_dev *dev, bool probe);
772 #else
773 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe)
774 {
775 return -ENOTTY;
776 }
777 #endif
778
779 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
780 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
781 struct resource *res);
782 #else
783 static inline int acpi_get_rc_resources(struct device *dev, const char *hid,
784 u16 segment, struct resource *res)
785 {
786 return -ENODEV;
787 }
788 #endif
789
790 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
791 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
792 static inline u64 pci_rebar_size_to_bytes(int size)
793 {
794 return 1ULL << (size + 20);
795 }
796
797 struct device_node;
798
799 #ifdef CONFIG_OF
800 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
801 int of_get_pci_domain_nr(struct device_node *node);
802 int of_pci_get_max_link_speed(struct device_node *node);
803 u32 of_pci_get_slot_power_limit(struct device_node *node,
804 u8 *slot_power_limit_value,
805 u8 *slot_power_limit_scale);
806 bool of_pci_preserve_config(struct device_node *node);
807 int pci_set_of_node(struct pci_dev *dev);
808 void pci_release_of_node(struct pci_dev *dev);
809 void pci_set_bus_of_node(struct pci_bus *bus);
810 void pci_release_bus_of_node(struct pci_bus *bus);
811
812 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
813 bool of_pci_supply_present(struct device_node *np);
814
815 #else
816 static inline int
817 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
818 {
819 return -EINVAL;
820 }
821
822 static inline int
823 of_get_pci_domain_nr(struct device_node *node)
824 {
825 return -1;
826 }
827
828 static inline int
829 of_pci_get_max_link_speed(struct device_node *node)
830 {
831 return -EINVAL;
832 }
833
834 static inline u32
835 of_pci_get_slot_power_limit(struct device_node *node,
836 u8 *slot_power_limit_value,
837 u8 *slot_power_limit_scale)
838 {
839 if (slot_power_limit_value)
840 *slot_power_limit_value = 0;
841 if (slot_power_limit_scale)
842 *slot_power_limit_scale = 0;
843 return 0;
844 }
845
846 static inline bool of_pci_preserve_config(struct device_node *node)
847 {
848 return false;
849 }
850
851 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; }
852 static inline void pci_release_of_node(struct pci_dev *dev) { }
853 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
854 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
855
856 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
857 {
858 return 0;
859 }
860
861 static inline bool of_pci_supply_present(struct device_node *np)
862 {
863 return false;
864 }
865 #endif /* CONFIG_OF */
866
867 struct of_changeset;
868
869 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES
870 void of_pci_make_dev_node(struct pci_dev *pdev);
871 void of_pci_remove_node(struct pci_dev *pdev);
872 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
873 struct device_node *np);
874 #else
875 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { }
876 static inline void of_pci_remove_node(struct pci_dev *pdev) { }
877 #endif
878
879 #ifdef CONFIG_PCIEAER
880 void pci_no_aer(void);
881 void pci_aer_init(struct pci_dev *dev);
882 void pci_aer_exit(struct pci_dev *dev);
883 extern const struct attribute_group aer_stats_attr_group;
884 void pci_aer_clear_fatal_status(struct pci_dev *dev);
885 int pci_aer_clear_status(struct pci_dev *dev);
886 int pci_aer_raw_clear_status(struct pci_dev *dev);
887 void pci_save_aer_state(struct pci_dev *dev);
888 void pci_restore_aer_state(struct pci_dev *dev);
889 #else
890 static inline void pci_no_aer(void) { }
891 static inline void pci_aer_init(struct pci_dev *d) { }
892 static inline void pci_aer_exit(struct pci_dev *d) { }
893 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
894 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
895 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
896 static inline void pci_save_aer_state(struct pci_dev *dev) { }
897 static inline void pci_restore_aer_state(struct pci_dev *dev) { }
898 #endif
899
900 #ifdef CONFIG_ACPI
901 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge);
902 int pci_acpi_program_hp_params(struct pci_dev *dev);
903 extern const struct attribute_group pci_dev_acpi_attr_group;
904 void pci_set_acpi_fwnode(struct pci_dev *dev);
905 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe);
906 bool acpi_pci_power_manageable(struct pci_dev *dev);
907 bool acpi_pci_bridge_d3(struct pci_dev *dev);
908 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state);
909 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev);
910 void acpi_pci_refresh_power_state(struct pci_dev *dev);
911 int acpi_pci_wakeup(struct pci_dev *dev, bool enable);
912 bool acpi_pci_need_resume(struct pci_dev *dev);
913 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev);
914 #else
915 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge)
916 {
917 return false;
918 }
919 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
920 {
921 return -ENOTTY;
922 }
923 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { }
924 static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
925 {
926 return -ENODEV;
927 }
928 static inline bool acpi_pci_power_manageable(struct pci_dev *dev)
929 {
930 return false;
931 }
932 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev)
933 {
934 return false;
935 }
936 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
937 {
938 return -ENODEV;
939 }
940 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
941 {
942 return PCI_UNKNOWN;
943 }
944 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { }
945 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
946 {
947 return -ENODEV;
948 }
949 static inline bool acpi_pci_need_resume(struct pci_dev *dev)
950 {
951 return false;
952 }
953 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
954 {
955 return PCI_POWER_ERROR;
956 }
957 #endif
958
959 #ifdef CONFIG_PCIEASPM
960 extern const struct attribute_group aspm_ctrl_attr_group;
961 #endif
962
963 extern const struct attribute_group pci_dev_reset_method_attr_group;
964
965 #ifdef CONFIG_X86_INTEL_MID
966 bool pci_use_mid_pm(void);
967 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state);
968 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev);
969 #else
970 static inline bool pci_use_mid_pm(void)
971 {
972 return false;
973 }
974 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state)
975 {
976 return -ENODEV;
977 }
978 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev)
979 {
980 return PCI_UNKNOWN;
981 }
982 #endif
983
984 int pcim_intx(struct pci_dev *dev, int enable);
985 int pcim_request_region_exclusive(struct pci_dev *pdev, int bar,
986 const char *name);
987 void pcim_release_region(struct pci_dev *pdev, int bar);
988
989 /*
990 * Config Address for PCI Configuration Mechanism #1
991 *
992 * See PCI Local Bus Specification, Revision 3.0,
993 * Section 3.2.2.3.2, Figure 3-2, p. 50.
994 */
995
996 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */
997 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */
998 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */
999
1000 #define PCI_CONF1_BUS_MASK 0xff
1001 #define PCI_CONF1_DEV_MASK 0x1f
1002 #define PCI_CONF1_FUNC_MASK 0x7
1003 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */
1004
1005 #define PCI_CONF1_ENABLE BIT(31)
1006 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT)
1007 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT)
1008 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT)
1009 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK)
1010
1011 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \
1012 (PCI_CONF1_ENABLE | \
1013 PCI_CONF1_BUS(bus) | \
1014 PCI_CONF1_DEV(dev) | \
1015 PCI_CONF1_FUNC(func) | \
1016 PCI_CONF1_REG(reg))
1017
1018 /*
1019 * Extension of PCI Config Address for accessing extended PCIe registers
1020 *
1021 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs
1022 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address
1023 * are used for specifying additional 4 high bits of PCI Express register.
1024 */
1025
1026 #define PCI_CONF1_EXT_REG_SHIFT 16
1027 #define PCI_CONF1_EXT_REG_MASK 0xf00
1028 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT)
1029
1030 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \
1031 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \
1032 PCI_CONF1_EXT_REG(reg))
1033
1034 #endif /* DRIVERS_PCI_H */
Kernel DRM miscellaneous fixes and cross-tree changes