| blob | 1d1db1737422a8edd29cf63201ee244270ee1e69 |
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2018 Marvell
4 *
5 * Authors:
6 * Evan Wang <xswang@marvell.com>
7 * Miquèl Raynal <miquel.raynal@bootlin.com>
8 * Pali Rohár <pali@kernel.org>
9 * Marek Behún <kabel@kernel.org>
10 *
11 * Structure inspired from phy-mvebu-cp110-comphy.c written by Antoine Tenart.
12 * Comphy code from ARM Trusted Firmware ported by Pali Rohár <pali@kernel.org>
13 * and Marek Behún <kabel@kernel.org>.
14 */
16 #include <linux/bitfield.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/iopoll.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/phy.h>
24 #include <linux/phy/phy.h>
25 #include <linux/platform_device.h>
26 #include <linux/spinlock.h>
28 #define PLL_SET_DELAY_US 600
29 #define COMPHY_PLL_SLEEP 1000
30 #define COMPHY_PLL_TIMEOUT 150000
32 /* Comphy lane2 indirect access register offset */
33 #define COMPHY_LANE2_INDIR_ADDR 0x0
34 #define COMPHY_LANE2_INDIR_DATA 0x4
36 /* SATA and USB3 PHY offset compared to SATA PHY */
37 #define COMPHY_LANE2_REGS_BASE 0x200
39 /*
40 * When accessing common PHY lane registers directly, we need to shift by 1,
41 * since the registers are 16-bit.
42 */
43 #define COMPHY_LANE_REG_DIRECT(reg) (((reg) & 0x7FF) << 1)
45 /* COMPHY registers */
46 #define COMPHY_POWER_PLL_CTRL 0x01
47 #define PU_IVREF_BIT BIT(15)
48 #define PU_PLL_BIT BIT(14)
49 #define PU_RX_BIT BIT(13)
50 #define PU_TX_BIT BIT(12)
51 #define PU_TX_INTP_BIT BIT(11)
52 #define PU_DFE_BIT BIT(10)
53 #define RESET_DTL_RX_BIT BIT(9)
54 #define PLL_LOCK_BIT BIT(8)
55 #define REF_FREF_SEL_MASK GENMASK(4, 0)
56 #define REF_FREF_SEL_SERDES_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x1)
57 #define REF_FREF_SEL_SERDES_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
58 #define REF_FREF_SEL_SERDES_50MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x4)
59 #define REF_FREF_SEL_PCIE_USB3_25MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x2)
60 #define REF_FREF_SEL_PCIE_USB3_40MHZ FIELD_PREP(REF_FREF_SEL_MASK, 0x3)
61 #define COMPHY_MODE_MASK GENMASK(7, 5)
62 #define COMPHY_MODE_SATA FIELD_PREP(COMPHY_MODE_MASK, 0x0)
63 #define COMPHY_MODE_PCIE FIELD_PREP(COMPHY_MODE_MASK, 0x3)
64 #define COMPHY_MODE_SERDES FIELD_PREP(COMPHY_MODE_MASK, 0x4)
65 #define COMPHY_MODE_USB3 FIELD_PREP(COMPHY_MODE_MASK, 0x5)
67 #define COMPHY_KVCO_CAL_CTRL 0x02
68 #define USE_MAX_PLL_RATE_BIT BIT(12)
69 #define SPEED_PLL_MASK GENMASK(7, 2)
70 #define SPEED_PLL_VALUE_16 FIELD_PREP(SPEED_PLL_MASK, 0x10)
72 #define COMPHY_DIG_LOOPBACK_EN 0x23
73 #define SEL_DATA_WIDTH_MASK GENMASK(11, 10)
74 #define DATA_WIDTH_10BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x0)
75 #define DATA_WIDTH_20BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x1)
76 #define DATA_WIDTH_40BIT FIELD_PREP(SEL_DATA_WIDTH_MASK, 0x2)
77 #define PLL_READY_TX_BIT BIT(4)
79 #define COMPHY_SYNC_PATTERN 0x24
80 #define TXD_INVERT_BIT BIT(10)
81 #define RXD_INVERT_BIT BIT(11)
83 #define COMPHY_SYNC_MASK_GEN 0x25
84 #define PHY_GEN_MAX_MASK GENMASK(11, 10)
85 #define PHY_GEN_MAX_USB3_5G FIELD_PREP(PHY_GEN_MAX_MASK, 0x1)
87 #define COMPHY_ISOLATION_CTRL 0x26
88 #define PHY_ISOLATE_MODE BIT(15)
90 #define COMPHY_GEN2_SET2 0x3e
91 #define GS2_TX_SSC_AMP_MASK GENMASK(15, 9)
92 #define GS2_TX_SSC_AMP_4128 FIELD_PREP(GS2_TX_SSC_AMP_MASK, 0x20)
93 #define GS2_VREG_RXTX_MAS_ISET_MASK GENMASK(8, 7)
94 #define GS2_VREG_RXTX_MAS_ISET_60U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
95 0x0)
96 #define GS2_VREG_RXTX_MAS_ISET_80U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
97 0x1)
98 #define GS2_VREG_RXTX_MAS_ISET_100U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
99 0x2)
100 #define GS2_VREG_RXTX_MAS_ISET_120U FIELD_PREP(GS2_VREG_RXTX_MAS_ISET_MASK,\
101 0x3)
102 #define GS2_RSVD_6_0_MASK GENMASK(6, 0)
104 #define COMPHY_GEN3_SET2 0x3f
106 #define COMPHY_IDLE_SYNC_EN 0x48
107 #define IDLE_SYNC_EN BIT(12)
109 #define COMPHY_MISC_CTRL0 0x4F
110 #define CLK100M_125M_EN BIT(4)
111 #define TXDCLK_2X_SEL BIT(6)
112 #define CLK500M_EN BIT(7)
113 #define PHY_REF_CLK_SEL BIT(10)
115 #define COMPHY_SFT_RESET 0x52
116 #define SFT_RST BIT(9)
117 #define SFT_RST_NO_REG BIT(10)
119 #define COMPHY_MISC_CTRL1 0x73
120 #define SEL_BITS_PCIE_FORCE BIT(15)
122 #define COMPHY_GEN2_SET3 0x112
123 #define GS3_FFE_CAP_SEL_MASK GENMASK(3, 0)
124 #define GS3_FFE_CAP_SEL_VALUE FIELD_PREP(GS3_FFE_CAP_SEL_MASK, 0xF)
126 /* PIPE registers */
127 #define COMPHY_PIPE_LANE_CFG0 0x180
128 #define PRD_TXDEEMPH0_MASK BIT(0)
129 #define PRD_TXMARGIN_MASK GENMASK(3, 1)
130 #define PRD_TXSWING_MASK BIT(4)
131 #define CFG_TX_ALIGN_POS_MASK GENMASK(8, 5)
133 #define COMPHY_PIPE_LANE_CFG1 0x181
134 #define PRD_TXDEEMPH1_MASK BIT(15)
135 #define USE_MAX_PLL_RATE_EN BIT(9)
136 #define TX_DET_RX_MODE BIT(6)
137 #define GEN2_TX_DATA_DLY_MASK GENMASK(4, 3)
138 #define GEN2_TX_DATA_DLY_DEFT FIELD_PREP(GEN2_TX_DATA_DLY_MASK, 2)
139 #define TX_ELEC_IDLE_MODE_EN BIT(0)
141 #define COMPHY_PIPE_LANE_STAT1 0x183
142 #define TXDCLK_PCLK_EN BIT(0)
144 #define COMPHY_PIPE_LANE_CFG4 0x188
145 #define SPREAD_SPECTRUM_CLK_EN BIT(7)
147 #define COMPHY_PIPE_RST_CLK_CTRL 0x1C1
148 #define PIPE_SOFT_RESET BIT(0)
149 #define PIPE_REG_RESET BIT(1)
150 #define MODE_CORE_CLK_FREQ_SEL BIT(9)
151 #define MODE_PIPE_WIDTH_32 BIT(3)
152 #define MODE_REFDIV_MASK GENMASK(5, 4)
153 #define MODE_REFDIV_BY_4 FIELD_PREP(MODE_REFDIV_MASK, 0x2)
155 #define COMPHY_PIPE_TEST_MODE_CTRL 0x1C2
156 #define MODE_MARGIN_OVERRIDE BIT(2)
158 #define COMPHY_PIPE_CLK_SRC_LO 0x1C3
159 #define MODE_CLK_SRC BIT(0)
160 #define BUNDLE_PERIOD_SEL BIT(1)
161 #define BUNDLE_PERIOD_SCALE_MASK GENMASK(3, 2)
162 #define BUNDLE_SAMPLE_CTRL BIT(4)
163 #define PLL_READY_DLY_MASK GENMASK(7, 5)
164 #define CFG_SEL_20B BIT(15)
166 #define COMPHY_PIPE_PWR_MGM_TIM1 0x1D0
167 #define CFG_PM_OSCCLK_WAIT_MASK GENMASK(15, 12)
168 #define CFG_PM_RXDEN_WAIT_MASK GENMASK(11, 8)
169 #define CFG_PM_RXDEN_WAIT_1_UNIT FIELD_PREP(CFG_PM_RXDEN_WAIT_MASK, 0x1)
170 #define CFG_PM_RXDLOZ_WAIT_MASK GENMASK(7, 0)
171 #define CFG_PM_RXDLOZ_WAIT_7_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0x7)
172 #define CFG_PM_RXDLOZ_WAIT_12_UNIT FIELD_PREP(CFG_PM_RXDLOZ_WAIT_MASK, 0xC)
174 /*
175 * This register is not from PHY lane register space. It only exists in the
176 * indirect register space, before the actual PHY lane 2 registers. So the
177 * offset is absolute, not relative to COMPHY_LANE2_REGS_BASE.
178 * It is used only for SATA PHY initialization.
179 */
180 #define COMPHY_RESERVED_REG 0x0E
181 #define PHYCTRL_FRM_PIN_BIT BIT(13)
183 /* South Bridge PHY Configuration Registers */
184 #define COMPHY_PHY_REG(lane, reg) (((1 - (lane)) * 0x28) + ((reg) & 0x3f))
186 /*
187 * lane0: USB3/GbE1 PHY Configuration 1
188 * lane1: PCIe/GbE0 PHY Configuration 1
189 * (used only by SGMII code)
190 */
191 #define COMPHY_PHY_CFG1 0x0
192 #define PIN_PU_IVREF_BIT BIT(1)
193 #define PIN_RESET_CORE_BIT BIT(11)
194 #define PIN_RESET_COMPHY_BIT BIT(12)
195 #define PIN_PU_PLL_BIT BIT(16)
196 #define PIN_PU_RX_BIT BIT(17)
197 #define PIN_PU_TX_BIT BIT(18)
198 #define PIN_TX_IDLE_BIT BIT(19)
199 #define GEN_RX_SEL_MASK GENMASK(25, 22)
200 #define GEN_RX_SEL_VALUE(val) FIELD_PREP(GEN_RX_SEL_MASK, (val))
201 #define GEN_TX_SEL_MASK GENMASK(29, 26)
202 #define GEN_TX_SEL_VALUE(val) FIELD_PREP(GEN_TX_SEL_MASK, (val))
203 #define SERDES_SPEED_1_25_G 0x6
204 #define SERDES_SPEED_3_125_G 0x8
205 #define PHY_RX_INIT_BIT BIT(30)
207 /*
208 * lane0: USB3/GbE1 PHY Status 1
209 * lane1: PCIe/GbE0 PHY Status 1
210 * (used only by SGMII code)
211 */
212 #define COMPHY_PHY_STAT1 0x18
213 #define PHY_RX_INIT_DONE_BIT BIT(0)
214 #define PHY_PLL_READY_RX_BIT BIT(2)
215 #define PHY_PLL_READY_TX_BIT BIT(3)
217 /* PHY Selector */
218 #define COMPHY_SELECTOR_PHY_REG 0xFC
219 /* bit0: 0: Lane1 is GbE0; 1: Lane1 is PCIe */
220 #define COMPHY_SELECTOR_PCIE_GBE0_SEL_BIT BIT(0)
221 /* bit4: 0: Lane0 is GbE1; 1: Lane0 is USB3 */
222 #define COMPHY_SELECTOR_USB3_GBE1_SEL_BIT BIT(4)
223 /* bit8: 0: Lane0 is USB3 instead of GbE1, Lane2 is SATA; 1: Lane2 is USB3 */
224 #define COMPHY_SELECTOR_USB3_PHY_SEL_BIT BIT(8)
230 };
232 #define MVEBU_A3700_COMPHY_CONF(_lane, _mode, _smode) \
233 { \
234 .lane = _lane, \
235 .mode = _mode, \
236 .submode = _smode, \
237 }
239 #define MVEBU_A3700_COMPHY_CONF_GEN(_lane, _mode) \
240 MVEBU_A3700_COMPHY_CONF(_lane, _mode, PHY_INTERFACE_MODE_NA)
242 #define MVEBU_A3700_COMPHY_CONF_ETH(_lane, _smode) \
243 MVEBU_A3700_COMPHY_CONF(_lane, PHY_MODE_ETHERNET, _smode)
246 /* lane 0 */
251 /* lane 1 */
256 /* lane 2 */
259 };
268 };
278 };
281 u16 addr;
282 u16 value;
283 };
285 /* Changes to 40M1G25 mode data required for running 40M3G125 init mode */
296 };
298 /* 40M1G25 mode init data */
300 /* 0 1 2 3 4 5 6 7 */
301 /*-----------------------------------------------------------*/
302 /* 8 9 A B C D E F */
367 };
370 {
371 u32 val;
376 }
379 {
380 u16 val;
385 }
387 /* Used for accessing lane 2 registers (SATA/USB3 PHY) */
390 {
395 }
399 {
401 /* lane 2 PHY registers are accessed indirectly */
412 }
413 }
418 {
422 u32 data;
424 /* lane 2 PHY registers are accessed indirectly */
427 COMPHY_LANE2_INDIR_ADDR);
430 COMPHY_LANE2_INDIR_DATA,
437 u16 data;
442 }
445 }
449 {
452 }
457 {
458 u32 data;
464 }
466 /* PHY selector configures with corresponding modes */
467 static int
469 {
475 /* SATA must be in Lane2 */
478 else
487 else
496 else
501 /* PCIE must be in Lane1 */
504 else
510 }
525 error:
529 }
531 static int
533 {
537 /* Configure phy selector for SATA */
542 /* Clear phy isolation mode to make it work in normal mode */
546 /* 0. Check the Polarity invert bits */
555 /* 1. Select 40-bit data width */
559 /* 2. Select reference clock(25M) and PHY mode (SATA) */
562 else
569 /* 3. Use maximum PLL rate (no power save) */
573 /* 4. Reset reserved bit */
577 /* 5. Set vendor-specific configuration (It is done in sata driver) */
578 /* XXX: in U-Boot below sequence was executed in this place, in Linux
579 * not. Now it is done only in U-Boot before this comphy
580 * initialization - tests shows that it works ok, but in case of any
581 * future problem it is left for reference.
582 * reg_set(MVEBU_REGS_BASE + 0xe00a0, 0, 0xffffffff);
583 * reg_set(MVEBU_REGS_BASE + 0xe00a4, BIT(6), BIT(6));
584 */
586 /* Wait for > 55 us to allow PLL be enabled */
589 /* Polling status */
592 COMPHY_PLL_TIMEOUT);
597 }
601 {
603 u16 val;
607 /*
608 * All PHY register values are defined in full for 3.125Gbps
609 * SERDES speed. The values required for 1.25 Gbps are almost
610 * the same and only few registers should be "fixed" in
611 * comparison to 3.125 Gbps values. These register values are
612 * stored in "gbe_phy_init_fix" array.
613 */
617 /* Use new value */
619 fix_idx++;
622 }
625 }
626 }
628 static int
630 {
634 /* Set selector */
639 /*
640 * 1. Reset PHY by setting PHY input port PIN_RESET=1.
641 * 2. Set PHY input port PIN_TX_IDLE=1, PIN_PU_IVREF=1 to keep
642 * PHY TXP/TXN output to idle state during PHY initialization
643 * 3. Set PHY input port PIN_PU_PLL=0, PIN_PU_RX=0, PIN_PU_TX=0.
644 */
650 /* 4. Release reset to the PHY by setting PIN_RESET=0. */
655 /*
656 * 5. Set PIN_PHY_GEN_TX[3:0] and PIN_PHY_GEN_RX[3:0] to decide COMPHY
657 * bit rate
658 */
662 /* SGMII 1G, SerDes speed 1.25G */
666 /* 2500Base-X, SerDes speed 3.125G */
670 /* Other rates are not supported */
675 }
680 /*
681 * 6. Wait 10mS for bandgap and reference clocks to stabilize; then
682 * start SW programming.
683 */
686 /* 7. Program COMPHY register PHY_MODE */
691 /*
692 * 8. Set COMPHY register REFCLK_SEL to select the correct REFCLK
693 * source
694 */
699 /*
700 * 9. Set correct reference clock frequency in COMPHY register
701 * REF_FREF_SEL.
702 */
705 else
711 /*
712 * 10. Program COMPHY register PHY_GEN_MAX[1:0]
713 * This step is mentioned in the flow received from verification team.
714 * However the PHY_GEN_MAX value is only meaningful for other interfaces
715 * (not SERDES). For instance, it selects SATA speed 1.5/3/6 Gbps or
716 * PCIe speed 2.5/5 Gbps
717 */
719 /*
720 * 11. Program COMPHY register SEL_BITS to set correct parallel data
721 * bus width
722 */
727 /*
728 * 12. As long as DFE function needs to be enabled in any mode,
729 * COMPHY register DFE_UPDATE_EN[5:0] shall be programmed to 0x3F
730 * for real chip during COMPHY power on.
731 * The value of the DFE_UPDATE_EN already is 0x3F, because it is the
732 * default value after reset of the PHY.
733 */
735 /*
736 * 13. Program COMPHY GEN registers.
737 * These registers should be programmed based on the lab testing result
738 * to achieve optimal performance. Please contact the CEA group to get
739 * the related GEN table during real chip bring-up. We only required to
740 * run though the entire registers programming flow defined by
741 * "comphy_gbe_phy_init" when the REF clock is 40 MHz. For REF clock
742 * 25 MHz the default values stored in PHY registers are OK.
743 */
750 /*
751 * 14. Check the PHY Polarity invert bit
752 */
761 /*
762 * 15. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1 to
763 * start PHY power up sequence. All the PHY register programming should
764 * be done before PIN_PU_PLL=1. There should be no register programming
765 * for normal PHY operation from this point.
766 */
771 /*
772 * 16. Wait for PHY power up sequence to finish by checking output ports
773 * PIN_PLL_READY_TX=1 and PIN_PLL_READY_RX=1.
774 */
776 PHY_PLL_READY_TX_BIT |
777 PHY_PLL_READY_RX_BIT,
783 }
785 /*
786 * 17. Set COMPHY input port PIN_TX_IDLE=0
787 */
790 /*
791 * 18. After valid data appear on PIN_RXDATA bus, set PIN_RX_INIT=1. To
792 * start RX initialization. PIN_RX_INIT_DONE will be cleared to 0 by the
793 * PHY After RX initialization is done, PIN_RX_INIT_DONE will be set to
794 * 1 by COMPHY Set PIN_RX_INIT=0 after PIN_RX_INIT_DONE= 1. Please
795 * refer to RX initialization part for details.
796 */
801 PHY_PLL_READY_TX_BIT |
802 PHY_PLL_READY_RX_BIT,
808 }
811 PHY_RX_INIT_DONE_BIT,
818 }
820 static int
822 {
826 /* Set phy seclector */
831 /* COMPHY register reset (cleared automatically) */
834 /*
835 * 0. Set PHY OTG Control(0x5d034), bit 4, Power up OTG module The
836 * register belong to UTMI module, so it is set in UTMI phy driver.
837 */
839 /*
840 * 1. Set PRD_TXDEEMPH (3.5db de-emph)
841 */
844 CFG_TX_ALIGN_POS_MASK;
847 /*
848 * 2. Set BIT0: enable transmitter in high impedance mode
849 * Set BIT[3:4]: delay 2 clock cycles for HiZ off latency
850 * Set BIT6: Tx detect Rx at HiZ mode
851 * Unset BIT15: set to 0 to set USB3 De-emphasize level to -3.5db
852 * together with bit 0 of COMPHY_PIPE_LANE_CFG0 register
853 */
856 TX_ELEC_IDLE_MODE_EN;
859 /*
860 * 3. Set Spread Spectrum Clock Enabled
861 */
865 /*
866 * 4. Set Override Margining Controls From the MAC:
867 * Use margining signals from lane configuration
868 */
872 /*
873 * 5. Set Lane-to-Lane Bundle Clock Sampling Period = per PCLK cycles
874 * set Mode Clock Source = PCLK is generated from REFCLK
875 */
881 /*
882 * 6. Set G2 Spread Spectrum Clock Amplitude at 4K
883 */
887 /*
888 * 7. Unset G3 Spread Spectrum Clock Amplitude
889 * set G3 TX and RX Register Master Current Select
890 */
893 GS2_RSVD_6_0_MASK;
896 /*
897 * 8. Check crystal jumper setting and program the Power and PLL Control
898 * accordingly Change RX wait
899 */
906 }
912 REF_FREF_SEL_MASK;
917 CFG_PM_RXDLOZ_WAIT_MASK;
920 /*
921 * 9. Enable idle sync
922 */
926 /*
927 * 10. Enable the output of 500M clock
928 */
931 /*
932 * 11. Set 20-bit data width
933 */
937 /*
938 * 12. Override Speed_PLL value and use MAC PLL
939 */
944 /*
945 * 13. Check the Polarity invert bit
946 */
955 /*
956 * 14. Set max speed generation to USB3.0 5Gbps
957 */
961 /*
962 * 15. Set capacitor value for FFE gain peaking to 0xF
963 */
967 /*
968 * 16. Release SW reset
969 */
974 /* Wait for > 55 us to allow PCLK be enabled */
983 }
985 static int
987 {
991 /* Configure phy selector for PCIe */
996 /* 1. Enable max PLL. */
1000 /* 2. Select 20 bit SERDES interface. */
1004 /* 3. Force to use reg setting for PCIe mode */
1008 /* 4. Change RX wait */
1011 CFG_PM_RXDLOZ_WAIT_MASK;
1014 /* 5. Enable idle sync */
1018 /* 6. Enable the output of 100M/125M/500M clock */
1023 /*
1024 * 7. Enable TX, PCIE global register, 0xd0074814, it is done in
1025 * PCI-E driver
1026 */
1028 /*
1029 * 8. Check crystal jumper setting and program the Power and PLL
1030 * Control accordingly
1031 */
1035 else
1043 /* 9. Override Speed_PLL value and use MAC PLL */
1048 /* 10. Check the Polarity invert bit */
1057 /* 11. Release SW reset */
1062 /* Wait for > 55 us to allow PCLK be enabled */
1071 }
1073 static void
1075 {
1076 /* Set phy isolation mode */
1080 /* Power off PLL, Tx, Rx */
1083 }
1085 static void
1087 {
1091 PHY_RX_INIT_BIT;
1094 }
1096 static void
1098 {
1099 /* Power off PLL, Tx, Rx */
1102 }
1105 {
1106 /*
1107 * The USB3 MAC sets the USB3 PHY to low state, so we do not
1108 * need to power off USB3 PHY again.
1109 */
1110 }
1115 {
1118 /* Unused PHY mux value is 0x0 */
1127 }
1133 }
1137 {
1143 }
1145 /* Mode cannot be changed while the PHY is powered on */
1150 /* Just remember the mode, ->power_on() will do the real setup */
1155 }
1158 {
1165 }
1183 }
1184 }
1187 {
1206 }
1207 }
1214 };
1218 {
1233 }
1239 }
1242 {
1279 /*
1280 * Driver needs to know if reference xtal clock is 40MHz or 25MHz.
1281 * Old DT bindings do not have xtal clk present. So do not fail here
1282 * and expects that default 25MHz reference clock is used.
1283 */
1294 ret);
1299 }
1301 }
1309 u32 lane_id;
1314 ret);
1316 }
1321 }
1327 }
1334 }
1345 /*
1346 * To avoid relying on the bootloader/firmware configuration,
1347 * power off all comphys.
1348 */
1350 }
1353 mvebu_a3700_comphy_xlate);
1356 }
1360 { },
1361 };
1369 },
1370 };