drm/rockchip: Don't change hdmi reference clock rate
[drm/drm-misc.git] / drivers / phy / qualcomm / phy-qcom-qmp-pcs-ufs-v2.h
bloba0803a8783d2636c6f8ad4d28c2622fe7f67f187
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
6 #ifndef QCOM_PHY_QMP_PCS_UFS_V2_H_
7 #define QCOM_PHY_QMP_PCS_UFS_V2_H_
9 #define QPHY_V2_PCS_UFS_PHY_START 0x000
10 #define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL 0x004
12 #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x034
13 #define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL 0x038
14 #define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x03c
15 #define QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL 0x040
17 #define QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0x0cc
18 #define QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL 0x13c
19 #define QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME 0x140
20 #define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2 0x148
21 #define QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND 0x154
23 #define QPHY_V2_PCS_UFS_READY_STATUS 0x168
25 #endif