1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
6 #include <linux/delay.h>
8 #include <linux/module.h>
10 #include <linux/phy/phy.h>
11 #include <linux/regulator/consumer.h>
12 #include <linux/platform_device.h>
13 #include <linux/clk.h>
14 #include <linux/slab.h>
16 #include <soc/tegra/fuse.h>
20 /* FUSE USB_CALIB registers */
21 #define HS_CURR_LEVEL_PADX_SHIFT(x) ((x) ? (11 + (x - 1) * 6) : 0)
22 #define HS_CURR_LEVEL_PAD_MASK 0x3f
23 #define HS_TERM_RANGE_ADJ_SHIFT 7
24 #define HS_TERM_RANGE_ADJ_MASK 0xf
25 #define HS_SQUELCH_SHIFT 29
26 #define HS_SQUELCH_MASK 0x7
28 #define RPD_CTRL_SHIFT 0
29 #define RPD_CTRL_MASK 0x1f
31 /* XUSB PADCTL registers */
32 #define XUSB_PADCTL_USB2_PAD_MUX 0x4
33 #define USB2_PORT_SHIFT(x) ((x) * 2)
34 #define USB2_PORT_MASK 0x3
36 #define HSIC_PORT_SHIFT(x) ((x) + 20)
37 #define HSIC_PORT_MASK 0x1
40 #define XUSB_PADCTL_USB2_PORT_CAP 0x8
41 #define XUSB_PADCTL_SS_PORT_CAP 0xc
42 #define PORTX_CAP_SHIFT(x) ((x) * 4)
43 #define PORT_CAP_MASK 0x3
44 #define PORT_CAP_DISABLED 0x0
45 #define PORT_CAP_HOST 0x1
46 #define PORT_CAP_DEVICE 0x2
47 #define PORT_CAP_OTG 0x3
49 #define XUSB_PADCTL_ELPG_PROGRAM 0x20
50 #define USB2_PORT_WAKE_INTERRUPT_ENABLE(x) BIT(x)
51 #define USB2_PORT_WAKEUP_EVENT(x) BIT((x) + 7)
52 #define SS_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 14)
53 #define SS_PORT_WAKEUP_EVENT(x) BIT((x) + 21)
54 #define USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x) BIT((x) + 28)
55 #define USB2_HSIC_PORT_WAKEUP_EVENT(x) BIT((x) + 30)
56 #define ALL_WAKE_EVENTS \
57 (USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
58 USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) | \
59 SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) | \
60 USB2_HSIC_PORT_WAKEUP_EVENT(0))
62 #define XUSB_PADCTL_ELPG_PROGRAM_1 0x24
63 #define SSPX_ELPG_CLAMP_EN(x) BIT(0 + (x) * 3)
64 #define SSPX_ELPG_CLAMP_EN_EARLY(x) BIT(1 + (x) * 3)
65 #define SSPX_ELPG_VCORE_DOWN(x) BIT(2 + (x) * 3)
66 #define XUSB_PADCTL_SS_PORT_CFG 0x2c
67 #define PORTX_SPEED_SUPPORT_SHIFT(x) ((x) * 4)
68 #define PORTX_SPEED_SUPPORT_MASK (0x3)
69 #define PORT_SPEED_SUPPORT_GEN1 (0x0)
71 #define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x) (0x88 + (x) * 0x40)
72 #define HS_CURR_LEVEL(x) ((x) & 0x3f)
73 #define TERM_SEL BIT(25)
74 #define USB2_OTG_PD BIT(26)
75 #define USB2_OTG_PD2 BIT(27)
76 #define USB2_OTG_PD2_OVRD_EN BIT(28)
77 #define USB2_OTG_PD_ZI BIT(29)
79 #define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x) (0x8c + (x) * 0x40)
80 #define USB2_OTG_PD_DR BIT(2)
81 #define TERM_RANGE_ADJ(x) (((x) & 0xf) << 3)
82 #define RPD_CTRL(x) (((x) & 0x1f) << 26)
84 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL0 0x284
85 #define BIAS_PAD_PD BIT(11)
86 #define HS_SQUELCH_LEVEL(x) (((x) & 0x7) << 0)
88 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL1 0x288
89 #define USB2_TRK_START_TIMER(x) (((x) & 0x7f) << 12)
90 #define USB2_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 19)
91 #define USB2_PD_TRK BIT(26)
92 #define USB2_TRK_COMPLETED BIT(31)
94 #define XUSB_PADCTL_USB2_BIAS_PAD_CTL2 0x28c
95 #define USB2_TRK_HW_MODE BIT(0)
96 #define CYA_TRK_CODE_UPDATE_ON_IDLE BIT(31)
98 #define XUSB_PADCTL_HSIC_PADX_CTL0(x) (0x300 + (x) * 0x20)
99 #define HSIC_PD_TX_DATA0 BIT(1)
100 #define HSIC_PD_TX_STROBE BIT(3)
101 #define HSIC_PD_RX_DATA0 BIT(4)
102 #define HSIC_PD_RX_STROBE BIT(6)
103 #define HSIC_PD_ZI_DATA0 BIT(7)
104 #define HSIC_PD_ZI_STROBE BIT(9)
105 #define HSIC_RPD_DATA0 BIT(13)
106 #define HSIC_RPD_STROBE BIT(15)
107 #define HSIC_RPU_DATA0 BIT(16)
108 #define HSIC_RPU_STROBE BIT(18)
110 #define XUSB_PADCTL_HSIC_PAD_TRK_CTL0 0x340
111 #define HSIC_TRK_START_TIMER(x) (((x) & 0x7f) << 5)
112 #define HSIC_TRK_DONE_RESET_TIMER(x) (((x) & 0x7f) << 12)
113 #define HSIC_PD_TRK BIT(19)
115 #define USB2_VBUS_ID 0x360
116 #define VBUS_OVERRIDE BIT(14)
117 #define ID_OVERRIDE(x) (((x) & 0xf) << 18)
118 #define ID_OVERRIDE_FLOATING ID_OVERRIDE(8)
119 #define ID_OVERRIDE_GROUNDED ID_OVERRIDE(0)
121 /* XUSB AO registers */
122 #define XUSB_AO_USB_DEBOUNCE_DEL (0x4)
123 #define UHSIC_LINE_DEB_CNT(x) (((x) & 0xf) << 4)
124 #define UTMIP_LINE_DEB_CNT(x) ((x) & 0xf)
126 #define XUSB_AO_UTMIP_TRIGGERS(x) (0x40 + (x) * 4)
127 #define CLR_WALK_PTR BIT(0)
128 #define CAP_CFG BIT(1)
129 #define CLR_WAKE_ALARM BIT(3)
131 #define XUSB_AO_UHSIC_TRIGGERS(x) (0x60 + (x) * 4)
132 #define HSIC_CLR_WALK_PTR BIT(0)
133 #define HSIC_CLR_WAKE_ALARM BIT(3)
134 #define HSIC_CAP_CFG BIT(4)
136 #define XUSB_AO_UTMIP_SAVED_STATE(x) (0x70 + (x) * 4)
137 #define SPEED(x) ((x) & 0x3)
138 #define UTMI_HS SPEED(0)
139 #define UTMI_FS SPEED(1)
140 #define UTMI_LS SPEED(2)
141 #define UTMI_RST SPEED(3)
143 #define XUSB_AO_UHSIC_SAVED_STATE(x) (0x90 + (x) * 4)
144 #define MODE(x) ((x) & 0x1)
145 #define MODE_HS MODE(0)
146 #define MODE_RST MODE(1)
148 #define XUSB_AO_UTMIP_SLEEPWALK_STATUS(x) (0xa0 + (x) * 4)
150 #define XUSB_AO_UTMIP_SLEEPWALK_CFG(x) (0xd0 + (x) * 4)
151 #define XUSB_AO_UHSIC_SLEEPWALK_CFG(x) (0xf0 + (x) * 4)
152 #define FAKE_USBOP_VAL BIT(0)
153 #define FAKE_USBON_VAL BIT(1)
154 #define FAKE_USBOP_EN BIT(2)
155 #define FAKE_USBON_EN BIT(3)
156 #define FAKE_STROBE_VAL BIT(0)
157 #define FAKE_DATA_VAL BIT(1)
158 #define FAKE_STROBE_EN BIT(2)
159 #define FAKE_DATA_EN BIT(3)
160 #define WAKE_WALK_EN BIT(14)
161 #define MASTER_ENABLE BIT(15)
162 #define LINEVAL_WALK_EN BIT(16)
163 #define WAKE_VAL(x) (((x) & 0xf) << 17)
164 #define WAKE_VAL_NONE WAKE_VAL(12)
165 #define WAKE_VAL_ANY WAKE_VAL(15)
166 #define WAKE_VAL_DS10 WAKE_VAL(2)
167 #define LINE_WAKEUP_EN BIT(21)
168 #define MASTER_CFG_SEL BIT(22)
170 #define XUSB_AO_UTMIP_SLEEPWALK(x) (0x100 + (x) * 4)
172 #define USBOP_RPD_A BIT(0)
173 #define USBON_RPD_A BIT(1)
176 #define HIGHZ_A BIT(6)
177 #define MASTER_ENABLE_A BIT(7)
179 #define USBOP_RPD_B BIT(8)
180 #define USBON_RPD_B BIT(9)
183 #define HIGHZ_B BIT(14)
184 #define MASTER_ENABLE_B BIT(15)
186 #define USBOP_RPD_C BIT(16)
187 #define USBON_RPD_C BIT(17)
190 #define HIGHZ_C BIT(22)
191 #define MASTER_ENABLE_C BIT(23)
193 #define USBOP_RPD_D BIT(24)
194 #define USBON_RPD_D BIT(25)
197 #define HIGHZ_D BIT(30)
198 #define MASTER_ENABLE_D BIT(31)
199 #define MASTER_ENABLE_B_C_D \
200 (MASTER_ENABLE_B | MASTER_ENABLE_C | MASTER_ENABLE_D)
202 #define XUSB_AO_UHSIC_SLEEPWALK(x) (0x120 + (x) * 4)
204 #define RPD_STROBE_A BIT(0)
205 #define RPD_DATA0_A BIT(1)
206 #define RPU_STROBE_A BIT(2)
207 #define RPU_DATA0_A BIT(3)
209 #define RPD_STROBE_B BIT(8)
210 #define RPD_DATA0_B BIT(9)
211 #define RPU_STROBE_B BIT(10)
212 #define RPU_DATA0_B BIT(11)
214 #define RPD_STROBE_C BIT(16)
215 #define RPD_DATA0_C BIT(17)
216 #define RPU_STROBE_C BIT(18)
217 #define RPU_DATA0_C BIT(19)
219 #define RPD_STROBE_D BIT(24)
220 #define RPD_DATA0_D BIT(25)
221 #define RPU_STROBE_D BIT(26)
222 #define RPU_DATA0_D BIT(27)
224 #define XUSB_AO_UTMIP_PAD_CFG(x) (0x130 + (x) * 4)
225 #define FSLS_USE_XUSB_AO BIT(3)
226 #define TRK_CTRL_USE_XUSB_AO BIT(4)
227 #define RPD_CTRL_USE_XUSB_AO BIT(5)
228 #define RPU_USE_XUSB_AO BIT(6)
229 #define VREG_USE_XUSB_AO BIT(7)
230 #define USBOP_VAL_PD BIT(8)
231 #define USBON_VAL_PD BIT(9)
232 #define E_DPD_OVRD_EN BIT(10)
233 #define E_DPD_OVRD_VAL BIT(11)
235 #define XUSB_AO_UHSIC_PAD_CFG(x) (0x150 + (x) * 4)
236 #define STROBE_VAL_PD BIT(0)
237 #define DATA0_VAL_PD BIT(1)
238 #define USE_XUSB_AO BIT(4)
240 #define TEGRA186_LANE(_name, _offset, _shift, _mask, _type) \
246 .num_funcs = ARRAY_SIZE(tegra186_##_type##_functions), \
247 .funcs = tegra186_##_type##_functions, \
250 struct tegra_xusb_fuse_calibration
{
253 u32 hs_term_range_adj
;
257 struct tegra186_xusb_padctl_context
{
264 struct tegra186_xusb_padctl
{
265 struct tegra_xusb_padctl base
;
266 void __iomem
*ao_regs
;
268 struct tegra_xusb_fuse_calibration calib
;
270 /* UTMI bias and tracking */
271 struct clk
*usb2_trk_clk
;
272 unsigned int bias_pad_enable
;
275 struct tegra186_xusb_padctl_context context
;
278 static inline void ao_writel(struct tegra186_xusb_padctl
*priv
, u32 value
, unsigned int offset
)
280 writel(value
, priv
->ao_regs
+ offset
);
283 static inline u32
ao_readl(struct tegra186_xusb_padctl
*priv
, unsigned int offset
)
285 return readl(priv
->ao_regs
+ offset
);
288 static inline struct tegra186_xusb_padctl
*
289 to_tegra186_xusb_padctl(struct tegra_xusb_padctl
*padctl
)
291 return container_of(padctl
, struct tegra186_xusb_padctl
, base
);
294 /* USB 2.0 UTMI PHY support */
295 static struct tegra_xusb_lane
*
296 tegra186_usb2_lane_probe(struct tegra_xusb_pad
*pad
, struct device_node
*np
,
299 struct tegra_xusb_usb2_lane
*usb2
;
302 usb2
= kzalloc(sizeof(*usb2
), GFP_KERNEL
);
304 return ERR_PTR(-ENOMEM
);
306 INIT_LIST_HEAD(&usb2
->base
.list
);
307 usb2
->base
.soc
= &pad
->soc
->lanes
[index
];
308 usb2
->base
.index
= index
;
309 usb2
->base
.pad
= pad
;
312 err
= tegra_xusb_lane_parse_dt(&usb2
->base
, np
);
321 static void tegra186_usb2_lane_remove(struct tegra_xusb_lane
*lane
)
323 struct tegra_xusb_usb2_lane
*usb2
= to_usb2_lane(lane
);
328 static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane
*lane
,
329 enum usb_device_speed speed
)
331 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
332 struct tegra186_xusb_padctl
*priv
= to_tegra186_xusb_padctl(padctl
);
333 unsigned int index
= lane
->index
;
336 mutex_lock(&padctl
->lock
);
338 /* ensure sleepwalk logic is disabled */
339 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
340 value
&= ~MASTER_ENABLE
;
341 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
343 /* ensure sleepwalk logics are in low power mode */
344 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
345 value
|= MASTER_CFG_SEL
;
346 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
348 /* set debounce time */
349 value
= ao_readl(priv
, XUSB_AO_USB_DEBOUNCE_DEL
);
350 value
&= ~UTMIP_LINE_DEB_CNT(~0);
351 value
|= UTMIP_LINE_DEB_CNT(1);
352 ao_writel(priv
, value
, XUSB_AO_USB_DEBOUNCE_DEL
);
354 /* ensure fake events of sleepwalk logic are desiabled */
355 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
356 value
&= ~(FAKE_USBOP_VAL
| FAKE_USBON_VAL
|
357 FAKE_USBOP_EN
| FAKE_USBON_EN
);
358 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
360 /* ensure wake events of sleepwalk logic are not latched */
361 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
362 value
&= ~LINE_WAKEUP_EN
;
363 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
365 /* disable wake event triggers of sleepwalk logic */
366 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
367 value
&= ~WAKE_VAL(~0);
368 value
|= WAKE_VAL_NONE
;
369 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
371 /* power down the line state detectors of the pad */
372 value
= ao_readl(priv
, XUSB_AO_UTMIP_PAD_CFG(index
));
373 value
|= (USBOP_VAL_PD
| USBON_VAL_PD
);
374 ao_writel(priv
, value
, XUSB_AO_UTMIP_PAD_CFG(index
));
376 /* save state per speed */
377 value
= ao_readl(priv
, XUSB_AO_UTMIP_SAVED_STATE(index
));
398 ao_writel(priv
, value
, XUSB_AO_UTMIP_SAVED_STATE(index
));
400 /* enable the trigger of the sleepwalk logic */
401 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
402 value
|= LINEVAL_WALK_EN
;
403 value
&= ~WAKE_WALK_EN
;
404 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
406 /* reset the walk pointer and clear the alarm of the sleepwalk logic,
407 * as well as capture the configuration of the USB2.0 pad
409 value
= ao_readl(priv
, XUSB_AO_UTMIP_TRIGGERS(index
));
410 value
|= (CLR_WALK_PTR
| CLR_WAKE_ALARM
| CAP_CFG
);
411 ao_writel(priv
, value
, XUSB_AO_UTMIP_TRIGGERS(index
));
413 /* setup the pull-ups and pull-downs of the signals during the four
414 * stages of sleepwalk.
415 * if device is connected, program sleepwalk logic to maintain a J and
416 * keep driving K upon seeing remote wake.
418 value
= USBOP_RPD_A
| USBOP_RPD_B
| USBOP_RPD_C
| USBOP_RPD_D
;
419 value
|= USBON_RPD_A
| USBON_RPD_B
| USBON_RPD_C
| USBON_RPD_D
;
424 /* J state: D+/D- = high/low, K state: D+/D- = low/high */
427 value
|= AN_B
| AN_C
| AN_D
;
428 if (padctl
->soc
->supports_lp_cfg_en
)
429 value
|= MASTER_ENABLE_B_C_D
;
433 /* J state: D+/D- = low/high, K state: D+/D- = high/low */
436 value
|= AP_B
| AP_C
| AP_D
;
437 if (padctl
->soc
->supports_lp_cfg_en
)
438 value
|= MASTER_ENABLE_B_C_D
;
442 value
|= HIGHZ_A
| HIGHZ_B
| HIGHZ_C
| HIGHZ_D
;
446 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK(index
));
448 /* power up the line state detectors of the pad */
449 value
= ao_readl(priv
, XUSB_AO_UTMIP_PAD_CFG(index
));
450 value
&= ~(USBOP_VAL_PD
| USBON_VAL_PD
);
451 ao_writel(priv
, value
, XUSB_AO_UTMIP_PAD_CFG(index
));
453 usleep_range(150, 200);
455 /* switch the electric control of the USB2.0 pad to XUSB_AO */
456 value
= ao_readl(priv
, XUSB_AO_UTMIP_PAD_CFG(index
));
457 value
|= FSLS_USE_XUSB_AO
| TRK_CTRL_USE_XUSB_AO
| RPD_CTRL_USE_XUSB_AO
|
458 RPU_USE_XUSB_AO
| VREG_USE_XUSB_AO
;
459 ao_writel(priv
, value
, XUSB_AO_UTMIP_PAD_CFG(index
));
461 /* set the wake signaling trigger events */
462 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
463 value
&= ~WAKE_VAL(~0);
464 value
|= WAKE_VAL_ANY
;
465 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
467 /* enable the wake detection */
468 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
469 value
|= MASTER_ENABLE
| LINE_WAKEUP_EN
;
470 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
472 mutex_unlock(&padctl
->lock
);
477 static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane
*lane
)
479 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
480 struct tegra186_xusb_padctl
*priv
= to_tegra186_xusb_padctl(padctl
);
481 unsigned int index
= lane
->index
;
484 mutex_lock(&padctl
->lock
);
486 /* disable the wake detection */
487 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
488 value
&= ~(MASTER_ENABLE
| LINE_WAKEUP_EN
);
489 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
491 /* switch the electric control of the USB2.0 pad to XUSB vcore logic */
492 value
= ao_readl(priv
, XUSB_AO_UTMIP_PAD_CFG(index
));
493 value
&= ~(FSLS_USE_XUSB_AO
| TRK_CTRL_USE_XUSB_AO
| RPD_CTRL_USE_XUSB_AO
|
494 RPU_USE_XUSB_AO
| VREG_USE_XUSB_AO
);
495 ao_writel(priv
, value
, XUSB_AO_UTMIP_PAD_CFG(index
));
497 /* disable wake event triggers of sleepwalk logic */
498 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
499 value
&= ~WAKE_VAL(~0);
500 value
|= WAKE_VAL_NONE
;
501 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK_CFG(index
));
503 if (padctl
->soc
->supports_lp_cfg_en
) {
504 /* disable the four stages of sleepwalk */
505 value
= ao_readl(priv
, XUSB_AO_UTMIP_SLEEPWALK(index
));
506 value
&= ~(MASTER_ENABLE_A
| MASTER_ENABLE_B_C_D
);
507 ao_writel(priv
, value
, XUSB_AO_UTMIP_SLEEPWALK(index
));
510 /* power down the line state detectors of the port */
511 value
= ao_readl(priv
, XUSB_AO_UTMIP_PAD_CFG(index
));
512 value
|= USBOP_VAL_PD
| USBON_VAL_PD
;
513 ao_writel(priv
, value
, XUSB_AO_UTMIP_PAD_CFG(index
));
515 /* clear alarm of the sleepwalk logic */
516 value
= ao_readl(priv
, XUSB_AO_UTMIP_TRIGGERS(index
));
517 value
|= CLR_WAKE_ALARM
;
518 ao_writel(priv
, value
, XUSB_AO_UTMIP_TRIGGERS(index
));
520 mutex_unlock(&padctl
->lock
);
525 static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane
*lane
)
527 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
528 unsigned int index
= lane
->index
;
531 mutex_lock(&padctl
->lock
);
533 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM
);
534 value
&= ~ALL_WAKE_EVENTS
;
535 value
|= USB2_PORT_WAKEUP_EVENT(index
);
536 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM
);
538 usleep_range(10, 20);
540 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM
);
541 value
&= ~ALL_WAKE_EVENTS
;
542 value
|= USB2_PORT_WAKE_INTERRUPT_ENABLE(index
);
543 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM
);
545 mutex_unlock(&padctl
->lock
);
550 static int tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane
*lane
)
552 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
553 unsigned int index
= lane
->index
;
556 mutex_lock(&padctl
->lock
);
558 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM
);
559 value
&= ~ALL_WAKE_EVENTS
;
560 value
&= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index
);
561 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM
);
563 usleep_range(10, 20);
565 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM
);
566 value
&= ~ALL_WAKE_EVENTS
;
567 value
|= USB2_PORT_WAKEUP_EVENT(index
);
568 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM
);
570 mutex_unlock(&padctl
->lock
);
575 static bool tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane
*lane
)
577 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
578 unsigned int index
= lane
->index
;
581 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM
);
582 if ((value
& USB2_PORT_WAKE_INTERRUPT_ENABLE(index
)) &&
583 (value
& USB2_PORT_WAKEUP_EVENT(index
)))
589 static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops
= {
590 .probe
= tegra186_usb2_lane_probe
,
591 .remove
= tegra186_usb2_lane_remove
,
592 .enable_phy_sleepwalk
= tegra186_utmi_enable_phy_sleepwalk
,
593 .disable_phy_sleepwalk
= tegra186_utmi_disable_phy_sleepwalk
,
594 .enable_phy_wake
= tegra186_utmi_enable_phy_wake
,
595 .disable_phy_wake
= tegra186_utmi_disable_phy_wake
,
596 .remote_wake_detected
= tegra186_utmi_phy_remote_wake_detected
,
599 static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl
*padctl
)
601 struct tegra186_xusb_padctl
*priv
= to_tegra186_xusb_padctl(padctl
);
602 struct device
*dev
= padctl
->dev
;
606 mutex_lock(&padctl
->lock
);
608 if (priv
->bias_pad_enable
++ > 0) {
609 mutex_unlock(&padctl
->lock
);
613 err
= clk_prepare_enable(priv
->usb2_trk_clk
);
615 dev_warn(dev
, "failed to enable USB2 trk clock: %d\n", err
);
617 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
618 value
&= ~USB2_TRK_START_TIMER(~0);
619 value
|= USB2_TRK_START_TIMER(0x1e);
620 value
&= ~USB2_TRK_DONE_RESET_TIMER(~0);
621 value
|= USB2_TRK_DONE_RESET_TIMER(0xa);
622 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
624 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL0
);
625 value
&= ~BIAS_PAD_PD
;
626 value
&= ~HS_SQUELCH_LEVEL(~0);
627 value
|= HS_SQUELCH_LEVEL(priv
->calib
.hs_squelch
);
628 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL0
);
632 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
633 value
&= ~USB2_PD_TRK
;
634 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
636 if (padctl
->soc
->poll_trk_completed
) {
637 err
= padctl_readl_poll(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
,
638 USB2_TRK_COMPLETED
, USB2_TRK_COMPLETED
, 100);
640 /* The failure with polling on trk complete will not
641 * cause the failure of powering on the bias pad.
643 dev_warn(dev
, "failed to poll USB2 trk completed: %d\n", err
);
646 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
647 value
|= USB2_TRK_COMPLETED
;
648 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
653 if (padctl
->soc
->trk_hw_mode
) {
654 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL2
);
655 value
|= USB2_TRK_HW_MODE
;
656 value
&= ~CYA_TRK_CODE_UPDATE_ON_IDLE
;
657 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL2
);
659 clk_disable_unprepare(priv
->usb2_trk_clk
);
662 mutex_unlock(&padctl
->lock
);
665 static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl
*padctl
)
667 struct tegra186_xusb_padctl
*priv
= to_tegra186_xusb_padctl(padctl
);
670 mutex_lock(&padctl
->lock
);
672 if (WARN_ON(priv
->bias_pad_enable
== 0)) {
673 mutex_unlock(&padctl
->lock
);
677 if (--priv
->bias_pad_enable
> 0) {
678 mutex_unlock(&padctl
->lock
);
682 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
683 value
|= USB2_PD_TRK
;
684 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL1
);
686 if (padctl
->soc
->trk_hw_mode
) {
687 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_BIAS_PAD_CTL2
);
688 value
&= ~USB2_TRK_HW_MODE
;
689 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_BIAS_PAD_CTL2
);
690 clk_disable_unprepare(priv
->usb2_trk_clk
);
693 mutex_unlock(&padctl
->lock
);
696 static void tegra186_utmi_pad_power_on(struct phy
*phy
)
698 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
699 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
700 struct tegra_xusb_usb2_port
*port
;
701 struct device
*dev
= padctl
->dev
;
702 unsigned int index
= lane
->index
;
708 port
= tegra_xusb_find_usb2_port(padctl
, index
);
710 dev_err(dev
, "no port found for USB2 lane %u\n", index
);
714 dev_dbg(dev
, "power on UTMI pad %u\n", index
);
716 tegra186_utmi_bias_pad_power_on(padctl
);
720 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index
));
721 value
&= ~USB2_OTG_PD
;
722 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index
));
724 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index
));
725 value
&= ~USB2_OTG_PD_DR
;
726 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index
));
729 static void tegra186_utmi_pad_power_down(struct phy
*phy
)
731 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
732 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
733 unsigned int index
= lane
->index
;
739 dev_dbg(padctl
->dev
, "power down UTMI pad %u\n", index
);
741 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index
));
742 value
|= USB2_OTG_PD
;
743 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index
));
745 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index
));
746 value
|= USB2_OTG_PD_DR
;
747 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index
));
751 tegra186_utmi_bias_pad_power_off(padctl
);
754 static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl
*padctl
,
759 dev_dbg(padctl
->dev
, "%s vbus override\n", status
? "set" : "clear");
761 value
= padctl_readl(padctl
, USB2_VBUS_ID
);
764 value
|= VBUS_OVERRIDE
;
765 value
&= ~ID_OVERRIDE(~0);
766 value
|= ID_OVERRIDE_FLOATING
;
768 value
&= ~VBUS_OVERRIDE
;
771 padctl_writel(padctl
, value
, USB2_VBUS_ID
);
776 static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl
*padctl
,
781 dev_dbg(padctl
->dev
, "%s id override\n", status
? "set" : "clear");
783 value
= padctl_readl(padctl
, USB2_VBUS_ID
);
786 if (value
& VBUS_OVERRIDE
) {
787 value
&= ~VBUS_OVERRIDE
;
788 padctl_writel(padctl
, value
, USB2_VBUS_ID
);
789 usleep_range(1000, 2000);
791 value
= padctl_readl(padctl
, USB2_VBUS_ID
);
794 value
&= ~ID_OVERRIDE(~0);
795 value
|= ID_OVERRIDE_GROUNDED
;
797 value
&= ~ID_OVERRIDE(~0);
798 value
|= ID_OVERRIDE_FLOATING
;
801 padctl_writel(padctl
, value
, USB2_VBUS_ID
);
806 static int tegra186_utmi_phy_set_mode(struct phy
*phy
, enum phy_mode mode
,
809 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
810 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
811 struct tegra_xusb_usb2_port
*port
= tegra_xusb_find_usb2_port(padctl
,
815 mutex_lock(&padctl
->lock
);
817 dev_dbg(&port
->base
.dev
, "%s: mode %d", __func__
, mode
);
819 if (mode
== PHY_MODE_USB_OTG
) {
820 if (submode
== USB_ROLE_HOST
) {
821 tegra186_xusb_padctl_id_override(padctl
, true);
823 err
= regulator_enable(port
->supply
);
824 } else if (submode
== USB_ROLE_DEVICE
) {
825 tegra186_xusb_padctl_vbus_override(padctl
, true);
826 } else if (submode
== USB_ROLE_NONE
) {
828 * When port is peripheral only or role transitions to
829 * USB_ROLE_NONE from USB_ROLE_DEVICE, regulator is not
832 if (regulator_is_enabled(port
->supply
))
833 regulator_disable(port
->supply
);
835 tegra186_xusb_padctl_id_override(padctl
, false);
836 tegra186_xusb_padctl_vbus_override(padctl
, false);
840 mutex_unlock(&padctl
->lock
);
845 static int tegra186_utmi_phy_power_on(struct phy
*phy
)
847 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
848 struct tegra_xusb_usb2_lane
*usb2
= to_usb2_lane(lane
);
849 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
850 struct tegra186_xusb_padctl
*priv
= to_tegra186_xusb_padctl(padctl
);
851 struct tegra_xusb_usb2_port
*port
;
852 unsigned int index
= lane
->index
;
853 struct device
*dev
= padctl
->dev
;
856 port
= tegra_xusb_find_usb2_port(padctl
, index
);
858 dev_err(dev
, "no port found for USB2 lane %u\n", index
);
862 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_PAD_MUX
);
863 value
&= ~(USB2_PORT_MASK
<< USB2_PORT_SHIFT(index
));
864 value
|= (PORT_XUSB
<< USB2_PORT_SHIFT(index
));
865 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_PAD_MUX
);
867 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_PORT_CAP
);
868 value
&= ~(PORT_CAP_MASK
<< PORTX_CAP_SHIFT(index
));
870 if (port
->mode
== USB_DR_MODE_UNKNOWN
)
871 value
|= (PORT_CAP_DISABLED
<< PORTX_CAP_SHIFT(index
));
872 else if (port
->mode
== USB_DR_MODE_PERIPHERAL
)
873 value
|= (PORT_CAP_DEVICE
<< PORTX_CAP_SHIFT(index
));
874 else if (port
->mode
== USB_DR_MODE_HOST
)
875 value
|= (PORT_CAP_HOST
<< PORTX_CAP_SHIFT(index
));
876 else if (port
->mode
== USB_DR_MODE_OTG
)
877 value
|= (PORT_CAP_OTG
<< PORTX_CAP_SHIFT(index
));
879 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_PORT_CAP
);
881 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index
));
882 value
&= ~USB2_OTG_PD_ZI
;
884 value
&= ~HS_CURR_LEVEL(~0);
886 if (usb2
->hs_curr_level_offset
) {
887 int hs_current_level
;
889 hs_current_level
= (int)priv
->calib
.hs_curr_level
[index
] +
890 usb2
->hs_curr_level_offset
;
892 if (hs_current_level
< 0)
893 hs_current_level
= 0;
894 if (hs_current_level
> 0x3f)
895 hs_current_level
= 0x3f;
897 value
|= HS_CURR_LEVEL(hs_current_level
);
899 value
|= HS_CURR_LEVEL(priv
->calib
.hs_curr_level
[index
]);
902 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index
));
904 value
= padctl_readl(padctl
, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index
));
905 value
&= ~TERM_RANGE_ADJ(~0);
906 value
|= TERM_RANGE_ADJ(priv
->calib
.hs_term_range_adj
);
907 value
&= ~RPD_CTRL(~0);
908 value
|= RPD_CTRL(priv
->calib
.rpd_ctrl
);
909 padctl_writel(padctl
, value
, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index
));
911 tegra186_utmi_pad_power_on(phy
);
916 static int tegra186_utmi_phy_power_off(struct phy
*phy
)
918 tegra186_utmi_pad_power_down(phy
);
923 static int tegra186_utmi_phy_init(struct phy
*phy
)
925 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
926 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
927 struct tegra_xusb_usb2_port
*port
;
928 unsigned int index
= lane
->index
;
929 struct device
*dev
= padctl
->dev
;
932 port
= tegra_xusb_find_usb2_port(padctl
, index
);
934 dev_err(dev
, "no port found for USB2 lane %u\n", index
);
938 if (port
->supply
&& port
->mode
== USB_DR_MODE_HOST
) {
939 err
= regulator_enable(port
->supply
);
941 dev_err(dev
, "failed to enable port %u VBUS: %d\n",
950 static int tegra186_utmi_phy_exit(struct phy
*phy
)
952 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
953 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
954 struct tegra_xusb_usb2_port
*port
;
955 unsigned int index
= lane
->index
;
956 struct device
*dev
= padctl
->dev
;
959 port
= tegra_xusb_find_usb2_port(padctl
, index
);
961 dev_err(dev
, "no port found for USB2 lane %u\n", index
);
965 if (port
->supply
&& port
->mode
== USB_DR_MODE_HOST
) {
966 err
= regulator_disable(port
->supply
);
968 dev_err(dev
, "failed to disable port %u VBUS: %d\n",
977 static const struct phy_ops utmi_phy_ops
= {
978 .init
= tegra186_utmi_phy_init
,
979 .exit
= tegra186_utmi_phy_exit
,
980 .power_on
= tegra186_utmi_phy_power_on
,
981 .power_off
= tegra186_utmi_phy_power_off
,
982 .set_mode
= tegra186_utmi_phy_set_mode
,
983 .owner
= THIS_MODULE
,
986 static struct tegra_xusb_pad
*
987 tegra186_usb2_pad_probe(struct tegra_xusb_padctl
*padctl
,
988 const struct tegra_xusb_pad_soc
*soc
,
989 struct device_node
*np
)
991 struct tegra186_xusb_padctl
*priv
= to_tegra186_xusb_padctl(padctl
);
992 struct tegra_xusb_usb2_pad
*usb2
;
993 struct tegra_xusb_pad
*pad
;
996 usb2
= kzalloc(sizeof(*usb2
), GFP_KERNEL
);
998 return ERR_PTR(-ENOMEM
);
1001 pad
->ops
= &tegra186_usb2_lane_ops
;
1004 err
= tegra_xusb_pad_init(pad
, padctl
, np
);
1010 priv
->usb2_trk_clk
= devm_clk_get(&pad
->dev
, "trk");
1011 if (IS_ERR(priv
->usb2_trk_clk
)) {
1012 err
= PTR_ERR(priv
->usb2_trk_clk
);
1013 dev_dbg(&pad
->dev
, "failed to get usb2 trk clock: %d\n", err
);
1017 err
= tegra_xusb_pad_register(pad
, &utmi_phy_ops
);
1021 dev_set_drvdata(&pad
->dev
, pad
);
1026 device_unregister(&pad
->dev
);
1028 return ERR_PTR(err
);
1031 static void tegra186_usb2_pad_remove(struct tegra_xusb_pad
*pad
)
1033 struct tegra_xusb_usb2_pad
*usb2
= to_usb2_pad(pad
);
1038 static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops
= {
1039 .probe
= tegra186_usb2_pad_probe
,
1040 .remove
= tegra186_usb2_pad_remove
,
1043 static const char * const tegra186_usb2_functions
[] = {
1047 static int tegra186_usb2_port_enable(struct tegra_xusb_port
*port
)
1052 static void tegra186_usb2_port_disable(struct tegra_xusb_port
*port
)
1056 static struct tegra_xusb_lane
*
1057 tegra186_usb2_port_map(struct tegra_xusb_port
*port
)
1059 return tegra_xusb_find_lane(port
->padctl
, "usb2", port
->index
);
1062 static const struct tegra_xusb_port_ops tegra186_usb2_port_ops
= {
1063 .release
= tegra_xusb_usb2_port_release
,
1064 .remove
= tegra_xusb_usb2_port_remove
,
1065 .enable
= tegra186_usb2_port_enable
,
1066 .disable
= tegra186_usb2_port_disable
,
1067 .map
= tegra186_usb2_port_map
,
1070 /* SuperSpeed PHY support */
1071 static struct tegra_xusb_lane
*
1072 tegra186_usb3_lane_probe(struct tegra_xusb_pad
*pad
, struct device_node
*np
,
1075 struct tegra_xusb_usb3_lane
*usb3
;
1078 usb3
= kzalloc(sizeof(*usb3
), GFP_KERNEL
);
1080 return ERR_PTR(-ENOMEM
);
1082 INIT_LIST_HEAD(&usb3
->base
.list
);
1083 usb3
->base
.soc
= &pad
->soc
->lanes
[index
];
1084 usb3
->base
.index
= index
;
1085 usb3
->base
.pad
= pad
;
1088 err
= tegra_xusb_lane_parse_dt(&usb3
->base
, np
);
1091 return ERR_PTR(err
);
1097 static void tegra186_usb3_lane_remove(struct tegra_xusb_lane
*lane
)
1099 struct tegra_xusb_usb3_lane
*usb3
= to_usb3_lane(lane
);
1104 static int tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane
*lane
,
1105 enum usb_device_speed speed
)
1107 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1108 unsigned int index
= lane
->index
;
1111 mutex_lock(&padctl
->lock
);
1113 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1114 value
|= SSPX_ELPG_CLAMP_EN_EARLY(index
);
1115 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1117 usleep_range(100, 200);
1119 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1120 value
|= SSPX_ELPG_CLAMP_EN(index
);
1121 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1123 usleep_range(250, 350);
1125 mutex_unlock(&padctl
->lock
);
1130 static int tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane
*lane
)
1132 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1133 unsigned int index
= lane
->index
;
1136 mutex_lock(&padctl
->lock
);
1138 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1139 value
&= ~SSPX_ELPG_CLAMP_EN_EARLY(index
);
1140 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1142 usleep_range(100, 200);
1144 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1145 value
&= ~SSPX_ELPG_CLAMP_EN(index
);
1146 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1148 mutex_unlock(&padctl
->lock
);
1153 static int tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane
*lane
)
1155 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1156 unsigned int index
= lane
->index
;
1159 mutex_lock(&padctl
->lock
);
1161 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM
);
1162 value
&= ~ALL_WAKE_EVENTS
;
1163 value
|= SS_PORT_WAKEUP_EVENT(index
);
1164 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM
);
1166 usleep_range(10, 20);
1168 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM
);
1169 value
&= ~ALL_WAKE_EVENTS
;
1170 value
|= SS_PORT_WAKE_INTERRUPT_ENABLE(index
);
1171 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM
);
1173 mutex_unlock(&padctl
->lock
);
1178 static int tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane
*lane
)
1180 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1181 unsigned int index
= lane
->index
;
1184 mutex_lock(&padctl
->lock
);
1186 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM
);
1187 value
&= ~ALL_WAKE_EVENTS
;
1188 value
&= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index
);
1189 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM
);
1191 usleep_range(10, 20);
1193 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM
);
1194 value
&= ~ALL_WAKE_EVENTS
;
1195 value
|= SS_PORT_WAKEUP_EVENT(index
);
1196 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM
);
1198 mutex_unlock(&padctl
->lock
);
1203 static bool tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane
*lane
)
1205 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1206 unsigned int index
= lane
->index
;
1209 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM
);
1210 if ((value
& SS_PORT_WAKE_INTERRUPT_ENABLE(index
)) && (value
& SS_PORT_WAKEUP_EVENT(index
)))
1216 static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops
= {
1217 .probe
= tegra186_usb3_lane_probe
,
1218 .remove
= tegra186_usb3_lane_remove
,
1219 .enable_phy_sleepwalk
= tegra186_usb3_enable_phy_sleepwalk
,
1220 .disable_phy_sleepwalk
= tegra186_usb3_disable_phy_sleepwalk
,
1221 .enable_phy_wake
= tegra186_usb3_enable_phy_wake
,
1222 .disable_phy_wake
= tegra186_usb3_disable_phy_wake
,
1223 .remote_wake_detected
= tegra186_usb3_phy_remote_wake_detected
,
1226 static int tegra186_usb3_port_enable(struct tegra_xusb_port
*port
)
1231 static void tegra186_usb3_port_disable(struct tegra_xusb_port
*port
)
1235 static struct tegra_xusb_lane
*
1236 tegra186_usb3_port_map(struct tegra_xusb_port
*port
)
1238 return tegra_xusb_find_lane(port
->padctl
, "usb3", port
->index
);
1241 static const struct tegra_xusb_port_ops tegra186_usb3_port_ops
= {
1242 .release
= tegra_xusb_usb3_port_release
,
1243 .enable
= tegra186_usb3_port_enable
,
1244 .disable
= tegra186_usb3_port_disable
,
1245 .map
= tegra186_usb3_port_map
,
1248 static int tegra186_usb3_phy_power_on(struct phy
*phy
)
1250 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1251 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1252 struct tegra_xusb_usb3_port
*port
;
1253 struct tegra_xusb_usb2_port
*usb2
;
1254 unsigned int index
= lane
->index
;
1255 struct device
*dev
= padctl
->dev
;
1258 port
= tegra_xusb_find_usb3_port(padctl
, index
);
1260 dev_err(dev
, "no port found for USB3 lane %u\n", index
);
1264 usb2
= tegra_xusb_find_usb2_port(padctl
, port
->port
);
1266 dev_err(dev
, "no companion port found for USB3 lane %u\n",
1271 mutex_lock(&padctl
->lock
);
1273 value
= padctl_readl(padctl
, XUSB_PADCTL_SS_PORT_CAP
);
1274 value
&= ~(PORT_CAP_MASK
<< PORTX_CAP_SHIFT(index
));
1276 if (usb2
->mode
== USB_DR_MODE_UNKNOWN
)
1277 value
|= (PORT_CAP_DISABLED
<< PORTX_CAP_SHIFT(index
));
1278 else if (usb2
->mode
== USB_DR_MODE_PERIPHERAL
)
1279 value
|= (PORT_CAP_DEVICE
<< PORTX_CAP_SHIFT(index
));
1280 else if (usb2
->mode
== USB_DR_MODE_HOST
)
1281 value
|= (PORT_CAP_HOST
<< PORTX_CAP_SHIFT(index
));
1282 else if (usb2
->mode
== USB_DR_MODE_OTG
)
1283 value
|= (PORT_CAP_OTG
<< PORTX_CAP_SHIFT(index
));
1285 padctl_writel(padctl
, value
, XUSB_PADCTL_SS_PORT_CAP
);
1287 if (padctl
->soc
->supports_gen2
&& port
->disable_gen2
) {
1288 value
= padctl_readl(padctl
, XUSB_PADCTL_SS_PORT_CFG
);
1289 value
&= ~(PORTX_SPEED_SUPPORT_MASK
<<
1290 PORTX_SPEED_SUPPORT_SHIFT(index
));
1291 value
|= (PORT_SPEED_SUPPORT_GEN1
<<
1292 PORTX_SPEED_SUPPORT_SHIFT(index
));
1293 padctl_writel(padctl
, value
, XUSB_PADCTL_SS_PORT_CFG
);
1296 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1297 value
&= ~SSPX_ELPG_VCORE_DOWN(index
);
1298 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1300 usleep_range(100, 200);
1302 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1303 value
&= ~SSPX_ELPG_CLAMP_EN_EARLY(index
);
1304 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1306 usleep_range(100, 200);
1308 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1309 value
&= ~SSPX_ELPG_CLAMP_EN(index
);
1310 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1312 mutex_unlock(&padctl
->lock
);
1317 static int tegra186_usb3_phy_power_off(struct phy
*phy
)
1319 struct tegra_xusb_lane
*lane
= phy_get_drvdata(phy
);
1320 struct tegra_xusb_padctl
*padctl
= lane
->pad
->padctl
;
1321 struct tegra_xusb_usb3_port
*port
;
1322 unsigned int index
= lane
->index
;
1323 struct device
*dev
= padctl
->dev
;
1326 port
= tegra_xusb_find_usb3_port(padctl
, index
);
1328 dev_err(dev
, "no port found for USB3 lane %u\n", index
);
1332 mutex_lock(&padctl
->lock
);
1334 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1335 value
|= SSPX_ELPG_CLAMP_EN_EARLY(index
);
1336 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1338 usleep_range(100, 200);
1340 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1341 value
|= SSPX_ELPG_CLAMP_EN(index
);
1342 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1344 usleep_range(250, 350);
1346 value
= padctl_readl(padctl
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1347 value
|= SSPX_ELPG_VCORE_DOWN(index
);
1348 padctl_writel(padctl
, value
, XUSB_PADCTL_ELPG_PROGRAM_1
);
1350 mutex_unlock(&padctl
->lock
);
1355 static int tegra186_usb3_phy_init(struct phy
*phy
)
1360 static int tegra186_usb3_phy_exit(struct phy
*phy
)
1365 static const struct phy_ops usb3_phy_ops
= {
1366 .init
= tegra186_usb3_phy_init
,
1367 .exit
= tegra186_usb3_phy_exit
,
1368 .power_on
= tegra186_usb3_phy_power_on
,
1369 .power_off
= tegra186_usb3_phy_power_off
,
1370 .owner
= THIS_MODULE
,
1373 static struct tegra_xusb_pad
*
1374 tegra186_usb3_pad_probe(struct tegra_xusb_padctl
*padctl
,
1375 const struct tegra_xusb_pad_soc
*soc
,
1376 struct device_node
*np
)
1378 struct tegra_xusb_usb3_pad
*usb3
;
1379 struct tegra_xusb_pad
*pad
;
1382 usb3
= kzalloc(sizeof(*usb3
), GFP_KERNEL
);
1384 return ERR_PTR(-ENOMEM
);
1387 pad
->ops
= &tegra186_usb3_lane_ops
;
1390 err
= tegra_xusb_pad_init(pad
, padctl
, np
);
1396 err
= tegra_xusb_pad_register(pad
, &usb3_phy_ops
);
1400 dev_set_drvdata(&pad
->dev
, pad
);
1405 device_unregister(&pad
->dev
);
1407 return ERR_PTR(err
);
1410 static void tegra186_usb3_pad_remove(struct tegra_xusb_pad
*pad
)
1412 struct tegra_xusb_usb2_pad
*usb2
= to_usb2_pad(pad
);
1417 static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops
= {
1418 .probe
= tegra186_usb3_pad_probe
,
1419 .remove
= tegra186_usb3_pad_remove
,
1422 static const char * const tegra186_usb3_functions
[] = {
1427 tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl
*padctl
)
1429 struct device
*dev
= padctl
->base
.dev
;
1430 unsigned int i
, count
;
1434 count
= padctl
->base
.soc
->ports
.usb2
.count
;
1436 level
= devm_kcalloc(dev
, count
, sizeof(u32
), GFP_KERNEL
);
1440 err
= tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0
, &value
);
1442 return dev_err_probe(dev
, err
,
1443 "failed to read calibration fuse\n");
1445 dev_dbg(dev
, "FUSE_USB_CALIB_0 %#x\n", value
);
1447 for (i
= 0; i
< count
; i
++)
1448 level
[i
] = (value
>> HS_CURR_LEVEL_PADX_SHIFT(i
)) &
1449 HS_CURR_LEVEL_PAD_MASK
;
1451 padctl
->calib
.hs_curr_level
= level
;
1453 padctl
->calib
.hs_squelch
= (value
>> HS_SQUELCH_SHIFT
) &
1455 padctl
->calib
.hs_term_range_adj
= (value
>> HS_TERM_RANGE_ADJ_SHIFT
) &
1456 HS_TERM_RANGE_ADJ_MASK
;
1458 err
= tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0
, &value
);
1460 dev_err(dev
, "failed to read calibration fuse: %d\n", err
);
1464 dev_dbg(dev
, "FUSE_USB_CALIB_EXT_0 %#x\n", value
);
1466 padctl
->calib
.rpd_ctrl
= (value
>> RPD_CTRL_SHIFT
) & RPD_CTRL_MASK
;
1471 static struct tegra_xusb_padctl
*
1472 tegra186_xusb_padctl_probe(struct device
*dev
,
1473 const struct tegra_xusb_padctl_soc
*soc
)
1475 struct platform_device
*pdev
= to_platform_device(dev
);
1476 struct tegra186_xusb_padctl
*priv
;
1477 struct resource
*res
;
1480 priv
= devm_kzalloc(dev
, sizeof(*priv
), GFP_KERNEL
);
1482 return ERR_PTR(-ENOMEM
);
1484 priv
->base
.dev
= dev
;
1485 priv
->base
.soc
= soc
;
1487 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "ao");
1488 priv
->ao_regs
= devm_ioremap_resource(dev
, res
);
1489 if (IS_ERR(priv
->ao_regs
))
1490 return ERR_CAST(priv
->ao_regs
);
1492 err
= tegra186_xusb_read_fuse_calibration(priv
);
1494 return ERR_PTR(err
);
1499 static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl
*padctl
)
1501 struct tegra186_xusb_padctl
*priv
= to_tegra186_xusb_padctl(padctl
);
1503 priv
->context
.vbus_id
= padctl_readl(padctl
, USB2_VBUS_ID
);
1504 priv
->context
.usb2_pad_mux
= padctl_readl(padctl
, XUSB_PADCTL_USB2_PAD_MUX
);
1505 priv
->context
.usb2_port_cap
= padctl_readl(padctl
, XUSB_PADCTL_USB2_PORT_CAP
);
1506 priv
->context
.ss_port_cap
= padctl_readl(padctl
, XUSB_PADCTL_SS_PORT_CAP
);
1509 static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl
*padctl
)
1511 struct tegra186_xusb_padctl
*priv
= to_tegra186_xusb_padctl(padctl
);
1513 padctl_writel(padctl
, priv
->context
.usb2_pad_mux
, XUSB_PADCTL_USB2_PAD_MUX
);
1514 padctl_writel(padctl
, priv
->context
.usb2_port_cap
, XUSB_PADCTL_USB2_PORT_CAP
);
1515 padctl_writel(padctl
, priv
->context
.ss_port_cap
, XUSB_PADCTL_SS_PORT_CAP
);
1516 padctl_writel(padctl
, priv
->context
.vbus_id
, USB2_VBUS_ID
);
1519 static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl
*padctl
)
1521 tegra186_xusb_padctl_save(padctl
);
1526 static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl
*padctl
)
1528 tegra186_xusb_padctl_restore(padctl
);
1533 static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl
*padctl
)
1537 static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops
= {
1538 .probe
= tegra186_xusb_padctl_probe
,
1539 .remove
= tegra186_xusb_padctl_remove
,
1540 .suspend_noirq
= tegra186_xusb_padctl_suspend_noirq
,
1541 .resume_noirq
= tegra186_xusb_padctl_resume_noirq
,
1542 .vbus_override
= tegra186_xusb_padctl_vbus_override
,
1543 .utmi_pad_power_on
= tegra186_utmi_pad_power_on
,
1544 .utmi_pad_power_down
= tegra186_utmi_pad_power_down
,
1547 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
1548 static const char * const tegra186_xusb_padctl_supply_names
[] = {
1555 static const struct tegra_xusb_lane_soc tegra186_usb2_lanes
[] = {
1556 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2
),
1557 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2
),
1558 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2
),
1561 static const struct tegra_xusb_pad_soc tegra186_usb2_pad
= {
1563 .num_lanes
= ARRAY_SIZE(tegra186_usb2_lanes
),
1564 .lanes
= tegra186_usb2_lanes
,
1565 .ops
= &tegra186_usb2_pad_ops
,
1568 static const struct tegra_xusb_lane_soc tegra186_usb3_lanes
[] = {
1569 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3
),
1570 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3
),
1571 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3
),
1574 static const struct tegra_xusb_pad_soc tegra186_usb3_pad
= {
1576 .num_lanes
= ARRAY_SIZE(tegra186_usb3_lanes
),
1577 .lanes
= tegra186_usb3_lanes
,
1578 .ops
= &tegra186_usb3_pad_ops
,
1581 static const struct tegra_xusb_pad_soc
* const tegra186_pads
[] = {
1584 #if 0 /* TODO implement */
1589 const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc
= {
1590 .num_pads
= ARRAY_SIZE(tegra186_pads
),
1591 .pads
= tegra186_pads
,
1594 .ops
= &tegra186_usb2_port_ops
,
1597 #if 0 /* TODO implement */
1599 .ops
= &tegra186_hsic_port_ops
,
1604 .ops
= &tegra186_usb3_port_ops
,
1608 .ops
= &tegra186_xusb_padctl_ops
,
1609 .supply_names
= tegra186_xusb_padctl_supply_names
,
1610 .num_supplies
= ARRAY_SIZE(tegra186_xusb_padctl_supply_names
),
1612 EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc
);
1615 #if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
1616 IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
1617 static const char * const tegra194_xusb_padctl_supply_names
[] = {
1622 static const struct tegra_xusb_lane_soc tegra194_usb2_lanes
[] = {
1623 TEGRA186_LANE("usb2-0", 0, 0, 0, usb2
),
1624 TEGRA186_LANE("usb2-1", 0, 0, 0, usb2
),
1625 TEGRA186_LANE("usb2-2", 0, 0, 0, usb2
),
1626 TEGRA186_LANE("usb2-3", 0, 0, 0, usb2
),
1629 static const struct tegra_xusb_pad_soc tegra194_usb2_pad
= {
1631 .num_lanes
= ARRAY_SIZE(tegra194_usb2_lanes
),
1632 .lanes
= tegra194_usb2_lanes
,
1633 .ops
= &tegra186_usb2_pad_ops
,
1636 static const struct tegra_xusb_lane_soc tegra194_usb3_lanes
[] = {
1637 TEGRA186_LANE("usb3-0", 0, 0, 0, usb3
),
1638 TEGRA186_LANE("usb3-1", 0, 0, 0, usb3
),
1639 TEGRA186_LANE("usb3-2", 0, 0, 0, usb3
),
1640 TEGRA186_LANE("usb3-3", 0, 0, 0, usb3
),
1643 static const struct tegra_xusb_pad_soc tegra194_usb3_pad
= {
1645 .num_lanes
= ARRAY_SIZE(tegra194_usb3_lanes
),
1646 .lanes
= tegra194_usb3_lanes
,
1647 .ops
= &tegra186_usb3_pad_ops
,
1650 static const struct tegra_xusb_pad_soc
* const tegra194_pads
[] = {
1655 const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc
= {
1656 .num_pads
= ARRAY_SIZE(tegra194_pads
),
1657 .pads
= tegra194_pads
,
1660 .ops
= &tegra186_usb2_port_ops
,
1664 .ops
= &tegra186_usb3_port_ops
,
1668 .ops
= &tegra186_xusb_padctl_ops
,
1669 .supply_names
= tegra194_xusb_padctl_supply_names
,
1670 .num_supplies
= ARRAY_SIZE(tegra194_xusb_padctl_supply_names
),
1671 .supports_gen2
= true,
1672 .poll_trk_completed
= true,
1674 EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc
);
1676 const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc
= {
1677 .num_pads
= ARRAY_SIZE(tegra194_pads
),
1678 .pads
= tegra194_pads
,
1681 .ops
= &tegra186_usb2_port_ops
,
1685 .ops
= &tegra186_usb3_port_ops
,
1689 .ops
= &tegra186_xusb_padctl_ops
,
1690 .supply_names
= tegra194_xusb_padctl_supply_names
,
1691 .num_supplies
= ARRAY_SIZE(tegra194_xusb_padctl_supply_names
),
1692 .supports_gen2
= true,
1693 .poll_trk_completed
= true,
1694 .trk_hw_mode
= true,
1695 .supports_lp_cfg_en
= true,
1697 EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc
);
1700 MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1701 MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1702 MODULE_LICENSE("GPL v2");