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accel/ivpu: Move recovery work to system_unbound_wq
[drm/drm-misc.git] / drivers / pinctrl / mediatek / pinctrl-paris.c
blob87e958d827bf939aa6006794287698be4936f25e
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * MediaTek Pinctrl Paris Driver, which implement the vendor per-pin
4 * bindings for MediaTek SoC.
5 *
6 * Copyright (C) 2018 MediaTek Inc.
7 * Author: Sean Wang <sean.wang@mediatek.com>
8 * Zhiyong Tao <zhiyong.tao@mediatek.com>
9 * Hongzhou.Yang <hongzhou.yang@mediatek.com>
10 */
11
12 #include <linux/gpio/driver.h>
13 #include <linux/module.h>
14 #include <linux/seq_file.h>
15
16 #include <linux/pinctrl/consumer.h>
17
18 #include <dt-bindings/pinctrl/mt65xx.h>
19
20 #include "pinctrl-paris.h"
21
22 #define PINCTRL_PINCTRL_DEV KBUILD_MODNAME
23
24 /* Custom pinconf parameters */
25 #define MTK_PIN_CONFIG_TDSEL (PIN_CONFIG_END + 1)
26 #define MTK_PIN_CONFIG_RDSEL (PIN_CONFIG_END + 2)
27 #define MTK_PIN_CONFIG_PU_ADV (PIN_CONFIG_END + 3)
28 #define MTK_PIN_CONFIG_PD_ADV (PIN_CONFIG_END + 4)
29 #define MTK_PIN_CONFIG_DRV_ADV (PIN_CONFIG_END + 5)
30
31 static const struct pinconf_generic_params mtk_custom_bindings[] = {
32 {"mediatek,tdsel", MTK_PIN_CONFIG_TDSEL, 0},
33 {"mediatek,rdsel", MTK_PIN_CONFIG_RDSEL, 0},
34 {"mediatek,pull-up-adv", MTK_PIN_CONFIG_PU_ADV, 1},
35 {"mediatek,pull-down-adv", MTK_PIN_CONFIG_PD_ADV, 1},
36 {"mediatek,drive-strength-adv", MTK_PIN_CONFIG_DRV_ADV, 2},
37 };
38
39 #ifdef CONFIG_DEBUG_FS
40 static const struct pin_config_item mtk_conf_items[] = {
41 PCONFDUMP(MTK_PIN_CONFIG_TDSEL, "tdsel", NULL, true),
42 PCONFDUMP(MTK_PIN_CONFIG_RDSEL, "rdsel", NULL, true),
43 PCONFDUMP(MTK_PIN_CONFIG_PU_ADV, "pu-adv", NULL, true),
44 PCONFDUMP(MTK_PIN_CONFIG_PD_ADV, "pd-adv", NULL, true),
45 PCONFDUMP(MTK_PIN_CONFIG_DRV_ADV, "drive-strength-adv", NULL, true),
46 };
47 #endif
48
49 static const char * const mtk_gpio_functions[] = {
50 "func0", "func1", "func2", "func3",
51 "func4", "func5", "func6", "func7",
52 "func8", "func9", "func10", "func11",
53 "func12", "func13", "func14", "func15",
54 };
55
56 /*
57 * This section supports converting to/from custom MTK_PIN_CONFIG_DRV_ADV
58 * and standard PIN_CONFIG_DRIVE_STRENGTH_UA pin configs.
59 *
60 * The custom value encodes three hardware bits as follows:
61 *
62 * | Bits |
63 * | 2 (E1) | 1 (E0) | 0 (EN) | drive strength (uA)
64 * ------------------------------------------------
65 * | x | x | 0 | disabled, use standard drive strength
66 * -------------------------------------
67 * | 0 | 0 | 1 | 125 uA
68 * | 0 | 1 | 1 | 250 uA
69 * | 1 | 0 | 1 | 500 uA
70 * | 1 | 1 | 1 | 1000 uA
71 */
72 static const int mtk_drv_adv_uA[] = { 125, 250, 500, 1000 };
73
74 static int mtk_drv_adv_to_uA(int val)
75 {
76 /* This should never happen. */
77 if (WARN_ON_ONCE(val < 0 || val > 7))
78 return -EINVAL;
79
80 /* Bit 0 simply enables this hardware part */
81 if (!(val & BIT(0)))
82 return -EINVAL;
83
84 return mtk_drv_adv_uA[(val >> 1)];
85 }
86
87 static int mtk_drv_uA_to_adv(int val)
88 {
89 switch (val) {
90 case 125:
91 return 0x1;
92 case 250:
93 return 0x3;
94 case 500:
95 return 0x5;
96 case 1000:
97 return 0x7;
98 }
99
100 return -EINVAL;
101 }
102
103 static int mtk_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
104 struct pinctrl_gpio_range *range,
105 unsigned int pin)
106 {
107 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
108 const struct mtk_pin_desc *desc;
109
110 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
111
112 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE,
113 hw->soc->gpio_m);
114 }
115
116 static int mtk_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
117 struct pinctrl_gpio_range *range,
118 unsigned int pin, bool input)
119 {
120 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
121 const struct mtk_pin_desc *desc;
122
123 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
124
125 /* hardware would take 0 as input direction */
126 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !input);
127 }
128
129 static int mtk_pinconf_get(struct pinctrl_dev *pctldev,
130 unsigned int pin, unsigned long *config)
131 {
132 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
133 u32 param = pinconf_to_config_param(*config);
134 int pullup, reg, err = -ENOTSUPP, ret = 1;
135 const struct mtk_pin_desc *desc;
136
137 if (pin >= hw->soc->npins)
138 return -EINVAL;
139
140 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
141
142 switch (param) {
143 case PIN_CONFIG_BIAS_DISABLE:
144 case PIN_CONFIG_BIAS_PULL_UP:
145 case PIN_CONFIG_BIAS_PULL_DOWN:
146 if (!hw->soc->bias_get_combo)
147 break;
148 err = hw->soc->bias_get_combo(hw, desc, &pullup, &ret);
149 if (err)
150 break;
151 if (ret == MTK_PUPD_SET_R1R0_00)
152 ret = MTK_DISABLE;
153 if (param == PIN_CONFIG_BIAS_DISABLE) {
154 if (ret != MTK_DISABLE)
155 err = -EINVAL;
156 } else if (param == PIN_CONFIG_BIAS_PULL_UP) {
157 if (!pullup || ret == MTK_DISABLE)
158 err = -EINVAL;
159 } else if (param == PIN_CONFIG_BIAS_PULL_DOWN) {
160 if (pullup || ret == MTK_DISABLE)
161 err = -EINVAL;
162 }
163 break;
164 case PIN_CONFIG_SLEW_RATE:
165 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SR, &ret);
166 break;
167 case PIN_CONFIG_INPUT_ENABLE:
168 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_IES, &ret);
169 if (!ret)
170 err = -EINVAL;
171 break;
172 case PIN_CONFIG_OUTPUT:
173 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
174 if (err)
175 break;
176
177 if (!ret) {
178 err = -EINVAL;
179 break;
180 }
181
182 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DO, &ret);
183 break;
184 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
185 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &ret);
186 if (err)
187 break;
188 /* return error when in output mode
189 * because schmitt trigger only work in input mode
190 */
191 if (ret) {
192 err = -EINVAL;
193 break;
194 }
195
196 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_SMT, &ret);
197 if (!ret)
198 err = -EINVAL;
199 break;
200 case PIN_CONFIG_DRIVE_STRENGTH:
201 if (!hw->soc->drive_get)
202 break;
203
204 if (hw->soc->adv_drive_get) {
205 err = hw->soc->adv_drive_get(hw, desc, &ret);
206 if (!err) {
207 err = mtk_drv_adv_to_uA(ret);
208 if (err > 0) {
209 /* PIN_CONFIG_DRIVE_STRENGTH_UA used */
210 err = -EINVAL;
211 break;
212 }
213 }
214 }
215
216 err = hw->soc->drive_get(hw, desc, &ret);
217 break;
218 case PIN_CONFIG_DRIVE_STRENGTH_UA:
219 if (!hw->soc->adv_drive_get)
220 break;
221
222 err = hw->soc->adv_drive_get(hw, desc, &ret);
223 if (err)
224 break;
225 err = mtk_drv_adv_to_uA(ret);
226 if (err < 0)
227 break;
228
229 ret = err;
230 err = 0;
231 break;
232 case MTK_PIN_CONFIG_TDSEL:
233 case MTK_PIN_CONFIG_RDSEL:
234 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
235 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
236 err = mtk_hw_get_value(hw, desc, reg, &ret);
237 break;
238 case MTK_PIN_CONFIG_PU_ADV:
239 case MTK_PIN_CONFIG_PD_ADV:
240 if (!hw->soc->adv_pull_get)
241 break;
242 pullup = param == MTK_PIN_CONFIG_PU_ADV;
243 err = hw->soc->adv_pull_get(hw, desc, pullup, &ret);
244 break;
245 case MTK_PIN_CONFIG_DRV_ADV:
246 if (!hw->soc->adv_drive_get)
247 break;
248 err = hw->soc->adv_drive_get(hw, desc, &ret);
249 break;
250 }
251
252 if (!err)
253 *config = pinconf_to_config_packed(param, ret);
254
255 return err;
256 }
257
258 static int mtk_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
259 enum pin_config_param param, u32 arg)
260 {
261 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
262 const struct mtk_pin_desc *desc;
263 int err = -ENOTSUPP;
264 u32 reg;
265
266 if (pin >= hw->soc->npins)
267 return -EINVAL;
268
269 desc = (const struct mtk_pin_desc *)&hw->soc->pins[pin];
270
271 switch ((u32)param) {
272 case PIN_CONFIG_BIAS_DISABLE:
273 if (!hw->soc->bias_set_combo)
274 break;
275 err = hw->soc->bias_set_combo(hw, desc, 0, MTK_DISABLE);
276 break;
277 case PIN_CONFIG_BIAS_PULL_UP:
278 if (!hw->soc->bias_set_combo)
279 break;
280 err = hw->soc->bias_set_combo(hw, desc, 1, arg);
281 break;
282 case PIN_CONFIG_BIAS_PULL_DOWN:
283 if (!hw->soc->bias_set_combo)
284 break;
285 err = hw->soc->bias_set_combo(hw, desc, 0, arg);
286 break;
287 case PIN_CONFIG_INPUT_ENABLE:
288 /* regard all non-zero value as enable */
289 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_IES, !!arg);
290 break;
291 case PIN_CONFIG_SLEW_RATE:
292 /* regard all non-zero value as enable */
293 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SR, !!arg);
294 break;
295 case PIN_CONFIG_OUTPUT:
296 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO,
297 arg);
298 if (err)
299 break;
300
301 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR,
302 MTK_OUTPUT);
303 break;
304 case PIN_CONFIG_INPUT_SCHMITT:
305 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
306 /* arg = 1: Input mode & SMT enable ;
307 * arg = 0: Output mode & SMT disable
308 */
309 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DIR, !arg);
310 if (err)
311 break;
312
313 err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, !!arg);
314 break;
315 case PIN_CONFIG_DRIVE_STRENGTH:
316 if (!hw->soc->drive_set)
317 break;
318 err = hw->soc->drive_set(hw, desc, arg);
319 break;
320 case PIN_CONFIG_DRIVE_STRENGTH_UA:
321 if (!hw->soc->adv_drive_set)
322 break;
323
324 err = mtk_drv_uA_to_adv(arg);
325 if (err < 0)
326 break;
327 err = hw->soc->adv_drive_set(hw, desc, err);
328 break;
329 case MTK_PIN_CONFIG_TDSEL:
330 case MTK_PIN_CONFIG_RDSEL:
331 reg = (param == MTK_PIN_CONFIG_TDSEL) ?
332 PINCTRL_PIN_REG_TDSEL : PINCTRL_PIN_REG_RDSEL;
333 err = mtk_hw_set_value(hw, desc, reg, arg);
334 break;
335 case MTK_PIN_CONFIG_PU_ADV:
336 case MTK_PIN_CONFIG_PD_ADV:
337 if (!hw->soc->adv_pull_set)
338 break;
339 err = hw->soc->adv_pull_set(hw, desc,
340 (param == MTK_PIN_CONFIG_PU_ADV),
341 arg);
342 break;
343 case MTK_PIN_CONFIG_DRV_ADV:
344 if (!hw->soc->adv_drive_set)
345 break;
346 err = hw->soc->adv_drive_set(hw, desc, arg);
347 break;
348 }
349
350 return err;
351 }
352
353 static struct mtk_pinctrl_group *
354 mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *hw, u32 pin)
355 {
356 int i;
357
358 for (i = 0; i < hw->soc->ngrps; i++) {
359 struct mtk_pinctrl_group *grp = hw->groups + i;
360
361 if (grp->pin == pin)
362 return grp;
363 }
364
365 return NULL;
366 }
367
368 static const struct mtk_func_desc *
369 mtk_pctrl_find_function_by_pin(struct mtk_pinctrl *hw, u32 pin_num, u32 fnum)
370 {
371 const struct mtk_pin_desc *pin = hw->soc->pins + pin_num;
372 const struct mtk_func_desc *func = pin->funcs;
373
374 while (func && func->name) {
375 if (func->muxval == fnum)
376 return func;
377 func++;
378 }
379
380 return NULL;
381 }
382
383 static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *hw, u32 pin_num,
384 u32 fnum)
385 {
386 int i;
387
388 for (i = 0; i < hw->soc->npins; i++) {
389 const struct mtk_pin_desc *pin = hw->soc->pins + i;
390
391 if (pin->number == pin_num) {
392 const struct mtk_func_desc *func = pin->funcs;
393
394 while (func && func->name) {
395 if (func->muxval == fnum)
396 return true;
397 func++;
398 }
399
400 break;
401 }
402 }
403
404 return false;
405 }
406
407 static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
408 u32 pin, u32 fnum,
409 struct mtk_pinctrl_group *grp,
410 struct pinctrl_map **map,
411 unsigned *reserved_maps,
412 unsigned *num_maps)
413 {
414 bool ret;
415
416 if (*num_maps == *reserved_maps)
417 return -ENOSPC;
418
419 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
420 (*map)[*num_maps].data.mux.group = grp->name;
421
422 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
423 if (!ret) {
424 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
425 fnum, pin);
426 return -EINVAL;
427 }
428
429 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
430 (*num_maps)++;
431
432 return 0;
433 }
434
435 static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
436 struct device_node *node,
437 struct pinctrl_map **map,
438 unsigned *reserved_maps,
439 unsigned *num_maps)
440 {
441 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
442 int num_pins, num_funcs, maps_per_pin, i, err;
443 struct mtk_pinctrl_group *grp;
444 unsigned int num_configs;
445 bool has_config = false;
446 unsigned long *configs;
447 u32 pinfunc, pin, func;
448 struct property *pins;
449 unsigned reserve = 0;
450
451 pins = of_find_property(node, "pinmux", NULL);
452 if (!pins) {
453 dev_err(hw->dev, "missing pins property in node %pOFn .\n",
454 node);
455 return -EINVAL;
456 }
457
458 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
459 &num_configs);
460 if (err)
461 return err;
462
463 if (num_configs)
464 has_config = true;
465
466 num_pins = pins->length / sizeof(u32);
467 num_funcs = num_pins;
468 maps_per_pin = 0;
469 if (num_funcs)
470 maps_per_pin++;
471 if (has_config && num_pins >= 1)
472 maps_per_pin++;
473
474 if (!num_pins || !maps_per_pin) {
475 err = -EINVAL;
476 goto exit;
477 }
478
479 reserve = num_pins * maps_per_pin;
480
481 err = pinctrl_utils_reserve_map(pctldev, map, reserved_maps, num_maps,
482 reserve);
483 if (err < 0)
484 goto exit;
485
486 for (i = 0; i < num_pins; i++) {
487 err = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
488 if (err)
489 goto exit;
490
491 pin = MTK_GET_PIN_NO(pinfunc);
492 func = MTK_GET_PIN_FUNC(pinfunc);
493
494 if (pin >= hw->soc->npins ||
495 func >= ARRAY_SIZE(mtk_gpio_functions)) {
496 dev_err(hw->dev, "invalid pins value.\n");
497 err = -EINVAL;
498 goto exit;
499 }
500
501 grp = mtk_pctrl_find_group_by_pin(hw, pin);
502 if (!grp) {
503 dev_err(hw->dev, "unable to match pin %d to group\n",
504 pin);
505 err = -EINVAL;
506 goto exit;
507 }
508
509 err = mtk_pctrl_dt_node_to_map_func(hw, pin, func, grp, map,
510 reserved_maps, num_maps);
511 if (err < 0)
512 goto exit;
513
514 if (has_config) {
515 err = pinctrl_utils_add_map_configs(pctldev, map,
516 reserved_maps,
517 num_maps,
518 grp->name,
519 configs,
520 num_configs,
521 PIN_MAP_TYPE_CONFIGS_GROUP);
522 if (err < 0)
523 goto exit;
524 }
525 }
526
527 err = 0;
528
529 exit:
530 kfree(configs);
531 return err;
532 }
533
534 static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
535 struct device_node *np_config,
536 struct pinctrl_map **map,
537 unsigned *num_maps)
538 {
539 unsigned reserved_maps;
540 int ret;
541
542 *map = NULL;
543 *num_maps = 0;
544 reserved_maps = 0;
545
546 for_each_child_of_node_scoped(np_config, np) {
547 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
548 &reserved_maps,
549 num_maps);
550 if (ret < 0) {
551 pinctrl_utils_free_map(pctldev, *map, *num_maps);
552 return ret;
553 }
554 }
555
556 return 0;
557 }
558
559 static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
560 {
561 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
562
563 return hw->soc->ngrps;
564 }
565
566 static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
567 unsigned group)
568 {
569 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
570
571 return hw->groups[group].name;
572 }
573
574 static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
575 unsigned group, const unsigned **pins,
576 unsigned *num_pins)
577 {
578 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
579
580 *pins = (unsigned *)&hw->groups[group].pin;
581 *num_pins = 1;
582
583 return 0;
584 }
585
586 static int mtk_hw_get_value_wrap(struct mtk_pinctrl *hw, unsigned int gpio, int field)
587 {
588 const struct mtk_pin_desc *desc;
589 int value, err;
590
591 if (gpio >= hw->soc->npins)
592 return -EINVAL;
593
594 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
595
596 err = mtk_hw_get_value(hw, desc, field, &value);
597 if (err)
598 return err;
599
600 return value;
601 }
602
603 #define mtk_pctrl_get_pinmux(hw, gpio) \
604 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_MODE)
605
606 #define mtk_pctrl_get_direction(hw, gpio) \
607 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DIR)
608
609 #define mtk_pctrl_get_out(hw, gpio) \
610 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DO)
611
612 #define mtk_pctrl_get_in(hw, gpio) \
613 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DI)
614
615 #define mtk_pctrl_get_smt(hw, gpio) \
616 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_SMT)
617
618 #define mtk_pctrl_get_ies(hw, gpio) \
619 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_IES)
620
621 #define mtk_pctrl_get_driving(hw, gpio) \
622 mtk_hw_get_value_wrap(hw, gpio, PINCTRL_PIN_REG_DRV)
623
624 ssize_t mtk_pctrl_show_one_pin(struct mtk_pinctrl *hw,
625 unsigned int gpio, char *buf, unsigned int buf_len)
626 {
627 int pinmux, pullup = 0, pullen = 0, len = 0, r1 = -1, r0 = -1, rsel = -1;
628 const struct mtk_pin_desc *desc;
629 u32 try_all_type = 0;
630
631 if (gpio >= hw->soc->npins)
632 return -EINVAL;
633
634 if (mtk_is_virt_gpio(hw, gpio))
635 return -EINVAL;
636
637 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
638 pinmux = mtk_pctrl_get_pinmux(hw, gpio);
639 if (pinmux >= hw->soc->nfuncs)
640 pinmux -= hw->soc->nfuncs;
641
642 mtk_pinconf_bias_get_combo(hw, desc, &pullup, &pullen);
643
644 if (hw->soc->pull_type)
645 try_all_type = hw->soc->pull_type[desc->number];
646
647 if (hw->rsel_si_unit && (try_all_type & MTK_PULL_RSEL_TYPE)) {
648 rsel = pullen;
649 pullen = 1;
650 } else {
651 /* Case for: R1R0 */
652 if (pullen == MTK_PUPD_SET_R1R0_00) {
653 pullen = 0;
654 r1 = 0;
655 r0 = 0;
656 } else if (pullen == MTK_PUPD_SET_R1R0_01) {
657 pullen = 1;
658 r1 = 0;
659 r0 = 1;
660 } else if (pullen == MTK_PUPD_SET_R1R0_10) {
661 pullen = 1;
662 r1 = 1;
663 r0 = 0;
664 } else if (pullen == MTK_PUPD_SET_R1R0_11) {
665 pullen = 1;
666 r1 = 1;
667 r0 = 1;
668 }
669
670 /* Case for: RSEL */
671 if (pullen >= MTK_PULL_SET_RSEL_000 &&
672 pullen <= MTK_PULL_SET_RSEL_111) {
673 rsel = pullen - MTK_PULL_SET_RSEL_000;
674 pullen = 1;
675 }
676 }
677 len += scnprintf(buf + len, buf_len - len,
678 "%03d: %1d%1d%1d%1d%02d%1d%1d%1d%1d",
679 gpio,
680 pinmux,
681 mtk_pctrl_get_direction(hw, gpio),
682 mtk_pctrl_get_out(hw, gpio),
683 mtk_pctrl_get_in(hw, gpio),
684 mtk_pctrl_get_driving(hw, gpio),
685 mtk_pctrl_get_smt(hw, gpio),
686 mtk_pctrl_get_ies(hw, gpio),
687 pullen,
688 pullup);
689
690 if (r1 != -1)
691 len += scnprintf(buf + len, buf_len - len, " (%1d %1d)", r1, r0);
692 else if (rsel != -1)
693 len += scnprintf(buf + len, buf_len - len, " (%1d)", rsel);
694
695 return len;
696 }
697 EXPORT_SYMBOL_GPL(mtk_pctrl_show_one_pin);
698
699 #define PIN_DBG_BUF_SZ 96
700 static void mtk_pctrl_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
701 unsigned int gpio)
702 {
703 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
704 char buf[PIN_DBG_BUF_SZ] = { 0 };
705
706 (void)mtk_pctrl_show_one_pin(hw, gpio, buf, PIN_DBG_BUF_SZ);
707
708 seq_printf(s, "%s", buf);
709 }
710
711 static const struct pinctrl_ops mtk_pctlops = {
712 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
713 .dt_free_map = pinctrl_utils_free_map,
714 .get_groups_count = mtk_pctrl_get_groups_count,
715 .get_group_name = mtk_pctrl_get_group_name,
716 .get_group_pins = mtk_pctrl_get_group_pins,
717 .pin_dbg_show = mtk_pctrl_dbg_show,
718 };
719
720 static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
721 {
722 return ARRAY_SIZE(mtk_gpio_functions);
723 }
724
725 static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
726 unsigned selector)
727 {
728 return mtk_gpio_functions[selector];
729 }
730
731 static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
732 unsigned function,
733 const char * const **groups,
734 unsigned * const num_groups)
735 {
736 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
737
738 *groups = hw->grp_names;
739 *num_groups = hw->soc->ngrps;
740
741 return 0;
742 }
743
744 static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
745 unsigned function,
746 unsigned group)
747 {
748 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
749 struct mtk_pinctrl_group *grp = hw->groups + group;
750 const struct mtk_func_desc *desc_func;
751 const struct mtk_pin_desc *desc;
752 bool ret;
753
754 ret = mtk_pctrl_is_function_valid(hw, grp->pin, function);
755 if (!ret) {
756 dev_err(hw->dev, "invalid function %d on group %d .\n",
757 function, group);
758 return -EINVAL;
759 }
760
761 desc_func = mtk_pctrl_find_function_by_pin(hw, grp->pin, function);
762 if (!desc_func)
763 return -EINVAL;
764
765 desc = (const struct mtk_pin_desc *)&hw->soc->pins[grp->pin];
766 return mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_MODE, desc_func->muxval);
767 }
768
769 static const struct pinmux_ops mtk_pmxops = {
770 .get_functions_count = mtk_pmx_get_funcs_cnt,
771 .get_function_name = mtk_pmx_get_func_name,
772 .get_function_groups = mtk_pmx_get_func_groups,
773 .set_mux = mtk_pmx_set_mux,
774 .gpio_set_direction = mtk_pinmux_gpio_set_direction,
775 .gpio_request_enable = mtk_pinmux_gpio_request_enable,
776 };
777
778 static int mtk_pconf_group_get(struct pinctrl_dev *pctldev, unsigned group,
779 unsigned long *config)
780 {
781 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
782 struct mtk_pinctrl_group *grp = &hw->groups[group];
783
784 /* One pin per group only */
785 return mtk_pinconf_get(pctldev, grp->pin, config);
786 }
787
788 static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
789 unsigned long *configs, unsigned num_configs)
790 {
791 struct mtk_pinctrl *hw = pinctrl_dev_get_drvdata(pctldev);
792 struct mtk_pinctrl_group *grp = &hw->groups[group];
793 bool drive_strength_uA_found = false;
794 bool adv_drve_strength_found = false;
795 int i, ret;
796
797 for (i = 0; i < num_configs; i++) {
798 ret = mtk_pinconf_set(pctldev, grp->pin,
799 pinconf_to_config_param(configs[i]),
800 pinconf_to_config_argument(configs[i]));
801 if (ret < 0)
802 return ret;
803
804 if (pinconf_to_config_param(configs[i]) == PIN_CONFIG_DRIVE_STRENGTH_UA)
805 drive_strength_uA_found = true;
806 if (pinconf_to_config_param(configs[i]) == MTK_PIN_CONFIG_DRV_ADV)
807 adv_drve_strength_found = true;
808 }
809
810 /*
811 * Disable advanced drive strength mode if drive-strength-microamp
812 * is not set. However, mediatek,drive-strength-adv takes precedence
813 * as its value can explicitly request the mode be enabled or not.
814 */
815 if (hw->soc->adv_drive_set && !drive_strength_uA_found &&
816 !adv_drve_strength_found)
817 hw->soc->adv_drive_set(hw, &hw->soc->pins[grp->pin], 0);
818
819 return 0;
820 }
821
822 static const struct pinconf_ops mtk_confops = {
823 .pin_config_get = mtk_pinconf_get,
824 .pin_config_group_get = mtk_pconf_group_get,
825 .pin_config_group_set = mtk_pconf_group_set,
826 .is_generic = true,
827 };
828
829 static struct pinctrl_desc mtk_desc = {
830 .name = PINCTRL_PINCTRL_DEV,
831 .pctlops = &mtk_pctlops,
832 .pmxops = &mtk_pmxops,
833 .confops = &mtk_confops,
834 .owner = THIS_MODULE,
835 };
836
837 static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
838 {
839 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
840 const struct mtk_pin_desc *desc;
841 int value, err;
842
843 if (gpio >= hw->soc->npins)
844 return -EINVAL;
845
846 /*
847 * "Virtual" GPIOs are always and only used for interrupts
848 * Since they are only used for interrupts, they are always inputs
849 */
850 if (mtk_is_virt_gpio(hw, gpio))
851 return 1;
852
853 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
854
855 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DIR, &value);
856 if (err)
857 return err;
858
859 if (value)
860 return GPIO_LINE_DIRECTION_OUT;
861
862 return GPIO_LINE_DIRECTION_IN;
863 }
864
865 static int mtk_gpio_get(struct gpio_chip *chip, unsigned int gpio)
866 {
867 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
868 const struct mtk_pin_desc *desc;
869 int value, err;
870
871 if (gpio >= hw->soc->npins)
872 return -EINVAL;
873
874 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
875
876 err = mtk_hw_get_value(hw, desc, PINCTRL_PIN_REG_DI, &value);
877 if (err)
878 return err;
879
880 return !!value;
881 }
882
883 static void mtk_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
884 {
885 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
886 const struct mtk_pin_desc *desc;
887
888 if (gpio >= hw->soc->npins)
889 return;
890
891 desc = (const struct mtk_pin_desc *)&hw->soc->pins[gpio];
892
893 mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_DO, !!value);
894 }
895
896 static int mtk_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
897 {
898 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
899
900 if (gpio >= hw->soc->npins)
901 return -EINVAL;
902
903 return pinctrl_gpio_direction_input(chip, gpio);
904 }
905
906 static int mtk_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
907 int value)
908 {
909 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
910
911 if (gpio >= hw->soc->npins)
912 return -EINVAL;
913
914 mtk_gpio_set(chip, gpio, value);
915
916 return pinctrl_gpio_direction_output(chip, gpio);
917 }
918
919 static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
920 {
921 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
922 const struct mtk_pin_desc *desc;
923
924 if (!hw->eint)
925 return -ENOTSUPP;
926
927 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
928
929 if (desc->eint.eint_n == EINT_NA)
930 return -ENOTSUPP;
931
932 return mtk_eint_find_irq(hw->eint, desc->eint.eint_n);
933 }
934
935 static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
936 unsigned long config)
937 {
938 struct mtk_pinctrl *hw = gpiochip_get_data(chip);
939 const struct mtk_pin_desc *desc;
940 u32 debounce;
941
942 desc = (const struct mtk_pin_desc *)&hw->soc->pins[offset];
943
944 if (!hw->eint ||
945 pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE ||
946 desc->eint.eint_n == EINT_NA)
947 return -ENOTSUPP;
948
949 debounce = pinconf_to_config_argument(config);
950
951 return mtk_eint_set_debounce(hw->eint, desc->eint.eint_n, debounce);
952 }
953
954 static int mtk_build_gpiochip(struct mtk_pinctrl *hw)
955 {
956 struct gpio_chip *chip = &hw->chip;
957 int ret;
958
959 chip->label = PINCTRL_PINCTRL_DEV;
960 chip->parent = hw->dev;
961 chip->request = gpiochip_generic_request;
962 chip->free = gpiochip_generic_free;
963 chip->get_direction = mtk_gpio_get_direction;
964 chip->direction_input = mtk_gpio_direction_input;
965 chip->direction_output = mtk_gpio_direction_output;
966 chip->get = mtk_gpio_get;
967 chip->set = mtk_gpio_set;
968 chip->to_irq = mtk_gpio_to_irq;
969 chip->set_config = mtk_gpio_set_config;
970 chip->base = -1;
971 chip->ngpio = hw->soc->npins;
972
973 ret = gpiochip_add_data(chip, hw);
974 if (ret < 0)
975 return ret;
976
977 return 0;
978 }
979
980 static int mtk_pctrl_build_state(struct platform_device *pdev)
981 {
982 struct mtk_pinctrl *hw = platform_get_drvdata(pdev);
983 int i;
984
985 /* Allocate groups */
986 hw->groups = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
987 sizeof(*hw->groups), GFP_KERNEL);
988 if (!hw->groups)
989 return -ENOMEM;
990
991 /* We assume that one pin is one group, use pin name as group name. */
992 hw->grp_names = devm_kmalloc_array(&pdev->dev, hw->soc->ngrps,
993 sizeof(*hw->grp_names), GFP_KERNEL);
994 if (!hw->grp_names)
995 return -ENOMEM;
996
997 for (i = 0; i < hw->soc->npins; i++) {
998 const struct mtk_pin_desc *pin = hw->soc->pins + i;
999 struct mtk_pinctrl_group *group = hw->groups + i;
1000
1001 group->name = pin->name;
1002 group->pin = pin->number;
1003
1004 hw->grp_names[i] = pin->name;
1005 }
1006
1007 return 0;
1008 }
1009
1010 int mtk_paris_pinctrl_probe(struct platform_device *pdev)
1011 {
1012 struct device *dev = &pdev->dev;
1013 struct pinctrl_pin_desc *pins;
1014 struct mtk_pinctrl *hw;
1015 int err, i;
1016
1017 hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
1018 if (!hw)
1019 return -ENOMEM;
1020
1021 platform_set_drvdata(pdev, hw);
1022
1023 hw->soc = device_get_match_data(dev);
1024 if (!hw->soc)
1025 return -ENOENT;
1026
1027 hw->dev = &pdev->dev;
1028
1029 if (!hw->soc->nbase_names)
1030 return dev_err_probe(dev, -EINVAL,
1031 "SoC should be assigned at least one register base\n");
1032
1033 hw->base = devm_kmalloc_array(&pdev->dev, hw->soc->nbase_names,
1034 sizeof(*hw->base), GFP_KERNEL);
1035 if (!hw->base)
1036 return -ENOMEM;
1037
1038 for (i = 0; i < hw->soc->nbase_names; i++) {
1039 hw->base[i] = devm_platform_ioremap_resource_byname(pdev,
1040 hw->soc->base_names[i]);
1041 if (IS_ERR(hw->base[i]))
1042 return PTR_ERR(hw->base[i]);
1043 }
1044
1045 hw->nbase = hw->soc->nbase_names;
1046
1047 hw->rsel_si_unit = of_property_read_bool(hw->dev->of_node,
1048 "mediatek,rsel-resistance-in-si-unit");
1049
1050 spin_lock_init(&hw->lock);
1051
1052 err = mtk_pctrl_build_state(pdev);
1053 if (err)
1054 return dev_err_probe(dev, err, "build state failed\n");
1055
1056 /* Copy from internal struct mtk_pin_desc to register to the core */
1057 pins = devm_kmalloc_array(&pdev->dev, hw->soc->npins, sizeof(*pins),
1058 GFP_KERNEL);
1059 if (!pins)
1060 return -ENOMEM;
1061
1062 for (i = 0; i < hw->soc->npins; i++) {
1063 pins[i].number = hw->soc->pins[i].number;
1064 pins[i].name = hw->soc->pins[i].name;
1065 }
1066
1067 /* Setup pins descriptions per SoC types */
1068 mtk_desc.pins = (const struct pinctrl_pin_desc *)pins;
1069 mtk_desc.npins = hw->soc->npins;
1070 mtk_desc.num_custom_params = ARRAY_SIZE(mtk_custom_bindings);
1071 mtk_desc.custom_params = mtk_custom_bindings;
1072 #ifdef CONFIG_DEBUG_FS
1073 mtk_desc.custom_conf_items = mtk_conf_items;
1074 #endif
1075
1076 err = devm_pinctrl_register_and_init(&pdev->dev, &mtk_desc, hw,
1077 &hw->pctrl);
1078 if (err)
1079 return err;
1080
1081 err = pinctrl_enable(hw->pctrl);
1082 if (err)
1083 return err;
1084
1085 err = mtk_build_eint(hw, pdev);
1086 if (err)
1087 dev_warn(&pdev->dev,
1088 "Failed to add EINT, but pinctrl still can work\n");
1089
1090 /* Build gpiochip should be after pinctrl_enable is done */
1091 err = mtk_build_gpiochip(hw);
1092 if (err)
1093 return dev_err_probe(dev, err, "Failed to add gpio_chip\n");
1094
1095 platform_set_drvdata(pdev, hw);
1096
1097 return 0;
1098 }
1099 EXPORT_SYMBOL_GPL(mtk_paris_pinctrl_probe);
1100
1101 static int mtk_paris_pinctrl_suspend(struct device *device)
1102 {
1103 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1104
1105 return mtk_eint_do_suspend(pctl->eint);
1106 }
1107
1108 static int mtk_paris_pinctrl_resume(struct device *device)
1109 {
1110 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1111
1112 return mtk_eint_do_resume(pctl->eint);
1113 }
1114
1115 EXPORT_GPL_DEV_SLEEP_PM_OPS(mtk_paris_pinctrl_pm_ops) = {
1116 NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_paris_pinctrl_suspend, mtk_paris_pinctrl_resume)
1117 };
1118
1119 MODULE_LICENSE("GPL v2");
1120 MODULE_DESCRIPTION("MediaTek Pinctrl Common Driver V2 Paris");
Kernel DRM miscellaneous fixes and cross-tree changes