1 // SPDX-License-Identifier: GPL-2.0
3 * SP7021 Pin Controller Driver.
4 * Copyright (C) Sunplus Tech / Tibbo Tech.
7 #include <linux/cleanup.h>
8 #include <linux/bitfield.h>
9 #include <linux/device.h>
10 #include <linux/err.h>
11 #include <linux/gpio/driver.h>
12 #include <linux/init.h>
13 #include <linux/module.h>
15 #include <linux/overflow.h>
16 #include <linux/platform_device.h>
17 #include <linux/seq_file.h>
18 #include <linux/slab.h>
20 #include <linux/pinctrl/pinconf.h>
21 #include <linux/pinctrl/pinconf-generic.h>
22 #include <linux/pinctrl/pinmux.h>
24 #include <dt-bindings/pinctrl/sppctl-sp7021.h>
27 #include "../pinctrl-utils.h"
31 struct sppctl_gpio_chip
{
32 void __iomem
*gpioxt_base
; /* MASTER, OE, OUT, IN, I_INV, O_INV, OD */
33 void __iomem
*first_base
; /* GPIO_FIRST */
35 struct gpio_chip chip
;
36 spinlock_t lock
; /* lock for accessing OE register */
39 static inline u32
sppctl_first_readl(struct sppctl_gpio_chip
*spp_gchip
, u32 off
)
41 return readl(spp_gchip
->first_base
+ SPPCTL_GPIO_OFF_FIRST
+ off
);
44 static inline void sppctl_first_writel(struct sppctl_gpio_chip
*spp_gchip
, u32 val
, u32 off
)
46 writel(val
, spp_gchip
->first_base
+ SPPCTL_GPIO_OFF_FIRST
+ off
);
49 static inline u32
sppctl_gpio_master_readl(struct sppctl_gpio_chip
*spp_gchip
, u32 off
)
51 return readl(spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_MASTER
+ off
);
54 static inline void sppctl_gpio_master_writel(struct sppctl_gpio_chip
*spp_gchip
, u32 val
,
57 writel(val
, spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_MASTER
+ off
);
60 static inline u32
sppctl_gpio_oe_readl(struct sppctl_gpio_chip
*spp_gchip
, u32 off
)
62 return readl(spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_OE
+ off
);
65 static inline void sppctl_gpio_oe_writel(struct sppctl_gpio_chip
*spp_gchip
, u32 val
, u32 off
)
67 writel(val
, spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_OE
+ off
);
70 static inline void sppctl_gpio_out_writel(struct sppctl_gpio_chip
*spp_gchip
, u32 val
, u32 off
)
72 writel(val
, spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_OUT
+ off
);
75 static inline u32
sppctl_gpio_in_readl(struct sppctl_gpio_chip
*spp_gchip
, u32 off
)
77 return readl(spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_IN
+ off
);
80 static inline u32
sppctl_gpio_iinv_readl(struct sppctl_gpio_chip
*spp_gchip
, u32 off
)
82 return readl(spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_IINV
+ off
);
85 static inline void sppctl_gpio_iinv_writel(struct sppctl_gpio_chip
*spp_gchip
, u32 val
,
88 writel(val
, spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_IINV
+ off
);
91 static inline u32
sppctl_gpio_oinv_readl(struct sppctl_gpio_chip
*spp_gchip
, u32 off
)
93 return readl(spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_OINV
+ off
);
96 static inline void sppctl_gpio_oinv_writel(struct sppctl_gpio_chip
*spp_gchip
, u32 val
,
99 writel(val
, spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_OINV
+ off
);
102 static inline u32
sppctl_gpio_od_readl(struct sppctl_gpio_chip
*spp_gchip
, u32 off
)
104 return readl(spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_OD
+ off
);
107 static inline void sppctl_gpio_od_writel(struct sppctl_gpio_chip
*spp_gchip
, u32 val
, u32 off
)
109 writel(val
, spp_gchip
->gpioxt_base
+ SPPCTL_GPIO_OFF_OD
+ off
);
112 static inline u32
sppctl_get_reg_and_bit_offset(unsigned int offset
, u32
*reg_off
)
116 /* Each register has 32 bits. */
117 *reg_off
= (offset
/ 32) * 4;
118 bit_off
= offset
% 32;
123 static inline u32
sppctl_get_moon_reg_and_bit_offset(unsigned int offset
, u32
*reg_off
)
128 * Each MOON register has 32 bits. Upper 16-bit word are mask-fields.
129 * The lower 16-bit word are the control-fields. The corresponding
130 * bits in mask-field should be set then you can write something to
133 *reg_off
= (offset
/ 16) * 4;
134 bit_off
= offset
% 16;
139 static inline u32
sppctl_prep_moon_reg_and_offset(unsigned int offset
, u32
*reg_off
, int val
)
143 bit_off
= sppctl_get_moon_reg_and_bit_offset(offset
, reg_off
);
145 return SPPCTL_SET_MOON_REG_BIT(bit_off
);
147 return SPPCTL_CLR_MOON_REG_BIT(bit_off
);
151 * sppctl_func_set() - Set pin of fully-pinmux function.
153 * Mask-fields and control-fields of fully-pinmux function of SP7021 are
154 * arranged as shown below:
156 * func# | register | mask-field | control-field
157 * -------+----------+--------------+---------------
158 * 0 | base[0] | (22 : 16) | ( 6 : 0)
159 * 1 | base[0] | (30 : 24) | (14 : 8)
160 * 2 | base[1] | (22 : 16) | ( 6 : 0)
161 * 3 | baeg[1] | (30 : 24) | (14 : 8)
164 * where mask-fields are used to protect control-fields from write-in
165 * accidentally. Set the corresponding bits in the mask-field before
166 * you write a value into a control-field.
168 * Control-fields are used to set where the function pin is going to
171 * Note that mask-fields and control-fields of even number of 'func'
172 * are located at bits (22:16) and (6:0), while odd number of 'func's
173 * are located at bits (30:24) and (14:8).
175 static void sppctl_func_set(struct sppctl_pdata
*pctl
, u8 func
, u8 val
)
180 * Note that upper 16-bit word are mask-fields and lower 16-bit
181 * word are the control-fields. Set corresponding bits in mask-
182 * field before write to a control-field.
184 reg
= SPPCTL_FULLY_PINMUX_MASK_MASK
| val
;
187 * MUXF_L2SW_CLK_OUT is the first fully-pinmux pin
188 * and its register offset is 0.
190 func
-= MUXF_L2SW_CLK_OUT
;
193 * Check if 'func' is an odd number or not. Mask and control-
194 * fields of odd number 'func' is located at upper portion of
195 * a register. Extra shift is needed.
198 reg
<<= SPPCTL_FULLY_PINMUX_UPPER_SHIFT
;
200 /* Convert func# to register offset w.r.t. base register. */
202 offset
&= GENMASK(31, 2);
204 writel(reg
, pctl
->moon2_base
+ offset
);
208 * sppctl_gmx_set() - Set pin of group-pinmux.
210 * Mask-fields and control-fields of group-pinmux function of SP7021 are
211 * arranged as shown below:
213 * register | mask-fields | control-fields
214 * ----------+--------------+----------------
215 * base[0] | (31 : 16) | (15 : 0)
216 * base[1] | (31 : 24) | (15 : 0)
217 * base[2] | (31 : 24) | (15 : 0)
220 * where mask-fields are used to protect control-fields from write-in
221 * accidentally. Set the corresponding bits in the mask-field before
222 * you write a value into a control-field.
224 * Control-fields are used to set where the function pin is going to
225 * be routed to. A control-field consists of one or more bits.
227 static void sppctl_gmx_set(struct sppctl_pdata
*pctl
, u8 reg_off
, u8 bit_off
, u8 bit_sz
,
233 * Note that upper 16-bit word are mask-fields and lower 16-bit
234 * word are the control-fields. Set corresponding bits in mask-
235 * field before write to a control-field.
237 mask
= GENMASK(bit_sz
- 1, 0) << SPPCTL_MOON_REG_MASK_SHIFT
;
238 reg
= (mask
| val
) << bit_off
;
240 writel(reg
, pctl
->moon1_base
+ reg_off
* 4);
244 * sppctl_first_get() - get bit of FIRST register.
246 * There are 4 FIRST registers. Each has 32 control-bits.
247 * Totally, there are 4 * 32 = 128 control-bits.
248 * Control-bits are arranged as shown below:
250 * registers | control-bits
251 * -----------+--------------
252 * first[0] | (31 : 0)
253 * first[1] | (63 : 32)
254 * first[2] | (95 : 64)
255 * first[3] | (127 : 96)
257 * Each control-bit sets type of a GPIO pin.
258 * 0: a fully-pinmux pin
259 * 1: a GPIO or IOP pin
261 static int sppctl_first_get(struct gpio_chip
*chip
, unsigned int offset
)
263 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
264 u32 reg_off
, bit_off
, reg
;
266 bit_off
= sppctl_get_reg_and_bit_offset(offset
, ®_off
);
267 reg
= sppctl_first_readl(spp_gchip
, reg_off
);
269 return (reg
& BIT(bit_off
)) ? 1 : 0;
273 * sppctl_master_get() - get bit of MASTER register.
275 * There are 8 MASTER registers. Each has 16 mask-bits and 16 control-bits.
276 * Upper 16-bit of MASTER registers are mask-bits while lower 16-bit are
277 * control-bits. Totally, there are 128 mask-bits and 128 control-bits.
278 * They are arranged as shown below:
280 * register | mask-bits | control-bits
281 * -----------+-------------+--------------
282 * master[0] | (15 : 0) | (15 : 0)
283 * master[1] | (31 : 16) | (31 : 16)
284 * master[2] | (47 : 32) | (47 : 32)
286 * master[7] | (127 : 112) | (127 : 112)
288 * where mask-bits are used to protect control-bits from write-in
289 * accidentally. Set the corresponding mask-bit before you write
290 * a value into a control-bit.
292 * Each control-bit sets type of a GPIO pin when FIRST bit is 1.
296 static int sppctl_master_get(struct gpio_chip
*chip
, unsigned int offset
)
298 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
299 u32 reg_off
, bit_off
, reg
;
301 bit_off
= sppctl_get_moon_reg_and_bit_offset(offset
, ®_off
);
302 reg
= sppctl_gpio_master_readl(spp_gchip
, reg_off
);
303 return (reg
& BIT(bit_off
)) ? 1 : 0;
306 static void sppctl_first_master_set(struct gpio_chip
*chip
, unsigned int offset
,
307 enum mux_first_reg first
, enum mux_master_reg master
)
309 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
310 u32 reg_off
, bit_off
, reg
;
311 enum mux_first_reg val
;
314 if (first
!= mux_f_keep
) {
315 bit_off
= sppctl_get_reg_and_bit_offset(offset
, ®_off
);
316 reg
= sppctl_first_readl(spp_gchip
, reg_off
);
317 val
= (reg
& BIT(bit_off
)) ? mux_f_gpio
: mux_f_mux
;
323 sppctl_first_writel(spp_gchip
, reg
, reg_off
);
327 reg
&= ~BIT(bit_off
);
328 sppctl_first_writel(spp_gchip
, reg
, reg_off
);
336 /* MASTER register */
337 if (master
!= mux_m_keep
) {
338 reg
= sppctl_prep_moon_reg_and_offset(offset
, ®_off
, (master
== mux_m_gpio
));
339 sppctl_gpio_master_writel(spp_gchip
, reg
, reg_off
);
343 static void sppctl_gpio_input_inv_set(struct gpio_chip
*chip
, unsigned int offset
)
345 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
348 reg
= sppctl_prep_moon_reg_and_offset(offset
, ®_off
, 1);
349 sppctl_gpio_iinv_writel(spp_gchip
, reg
, reg_off
);
352 static void sppctl_gpio_output_inv_set(struct gpio_chip
*chip
, unsigned int offset
)
354 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
357 reg
= sppctl_prep_moon_reg_and_offset(offset
, ®_off
, 1);
358 sppctl_gpio_oinv_writel(spp_gchip
, reg
, reg_off
);
361 static int sppctl_gpio_output_od_get(struct gpio_chip
*chip
, unsigned int offset
)
363 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
364 u32 reg_off
, bit_off
, reg
;
366 bit_off
= sppctl_get_moon_reg_and_bit_offset(offset
, ®_off
);
367 reg
= sppctl_gpio_od_readl(spp_gchip
, reg_off
);
369 return (reg
& BIT(bit_off
)) ? 1 : 0;
372 static void sppctl_gpio_output_od_set(struct gpio_chip
*chip
, unsigned int offset
,
375 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
378 reg
= sppctl_prep_moon_reg_and_offset(offset
, ®_off
, val
);
379 sppctl_gpio_od_writel(spp_gchip
, reg
, reg_off
);
382 static int sppctl_gpio_get_direction(struct gpio_chip
*chip
, unsigned int offset
)
384 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
385 u32 reg_off
, bit_off
, reg
;
387 bit_off
= sppctl_get_moon_reg_and_bit_offset(offset
, ®_off
);
388 reg
= sppctl_gpio_oe_readl(spp_gchip
, reg_off
);
390 return (reg
& BIT(bit_off
)) ? 0 : 1;
393 static int sppctl_gpio_inv_get(struct gpio_chip
*chip
, unsigned int offset
)
395 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
396 u32 reg_off
, bit_off
, reg
;
399 bit_off
= sppctl_get_moon_reg_and_bit_offset(offset
, ®_off
);
401 spin_lock_irqsave(&spp_gchip
->lock
, flags
);
403 if (sppctl_gpio_get_direction(chip
, offset
))
404 reg
= sppctl_gpio_iinv_readl(spp_gchip
, reg_off
);
406 reg
= sppctl_gpio_oinv_readl(spp_gchip
, reg_off
);
408 spin_unlock_irqrestore(&spp_gchip
->lock
, flags
);
410 return (reg
& BIT(bit_off
)) ? 1 : 0;
413 static int sppctl_gpio_direction_input(struct gpio_chip
*chip
, unsigned int offset
)
415 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
419 reg
= sppctl_prep_moon_reg_and_offset(offset
, ®_off
, 0);
421 spin_lock_irqsave(&spp_gchip
->lock
, flags
);
423 sppctl_gpio_oe_writel(spp_gchip
, reg
, reg_off
);
425 spin_unlock_irqrestore(&spp_gchip
->lock
, flags
);
429 static int sppctl_gpio_direction_output(struct gpio_chip
*chip
, unsigned int offset
, int val
)
431 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
435 reg
= sppctl_prep_moon_reg_and_offset(offset
, ®_off
, 1);
437 spin_lock_irqsave(&spp_gchip
->lock
, flags
);
439 sppctl_gpio_oe_writel(spp_gchip
, reg
, reg_off
);
442 spin_unlock_irqrestore(&spp_gchip
->lock
, flags
);
446 reg
= sppctl_prep_moon_reg_and_offset(offset
, ®_off
, val
);
447 sppctl_gpio_out_writel(spp_gchip
, reg
, reg_off
);
449 spin_unlock_irqrestore(&spp_gchip
->lock
, flags
);
453 static int sppctl_gpio_get(struct gpio_chip
*chip
, unsigned int offset
)
455 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
456 u32 reg_off
, bit_off
, reg
;
458 bit_off
= sppctl_get_reg_and_bit_offset(offset
, ®_off
);
459 reg
= sppctl_gpio_in_readl(spp_gchip
, reg_off
);
461 return (reg
& BIT(bit_off
)) ? 1 : 0;
464 static void sppctl_gpio_set(struct gpio_chip
*chip
, unsigned int offset
, int val
)
466 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
469 reg
= sppctl_prep_moon_reg_and_offset(offset
, ®_off
, val
);
470 sppctl_gpio_out_writel(spp_gchip
, reg
, reg_off
);
473 static int sppctl_gpio_set_config(struct gpio_chip
*chip
, unsigned int offset
,
474 unsigned long config
)
476 enum pin_config_param param
= pinconf_to_config_param(config
);
477 struct sppctl_gpio_chip
*spp_gchip
= gpiochip_get_data(chip
);
481 case PIN_CONFIG_DRIVE_OPEN_DRAIN
:
482 reg
= sppctl_prep_moon_reg_and_offset(offset
, ®_off
, 1);
483 sppctl_gpio_od_writel(spp_gchip
, reg
, reg_off
);
486 case PIN_CONFIG_INPUT_ENABLE
:
489 case PIN_CONFIG_OUTPUT
:
490 return sppctl_gpio_direction_output(chip
, offset
, 0);
492 case PIN_CONFIG_PERSIST_STATE
:
502 static void sppctl_gpio_dbg_show(struct seq_file
*s
, struct gpio_chip
*chip
)
506 for (i
= 0; i
< chip
->ngpio
; i
++) {
507 char *label
__free(kfree
) = gpiochip_dup_line_label(chip
, i
);
511 seq_printf(s
, " gpio-%03d (%-16.16s | %-16.16s)", i
+ chip
->base
,
512 chip
->names
[i
], label
?: "");
513 seq_printf(s
, " %c", sppctl_gpio_get_direction(chip
, i
) ? 'I' : 'O');
514 seq_printf(s
, ":%d", sppctl_gpio_get(chip
, i
));
515 seq_printf(s
, " %s", sppctl_first_get(chip
, i
) ? "gpi" : "mux");
516 seq_printf(s
, " %s", sppctl_master_get(chip
, i
) ? "gpi" : "iop");
517 seq_printf(s
, " %s", sppctl_gpio_inv_get(chip
, i
) ? "inv" : " ");
518 seq_printf(s
, " %s", sppctl_gpio_output_od_get(chip
, i
) ? "oDr" : "");
523 static int sppctl_gpio_new(struct platform_device
*pdev
, struct sppctl_pdata
*pctl
)
525 struct sppctl_gpio_chip
*spp_gchip
;
526 struct gpio_chip
*gchip
;
529 spp_gchip
= devm_kzalloc(&pdev
->dev
, sizeof(*spp_gchip
), GFP_KERNEL
);
532 pctl
->spp_gchip
= spp_gchip
;
534 spp_gchip
->gpioxt_base
= pctl
->gpioxt_base
;
535 spp_gchip
->first_base
= pctl
->first_base
;
536 spin_lock_init(&spp_gchip
->lock
);
538 gchip
= &spp_gchip
->chip
;
539 gchip
->label
= SPPCTL_MODULE_NAME
;
540 gchip
->parent
= &pdev
->dev
;
541 gchip
->owner
= THIS_MODULE
;
542 gchip
->request
= gpiochip_generic_request
;
543 gchip
->free
= gpiochip_generic_free
;
544 gchip
->get_direction
= sppctl_gpio_get_direction
;
545 gchip
->direction_input
= sppctl_gpio_direction_input
;
546 gchip
->direction_output
= sppctl_gpio_direction_output
;
547 gchip
->get
= sppctl_gpio_get
;
548 gchip
->set
= sppctl_gpio_set
;
549 gchip
->set_config
= sppctl_gpio_set_config
;
550 gchip
->dbg_show
= IS_ENABLED(CONFIG_DEBUG_FS
) ?
551 sppctl_gpio_dbg_show
: NULL
;
553 gchip
->ngpio
= sppctl_gpio_list_sz
;
554 gchip
->names
= sppctl_gpio_list_s
;
556 pctl
->pctl_grange
.npins
= gchip
->ngpio
;
557 pctl
->pctl_grange
.name
= gchip
->label
;
558 pctl
->pctl_grange
.gc
= gchip
;
560 err
= devm_gpiochip_add_data(&pdev
->dev
, gchip
, spp_gchip
);
562 return dev_err_probe(&pdev
->dev
, err
, "Failed to add gpiochip!\n");
567 static int sppctl_pin_config_get(struct pinctrl_dev
*pctldev
, unsigned int pin
,
568 unsigned long *config
)
570 struct sppctl_pdata
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
571 unsigned int param
= pinconf_to_config_param(*config
);
575 case PIN_CONFIG_DRIVE_OPEN_DRAIN
:
576 if (!sppctl_gpio_output_od_get(&pctl
->spp_gchip
->chip
, pin
))
581 case PIN_CONFIG_OUTPUT
:
582 if (!sppctl_first_get(&pctl
->spp_gchip
->chip
, pin
))
584 if (!sppctl_master_get(&pctl
->spp_gchip
->chip
, pin
))
586 if (sppctl_gpio_get_direction(&pctl
->spp_gchip
->chip
, pin
))
588 arg
= sppctl_gpio_get(&pctl
->spp_gchip
->chip
, pin
);
594 *config
= pinconf_to_config_packed(param
, arg
);
599 static int sppctl_pin_config_set(struct pinctrl_dev
*pctldev
, unsigned int pin
,
600 unsigned long *configs
, unsigned int num_configs
)
602 struct sppctl_pdata
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
605 /* Special handling for IOP pins */
606 if (configs
[0] == SPPCTL_IOP_CONFIGS
) {
607 sppctl_first_master_set(&pctl
->spp_gchip
->chip
, pin
, mux_f_gpio
, mux_m_iop
);
611 for (i
= 0; i
< num_configs
; i
++) {
612 if (configs
[i
] & SPPCTL_PCTL_L_OUT
)
613 sppctl_gpio_direction_output(&pctl
->spp_gchip
->chip
, pin
, 0);
614 if (configs
[i
] & SPPCTL_PCTL_L_OU1
)
615 sppctl_gpio_direction_output(&pctl
->spp_gchip
->chip
, pin
, 1);
616 if (configs
[i
] & SPPCTL_PCTL_L_INV
)
617 sppctl_gpio_input_inv_set(&pctl
->spp_gchip
->chip
, pin
);
618 if (configs
[i
] & SPPCTL_PCTL_L_ONV
)
619 sppctl_gpio_output_inv_set(&pctl
->spp_gchip
->chip
, pin
);
620 if (configs
[i
] & SPPCTL_PCTL_L_ODR
)
621 sppctl_gpio_output_od_set(&pctl
->spp_gchip
->chip
, pin
, 1);
627 static const struct pinconf_ops sppctl_pconf_ops
= {
629 .pin_config_get
= sppctl_pin_config_get
,
630 .pin_config_set
= sppctl_pin_config_set
,
633 static int sppctl_get_functions_count(struct pinctrl_dev
*pctldev
)
635 return sppctl_list_funcs_sz
;
638 static const char *sppctl_get_function_name(struct pinctrl_dev
*pctldev
,
639 unsigned int selector
)
641 return sppctl_list_funcs
[selector
].name
;
644 static int sppctl_get_function_groups(struct pinctrl_dev
*pctldev
, unsigned int selector
,
645 const char * const **groups
, unsigned int *num_groups
)
647 struct sppctl_pdata
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
648 const struct sppctl_func
*f
= &sppctl_list_funcs
[selector
];
653 case pinmux_type_fpmx
:
654 *num_groups
= sppctl_pmux_list_sz
;
655 *groups
= sppctl_pmux_list_s
;
658 case pinmux_type_grp
:
662 *num_groups
= f
->gnum
;
663 for (i
= 0; i
< pctl
->unq_grps_sz
; i
++)
664 if (pctl
->g2fp_maps
[i
].f_idx
== selector
)
666 *groups
= &pctl
->unq_grps
[i
];
670 dev_err(pctldev
->dev
, "Unknown pinmux (selector: %d, type: %d)\n",
679 * sppctl_fully_pinmux_conv - Convert GPIO# to fully-pinmux control-field setting
681 * Each fully-pinmux function can be mapped to any of GPIO 8 ~ 71 by
682 * settings its control-field. Refer to following table:
684 * control-field | GPIO
685 * --------------+--------
693 static inline int sppctl_fully_pinmux_conv(unsigned int offset
)
695 return (offset
< 8) ? 0 : offset
- 7;
698 static int sppctl_set_mux(struct pinctrl_dev
*pctldev
, unsigned int func_selector
,
699 unsigned int group_selector
)
701 const struct sppctl_func
*f
= &sppctl_list_funcs
[func_selector
];
702 struct sppctl_pdata
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
703 struct grp2fp_map g2fpm
= pctl
->g2fp_maps
[group_selector
];
707 case pinmux_type_fpmx
:
708 sppctl_first_master_set(&pctl
->spp_gchip
->chip
, group_selector
,
709 mux_f_mux
, mux_m_keep
);
710 sppctl_func_set(pctl
, func_selector
, sppctl_fully_pinmux_conv(group_selector
));
713 case pinmux_type_grp
:
714 for (i
= 0; i
< f
->grps
[g2fpm
.g_idx
].pnum
; i
++)
715 sppctl_first_master_set(&pctl
->spp_gchip
->chip
,
716 f
->grps
[g2fpm
.g_idx
].pins
[i
],
717 mux_f_mux
, mux_m_keep
);
718 sppctl_gmx_set(pctl
, f
->roff
, f
->boff
, f
->blen
, f
->grps
[g2fpm
.g_idx
].gval
);
722 dev_err(pctldev
->dev
, "Unknown pinmux type (func_selector: %d, type: %d)\n",
723 func_selector
, f
->type
);
730 static int sppctl_gpio_request_enable(struct pinctrl_dev
*pctldev
,
731 struct pinctrl_gpio_range
*range
, unsigned int offset
)
733 struct sppctl_pdata
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
736 g_f
= sppctl_first_get(&pctl
->spp_gchip
->chip
, offset
);
737 g_m
= sppctl_master_get(&pctl
->spp_gchip
->chip
, offset
);
738 if (g_f
== mux_f_gpio
&& g_m
== mux_m_gpio
)
741 sppctl_first_master_set(&pctl
->spp_gchip
->chip
, offset
, mux_f_gpio
, mux_m_gpio
);
745 static const struct pinmux_ops sppctl_pinmux_ops
= {
746 .get_functions_count
= sppctl_get_functions_count
,
747 .get_function_name
= sppctl_get_function_name
,
748 .get_function_groups
= sppctl_get_function_groups
,
749 .set_mux
= sppctl_set_mux
,
750 .gpio_request_enable
= sppctl_gpio_request_enable
,
754 static int sppctl_get_groups_count(struct pinctrl_dev
*pctldev
)
756 struct sppctl_pdata
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
758 return pctl
->unq_grps_sz
;
761 static const char *sppctl_get_group_name(struct pinctrl_dev
*pctldev
, unsigned int selector
)
763 struct sppctl_pdata
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
765 return pctl
->unq_grps
[selector
];
768 static int sppctl_get_group_pins(struct pinctrl_dev
*pctldev
, unsigned int selector
,
769 const unsigned int **pins
, unsigned int *num_pins
)
771 struct sppctl_pdata
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
772 struct grp2fp_map g2fpm
= pctl
->g2fp_maps
[selector
];
773 const struct sppctl_func
*f
;
775 f
= &sppctl_list_funcs
[g2fpm
.f_idx
];
778 /* Except group-pinmux, each group has 1 pin. */
779 if (f
->type
!= pinmux_type_grp
) {
781 *pins
= &sppctl_pins_gpio
[selector
];
785 /* Group-pinmux may have more than one pin. */
792 *num_pins
= f
->grps
[g2fpm
.g_idx
].pnum
;
793 *pins
= f
->grps
[g2fpm
.g_idx
].pins
;
798 #ifdef CONFIG_DEBUG_FS
799 static void sppctl_pin_dbg_show(struct pinctrl_dev
*pctldev
, struct seq_file
*s
,
802 struct sppctl_pdata
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
803 const char *pin_type
;
806 first
= sppctl_first_get(&pctl
->spp_gchip
->chip
, offset
);
807 master
= sppctl_master_get(&pctl
->spp_gchip
->chip
, offset
);
815 seq_printf(s
, " %s", pin_type
);
819 static int sppctl_dt_node_to_map(struct pinctrl_dev
*pctldev
, struct device_node
*np_config
,
820 struct pinctrl_map
**map
, unsigned int *num_maps
)
822 struct sppctl_pdata
*pctl
= pinctrl_dev_get_drvdata(pctldev
);
823 int nmG
= of_property_count_strings(np_config
, "groups");
824 const struct sppctl_func
*f
= NULL
;
825 u8 pin_num
, pin_type
, pin_func
;
826 struct device_node
*parent
;
827 unsigned long *configs
;
828 struct property
*prop
;
829 const char *s_f
, *s_g
;
835 list
= of_get_property(np_config
, "sunplus,pins", &size
);
836 *num_maps
= size
/ sizeof(*list
);
840 * sunplus,pins = < u32 u32 u32 ... >;
842 * Each 32-bit integer defines a individual pin in which:
844 * Bit 32~24: defines GPIO pin number. Its range is 0 ~ 98.
845 * Bit 23~16: defines types: (1) fully-pinmux pins
846 * (2) IO processor pins
847 * (3) digital GPIO pins
848 * Bit 15~8: defines pins of peripherals (which are defined in
849 * 'include/dt-binging/pinctrl/sppctl.h').
850 * Bit 7~0: defines types or initial-state of digital GPIO pins.
852 for (i
= 0; i
< (*num_maps
); i
++) {
853 dt_pin
= be32_to_cpu(list
[i
]);
854 pin_num
= FIELD_GET(GENMASK(31, 24), dt_pin
);
856 if (pin_num
>= sppctl_pins_all_sz
) {
857 dev_err(pctldev
->dev
, "Invalid pin property at index %d (0x%08x)\n",
866 *map
= kcalloc(*num_maps
+ nmG
, sizeof(**map
), GFP_KERNEL
);
870 parent
= of_get_parent(np_config
);
871 for (i
= 0; i
< (*num_maps
); i
++) {
872 dt_pin
= be32_to_cpu(list
[i
]);
873 pin_num
= FIELD_GET(GENMASK(31, 24), dt_pin
);
874 pin_type
= FIELD_GET(GENMASK(23, 16), dt_pin
);
875 pin_func
= FIELD_GET(GENMASK(15, 8), dt_pin
);
876 (*map
)[i
].name
= parent
->name
;
878 if (pin_type
== SPPCTL_PCTL_G_GPIO
) {
879 /* A digital GPIO pin */
880 (*map
)[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
881 (*map
)[i
].data
.configs
.num_configs
= 1;
882 (*map
)[i
].data
.configs
.group_or_pin
= pin_get_name(pctldev
, pin_num
);
883 configs
= kmalloc(sizeof(*configs
), GFP_KERNEL
);
886 *configs
= FIELD_GET(GENMASK(7, 0), dt_pin
);
887 (*map
)[i
].data
.configs
.configs
= configs
;
889 dev_dbg(pctldev
->dev
, "%s: GPIO (%s)\n",
890 (*map
)[i
].data
.configs
.group_or_pin
,
891 (*configs
& (SPPCTL_PCTL_L_OUT
| SPPCTL_PCTL_L_OU1
)) ?
893 } else if (pin_type
== SPPCTL_PCTL_G_IOPP
) {
894 /* A IO Processor (IOP) pin */
895 (*map
)[i
].type
= PIN_MAP_TYPE_CONFIGS_PIN
;
896 (*map
)[i
].data
.configs
.num_configs
= 1;
897 (*map
)[i
].data
.configs
.group_or_pin
= pin_get_name(pctldev
, pin_num
);
898 configs
= kmalloc(sizeof(*configs
), GFP_KERNEL
);
901 *configs
= SPPCTL_IOP_CONFIGS
;
902 (*map
)[i
].data
.configs
.configs
= configs
;
904 dev_dbg(pctldev
->dev
, "%s: IOP\n",
905 (*map
)[i
].data
.configs
.group_or_pin
);
907 /* A fully-pinmux pin */
908 (*map
)[i
].type
= PIN_MAP_TYPE_MUX_GROUP
;
909 (*map
)[i
].data
.mux
.function
= sppctl_list_funcs
[pin_func
].name
;
910 (*map
)[i
].data
.mux
.group
= pin_get_name(pctldev
, pin_num
);
912 dev_dbg(pctldev
->dev
, "%s: %s\n", (*map
)[i
].data
.mux
.group
,
913 (*map
)[i
].data
.mux
.function
);
918 * Process properties:
922 if (nmG
> 0 && of_property_read_string(np_config
, "function", &s_f
) == 0) {
923 of_property_for_each_string(np_config
, "groups", prop
, s_g
) {
924 (*map
)[*num_maps
].type
= PIN_MAP_TYPE_MUX_GROUP
;
925 (*map
)[*num_maps
].data
.mux
.function
= s_f
;
926 (*map
)[*num_maps
].data
.mux
.group
= s_g
;
929 dev_dbg(pctldev
->dev
, "%s: %s\n", s_f
, s_g
);
935 * sunplus,zerofunc = < u32 u32 u32 ...>
937 list
= of_get_property(np_config
, "sunplus,zerofunc", &size
);
939 for (i
= 0; i
< (size
/ sizeof(*list
)); i
++) {
940 dt_fun
= be32_to_cpu(list
[i
]);
941 if (dt_fun
>= sppctl_list_funcs_sz
) {
942 dev_err(pctldev
->dev
, "Zero-func %d out of range!\n",
947 f
= &sppctl_list_funcs
[dt_fun
];
949 case pinmux_type_fpmx
:
950 sppctl_func_set(pctl
, dt_fun
, 0);
951 dev_dbg(pctldev
->dev
, "%s: No map\n", f
->name
);
954 case pinmux_type_grp
:
955 sppctl_gmx_set(pctl
, f
->roff
, f
->boff
, f
->blen
, 0);
956 dev_dbg(pctldev
->dev
, "%s: No map\n", f
->name
);
960 dev_err(pctldev
->dev
, "Wrong zero-group: %d (%s)\n",
968 dev_dbg(pctldev
->dev
, "%d pins mapped\n", *num_maps
);
972 for (i
= 0; i
< (*num_maps
); i
++)
973 if ((*map
)[i
].type
== PIN_MAP_TYPE_CONFIGS_PIN
)
974 kfree((*map
)[i
].data
.configs
.configs
);
980 static const struct pinctrl_ops sppctl_pctl_ops
= {
981 .get_groups_count
= sppctl_get_groups_count
,
982 .get_group_name
= sppctl_get_group_name
,
983 .get_group_pins
= sppctl_get_group_pins
,
984 #ifdef CONFIG_DEBUG_FS
985 .pin_dbg_show
= sppctl_pin_dbg_show
,
987 .dt_node_to_map
= sppctl_dt_node_to_map
,
988 .dt_free_map
= pinctrl_utils_free_map
,
991 static int sppctl_group_groups(struct platform_device
*pdev
)
993 struct sppctl_pdata
*sppctl
= platform_get_drvdata(pdev
);
996 /* Calculate number of total group (GPIO + group-pinmux group). */
997 sppctl
->unq_grps_sz
= sppctl_gpio_list_sz
;
998 for (i
= 0; i
< sppctl_list_funcs_sz
; i
++)
999 if (sppctl_list_funcs
[i
].type
== pinmux_type_grp
)
1000 sppctl
->unq_grps_sz
+= sppctl_list_funcs
[i
].gnum
;
1002 sppctl
->unq_grps
= devm_kcalloc(&pdev
->dev
, sppctl
->unq_grps_sz
+ 1,
1003 sizeof(*sppctl
->unq_grps
), GFP_KERNEL
);
1004 if (!sppctl
->unq_grps
)
1007 sppctl
->g2fp_maps
= devm_kcalloc(&pdev
->dev
, sppctl
->unq_grps_sz
+ 1,
1008 sizeof(*sppctl
->g2fp_maps
), GFP_KERNEL
);
1009 if (!sppctl
->g2fp_maps
)
1012 /* Add GPIO pins. */
1013 for (i
= 0; i
< sppctl_gpio_list_sz
; i
++) {
1014 sppctl
->unq_grps
[i
] = sppctl_gpio_list_s
[i
];
1015 sppctl
->g2fp_maps
[i
].f_idx
= 0;
1016 sppctl
->g2fp_maps
[i
].g_idx
= i
;
1019 /* Add group-pinmux to end of GPIO pins. */
1020 j
= sppctl_gpio_list_sz
;
1021 for (i
= 0; i
< sppctl_list_funcs_sz
; i
++) {
1022 if (sppctl_list_funcs
[i
].type
!= pinmux_type_grp
)
1025 for (k
= 0; k
< sppctl_list_funcs
[i
].gnum
; k
++) {
1026 sppctl
->unq_grps
[j
] = sppctl_list_funcs
[i
].grps
[k
].name
;
1027 sppctl
->g2fp_maps
[j
].f_idx
= i
;
1028 sppctl
->g2fp_maps
[j
].g_idx
= k
;
1036 static int sppctl_pinctrl_init(struct platform_device
*pdev
)
1038 struct sppctl_pdata
*sppctl
= platform_get_drvdata(pdev
);
1041 sppctl
->pctl_desc
.owner
= THIS_MODULE
;
1042 sppctl
->pctl_desc
.name
= dev_name(&pdev
->dev
);
1043 sppctl
->pctl_desc
.pins
= sppctl_pins_all
;
1044 sppctl
->pctl_desc
.npins
= sppctl_pins_all_sz
;
1045 sppctl
->pctl_desc
.pctlops
= &sppctl_pctl_ops
;
1046 sppctl
->pctl_desc
.confops
= &sppctl_pconf_ops
;
1047 sppctl
->pctl_desc
.pmxops
= &sppctl_pinmux_ops
;
1049 err
= sppctl_group_groups(pdev
);
1053 err
= devm_pinctrl_register_and_init(&pdev
->dev
, &sppctl
->pctl_desc
,
1054 sppctl
, &sppctl
->pctl_dev
);
1056 return dev_err_probe(&pdev
->dev
, err
, "Failed to register pinctrl!\n");
1058 pinctrl_enable(sppctl
->pctl_dev
);
1062 static int sppctl_resource_map(struct platform_device
*pdev
, struct sppctl_pdata
*sppctl
)
1064 sppctl
->moon2_base
= devm_platform_ioremap_resource_byname(pdev
, "moon2");
1065 if (IS_ERR(sppctl
->moon2_base
))
1066 return PTR_ERR(sppctl
->moon2_base
);
1068 sppctl
->gpioxt_base
= devm_platform_ioremap_resource_byname(pdev
, "gpioxt");
1069 if (IS_ERR(sppctl
->gpioxt_base
))
1070 return PTR_ERR(sppctl
->gpioxt_base
);
1072 sppctl
->first_base
= devm_platform_ioremap_resource_byname(pdev
, "first");
1073 if (IS_ERR(sppctl
->first_base
))
1074 return PTR_ERR(sppctl
->first_base
);
1076 sppctl
->moon1_base
= devm_platform_ioremap_resource_byname(pdev
, "moon1");
1077 if (IS_ERR(sppctl
->moon1_base
))
1078 return PTR_ERR(sppctl
->moon1_base
);
1083 static int sppctl_probe(struct platform_device
*pdev
)
1085 struct sppctl_pdata
*sppctl
;
1088 sppctl
= devm_kzalloc(&pdev
->dev
, sizeof(*sppctl
), GFP_KERNEL
);
1091 platform_set_drvdata(pdev
, sppctl
);
1093 ret
= sppctl_resource_map(pdev
, sppctl
);
1097 ret
= sppctl_gpio_new(pdev
, sppctl
);
1101 ret
= sppctl_pinctrl_init(pdev
);
1105 pinctrl_add_gpio_range(sppctl
->pctl_dev
, &sppctl
->pctl_grange
);
1110 static const struct of_device_id sppctl_match_table
[] = {
1111 { .compatible
= "sunplus,sp7021-pctl" },
1115 static struct platform_driver sppctl_pinctrl_driver
= {
1117 .name
= SPPCTL_MODULE_NAME
,
1118 .of_match_table
= sppctl_match_table
,
1120 .probe
= sppctl_probe
,
1122 builtin_platform_driver(sppctl_pinctrl_driver
)
1124 MODULE_AUTHOR("Dvorkin Dmitry <dvorkin@tibbo.com>");
1125 MODULE_AUTHOR("Wells Lu <wellslutw@gmail.com>");
1126 MODULE_DESCRIPTION("Sunplus SP7021 Pin Control and GPIO driver");
1127 MODULE_LICENSE("GPL v2");