drivers/pmdomain/mediatek/mt8167-pm-domains.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
   4 #define __SOC_MEDIATEK_MT8167_PM_DOMAINS_H
   5
   6 #include "mtk-pm-domains.h"
   7 #include <dt-bindings/power/mt8167-power.h>
   8
   9 #define MT8167_PWR_STATUS_MFG_2D        BIT(24)
  10 #define MT8167_PWR_STATUS_MFG_ASYNC     BIT(25)
  11
  12 /*
  13  * MT8167 power domain support
  14  */
  15
  16 static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = {
  17         [MT8167_POWER_DOMAIN_MM] = {
  18                 .name = "mm",
  19                 .sta_mask = PWR_STATUS_DISP,
  20                 .ctl_offs = SPM_DIS_PWR_CON,
  21                 .pwr_sta_offs = SPM_PWR_STATUS,
  22                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  23                 .sram_pdn_bits = GENMASK(11, 8),
  24                 .sram_pdn_ack_bits = GENMASK(12, 12),
  25                 .bp_cfg = {
  26                         BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MM_EMI |
  27                                                      MT8167_TOP_AXI_PROT_EN_MCU_MM),
  28                 },
  29                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
  30         },
  31         [MT8167_POWER_DOMAIN_VDEC] = {
  32                 .name = "vdec",
  33                 .sta_mask = PWR_STATUS_VDEC,
  34                 .ctl_offs = SPM_VDE_PWR_CON,
  35                 .pwr_sta_offs = SPM_PWR_STATUS,
  36                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  37                 .sram_pdn_bits = GENMASK(8, 8),
  38                 .sram_pdn_ack_bits = GENMASK(12, 12),
  39                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
  40         },
  41         [MT8167_POWER_DOMAIN_ISP] = {
  42                 .name = "isp",
  43                 .sta_mask = PWR_STATUS_ISP,
  44                 .ctl_offs = SPM_ISP_PWR_CON,
  45                 .pwr_sta_offs = SPM_PWR_STATUS,
  46                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  47                 .sram_pdn_bits = GENMASK(11, 8),
  48                 .sram_pdn_ack_bits = GENMASK(13, 12),
  49                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
  50         },
  51         [MT8167_POWER_DOMAIN_MFG_ASYNC] = {
  52                 .name = "mfg_async",
  53                 .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC,
  54                 .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
  55                 .pwr_sta_offs = SPM_PWR_STATUS,
  56                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  57                 .sram_pdn_bits = 0,
  58                 .sram_pdn_ack_bits = 0,
  59                 .bp_cfg = {
  60                         BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_MCU_MFG |
  61                                                      MT8167_TOP_AXI_PROT_EN_MFG_EMI),
  62                 },
  63         },
  64         [MT8167_POWER_DOMAIN_MFG_2D] = {
  65                 .name = "mfg_2d",
  66                 .sta_mask = MT8167_PWR_STATUS_MFG_2D,
  67                 .ctl_offs = SPM_MFG_2D_PWR_CON,
  68                 .pwr_sta_offs = SPM_PWR_STATUS,
  69                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  70                 .sram_pdn_bits = GENMASK(11, 8),
  71                 .sram_pdn_ack_bits = GENMASK(15, 12),
  72         },
  73         [MT8167_POWER_DOMAIN_MFG] = {
  74                 .name = "mfg",
  75                 .sta_mask = PWR_STATUS_MFG,
  76                 .ctl_offs = SPM_MFG_PWR_CON,
  77                 .pwr_sta_offs = SPM_PWR_STATUS,
  78                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  79                 .sram_pdn_bits = GENMASK(11, 8),
  80                 .sram_pdn_ack_bits = GENMASK(15, 12),
  81         },
  82         [MT8167_POWER_DOMAIN_CONN] = {
  83                 .name = "conn",
  84                 .sta_mask = PWR_STATUS_CONN,
  85                 .ctl_offs = SPM_CONN_PWR_CON,
  86                 .pwr_sta_offs = SPM_PWR_STATUS,
  87                 .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND,
  88                 .sram_pdn_bits = GENMASK(8, 8),
  89                 .sram_pdn_ack_bits = 0,
  90                 .caps = MTK_SCPD_ACTIVE_WAKEUP,
  91                 .bp_cfg = {
  92                         BUS_PROT_INFRA_UPDATE_TOPAXI(MT8167_TOP_AXI_PROT_EN_CONN_EMI |
  93                                                      MT8167_TOP_AXI_PROT_EN_CONN_MCU |
  94                                                      MT8167_TOP_AXI_PROT_EN_MCU_CONN),
  95                 },
  96         },
  97 };
  98
  99 static const struct scpsys_soc_data mt8167_scpsys_data = {
 100         .domains_data = scpsys_domain_data_mt8167,
 101         .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167),
 102 };
 103
 104 #endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */
 105