?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
drm/nouveau: fix kernel-doc comments
[drm/drm-misc.git] / drivers / regulator / mt6359-regulator.c
blobc8a788858824909cf5de4e5fb75b80e151d1e9d2
1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright (c) 2021 MediaTek Inc.
4
5 #include <linux/platform_device.h>
6 #include <linux/mfd/mt6359/registers.h>
7 #include <linux/mfd/mt6359p/registers.h>
8 #include <linux/mfd/mt6397/core.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/regmap.h>
12 #include <linux/regulator/driver.h>
13 #include <linux/regulator/machine.h>
14 #include <linux/regulator/mt6359-regulator.h>
15 #include <linux/regulator/of_regulator.h>
16
17 #define MT6359_BUCK_MODE_AUTO 0
18 #define MT6359_BUCK_MODE_FORCE_PWM 1
19 #define MT6359_BUCK_MODE_NORMAL 0
20 #define MT6359_BUCK_MODE_LP 2
21
22 /*
23 * MT6359 regulators' information
24 *
25 * @desc: standard fields of regulator description.
26 * @status_reg: for query status of regulators.
27 * @qi: Mask for query enable signal status of regulators.
28 * @modeset_reg: for operating AUTO/PWM mode register.
29 * @modeset_mask: MASK for operating modeset register.
30 */
31 struct mt6359_regulator_info {
32 struct regulator_desc desc;
33 u32 status_reg;
34 u32 qi;
35 u32 modeset_reg;
36 u32 modeset_mask;
37 u32 lp_mode_reg;
38 u32 lp_mode_mask;
39 };
40
41 #define MT6359_BUCK(match, _name, min, max, step, \
42 _enable_reg, _status_reg, \
43 _vsel_reg, _vsel_mask, \
44 _lp_mode_reg, _lp_mode_shift, \
45 _modeset_reg, _modeset_shift) \
46 [MT6359_ID_##_name] = { \
47 .desc = { \
48 .name = #_name, \
49 .of_match = of_match_ptr(match), \
50 .regulators_node = of_match_ptr("regulators"), \
51 .ops = &mt6359_volt_linear_ops, \
52 .type = REGULATOR_VOLTAGE, \
53 .id = MT6359_ID_##_name, \
54 .owner = THIS_MODULE, \
55 .uV_step = (step), \
56 .n_voltages = ((max) - (min)) / (step) + 1, \
57 .min_uV = (min), \
58 .vsel_reg = _vsel_reg, \
59 .vsel_mask = _vsel_mask, \
60 .enable_reg = _enable_reg, \
61 .enable_mask = BIT(0), \
62 .of_map_mode = mt6359_map_mode, \
63 }, \
64 .status_reg = _status_reg, \
65 .qi = BIT(0), \
66 .lp_mode_reg = _lp_mode_reg, \
67 .lp_mode_mask = BIT(_lp_mode_shift), \
68 .modeset_reg = _modeset_reg, \
69 .modeset_mask = BIT(_modeset_shift), \
70 }
71
72 #define MT6359_LDO_LINEAR(match, _name, min, max, step, \
73 _enable_reg, _status_reg, _vsel_reg, _vsel_mask) \
74 [MT6359_ID_##_name] = { \
75 .desc = { \
76 .name = #_name, \
77 .of_match = of_match_ptr(match), \
78 .regulators_node = of_match_ptr("regulators"), \
79 .ops = &mt6359_volt_linear_ops, \
80 .type = REGULATOR_VOLTAGE, \
81 .id = MT6359_ID_##_name, \
82 .owner = THIS_MODULE, \
83 .uV_step = (step), \
84 .n_voltages = ((max) - (min)) / (step) + 1, \
85 .min_uV = (min), \
86 .vsel_reg = _vsel_reg, \
87 .vsel_mask = _vsel_mask, \
88 .enable_reg = _enable_reg, \
89 .enable_mask = BIT(0), \
90 }, \
91 .status_reg = _status_reg, \
92 .qi = BIT(0), \
93 }
94
95 #define MT6359_LDO(match, _name, _volt_table, \
96 _enable_reg, _enable_mask, _status_reg, \
97 _vsel_reg, _vsel_mask, _en_delay) \
98 [MT6359_ID_##_name] = { \
99 .desc = { \
100 .name = #_name, \
101 .of_match = of_match_ptr(match), \
102 .regulators_node = of_match_ptr("regulators"), \
103 .ops = &mt6359_volt_table_ops, \
104 .type = REGULATOR_VOLTAGE, \
105 .id = MT6359_ID_##_name, \
106 .owner = THIS_MODULE, \
107 .n_voltages = ARRAY_SIZE(_volt_table), \
108 .volt_table = _volt_table, \
109 .vsel_reg = _vsel_reg, \
110 .vsel_mask = _vsel_mask, \
111 .enable_reg = _enable_reg, \
112 .enable_mask = BIT(_enable_mask), \
113 .enable_time = _en_delay, \
114 }, \
115 .status_reg = _status_reg, \
116 .qi = BIT(0), \
117 }
118
119 #define MT6359_REG_FIXED(match, _name, _enable_reg, \
120 _status_reg, _fixed_volt) \
121 [MT6359_ID_##_name] = { \
122 .desc = { \
123 .name = #_name, \
124 .of_match = of_match_ptr(match), \
125 .regulators_node = of_match_ptr("regulators"), \
126 .ops = &mt6359_volt_fixed_ops, \
127 .type = REGULATOR_VOLTAGE, \
128 .id = MT6359_ID_##_name, \
129 .owner = THIS_MODULE, \
130 .n_voltages = 1, \
131 .enable_reg = _enable_reg, \
132 .enable_mask = BIT(0), \
133 .fixed_uV = (_fixed_volt), \
134 }, \
135 .status_reg = _status_reg, \
136 .qi = BIT(0), \
137 }
138
139 #define MT6359P_LDO1(match, _name, _ops, _volt_table, \
140 _enable_reg, _enable_mask, _status_reg, \
141 _vsel_reg, _vsel_mask) \
142 [MT6359_ID_##_name] = { \
143 .desc = { \
144 .name = #_name, \
145 .of_match = of_match_ptr(match), \
146 .regulators_node = of_match_ptr("regulators"), \
147 .ops = &_ops, \
148 .type = REGULATOR_VOLTAGE, \
149 .id = MT6359_ID_##_name, \
150 .owner = THIS_MODULE, \
151 .n_voltages = ARRAY_SIZE(_volt_table), \
152 .volt_table = _volt_table, \
153 .vsel_reg = _vsel_reg, \
154 .vsel_mask = _vsel_mask, \
155 .enable_reg = _enable_reg, \
156 .enable_mask = BIT(_enable_mask), \
157 }, \
158 .status_reg = _status_reg, \
159 .qi = BIT(0), \
160 }
161
162 static const unsigned int vsim1_voltages[] = {
163 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000,
164 };
165
166 static const unsigned int vibr_voltages[] = {
167 1200000, 1300000, 1500000, 0, 1800000, 2000000, 0, 0, 2700000, 2800000,
168 0, 3000000, 0, 3300000,
169 };
170
171 static const unsigned int vrf12_voltages[] = {
172 0, 0, 1100000, 1200000, 1300000,
173 };
174
175 static const unsigned int volt18_voltages[] = {
176 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000,
177 };
178
179 static const unsigned int vcn13_voltages[] = {
180 900000, 1000000, 0, 1200000, 1300000,
181 };
182
183 static const unsigned int vcn33_voltages[] = {
184 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 0, 0, 0, 3300000, 3400000, 3500000,
185 };
186
187 static const unsigned int vefuse_voltages[] = {
188 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1700000, 1800000, 1900000, 2000000,
189 };
190
191 static const unsigned int vxo22_voltages[] = {
192 1800000, 0, 0, 0, 2200000,
193 };
194
195 static const unsigned int vrfck_voltages[] = {
196 0, 0, 1500000, 0, 0, 0, 0, 1600000, 0, 0, 0, 0, 1700000,
197 };
198
199 static const unsigned int vrfck_voltages_1[] = {
200 1240000, 1600000,
201 };
202
203 static const unsigned int vio28_voltages[] = {
204 0, 0, 0, 0, 0, 0, 0, 0, 0, 2800000, 2900000, 3000000, 3100000, 3300000,
205 };
206
207 static const unsigned int vemc_voltages[] = {
208 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2900000, 3000000, 0, 3300000,
209 };
210
211 static const unsigned int vemc_voltages_1[] = {
212 0, 0, 0, 0, 0, 0, 0, 0, 2500000, 2800000, 2900000, 3000000, 3100000,
213 3300000,
214 };
215
216 static const unsigned int va12_voltages[] = {
217 0, 0, 0, 0, 0, 0, 1200000, 1300000,
218 };
219
220 static const unsigned int va09_voltages[] = {
221 0, 0, 800000, 900000, 0, 0, 1200000,
222 };
223
224 static const unsigned int vrf18_voltages[] = {
225 0, 0, 0, 0, 0, 1700000, 1800000, 1810000,
226 };
227
228 static const unsigned int vbbck_voltages[] = {
229 0, 0, 0, 0, 1100000, 0, 0, 0, 1150000, 0, 0, 0, 1200000,
230 };
231
232 static const unsigned int vsim2_voltages[] = {
233 0, 0, 0, 1700000, 1800000, 0, 0, 0, 2700000, 0, 0, 3000000, 3100000,
234 };
235
236 static inline unsigned int mt6359_map_mode(unsigned int mode)
237 {
238 switch (mode) {
239 case MT6359_BUCK_MODE_NORMAL:
240 return REGULATOR_MODE_NORMAL;
241 case MT6359_BUCK_MODE_FORCE_PWM:
242 return REGULATOR_MODE_FAST;
243 case MT6359_BUCK_MODE_LP:
244 return REGULATOR_MODE_IDLE;
245 default:
246 return REGULATOR_MODE_INVALID;
247 }
248 }
249
250 static int mt6359_get_status(struct regulator_dev *rdev)
251 {
252 int ret;
253 u32 regval;
254 struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
255
256 ret = regmap_read(rdev->regmap, info->status_reg, &regval);
257 if (ret != 0) {
258 dev_err(&rdev->dev, "Failed to get enable reg: %d\n", ret);
259 return ret;
260 }
261
262 if (regval & info->qi)
263 return REGULATOR_STATUS_ON;
264 else
265 return REGULATOR_STATUS_OFF;
266 }
267
268 static unsigned int mt6359_regulator_get_mode(struct regulator_dev *rdev)
269 {
270 struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
271 int ret, regval;
272
273 ret = regmap_read(rdev->regmap, info->modeset_reg, &regval);
274 if (ret != 0) {
275 dev_err(&rdev->dev,
276 "Failed to get mt6359 buck mode: %d\n", ret);
277 return ret;
278 }
279
280 regval &= info->modeset_mask;
281 regval >>= ffs(info->modeset_mask) - 1;
282
283 if (regval == MT6359_BUCK_MODE_FORCE_PWM)
284 return REGULATOR_MODE_FAST;
285
286 ret = regmap_read(rdev->regmap, info->lp_mode_reg, &regval);
287 if (ret != 0) {
288 dev_err(&rdev->dev,
289 "Failed to get mt6359 buck lp mode: %d\n", ret);
290 return ret;
291 }
292
293 if (regval & info->lp_mode_mask)
294 return REGULATOR_MODE_IDLE;
295 else
296 return REGULATOR_MODE_NORMAL;
297 }
298
299 static int mt6359_regulator_set_mode(struct regulator_dev *rdev,
300 unsigned int mode)
301 {
302 struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
303 int ret = 0, val;
304 int curr_mode;
305
306 curr_mode = mt6359_regulator_get_mode(rdev);
307 switch (mode) {
308 case REGULATOR_MODE_FAST:
309 val = MT6359_BUCK_MODE_FORCE_PWM;
310 val <<= ffs(info->modeset_mask) - 1;
311 ret = regmap_update_bits(rdev->regmap,
312 info->modeset_reg,
313 info->modeset_mask,
314 val);
315 break;
316 case REGULATOR_MODE_NORMAL:
317 if (curr_mode == REGULATOR_MODE_FAST) {
318 val = MT6359_BUCK_MODE_AUTO;
319 val <<= ffs(info->modeset_mask) - 1;
320 ret = regmap_update_bits(rdev->regmap,
321 info->modeset_reg,
322 info->modeset_mask,
323 val);
324 } else if (curr_mode == REGULATOR_MODE_IDLE) {
325 val = MT6359_BUCK_MODE_NORMAL;
326 val <<= ffs(info->lp_mode_mask) - 1;
327 ret = regmap_update_bits(rdev->regmap,
328 info->lp_mode_reg,
329 info->lp_mode_mask,
330 val);
331 udelay(100);
332 }
333 break;
334 case REGULATOR_MODE_IDLE:
335 val = MT6359_BUCK_MODE_LP >> 1;
336 val <<= ffs(info->lp_mode_mask) - 1;
337 ret = regmap_update_bits(rdev->regmap,
338 info->lp_mode_reg,
339 info->lp_mode_mask,
340 val);
341 break;
342 default:
343 return -EINVAL;
344 }
345
346 if (ret != 0) {
347 dev_err(&rdev->dev,
348 "Failed to set mt6359 buck mode: %d\n", ret);
349 }
350
351 return ret;
352 }
353
354 static int mt6359p_vemc_set_voltage_sel(struct regulator_dev *rdev,
355 u32 sel)
356 {
357 struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
358 int ret;
359 u32 val = 0;
360
361 sel <<= ffs(info->desc.vsel_mask) - 1;
362 ret = regmap_write(rdev->regmap, MT6359P_TMA_KEY_ADDR, TMA_KEY);
363 if (ret)
364 return ret;
365
366 ret = regmap_read(rdev->regmap, MT6359P_VM_MODE_ADDR, &val);
367 if (ret)
368 return ret;
369
370 switch (val) {
371 case 0:
372 /* If HW trapping is 0, use VEMC_VOSEL_0 */
373 ret = regmap_update_bits(rdev->regmap,
374 info->desc.vsel_reg,
375 info->desc.vsel_mask, sel);
376 break;
377 case 1:
378 /* If HW trapping is 1, use VEMC_VOSEL_1 */
379 ret = regmap_update_bits(rdev->regmap,
380 info->desc.vsel_reg + 0x2,
381 info->desc.vsel_mask, sel);
382 break;
383 default:
384 return -EINVAL;
385 }
386
387 if (ret)
388 return ret;
389
390 ret = regmap_write(rdev->regmap, MT6359P_TMA_KEY_ADDR, 0);
391 return ret;
392 }
393
394 static int mt6359p_vemc_get_voltage_sel(struct regulator_dev *rdev)
395 {
396 struct mt6359_regulator_info *info = rdev_get_drvdata(rdev);
397 int ret;
398 u32 val = 0;
399
400 ret = regmap_read(rdev->regmap, MT6359P_VM_MODE_ADDR, &val);
401 if (ret)
402 return ret;
403 switch (val) {
404 case 0:
405 /* If HW trapping is 0, use VEMC_VOSEL_0 */
406 ret = regmap_read(rdev->regmap,
407 info->desc.vsel_reg, &val);
408 break;
409 case 1:
410 /* If HW trapping is 1, use VEMC_VOSEL_1 */
411 ret = regmap_read(rdev->regmap,
412 info->desc.vsel_reg + 0x2, &val);
413 break;
414 default:
415 return -EINVAL;
416 }
417 if (ret)
418 return ret;
419
420 val &= info->desc.vsel_mask;
421 val >>= ffs(info->desc.vsel_mask) - 1;
422
423 return val;
424 }
425
426 static const struct regulator_ops mt6359_volt_linear_ops = {
427 .list_voltage = regulator_list_voltage_linear,
428 .map_voltage = regulator_map_voltage_linear,
429 .set_voltage_sel = regulator_set_voltage_sel_regmap,
430 .get_voltage_sel = regulator_get_voltage_sel_regmap,
431 .set_voltage_time_sel = regulator_set_voltage_time_sel,
432 .enable = regulator_enable_regmap,
433 .disable = regulator_disable_regmap,
434 .is_enabled = regulator_is_enabled_regmap,
435 .get_status = mt6359_get_status,
436 .set_mode = mt6359_regulator_set_mode,
437 .get_mode = mt6359_regulator_get_mode,
438 };
439
440 static const struct regulator_ops mt6359_volt_table_ops = {
441 .list_voltage = regulator_list_voltage_table,
442 .map_voltage = regulator_map_voltage_iterate,
443 .set_voltage_sel = regulator_set_voltage_sel_regmap,
444 .get_voltage_sel = regulator_get_voltage_sel_regmap,
445 .set_voltage_time_sel = regulator_set_voltage_time_sel,
446 .enable = regulator_enable_regmap,
447 .disable = regulator_disable_regmap,
448 .is_enabled = regulator_is_enabled_regmap,
449 .get_status = mt6359_get_status,
450 };
451
452 static const struct regulator_ops mt6359_volt_fixed_ops = {
453 .enable = regulator_enable_regmap,
454 .disable = regulator_disable_regmap,
455 .is_enabled = regulator_is_enabled_regmap,
456 .get_status = mt6359_get_status,
457 };
458
459 static const struct regulator_ops mt6359p_vemc_ops = {
460 .list_voltage = regulator_list_voltage_table,
461 .map_voltage = regulator_map_voltage_iterate,
462 .set_voltage_sel = mt6359p_vemc_set_voltage_sel,
463 .get_voltage_sel = mt6359p_vemc_get_voltage_sel,
464 .set_voltage_time_sel = regulator_set_voltage_time_sel,
465 .enable = regulator_enable_regmap,
466 .disable = regulator_disable_regmap,
467 .is_enabled = regulator_is_enabled_regmap,
468 .get_status = mt6359_get_status,
469 };
470
471 /* The array is indexed by id(MT6359_ID_XXX) */
472 static struct mt6359_regulator_info mt6359_regulators[] = {
473 MT6359_BUCK("buck_vs1", VS1, 800000, 2200000, 12500,
474 MT6359_RG_BUCK_VS1_EN_ADDR,
475 MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR,
476 MT6359_RG_BUCK_VS1_VOSEL_MASK <<
477 MT6359_RG_BUCK_VS1_VOSEL_SHIFT,
478 MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT,
479 MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT),
480 MT6359_BUCK("buck_vgpu11", VGPU11, 400000, 1193750, 6250,
481 MT6359_RG_BUCK_VGPU11_EN_ADDR,
482 MT6359_DA_VGPU11_EN_ADDR, MT6359_RG_BUCK_VGPU11_VOSEL_ADDR,
483 MT6359_RG_BUCK_VGPU11_VOSEL_MASK <<
484 MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT,
485 MT6359_RG_BUCK_VGPU11_LP_ADDR,
486 MT6359_RG_BUCK_VGPU11_LP_SHIFT,
487 MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT),
488 MT6359_BUCK("buck_vmodem", VMODEM, 400000, 1100000, 6250,
489 MT6359_RG_BUCK_VMODEM_EN_ADDR,
490 MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR,
491 MT6359_RG_BUCK_VMODEM_VOSEL_MASK <<
492 MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT,
493 MT6359_RG_BUCK_VMODEM_LP_ADDR,
494 MT6359_RG_BUCK_VMODEM_LP_SHIFT,
495 MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT),
496 MT6359_BUCK("buck_vpu", VPU, 400000, 1193750, 6250,
497 MT6359_RG_BUCK_VPU_EN_ADDR,
498 MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR,
499 MT6359_RG_BUCK_VPU_VOSEL_MASK <<
500 MT6359_RG_BUCK_VPU_VOSEL_SHIFT,
501 MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT,
502 MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT),
503 MT6359_BUCK("buck_vcore", VCORE, 400000, 1193750, 6250,
504 MT6359_RG_BUCK_VCORE_EN_ADDR,
505 MT6359_DA_VCORE_EN_ADDR, MT6359_RG_BUCK_VCORE_VOSEL_ADDR,
506 MT6359_RG_BUCK_VCORE_VOSEL_MASK <<
507 MT6359_RG_BUCK_VCORE_VOSEL_SHIFT,
508 MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT,
509 MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT),
510 MT6359_BUCK("buck_vs2", VS2, 800000, 1600000, 12500,
511 MT6359_RG_BUCK_VS2_EN_ADDR,
512 MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR,
513 MT6359_RG_BUCK_VS2_VOSEL_MASK <<
514 MT6359_RG_BUCK_VS2_VOSEL_SHIFT,
515 MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT,
516 MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT),
517 MT6359_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
518 MT6359_RG_BUCK_VPA_EN_ADDR,
519 MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR,
520 MT6359_RG_BUCK_VPA_VOSEL_MASK <<
521 MT6359_RG_BUCK_VPA_VOSEL_SHIFT,
522 MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT,
523 MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT),
524 MT6359_BUCK("buck_vproc2", VPROC2, 400000, 1193750, 6250,
525 MT6359_RG_BUCK_VPROC2_EN_ADDR,
526 MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR,
527 MT6359_RG_BUCK_VPROC2_VOSEL_MASK <<
528 MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT,
529 MT6359_RG_BUCK_VPROC2_LP_ADDR,
530 MT6359_RG_BUCK_VPROC2_LP_SHIFT,
531 MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT),
532 MT6359_BUCK("buck_vproc1", VPROC1, 400000, 1193750, 6250,
533 MT6359_RG_BUCK_VPROC1_EN_ADDR,
534 MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR,
535 MT6359_RG_BUCK_VPROC1_VOSEL_MASK <<
536 MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT,
537 MT6359_RG_BUCK_VPROC1_LP_ADDR,
538 MT6359_RG_BUCK_VPROC1_LP_SHIFT,
539 MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT),
540 MT6359_BUCK("buck_vcore_sshub", VCORE_SSHUB, 400000, 1193750, 6250,
541 MT6359_RG_BUCK_VCORE_SSHUB_EN_ADDR,
542 MT6359_DA_VCORE_EN_ADDR,
543 MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_ADDR,
544 MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_MASK <<
545 MT6359_RG_BUCK_VCORE_SSHUB_VOSEL_SHIFT,
546 MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT,
547 MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT),
548 MT6359_REG_FIXED("ldo_vaud18", VAUD18, MT6359_RG_LDO_VAUD18_EN_ADDR,
549 MT6359_DA_VAUD18_B_EN_ADDR, 1800000),
550 MT6359_LDO("ldo_vsim1", VSIM1, vsim1_voltages,
551 MT6359_RG_LDO_VSIM1_EN_ADDR, MT6359_RG_LDO_VSIM1_EN_SHIFT,
552 MT6359_DA_VSIM1_B_EN_ADDR, MT6359_RG_VSIM1_VOSEL_ADDR,
553 MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT,
554 480),
555 MT6359_LDO("ldo_vibr", VIBR, vibr_voltages,
556 MT6359_RG_LDO_VIBR_EN_ADDR, MT6359_RG_LDO_VIBR_EN_SHIFT,
557 MT6359_DA_VIBR_B_EN_ADDR, MT6359_RG_VIBR_VOSEL_ADDR,
558 MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT,
559 240),
560 MT6359_LDO("ldo_vrf12", VRF12, vrf12_voltages,
561 MT6359_RG_LDO_VRF12_EN_ADDR, MT6359_RG_LDO_VRF12_EN_SHIFT,
562 MT6359_DA_VRF12_B_EN_ADDR, MT6359_RG_VRF12_VOSEL_ADDR,
563 MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT,
564 120),
565 MT6359_REG_FIXED("ldo_vusb", VUSB, MT6359_RG_LDO_VUSB_EN_0_ADDR,
566 MT6359_DA_VUSB_B_EN_ADDR, 3000000),
567 MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1293750, 6250,
568 MT6359_RG_LDO_VSRAM_PROC2_EN_ADDR,
569 MT6359_DA_VSRAM_PROC2_B_EN_ADDR,
570 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_ADDR,
571 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK <<
572 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT),
573 MT6359_LDO("ldo_vio18", VIO18, volt18_voltages,
574 MT6359_RG_LDO_VIO18_EN_ADDR, MT6359_RG_LDO_VIO18_EN_SHIFT,
575 MT6359_DA_VIO18_B_EN_ADDR, MT6359_RG_VIO18_VOSEL_ADDR,
576 MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT,
577 960),
578 MT6359_LDO("ldo_vcamio", VCAMIO, volt18_voltages,
579 MT6359_RG_LDO_VCAMIO_EN_ADDR, MT6359_RG_LDO_VCAMIO_EN_SHIFT,
580 MT6359_DA_VCAMIO_B_EN_ADDR, MT6359_RG_VCAMIO_VOSEL_ADDR,
581 MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT,
582 1290),
583 MT6359_REG_FIXED("ldo_vcn18", VCN18, MT6359_RG_LDO_VCN18_EN_ADDR,
584 MT6359_DA_VCN18_B_EN_ADDR, 1800000),
585 MT6359_REG_FIXED("ldo_vfe28", VFE28, MT6359_RG_LDO_VFE28_EN_ADDR,
586 MT6359_DA_VFE28_B_EN_ADDR, 2800000),
587 MT6359_LDO("ldo_vcn13", VCN13, vcn13_voltages,
588 MT6359_RG_LDO_VCN13_EN_ADDR, MT6359_RG_LDO_VCN13_EN_SHIFT,
589 MT6359_DA_VCN13_B_EN_ADDR, MT6359_RG_VCN13_VOSEL_ADDR,
590 MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT,
591 240),
592 MT6359_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages,
593 MT6359_RG_LDO_VCN33_1_EN_0_ADDR,
594 MT6359_RG_LDO_VCN33_1_EN_0_SHIFT,
595 MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR,
596 MT6359_RG_VCN33_1_VOSEL_MASK <<
597 MT6359_RG_VCN33_1_VOSEL_SHIFT, 240),
598 MT6359_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages,
599 MT6359_RG_LDO_VCN33_1_EN_1_ADDR,
600 MT6359_RG_LDO_VCN33_1_EN_1_SHIFT,
601 MT6359_DA_VCN33_1_B_EN_ADDR, MT6359_RG_VCN33_1_VOSEL_ADDR,
602 MT6359_RG_VCN33_1_VOSEL_MASK <<
603 MT6359_RG_VCN33_1_VOSEL_SHIFT, 240),
604 MT6359_REG_FIXED("ldo_vaux18", VAUX18, MT6359_RG_LDO_VAUX18_EN_ADDR,
605 MT6359_DA_VAUX18_B_EN_ADDR, 1800000),
606 MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750,
607 6250,
608 MT6359_RG_LDO_VSRAM_OTHERS_EN_ADDR,
609 MT6359_DA_VSRAM_OTHERS_B_EN_ADDR,
610 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR,
611 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK <<
612 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT),
613 MT6359_LDO("ldo_vefuse", VEFUSE, vefuse_voltages,
614 MT6359_RG_LDO_VEFUSE_EN_ADDR, MT6359_RG_LDO_VEFUSE_EN_SHIFT,
615 MT6359_DA_VEFUSE_B_EN_ADDR, MT6359_RG_VEFUSE_VOSEL_ADDR,
616 MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT,
617 240),
618 MT6359_LDO("ldo_vxo22", VXO22, vxo22_voltages,
619 MT6359_RG_LDO_VXO22_EN_ADDR, MT6359_RG_LDO_VXO22_EN_SHIFT,
620 MT6359_DA_VXO22_B_EN_ADDR, MT6359_RG_VXO22_VOSEL_ADDR,
621 MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT,
622 120),
623 MT6359_LDO("ldo_vrfck", VRFCK, vrfck_voltages,
624 MT6359_RG_LDO_VRFCK_EN_ADDR, MT6359_RG_LDO_VRFCK_EN_SHIFT,
625 MT6359_DA_VRFCK_B_EN_ADDR, MT6359_RG_VRFCK_VOSEL_ADDR,
626 MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT,
627 480),
628 MT6359_REG_FIXED("ldo_vbif28", VBIF28, MT6359_RG_LDO_VBIF28_EN_ADDR,
629 MT6359_DA_VBIF28_B_EN_ADDR, 2800000),
630 MT6359_LDO("ldo_vio28", VIO28, vio28_voltages,
631 MT6359_RG_LDO_VIO28_EN_ADDR, MT6359_RG_LDO_VIO28_EN_SHIFT,
632 MT6359_DA_VIO28_B_EN_ADDR, MT6359_RG_VIO28_VOSEL_ADDR,
633 MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT,
634 240),
635 MT6359_LDO("ldo_vemc", VEMC, vemc_voltages,
636 MT6359_RG_LDO_VEMC_EN_ADDR, MT6359_RG_LDO_VEMC_EN_SHIFT,
637 MT6359_DA_VEMC_B_EN_ADDR, MT6359_RG_VEMC_VOSEL_ADDR,
638 MT6359_RG_VEMC_VOSEL_MASK << MT6359_RG_VEMC_VOSEL_SHIFT,
639 240),
640 MT6359_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages,
641 MT6359_RG_LDO_VCN33_2_EN_0_ADDR,
642 MT6359_RG_LDO_VCN33_2_EN_0_SHIFT,
643 MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR,
644 MT6359_RG_VCN33_2_VOSEL_MASK <<
645 MT6359_RG_VCN33_2_VOSEL_SHIFT, 240),
646 MT6359_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages,
647 MT6359_RG_LDO_VCN33_2_EN_1_ADDR,
648 MT6359_RG_LDO_VCN33_2_EN_1_SHIFT,
649 MT6359_DA_VCN33_2_B_EN_ADDR, MT6359_RG_VCN33_2_VOSEL_ADDR,
650 MT6359_RG_VCN33_2_VOSEL_MASK <<
651 MT6359_RG_VCN33_2_VOSEL_SHIFT, 240),
652 MT6359_LDO("ldo_va12", VA12, va12_voltages,
653 MT6359_RG_LDO_VA12_EN_ADDR, MT6359_RG_LDO_VA12_EN_SHIFT,
654 MT6359_DA_VA12_B_EN_ADDR, MT6359_RG_VA12_VOSEL_ADDR,
655 MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT,
656 240),
657 MT6359_LDO("ldo_va09", VA09, va09_voltages,
658 MT6359_RG_LDO_VA09_EN_ADDR, MT6359_RG_LDO_VA09_EN_SHIFT,
659 MT6359_DA_VA09_B_EN_ADDR, MT6359_RG_VA09_VOSEL_ADDR,
660 MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT,
661 240),
662 MT6359_LDO("ldo_vrf18", VRF18, vrf18_voltages,
663 MT6359_RG_LDO_VRF18_EN_ADDR, MT6359_RG_LDO_VRF18_EN_SHIFT,
664 MT6359_DA_VRF18_B_EN_ADDR, MT6359_RG_VRF18_VOSEL_ADDR,
665 MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT,
666 120),
667 MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1100000, 6250,
668 MT6359_RG_LDO_VSRAM_MD_EN_ADDR,
669 MT6359_DA_VSRAM_MD_B_EN_ADDR,
670 MT6359_RG_LDO_VSRAM_MD_VOSEL_ADDR,
671 MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK <<
672 MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT),
673 MT6359_LDO("ldo_vufs", VUFS, volt18_voltages,
674 MT6359_RG_LDO_VUFS_EN_ADDR, MT6359_RG_LDO_VUFS_EN_SHIFT,
675 MT6359_DA_VUFS_B_EN_ADDR, MT6359_RG_VUFS_VOSEL_ADDR,
676 MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT,
677 1920),
678 MT6359_LDO("ldo_vm18", VM18, volt18_voltages,
679 MT6359_RG_LDO_VM18_EN_ADDR, MT6359_RG_LDO_VM18_EN_SHIFT,
680 MT6359_DA_VM18_B_EN_ADDR, MT6359_RG_VM18_VOSEL_ADDR,
681 MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT,
682 1920),
683 MT6359_LDO("ldo_vbbck", VBBCK, vbbck_voltages,
684 MT6359_RG_LDO_VBBCK_EN_ADDR, MT6359_RG_LDO_VBBCK_EN_SHIFT,
685 MT6359_DA_VBBCK_B_EN_ADDR, MT6359_RG_VBBCK_VOSEL_ADDR,
686 MT6359_RG_VBBCK_VOSEL_MASK << MT6359_RG_VBBCK_VOSEL_SHIFT,
687 240),
688 MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1293750, 6250,
689 MT6359_RG_LDO_VSRAM_PROC1_EN_ADDR,
690 MT6359_DA_VSRAM_PROC1_B_EN_ADDR,
691 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_ADDR,
692 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK <<
693 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT),
694 MT6359_LDO("ldo_vsim2", VSIM2, vsim2_voltages,
695 MT6359_RG_LDO_VSIM2_EN_ADDR, MT6359_RG_LDO_VSIM2_EN_SHIFT,
696 MT6359_DA_VSIM2_B_EN_ADDR, MT6359_RG_VSIM2_VOSEL_ADDR,
697 MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT,
698 480),
699 MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB,
700 500000, 1293750, 6250,
701 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR,
702 MT6359_DA_VSRAM_OTHERS_B_EN_ADDR,
703 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR,
704 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK <<
705 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT),
706 };
707
708 static struct mt6359_regulator_info mt6359p_regulators[] = {
709 MT6359_BUCK("buck_vs1", VS1, 800000, 2200000, 12500,
710 MT6359_RG_BUCK_VS1_EN_ADDR,
711 MT6359_DA_VS1_EN_ADDR, MT6359_RG_BUCK_VS1_VOSEL_ADDR,
712 MT6359_RG_BUCK_VS1_VOSEL_MASK <<
713 MT6359_RG_BUCK_VS1_VOSEL_SHIFT,
714 MT6359_RG_BUCK_VS1_LP_ADDR, MT6359_RG_BUCK_VS1_LP_SHIFT,
715 MT6359_RG_VS1_FPWM_ADDR, MT6359_RG_VS1_FPWM_SHIFT),
716 MT6359_BUCK("buck_vgpu11", VGPU11, 400000, 1193750, 6250,
717 MT6359_RG_BUCK_VGPU11_EN_ADDR,
718 MT6359_DA_VGPU11_EN_ADDR, MT6359P_RG_BUCK_VGPU11_VOSEL_ADDR,
719 MT6359_RG_BUCK_VGPU11_VOSEL_MASK <<
720 MT6359_RG_BUCK_VGPU11_VOSEL_SHIFT,
721 MT6359_RG_BUCK_VGPU11_LP_ADDR,
722 MT6359_RG_BUCK_VGPU11_LP_SHIFT,
723 MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT),
724 MT6359_BUCK("buck_vmodem", VMODEM, 400000, 1100000, 6250,
725 MT6359_RG_BUCK_VMODEM_EN_ADDR,
726 MT6359_DA_VMODEM_EN_ADDR, MT6359_RG_BUCK_VMODEM_VOSEL_ADDR,
727 MT6359_RG_BUCK_VMODEM_VOSEL_MASK <<
728 MT6359_RG_BUCK_VMODEM_VOSEL_SHIFT,
729 MT6359_RG_BUCK_VMODEM_LP_ADDR,
730 MT6359_RG_BUCK_VMODEM_LP_SHIFT,
731 MT6359_RG_VMODEM_FCCM_ADDR, MT6359_RG_VMODEM_FCCM_SHIFT),
732 MT6359_BUCK("buck_vpu", VPU, 400000, 1193750, 6250,
733 MT6359_RG_BUCK_VPU_EN_ADDR,
734 MT6359_DA_VPU_EN_ADDR, MT6359_RG_BUCK_VPU_VOSEL_ADDR,
735 MT6359_RG_BUCK_VPU_VOSEL_MASK <<
736 MT6359_RG_BUCK_VPU_VOSEL_SHIFT,
737 MT6359_RG_BUCK_VPU_LP_ADDR, MT6359_RG_BUCK_VPU_LP_SHIFT,
738 MT6359_RG_VPU_FCCM_ADDR, MT6359_RG_VPU_FCCM_SHIFT),
739 MT6359_BUCK("buck_vcore", VCORE, 506250, 1300000, 6250,
740 MT6359_RG_BUCK_VCORE_EN_ADDR,
741 MT6359_DA_VCORE_EN_ADDR, MT6359P_RG_BUCK_VCORE_VOSEL_ADDR,
742 MT6359_RG_BUCK_VCORE_VOSEL_MASK <<
743 MT6359_RG_BUCK_VCORE_VOSEL_SHIFT,
744 MT6359_RG_BUCK_VCORE_LP_ADDR, MT6359_RG_BUCK_VCORE_LP_SHIFT,
745 MT6359_RG_VCORE_FCCM_ADDR, MT6359_RG_VCORE_FCCM_SHIFT),
746 MT6359_BUCK("buck_vs2", VS2, 800000, 1600000, 12500,
747 MT6359_RG_BUCK_VS2_EN_ADDR,
748 MT6359_DA_VS2_EN_ADDR, MT6359_RG_BUCK_VS2_VOSEL_ADDR,
749 MT6359_RG_BUCK_VS2_VOSEL_MASK <<
750 MT6359_RG_BUCK_VS2_VOSEL_SHIFT,
751 MT6359_RG_BUCK_VS2_LP_ADDR, MT6359_RG_BUCK_VS2_LP_SHIFT,
752 MT6359_RG_VS2_FPWM_ADDR, MT6359_RG_VS2_FPWM_SHIFT),
753 MT6359_BUCK("buck_vpa", VPA, 500000, 3650000, 50000,
754 MT6359_RG_BUCK_VPA_EN_ADDR,
755 MT6359_DA_VPA_EN_ADDR, MT6359_RG_BUCK_VPA_VOSEL_ADDR,
756 MT6359_RG_BUCK_VPA_VOSEL_MASK <<
757 MT6359_RG_BUCK_VPA_VOSEL_SHIFT,
758 MT6359_RG_BUCK_VPA_LP_ADDR, MT6359_RG_BUCK_VPA_LP_SHIFT,
759 MT6359_RG_VPA_MODESET_ADDR, MT6359_RG_VPA_MODESET_SHIFT),
760 MT6359_BUCK("buck_vproc2", VPROC2, 400000, 1193750, 6250,
761 MT6359_RG_BUCK_VPROC2_EN_ADDR,
762 MT6359_DA_VPROC2_EN_ADDR, MT6359_RG_BUCK_VPROC2_VOSEL_ADDR,
763 MT6359_RG_BUCK_VPROC2_VOSEL_MASK <<
764 MT6359_RG_BUCK_VPROC2_VOSEL_SHIFT,
765 MT6359_RG_BUCK_VPROC2_LP_ADDR,
766 MT6359_RG_BUCK_VPROC2_LP_SHIFT,
767 MT6359_RG_VPROC2_FCCM_ADDR, MT6359_RG_VPROC2_FCCM_SHIFT),
768 MT6359_BUCK("buck_vproc1", VPROC1, 400000, 1193750, 6250,
769 MT6359_RG_BUCK_VPROC1_EN_ADDR,
770 MT6359_DA_VPROC1_EN_ADDR, MT6359_RG_BUCK_VPROC1_VOSEL_ADDR,
771 MT6359_RG_BUCK_VPROC1_VOSEL_MASK <<
772 MT6359_RG_BUCK_VPROC1_VOSEL_SHIFT,
773 MT6359_RG_BUCK_VPROC1_LP_ADDR,
774 MT6359_RG_BUCK_VPROC1_LP_SHIFT,
775 MT6359_RG_VPROC1_FCCM_ADDR, MT6359_RG_VPROC1_FCCM_SHIFT),
776 MT6359_BUCK("buck_vgpu11_sshub", VGPU11_SSHUB, 400000, 1193750, 6250,
777 MT6359P_RG_BUCK_VGPU11_SSHUB_EN_ADDR,
778 MT6359_DA_VGPU11_EN_ADDR,
779 MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_ADDR,
780 MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_MASK <<
781 MT6359P_RG_BUCK_VGPU11_SSHUB_VOSEL_SHIFT,
782 MT6359_RG_BUCK_VGPU11_LP_ADDR,
783 MT6359_RG_BUCK_VGPU11_LP_SHIFT,
784 MT6359_RG_VGPU11_FCCM_ADDR, MT6359_RG_VGPU11_FCCM_SHIFT),
785 MT6359_REG_FIXED("ldo_vaud18", VAUD18, MT6359P_RG_LDO_VAUD18_EN_ADDR,
786 MT6359P_DA_VAUD18_B_EN_ADDR, 1800000),
787 MT6359_LDO("ldo_vsim1", VSIM1, vsim1_voltages,
788 MT6359P_RG_LDO_VSIM1_EN_ADDR, MT6359P_RG_LDO_VSIM1_EN_SHIFT,
789 MT6359P_DA_VSIM1_B_EN_ADDR, MT6359P_RG_VSIM1_VOSEL_ADDR,
790 MT6359_RG_VSIM1_VOSEL_MASK << MT6359_RG_VSIM1_VOSEL_SHIFT,
791 480),
792 MT6359_LDO("ldo_vibr", VIBR, vibr_voltages,
793 MT6359P_RG_LDO_VIBR_EN_ADDR, MT6359P_RG_LDO_VIBR_EN_SHIFT,
794 MT6359P_DA_VIBR_B_EN_ADDR, MT6359P_RG_VIBR_VOSEL_ADDR,
795 MT6359_RG_VIBR_VOSEL_MASK << MT6359_RG_VIBR_VOSEL_SHIFT,
796 240),
797 MT6359_LDO("ldo_vrf12", VRF12, vrf12_voltages,
798 MT6359P_RG_LDO_VRF12_EN_ADDR, MT6359P_RG_LDO_VRF12_EN_SHIFT,
799 MT6359P_DA_VRF12_B_EN_ADDR, MT6359P_RG_VRF12_VOSEL_ADDR,
800 MT6359_RG_VRF12_VOSEL_MASK << MT6359_RG_VRF12_VOSEL_SHIFT,
801 480),
802 MT6359_REG_FIXED("ldo_vusb", VUSB, MT6359P_RG_LDO_VUSB_EN_0_ADDR,
803 MT6359P_DA_VUSB_B_EN_ADDR, 3000000),
804 MT6359_LDO_LINEAR("ldo_vsram_proc2", VSRAM_PROC2, 500000, 1293750, 6250,
805 MT6359P_RG_LDO_VSRAM_PROC2_EN_ADDR,
806 MT6359P_DA_VSRAM_PROC2_B_EN_ADDR,
807 MT6359P_RG_LDO_VSRAM_PROC2_VOSEL_ADDR,
808 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_MASK <<
809 MT6359_RG_LDO_VSRAM_PROC2_VOSEL_SHIFT),
810 MT6359_LDO("ldo_vio18", VIO18, volt18_voltages,
811 MT6359P_RG_LDO_VIO18_EN_ADDR, MT6359P_RG_LDO_VIO18_EN_SHIFT,
812 MT6359P_DA_VIO18_B_EN_ADDR, MT6359P_RG_VIO18_VOSEL_ADDR,
813 MT6359_RG_VIO18_VOSEL_MASK << MT6359_RG_VIO18_VOSEL_SHIFT,
814 960),
815 MT6359_LDO("ldo_vcamio", VCAMIO, volt18_voltages,
816 MT6359P_RG_LDO_VCAMIO_EN_ADDR,
817 MT6359P_RG_LDO_VCAMIO_EN_SHIFT,
818 MT6359P_DA_VCAMIO_B_EN_ADDR, MT6359P_RG_VCAMIO_VOSEL_ADDR,
819 MT6359_RG_VCAMIO_VOSEL_MASK << MT6359_RG_VCAMIO_VOSEL_SHIFT,
820 1290),
821 MT6359_REG_FIXED("ldo_vcn18", VCN18, MT6359P_RG_LDO_VCN18_EN_ADDR,
822 MT6359P_DA_VCN18_B_EN_ADDR, 1800000),
823 MT6359_REG_FIXED("ldo_vfe28", VFE28, MT6359P_RG_LDO_VFE28_EN_ADDR,
824 MT6359P_DA_VFE28_B_EN_ADDR, 2800000),
825 MT6359_LDO("ldo_vcn13", VCN13, vcn13_voltages,
826 MT6359P_RG_LDO_VCN13_EN_ADDR, MT6359P_RG_LDO_VCN13_EN_SHIFT,
827 MT6359P_DA_VCN13_B_EN_ADDR, MT6359P_RG_VCN13_VOSEL_ADDR,
828 MT6359_RG_VCN13_VOSEL_MASK << MT6359_RG_VCN13_VOSEL_SHIFT,
829 240),
830 MT6359_LDO("ldo_vcn33_1_bt", VCN33_1_BT, vcn33_voltages,
831 MT6359P_RG_LDO_VCN33_1_EN_0_ADDR,
832 MT6359_RG_LDO_VCN33_1_EN_0_SHIFT,
833 MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR,
834 MT6359_RG_VCN33_1_VOSEL_MASK <<
835 MT6359_RG_VCN33_1_VOSEL_SHIFT, 240),
836 MT6359_LDO("ldo_vcn33_1_wifi", VCN33_1_WIFI, vcn33_voltages,
837 MT6359P_RG_LDO_VCN33_1_EN_1_ADDR,
838 MT6359P_RG_LDO_VCN33_1_EN_1_SHIFT,
839 MT6359P_DA_VCN33_1_B_EN_ADDR, MT6359P_RG_VCN33_1_VOSEL_ADDR,
840 MT6359_RG_VCN33_1_VOSEL_MASK <<
841 MT6359_RG_VCN33_1_VOSEL_SHIFT, 240),
842 MT6359_REG_FIXED("ldo_vaux18", VAUX18, MT6359P_RG_LDO_VAUX18_EN_ADDR,
843 MT6359P_DA_VAUX18_B_EN_ADDR, 1800000),
844 MT6359_LDO_LINEAR("ldo_vsram_others", VSRAM_OTHERS, 500000, 1293750,
845 6250,
846 MT6359P_RG_LDO_VSRAM_OTHERS_EN_ADDR,
847 MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR,
848 MT6359P_RG_LDO_VSRAM_OTHERS_VOSEL_ADDR,
849 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_MASK <<
850 MT6359_RG_LDO_VSRAM_OTHERS_VOSEL_SHIFT),
851 MT6359_LDO("ldo_vefuse", VEFUSE, vefuse_voltages,
852 MT6359P_RG_LDO_VEFUSE_EN_ADDR,
853 MT6359P_RG_LDO_VEFUSE_EN_SHIFT,
854 MT6359P_DA_VEFUSE_B_EN_ADDR, MT6359P_RG_VEFUSE_VOSEL_ADDR,
855 MT6359_RG_VEFUSE_VOSEL_MASK << MT6359_RG_VEFUSE_VOSEL_SHIFT,
856 240),
857 MT6359_LDO("ldo_vxo22", VXO22, vxo22_voltages,
858 MT6359P_RG_LDO_VXO22_EN_ADDR, MT6359P_RG_LDO_VXO22_EN_SHIFT,
859 MT6359P_DA_VXO22_B_EN_ADDR, MT6359P_RG_VXO22_VOSEL_ADDR,
860 MT6359_RG_VXO22_VOSEL_MASK << MT6359_RG_VXO22_VOSEL_SHIFT,
861 480),
862 MT6359_LDO("ldo_vrfck_1", VRFCK, vrfck_voltages_1,
863 MT6359P_RG_LDO_VRFCK_EN_ADDR, MT6359P_RG_LDO_VRFCK_EN_SHIFT,
864 MT6359P_DA_VRFCK_B_EN_ADDR, MT6359P_RG_VRFCK_VOSEL_ADDR,
865 MT6359_RG_VRFCK_VOSEL_MASK << MT6359_RG_VRFCK_VOSEL_SHIFT,
866 480),
867 MT6359_REG_FIXED("ldo_vbif28", VBIF28, MT6359P_RG_LDO_VBIF28_EN_ADDR,
868 MT6359P_DA_VBIF28_B_EN_ADDR, 2800000),
869 MT6359_LDO("ldo_vio28", VIO28, vio28_voltages,
870 MT6359P_RG_LDO_VIO28_EN_ADDR, MT6359P_RG_LDO_VIO28_EN_SHIFT,
871 MT6359P_DA_VIO28_B_EN_ADDR, MT6359P_RG_VIO28_VOSEL_ADDR,
872 MT6359_RG_VIO28_VOSEL_MASK << MT6359_RG_VIO28_VOSEL_SHIFT,
873 1920),
874 MT6359P_LDO1("ldo_vemc_1", VEMC, mt6359p_vemc_ops, vemc_voltages_1,
875 MT6359P_RG_LDO_VEMC_EN_ADDR, MT6359P_RG_LDO_VEMC_EN_SHIFT,
876 MT6359P_DA_VEMC_B_EN_ADDR,
877 MT6359P_RG_LDO_VEMC_VOSEL_0_ADDR,
878 MT6359P_RG_LDO_VEMC_VOSEL_0_MASK <<
879 MT6359P_RG_LDO_VEMC_VOSEL_0_SHIFT),
880 MT6359_LDO("ldo_vcn33_2_bt", VCN33_2_BT, vcn33_voltages,
881 MT6359P_RG_LDO_VCN33_2_EN_0_ADDR,
882 MT6359P_RG_LDO_VCN33_2_EN_0_SHIFT,
883 MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR,
884 MT6359_RG_VCN33_2_VOSEL_MASK <<
885 MT6359_RG_VCN33_2_VOSEL_SHIFT, 240),
886 MT6359_LDO("ldo_vcn33_2_wifi", VCN33_2_WIFI, vcn33_voltages,
887 MT6359P_RG_LDO_VCN33_2_EN_1_ADDR,
888 MT6359_RG_LDO_VCN33_2_EN_1_SHIFT,
889 MT6359P_DA_VCN33_2_B_EN_ADDR, MT6359P_RG_VCN33_2_VOSEL_ADDR,
890 MT6359_RG_VCN33_2_VOSEL_MASK <<
891 MT6359_RG_VCN33_2_VOSEL_SHIFT, 240),
892 MT6359_LDO("ldo_va12", VA12, va12_voltages,
893 MT6359P_RG_LDO_VA12_EN_ADDR, MT6359P_RG_LDO_VA12_EN_SHIFT,
894 MT6359P_DA_VA12_B_EN_ADDR, MT6359P_RG_VA12_VOSEL_ADDR,
895 MT6359_RG_VA12_VOSEL_MASK << MT6359_RG_VA12_VOSEL_SHIFT,
896 960),
897 MT6359_LDO("ldo_va09", VA09, va09_voltages,
898 MT6359P_RG_LDO_VA09_EN_ADDR, MT6359P_RG_LDO_VA09_EN_SHIFT,
899 MT6359P_DA_VA09_B_EN_ADDR, MT6359P_RG_VA09_VOSEL_ADDR,
900 MT6359_RG_VA09_VOSEL_MASK << MT6359_RG_VA09_VOSEL_SHIFT,
901 960),
902 MT6359_LDO("ldo_vrf18", VRF18, vrf18_voltages,
903 MT6359P_RG_LDO_VRF18_EN_ADDR, MT6359P_RG_LDO_VRF18_EN_SHIFT,
904 MT6359P_DA_VRF18_B_EN_ADDR, MT6359P_RG_VRF18_VOSEL_ADDR,
905 MT6359_RG_VRF18_VOSEL_MASK << MT6359_RG_VRF18_VOSEL_SHIFT,
906 240),
907 MT6359_LDO_LINEAR("ldo_vsram_md", VSRAM_MD, 500000, 1293750, 6250,
908 MT6359P_RG_LDO_VSRAM_MD_EN_ADDR,
909 MT6359P_DA_VSRAM_MD_B_EN_ADDR,
910 MT6359P_RG_LDO_VSRAM_MD_VOSEL_ADDR,
911 MT6359_RG_LDO_VSRAM_MD_VOSEL_MASK <<
912 MT6359_RG_LDO_VSRAM_MD_VOSEL_SHIFT),
913 MT6359_LDO("ldo_vufs", VUFS, volt18_voltages,
914 MT6359P_RG_LDO_VUFS_EN_ADDR, MT6359P_RG_LDO_VUFS_EN_SHIFT,
915 MT6359P_DA_VUFS_B_EN_ADDR, MT6359P_RG_VUFS_VOSEL_ADDR,
916 MT6359_RG_VUFS_VOSEL_MASK << MT6359_RG_VUFS_VOSEL_SHIFT,
917 1920),
918 MT6359_LDO("ldo_vm18", VM18, volt18_voltages,
919 MT6359P_RG_LDO_VM18_EN_ADDR, MT6359P_RG_LDO_VM18_EN_SHIFT,
920 MT6359P_DA_VM18_B_EN_ADDR, MT6359P_RG_VM18_VOSEL_ADDR,
921 MT6359_RG_VM18_VOSEL_MASK << MT6359_RG_VM18_VOSEL_SHIFT,
922 1920),
923 MT6359_LDO("ldo_vbbck", VBBCK, vbbck_voltages,
924 MT6359P_RG_LDO_VBBCK_EN_ADDR, MT6359P_RG_LDO_VBBCK_EN_SHIFT,
925 MT6359P_DA_VBBCK_B_EN_ADDR, MT6359P_RG_VBBCK_VOSEL_ADDR,
926 MT6359P_RG_VBBCK_VOSEL_MASK << MT6359P_RG_VBBCK_VOSEL_SHIFT,
927 480),
928 MT6359_LDO_LINEAR("ldo_vsram_proc1", VSRAM_PROC1, 500000, 1293750, 6250,
929 MT6359P_RG_LDO_VSRAM_PROC1_EN_ADDR,
930 MT6359P_DA_VSRAM_PROC1_B_EN_ADDR,
931 MT6359P_RG_LDO_VSRAM_PROC1_VOSEL_ADDR,
932 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_MASK <<
933 MT6359_RG_LDO_VSRAM_PROC1_VOSEL_SHIFT),
934 MT6359_LDO("ldo_vsim2", VSIM2, vsim2_voltages,
935 MT6359P_RG_LDO_VSIM2_EN_ADDR, MT6359P_RG_LDO_VSIM2_EN_SHIFT,
936 MT6359P_DA_VSIM2_B_EN_ADDR, MT6359P_RG_VSIM2_VOSEL_ADDR,
937 MT6359_RG_VSIM2_VOSEL_MASK << MT6359_RG_VSIM2_VOSEL_SHIFT,
938 480),
939 MT6359_LDO_LINEAR("ldo_vsram_others_sshub", VSRAM_OTHERS_SSHUB,
940 500000, 1293750, 6250,
941 MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_EN_ADDR,
942 MT6359P_DA_VSRAM_OTHERS_B_EN_ADDR,
943 MT6359P_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_ADDR,
944 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_MASK <<
945 MT6359_RG_LDO_VSRAM_OTHERS_SSHUB_VOSEL_SHIFT),
946 };
947
948 static int mt6359_regulator_probe(struct platform_device *pdev)
949 {
950 struct mt6397_chip *mt6397 = dev_get_drvdata(pdev->dev.parent);
951 struct regulator_config config = {};
952 struct regulator_dev *rdev;
953 struct mt6359_regulator_info *mt6359_info;
954 int i, hw_ver, ret;
955
956 ret = regmap_read(mt6397->regmap, MT6359P_HWCID, &hw_ver);
957 if (ret)
958 return ret;
959
960 if (hw_ver >= MT6359P_CHIP_VER)
961 mt6359_info = mt6359p_regulators;
962 else
963 mt6359_info = mt6359_regulators;
964
965 config.dev = mt6397->dev;
966 config.regmap = mt6397->regmap;
967 for (i = 0; i < MT6359_MAX_REGULATOR; i++, mt6359_info++) {
968 config.driver_data = mt6359_info;
969 rdev = devm_regulator_register(&pdev->dev, &mt6359_info->desc, &config);
970 if (IS_ERR(rdev)) {
971 dev_err(&pdev->dev, "failed to register %s\n", mt6359_info->desc.name);
972 return PTR_ERR(rdev);
973 }
974 }
975
976 return 0;
977 }
978
979 static const struct platform_device_id mt6359_platform_ids[] = {
980 {"mt6359-regulator", 0},
981 { /* sentinel */ },
982 };
983 MODULE_DEVICE_TABLE(platform, mt6359_platform_ids);
984
985 static struct platform_driver mt6359_regulator_driver = {
986 .driver = {
987 .name = "mt6359-regulator",
988 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
989 },
990 .probe = mt6359_regulator_probe,
991 .id_table = mt6359_platform_ids,
992 };
993
994 module_platform_driver(mt6359_regulator_driver);
995
996 MODULE_AUTHOR("Wen Su <wen.su@mediatek.com>");
997 MODULE_DESCRIPTION("Regulator Driver for MediaTek MT6359 PMIC");
998 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes