1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Reset driver for the StarFive JH7100 SoC
5 * Copyright (C) 2021 Emil Renner Berthing <kernel@esmil.dk>
8 #include <linux/mod_devicetable.h>
9 #include <linux/platform_device.h>
11 #include "reset-starfive-jh71x0.h"
13 #include <dt-bindings/reset/starfive-jh7100.h>
15 /* register offsets */
16 #define JH7100_RESET_ASSERT0 0x00
17 #define JH7100_RESET_ASSERT1 0x04
18 #define JH7100_RESET_ASSERT2 0x08
19 #define JH7100_RESET_ASSERT3 0x0c
20 #define JH7100_RESET_STATUS0 0x10
21 #define JH7100_RESET_STATUS1 0x14
22 #define JH7100_RESET_STATUS2 0x18
23 #define JH7100_RESET_STATUS3 0x1c
26 * Writing a 1 to the n'th bit of the m'th ASSERT register asserts
27 * line 32m + n, and writing a 0 deasserts the same line.
28 * Most reset lines have their status inverted so a 0 bit in the STATUS
29 * register means the line is asserted and a 1 means it's deasserted. A few
30 * lines don't though, so store the expected value of the status registers when
31 * all lines are asserted.
33 static const u32 jh7100_reset_asserted
[4] = {
35 BIT(JH7100_RST_U74
% 32) |
36 BIT(JH7100_RST_VP6_DRESET
% 32) |
37 BIT(JH7100_RST_VP6_BRESET
% 32),
39 BIT(JH7100_RST_HIFI4_DRESET
% 32) |
40 BIT(JH7100_RST_HIFI4_BRESET
% 32),
42 BIT(JH7100_RST_E24
% 32),
47 static int __init
jh7100_reset_probe(struct platform_device
*pdev
)
49 void __iomem
*base
= devm_platform_ioremap_resource(pdev
, 0);
54 return reset_starfive_jh71x0_register(&pdev
->dev
, pdev
->dev
.of_node
,
55 base
+ JH7100_RESET_ASSERT0
,
56 base
+ JH7100_RESET_STATUS0
,
57 jh7100_reset_asserted
,
62 static const struct of_device_id jh7100_reset_dt_ids
[] = {
63 { .compatible
= "starfive,jh7100-reset" },
67 static struct platform_driver jh7100_reset_driver
= {
69 .name
= "jh7100-reset",
70 .of_match_table
= jh7100_reset_dt_ids
,
71 .suppress_bind_attrs
= true,
74 builtin_platform_driver_probe(jh7100_reset_driver
, jh7100_reset_probe
);