drm/nouveau: consume the return of large GSP message
[drm/drm-misc.git] / drivers / scsi / hisi_sas / hisi_sas.h
bloba44768bceb9ab25320f85037580e5127eeda392a
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Copyright (c) 2015 Linaro Ltd.
4 * Copyright (c) 2015 Hisilicon Limited.
5 */
7 #ifndef _HISI_SAS_H_
8 #define _HISI_SAS_H_
10 #include <linux/acpi.h>
11 #include <linux/blk-mq.h>
12 #include <linux/blk-mq-pci.h>
13 #include <linux/clk.h>
14 #include <linux/debugfs.h>
15 #include <linux/dmapool.h>
16 #include <linux/iopoll.h>
17 #include <linux/irq.h>
18 #include <linux/lcm.h>
19 #include <linux/libata.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/pci.h>
24 #include <linux/platform_device.h>
25 #include <linux/pm_runtime.h>
26 #include <linux/property.h>
27 #include <linux/regmap.h>
28 #include <linux/timer.h>
29 #include <scsi/sas_ata.h>
30 #include <scsi/libsas.h>
32 #define HISI_SAS_MAX_PHYS 9
33 #define HISI_SAS_MAX_QUEUES 32
34 #define HISI_SAS_QUEUE_SLOTS 4096
35 #define HISI_SAS_MAX_ITCT_ENTRIES 1024
36 #define HISI_SAS_MAX_DEVICES HISI_SAS_MAX_ITCT_ENTRIES
37 #define HISI_SAS_RESETTING_BIT 0
38 #define HISI_SAS_REJECT_CMD_BIT 1
39 #define HISI_SAS_PM_BIT 2
40 #define HISI_SAS_HW_FAULT_BIT 3
41 #define HISI_SAS_MAX_COMMANDS (HISI_SAS_QUEUE_SLOTS)
42 #define HISI_SAS_RESERVED_IPTT 96
43 #define HISI_SAS_UNRESERVED_IPTT \
44 (HISI_SAS_MAX_COMMANDS - HISI_SAS_RESERVED_IPTT)
46 #define HISI_SAS_IOST_ITCT_CACHE_NUM 64
47 #define HISI_SAS_IOST_ITCT_CACHE_DW_SZ 10
48 #define HISI_SAS_FIFO_DATA_DW_SIZE 32
50 #define HISI_SAS_STATUS_BUF_SZ (sizeof(struct hisi_sas_status_buffer))
51 #define HISI_SAS_COMMAND_TABLE_SZ (sizeof(union hisi_sas_command_table))
53 #define hisi_sas_status_buf_addr(buf) \
54 ((buf) + offsetof(struct hisi_sas_slot_buf_table, status_buffer))
55 #define hisi_sas_status_buf_addr_mem(slot) hisi_sas_status_buf_addr((slot)->buf)
56 #define hisi_sas_status_buf_addr_dma(slot) \
57 hisi_sas_status_buf_addr((slot)->buf_dma)
59 #define hisi_sas_cmd_hdr_addr(buf) \
60 ((buf) + offsetof(struct hisi_sas_slot_buf_table, command_header))
61 #define hisi_sas_cmd_hdr_addr_mem(slot) hisi_sas_cmd_hdr_addr((slot)->buf)
62 #define hisi_sas_cmd_hdr_addr_dma(slot) hisi_sas_cmd_hdr_addr((slot)->buf_dma)
64 #define hisi_sas_sge_addr(buf) \
65 ((buf) + offsetof(struct hisi_sas_slot_buf_table, sge_page))
66 #define hisi_sas_sge_addr_mem(slot) hisi_sas_sge_addr((slot)->buf)
67 #define hisi_sas_sge_addr_dma(slot) hisi_sas_sge_addr((slot)->buf_dma)
69 #define hisi_sas_sge_dif_addr(buf) \
70 ((buf) + offsetof(struct hisi_sas_slot_dif_buf_table, sge_dif_page))
71 #define hisi_sas_sge_dif_addr_mem(slot) hisi_sas_sge_dif_addr((slot)->buf)
72 #define hisi_sas_sge_dif_addr_dma(slot) hisi_sas_sge_dif_addr((slot)->buf_dma)
74 #define HISI_SAS_MAX_SSP_RESP_SZ (sizeof(struct ssp_frame_hdr) + 1024)
75 #define HISI_SAS_MAX_SMP_RESP_SZ 1028
76 #define HISI_SAS_MAX_STP_RESP_SZ 28
78 #define HISI_SAS_SATA_PROTOCOL_NONDATA 0x1
79 #define HISI_SAS_SATA_PROTOCOL_PIO 0x2
80 #define HISI_SAS_SATA_PROTOCOL_DMA 0x4
81 #define HISI_SAS_SATA_PROTOCOL_FPDMA 0x8
82 #define HISI_SAS_SATA_PROTOCOL_ATAPI 0x10
84 #define HISI_SAS_DIF_PROT_MASK (SHOST_DIF_TYPE1_PROTECTION | \
85 SHOST_DIF_TYPE2_PROTECTION | \
86 SHOST_DIF_TYPE3_PROTECTION)
88 #define HISI_SAS_DIX_PROT_MASK (SHOST_DIX_TYPE1_PROTECTION | \
89 SHOST_DIX_TYPE2_PROTECTION | \
90 SHOST_DIX_TYPE3_PROTECTION)
92 #define HISI_SAS_PROT_MASK (HISI_SAS_DIF_PROT_MASK | HISI_SAS_DIX_PROT_MASK)
94 #define HISI_SAS_WAIT_PHYUP_TIMEOUT (30 * HZ)
95 #define HISI_SAS_CLEAR_ITCT_TIMEOUT (20 * HZ)
97 struct hisi_hba;
99 enum {
100 PORT_TYPE_SAS = (1U << 1),
101 PORT_TYPE_SATA = (1U << 0),
104 enum dev_status {
105 HISI_SAS_DEV_INIT,
106 HISI_SAS_DEV_NORMAL,
107 HISI_SAS_DEV_NCQ_ERR,
110 enum {
111 HISI_SAS_INT_ABT_CMD = 0,
112 HISI_SAS_INT_ABT_DEV = 1,
115 enum hisi_sas_dev_type {
116 HISI_SAS_DEV_TYPE_STP = 0,
117 HISI_SAS_DEV_TYPE_SSP,
118 HISI_SAS_DEV_TYPE_SATA,
121 struct hisi_sas_hw_error {
122 u32 irq_msk;
123 u32 msk;
124 int shift;
125 const char *msg;
126 int reg;
127 const struct hisi_sas_hw_error *sub;
130 struct hisi_sas_rst {
131 struct hisi_hba *hisi_hba;
132 struct completion *completion;
133 struct work_struct work;
134 bool done;
137 #define HISI_SAS_RST_WORK_INIT(r, c) \
138 { .hisi_hba = hisi_hba, \
139 .completion = &c, \
140 .work = __WORK_INITIALIZER(r.work, \
141 hisi_sas_sync_rst_work_handler), \
142 .done = false, \
145 #define HISI_SAS_DECLARE_RST_WORK_ON_STACK(r) \
146 DECLARE_COMPLETION_ONSTACK(c); \
147 struct hisi_sas_rst r = HISI_SAS_RST_WORK_INIT(r, c)
149 enum hisi_sas_bit_err_type {
150 HISI_SAS_ERR_SINGLE_BIT_ECC = 0x0,
151 HISI_SAS_ERR_MULTI_BIT_ECC = 0x1,
154 enum hisi_sas_phy_event {
155 HISI_PHYE_PHY_UP = 0U,
156 HISI_PHYE_LINK_RESET,
157 HISI_PHYE_PHY_UP_PM,
158 HISI_PHYES_NUM,
161 struct hisi_sas_debugfs_fifo {
162 u32 signal_sel;
163 u32 dump_msk;
164 u32 dump_mode;
165 u32 trigger;
166 u32 trigger_msk;
167 u32 trigger_mode;
168 u32 rd_data[HISI_SAS_FIFO_DATA_DW_SIZE];
171 struct hisi_sas_phy {
172 struct work_struct works[HISI_PHYES_NUM];
173 struct hisi_hba *hisi_hba;
174 struct hisi_sas_port *port;
175 struct asd_sas_phy sas_phy;
176 struct sas_identify identify;
177 struct completion *reset_completion;
178 struct timer_list timer;
179 spinlock_t lock;
180 u64 port_id; /* from hw */
181 u64 frame_rcvd_size;
182 u8 frame_rcvd[32];
183 u8 phy_attached;
184 u8 in_reset;
185 u8 reserved[2];
186 u32 phy_type;
187 u32 code_violation_err_count;
188 enum sas_linkrate minimum_linkrate;
189 enum sas_linkrate maximum_linkrate;
190 int enable;
191 int wait_phyup_cnt;
192 atomic_t down_cnt;
194 /* Trace FIFO */
195 struct hisi_sas_debugfs_fifo fifo;
198 struct hisi_sas_port {
199 struct asd_sas_port sas_port;
200 u8 port_attached;
201 u8 id; /* from hw */
204 struct hisi_sas_cq {
205 struct hisi_hba *hisi_hba;
206 const struct cpumask *irq_mask;
207 int rd_point;
208 int id;
209 int irq_no;
210 spinlock_t poll_lock;
213 struct hisi_sas_dq {
214 struct hisi_hba *hisi_hba;
215 struct list_head list;
216 spinlock_t lock;
217 int wr_point;
218 int id;
221 struct hisi_sas_device {
222 struct hisi_hba *hisi_hba;
223 struct domain_device *sas_device;
224 struct completion *completion;
225 struct hisi_sas_dq *dq;
226 struct list_head list;
227 enum sas_device_type dev_type;
228 enum dev_status dev_status;
229 int device_id;
230 int sata_idx;
231 spinlock_t lock; /* For protecting slots */
234 struct hisi_sas_slot {
235 struct list_head entry;
236 struct list_head delivery;
237 struct sas_task *task;
238 struct hisi_sas_port *port;
239 u64 n_elem;
240 u64 n_elem_dif;
241 int dlvry_queue;
242 int dlvry_queue_slot;
243 int cmplt_queue;
244 int cmplt_queue_slot;
245 int abort;
246 int ready;
247 int device_id;
248 void *cmd_hdr;
249 dma_addr_t cmd_hdr_dma;
250 struct timer_list internal_abort_timer;
251 bool is_internal;
252 struct sas_tmf_task *tmf;
253 /* Do not reorder/change members after here */
254 void *buf;
255 dma_addr_t buf_dma;
256 u16 idx;
259 struct hisi_sas_iost_itct_cache {
260 u32 data[HISI_SAS_IOST_ITCT_CACHE_DW_SZ];
263 enum hisi_sas_debugfs_reg_array_member {
264 DEBUGFS_GLOBAL = 0,
265 DEBUGFS_AXI,
266 DEBUGFS_RAS,
267 DEBUGFS_REGS_NUM
270 enum hisi_sas_debugfs_cache_type {
271 HISI_SAS_ITCT_CACHE,
272 HISI_SAS_IOST_CACHE,
275 enum hisi_sas_debugfs_bist_ffe_cfg {
276 FFE_SAS_1_5_GBPS,
277 FFE_SAS_3_0_GBPS,
278 FFE_SAS_6_0_GBPS,
279 FFE_SAS_12_0_GBPS,
280 FFE_RESV,
281 FFE_SATA_1_5_GBPS,
282 FFE_SATA_3_0_GBPS,
283 FFE_SATA_6_0_GBPS,
284 FFE_CFG_MAX
287 enum hisi_sas_debugfs_bist_fixed_code {
288 FIXED_CODE,
289 FIXED_CODE_1,
290 FIXED_CODE_MAX
293 enum {
294 HISI_SAS_BIST_CODE_MODE_PRBS7,
295 HISI_SAS_BIST_CODE_MODE_PRBS23,
296 HISI_SAS_BIST_CODE_MODE_PRBS31,
297 HISI_SAS_BIST_CODE_MODE_JTPAT,
298 HISI_SAS_BIST_CODE_MODE_CJTPAT,
299 HISI_SAS_BIST_CODE_MODE_SCRAMBED_0,
300 HISI_SAS_BIST_CODE_MODE_TRAIN,
301 HISI_SAS_BIST_CODE_MODE_TRAIN_DONE,
302 HISI_SAS_BIST_CODE_MODE_HFTP,
303 HISI_SAS_BIST_CODE_MODE_MFTP,
304 HISI_SAS_BIST_CODE_MODE_LFTP,
305 HISI_SAS_BIST_CODE_MODE_FIXED_DATA,
308 struct hisi_sas_hw {
309 int (*hw_init)(struct hisi_hba *hisi_hba);
310 int (*fw_info_check)(struct hisi_hba *hisi_hba);
311 int (*interrupt_preinit)(struct hisi_hba *hisi_hba);
312 void (*setup_itct)(struct hisi_hba *hisi_hba,
313 struct hisi_sas_device *device);
314 int (*slot_index_alloc)(struct hisi_hba *hisi_hba,
315 struct domain_device *device);
316 struct hisi_sas_device *(*alloc_dev)(struct domain_device *device);
317 void (*sl_notify_ssp)(struct hisi_hba *hisi_hba, int phy_no);
318 void (*start_delivery)(struct hisi_sas_dq *dq);
319 void (*prep_ssp)(struct hisi_hba *hisi_hba,
320 struct hisi_sas_slot *slot);
321 void (*prep_smp)(struct hisi_hba *hisi_hba,
322 struct hisi_sas_slot *slot);
323 void (*prep_stp)(struct hisi_hba *hisi_hba,
324 struct hisi_sas_slot *slot);
325 void (*prep_abort)(struct hisi_hba *hisi_hba,
326 struct hisi_sas_slot *slot);
327 void (*phys_init)(struct hisi_hba *hisi_hba);
328 void (*phy_start)(struct hisi_hba *hisi_hba, int phy_no);
329 void (*phy_disable)(struct hisi_hba *hisi_hba, int phy_no);
330 void (*phy_hard_reset)(struct hisi_hba *hisi_hba, int phy_no);
331 void (*get_events)(struct hisi_hba *hisi_hba, int phy_no);
332 void (*phy_set_linkrate)(struct hisi_hba *hisi_hba, int phy_no,
333 struct sas_phy_linkrates *linkrates);
334 enum sas_linkrate (*phy_get_max_linkrate)(void);
335 int (*clear_itct)(struct hisi_hba *hisi_hba,
336 struct hisi_sas_device *dev);
337 void (*free_device)(struct hisi_sas_device *sas_dev);
338 int (*get_wideport_bitmap)(struct hisi_hba *hisi_hba, int port_id);
339 void (*dereg_device)(struct hisi_hba *hisi_hba,
340 struct domain_device *device);
341 int (*soft_reset)(struct hisi_hba *hisi_hba);
342 u32 (*get_phys_state)(struct hisi_hba *hisi_hba);
343 int (*write_gpio)(struct hisi_hba *hisi_hba, u8 reg_type,
344 u8 reg_index, u8 reg_count, u8 *write_data);
345 void (*wait_cmds_complete_timeout)(struct hisi_hba *hisi_hba,
346 int delay_ms, int timeout_ms);
347 int (*debugfs_snapshot_regs)(struct hisi_hba *hisi_hba);
348 int complete_hdr_size;
349 const struct scsi_host_template *sht;
352 #define HISI_SAS_MAX_DEBUGFS_DUMP (50)
354 struct hisi_sas_debugfs_cq {
355 struct hisi_sas_cq *cq;
356 void *complete_hdr;
359 struct hisi_sas_debugfs_dq {
360 struct hisi_sas_dq *dq;
361 struct hisi_sas_cmd_hdr *hdr;
364 struct hisi_sas_debugfs_regs {
365 struct hisi_hba *hisi_hba;
366 u32 *data;
369 struct hisi_sas_debugfs_port {
370 struct hisi_sas_phy *phy;
371 u32 *data;
374 struct hisi_sas_debugfs_iost {
375 struct hisi_sas_iost *iost;
378 struct hisi_sas_debugfs_itct {
379 struct hisi_sas_itct *itct;
382 struct hisi_sas_debugfs_iost_cache {
383 struct hisi_sas_iost_itct_cache *cache;
386 struct hisi_sas_debugfs_itct_cache {
387 struct hisi_sas_iost_itct_cache *cache;
390 struct hisi_hba {
391 /* This must be the first element, used by SHOST_TO_SAS_HA */
392 struct sas_ha_struct *p;
394 struct platform_device *platform_dev;
395 struct pci_dev *pci_dev;
396 struct device *dev;
398 int prot_mask;
400 void __iomem *regs;
401 void __iomem *sgpio_regs;
402 struct regmap *ctrl;
403 u32 ctrl_reset_reg;
404 u32 ctrl_reset_sts_reg;
405 u32 ctrl_clock_ena_reg;
406 u32 refclk_frequency_mhz;
407 u8 sas_addr[SAS_ADDR_SIZE];
409 int *irq_map; /* v2 hw */
411 int n_phy;
412 spinlock_t lock;
413 struct semaphore sem;
415 struct timer_list timer;
416 struct workqueue_struct *wq;
418 int slot_index_count;
419 int last_slot_index;
420 int last_dev_id;
421 unsigned long *slot_index_tags;
422 unsigned long reject_stp_links_msk;
424 /* SCSI/SAS glue */
425 struct sas_ha_struct sha;
426 struct Scsi_Host *shost;
428 struct hisi_sas_cq cq[HISI_SAS_MAX_QUEUES];
429 struct hisi_sas_dq dq[HISI_SAS_MAX_QUEUES];
430 struct hisi_sas_phy phy[HISI_SAS_MAX_PHYS];
431 struct hisi_sas_port port[HISI_SAS_MAX_PHYS];
433 int queue_count;
435 struct hisi_sas_device devices[HISI_SAS_MAX_DEVICES];
436 struct hisi_sas_cmd_hdr *cmd_hdr[HISI_SAS_MAX_QUEUES];
437 dma_addr_t cmd_hdr_dma[HISI_SAS_MAX_QUEUES];
438 void *complete_hdr[HISI_SAS_MAX_QUEUES];
439 dma_addr_t complete_hdr_dma[HISI_SAS_MAX_QUEUES];
440 struct hisi_sas_initial_fis *initial_fis;
441 dma_addr_t initial_fis_dma;
442 struct hisi_sas_itct *itct;
443 dma_addr_t itct_dma;
444 struct hisi_sas_iost *iost;
445 dma_addr_t iost_dma;
446 struct hisi_sas_breakpoint *breakpoint;
447 dma_addr_t breakpoint_dma;
448 struct hisi_sas_breakpoint *sata_breakpoint;
449 dma_addr_t sata_breakpoint_dma;
450 struct hisi_sas_slot *slot_info;
451 unsigned long flags;
452 const struct hisi_sas_hw *hw; /* Low level hw interface */
453 unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)];
454 struct work_struct rst_work;
455 u32 phy_state;
456 u32 intr_coal_ticks; /* Time of interrupt coalesce in us */
457 u32 intr_coal_count; /* Interrupt count to coalesce */
459 int cq_nvecs;
461 /* bist */
462 enum sas_linkrate debugfs_bist_linkrate;
463 int debugfs_bist_code_mode;
464 int debugfs_bist_phy_no;
465 int debugfs_bist_mode;
466 u32 debugfs_bist_cnt;
467 int debugfs_bist_enable;
468 u32 debugfs_bist_ffe[HISI_SAS_MAX_PHYS][FFE_CFG_MAX];
469 u32 debugfs_bist_fixed_code[FIXED_CODE_MAX];
471 /* debugfs memories */
472 /* Put Global AXI and RAS Register into register array */
473 struct hisi_sas_debugfs_regs debugfs_regs[HISI_SAS_MAX_DEBUGFS_DUMP][DEBUGFS_REGS_NUM];
474 struct hisi_sas_debugfs_port debugfs_port_reg[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_PHYS];
475 struct hisi_sas_debugfs_cq debugfs_cq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES];
476 struct hisi_sas_debugfs_dq debugfs_dq[HISI_SAS_MAX_DEBUGFS_DUMP][HISI_SAS_MAX_QUEUES];
477 struct hisi_sas_debugfs_iost debugfs_iost[HISI_SAS_MAX_DEBUGFS_DUMP];
478 struct hisi_sas_debugfs_itct debugfs_itct[HISI_SAS_MAX_DEBUGFS_DUMP];
479 struct hisi_sas_debugfs_iost_cache debugfs_iost_cache[HISI_SAS_MAX_DEBUGFS_DUMP];
480 struct hisi_sas_debugfs_itct_cache debugfs_itct_cache[HISI_SAS_MAX_DEBUGFS_DUMP];
482 u64 debugfs_timestamp[HISI_SAS_MAX_DEBUGFS_DUMP];
483 int debugfs_dump_index;
484 struct dentry *debugfs_dir;
485 struct dentry *debugfs_dump_dentry;
486 struct dentry *debugfs_bist_dentry;
487 struct dentry *debugfs_fifo_dentry;
489 int iopoll_q_cnt;
492 /* Generic HW DMA host memory structures */
493 /* Delivery queue header */
494 struct hisi_sas_cmd_hdr {
495 /* dw0 */
496 __le32 dw0;
498 /* dw1 */
499 __le32 dw1;
501 /* dw2 */
502 __le32 dw2;
504 /* dw3 */
505 __le32 transfer_tags;
507 /* dw4 */
508 __le32 data_transfer_len;
510 /* dw5 */
511 __le32 first_burst_num;
513 /* dw6 */
514 __le32 sg_len;
516 /* dw7 */
517 __le32 dw7;
519 /* dw8-9 */
520 __le64 cmd_table_addr;
522 /* dw10-11 */
523 __le64 sts_buffer_addr;
525 /* dw12-13 */
526 __le64 prd_table_addr;
528 /* dw14-15 */
529 __le64 dif_prd_table_addr;
532 struct hisi_sas_itct {
533 __le64 qw0;
534 __le64 sas_addr;
535 __le64 qw2;
536 __le64 qw3;
537 __le64 qw4_15[12];
540 struct hisi_sas_iost {
541 __le64 qw0;
542 __le64 qw1;
543 __le64 qw2;
544 __le64 qw3;
547 struct hisi_sas_err_record {
548 u32 data[4];
551 struct hisi_sas_initial_fis {
552 struct hisi_sas_err_record err_record;
553 struct dev_to_host_fis fis;
554 u32 rsvd[3];
557 struct hisi_sas_breakpoint {
558 u8 data[128];
561 struct hisi_sas_sata_breakpoint {
562 struct hisi_sas_breakpoint tag[32];
565 struct hisi_sas_sge {
566 __le64 addr;
567 __le32 page_ctrl_0;
568 __le32 page_ctrl_1;
569 __le32 data_len;
570 __le32 data_off;
573 struct hisi_sas_command_table_smp {
574 u8 bytes[44];
577 struct hisi_sas_command_table_stp {
578 struct host_to_dev_fis command_fis;
579 u8 dummy[12];
580 u8 atapi_cdb[ATAPI_CDB_LEN];
583 #define HISI_SAS_SGE_PAGE_CNT (124)
584 struct hisi_sas_sge_page {
585 struct hisi_sas_sge sge[HISI_SAS_SGE_PAGE_CNT];
586 } __aligned(16);
588 #define HISI_SAS_SGE_DIF_PAGE_CNT HISI_SAS_SGE_PAGE_CNT
589 struct hisi_sas_sge_dif_page {
590 struct hisi_sas_sge sge[HISI_SAS_SGE_DIF_PAGE_CNT];
591 } __aligned(16);
593 struct hisi_sas_command_table_ssp {
594 struct ssp_frame_hdr hdr;
595 union {
596 struct {
597 struct ssp_command_iu task;
598 u32 prot[7];
600 struct ssp_tmf_iu ssp_task;
601 struct xfer_rdy_iu xfer_rdy;
602 struct ssp_response_iu ssp_res;
603 } u;
606 union hisi_sas_command_table {
607 struct hisi_sas_command_table_ssp ssp;
608 struct hisi_sas_command_table_smp smp;
609 struct hisi_sas_command_table_stp stp;
610 } __aligned(16);
612 struct hisi_sas_status_buffer {
613 struct hisi_sas_err_record err;
614 u8 iu[1024];
615 } __aligned(16);
617 struct hisi_sas_slot_buf_table {
618 struct hisi_sas_status_buffer status_buffer;
619 union hisi_sas_command_table command_header;
620 struct hisi_sas_sge_page sge_page;
623 struct hisi_sas_slot_dif_buf_table {
624 struct hisi_sas_slot_buf_table slot_buf;
625 struct hisi_sas_sge_dif_page sge_dif_page;
628 extern struct scsi_transport_template *hisi_sas_stt;
630 extern bool hisi_sas_debugfs_enable;
631 extern u32 hisi_sas_debugfs_dump_count;
632 extern struct dentry *hisi_sas_debugfs_dir;
634 extern void hisi_sas_stop_phys(struct hisi_hba *hisi_hba);
635 extern int hisi_sas_alloc(struct hisi_hba *hisi_hba);
636 extern void hisi_sas_free(struct hisi_hba *hisi_hba);
637 extern u8 hisi_sas_get_ata_protocol(struct host_to_dev_fis *fis,
638 int direction);
639 extern struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port);
640 extern void hisi_sas_sata_done(struct sas_task *task,
641 struct hisi_sas_slot *slot);
642 extern int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba);
643 extern int hisi_sas_probe(struct platform_device *pdev,
644 const struct hisi_sas_hw *ops);
645 extern void hisi_sas_remove(struct platform_device *pdev);
647 int hisi_sas_device_configure(struct scsi_device *sdev,
648 struct queue_limits *lim);
649 extern int hisi_sas_slave_alloc(struct scsi_device *sdev);
650 extern int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time);
651 extern void hisi_sas_scan_start(struct Scsi_Host *shost);
652 extern int hisi_sas_host_reset(struct Scsi_Host *shost, int reset_type);
653 extern void hisi_sas_phy_enable(struct hisi_hba *hisi_hba, int phy_no,
654 int enable);
655 extern void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy,
656 gfp_t gfp_flags);
657 extern void hisi_sas_phy_bcast(struct hisi_sas_phy *phy);
658 extern void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba,
659 struct sas_task *task,
660 struct hisi_sas_slot *slot,
661 bool need_lock);
662 extern void hisi_sas_init_mem(struct hisi_hba *hisi_hba);
663 extern void hisi_sas_rst_work_handler(struct work_struct *work);
664 extern void hisi_sas_sync_rst_work_handler(struct work_struct *work);
665 extern void hisi_sas_phy_oob_ready(struct hisi_hba *hisi_hba, int phy_no);
666 extern bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy,
667 enum hisi_sas_phy_event event);
668 extern void hisi_sas_release_tasks(struct hisi_hba *hisi_hba);
669 extern u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max);
670 extern void hisi_sas_sync_cqs(struct hisi_hba *hisi_hba);
671 extern void hisi_sas_sync_poll_cqs(struct hisi_hba *hisi_hba);
672 extern void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba);
673 extern void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba);
674 #endif