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drm/atomic-helper: document drm_atomic_helper_check() restrictions
[drm/drm-misc.git] / drivers / scsi / isci / host.c
blob35589b6af90d6e40896b2b5979bbb8cad6a749db
1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * GPL LICENSE SUMMARY
6 *
7 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21 * The full GNU General Public License is included in this distribution
22 * in the file called LICENSE.GPL.
23 *
24 * BSD LICENSE
25 *
26 * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27 * All rights reserved.
28 *
29 * Redistribution and use in source and binary forms, with or without
30 * modification, are permitted provided that the following conditions
31 * are met:
32 *
33 * * Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * * Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in
37 * the documentation and/or other materials provided with the
38 * distribution.
39 * * Neither the name of Intel Corporation nor the names of its
40 * contributors may be used to endorse or promote products derived
41 * from this software without specific prior written permission.
42 *
43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 */
55 #include <linux/circ_buf.h>
56 #include <linux/device.h>
57 #include <scsi/sas.h>
58 #include "host.h"
59 #include "isci.h"
60 #include "port.h"
61 #include "probe_roms.h"
62 #include "remote_device.h"
63 #include "request.h"
64 #include "scu_completion_codes.h"
65 #include "scu_event_codes.h"
66 #include "registers.h"
67 #include "scu_remote_node_context.h"
68 #include "scu_task_context.h"
69
70 #define SCU_CONTEXT_RAM_INIT_STALL_TIME 200
71
72 #define smu_max_ports(dcc_value) \
73 (\
74 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_MASK) \
75 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_LP_SHIFT) + 1 \
76 )
77
78 #define smu_max_task_contexts(dcc_value) \
79 (\
80 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_MASK) \
81 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_TC_SHIFT) + 1 \
82 )
83
84 #define smu_max_rncs(dcc_value) \
85 (\
86 (((dcc_value) & SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_MASK) \
87 >> SMU_DEVICE_CONTEXT_CAPACITY_MAX_RNC_SHIFT) + 1 \
88 )
89
90 #define SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT 100
91
92 /*
93 * The number of milliseconds to wait while a given phy is consuming power
94 * before allowing another set of phys to consume power. Ultimately, this will
95 * be specified by OEM parameter.
96 */
97 #define SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL 500
98
99 /*
100 * NORMALIZE_PUT_POINTER() -
101 *
102 * This macro will normalize the completion queue put pointer so its value can
103 * be used as an array inde
104 */
105 #define NORMALIZE_PUT_POINTER(x) \
106 ((x) & SMU_COMPLETION_QUEUE_PUT_POINTER_MASK)
107
108
109 /*
110 * NORMALIZE_EVENT_POINTER() -
111 *
112 * This macro will normalize the completion queue event entry so its value can
113 * be used as an index.
114 */
115 #define NORMALIZE_EVENT_POINTER(x) \
116 (\
117 ((x) & SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_MASK) \
118 >> SMU_COMPLETION_QUEUE_GET_EVENT_POINTER_SHIFT \
119 )
120
121 /*
122 * NORMALIZE_GET_POINTER() -
123 *
124 * This macro will normalize the completion queue get pointer so its value can
125 * be used as an index into an array
126 */
127 #define NORMALIZE_GET_POINTER(x) \
128 ((x) & SMU_COMPLETION_QUEUE_GET_POINTER_MASK)
129
130 /*
131 * NORMALIZE_GET_POINTER_CYCLE_BIT() -
132 *
133 * This macro will normalize the completion queue cycle pointer so it matches
134 * the completion queue cycle bit
135 */
136 #define NORMALIZE_GET_POINTER_CYCLE_BIT(x) \
137 ((SMU_CQGR_CYCLE_BIT & (x)) << (31 - SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT))
138
139 /*
140 * COMPLETION_QUEUE_CYCLE_BIT() -
141 *
142 * This macro will return the cycle bit of the completion queue entry
143 */
144 #define COMPLETION_QUEUE_CYCLE_BIT(x) ((x) & 0x80000000)
145
146 /* Init the state machine and call the state entry function (if any) */
147 void sci_init_sm(struct sci_base_state_machine *sm,
148 const struct sci_base_state *state_table, u32 initial_state)
149 {
150 sci_state_transition_t handler;
151
152 sm->initial_state_id = initial_state;
153 sm->previous_state_id = initial_state;
154 sm->current_state_id = initial_state;
155 sm->state_table = state_table;
156
157 handler = sm->state_table[initial_state].enter_state;
158 if (handler)
159 handler(sm);
160 }
161
162 /* Call the state exit fn, update the current state, call the state entry fn */
163 void sci_change_state(struct sci_base_state_machine *sm, u32 next_state)
164 {
165 sci_state_transition_t handler;
166
167 handler = sm->state_table[sm->current_state_id].exit_state;
168 if (handler)
169 handler(sm);
170
171 sm->previous_state_id = sm->current_state_id;
172 sm->current_state_id = next_state;
173
174 handler = sm->state_table[sm->current_state_id].enter_state;
175 if (handler)
176 handler(sm);
177 }
178
179 static bool sci_controller_completion_queue_has_entries(struct isci_host *ihost)
180 {
181 u32 get_value = ihost->completion_queue_get;
182 u32 get_index = get_value & SMU_COMPLETION_QUEUE_GET_POINTER_MASK;
183
184 if (NORMALIZE_GET_POINTER_CYCLE_BIT(get_value) ==
185 COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index]))
186 return true;
187
188 return false;
189 }
190
191 static bool sci_controller_isr(struct isci_host *ihost)
192 {
193 if (sci_controller_completion_queue_has_entries(ihost))
194 return true;
195
196 /* we have a spurious interrupt it could be that we have already
197 * emptied the completion queue from a previous interrupt
198 * FIXME: really!?
199 */
200 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
201
202 /* There is a race in the hardware that could cause us not to be
203 * notified of an interrupt completion if we do not take this
204 * step. We will mask then unmask the interrupts so if there is
205 * another interrupt pending the clearing of the interrupt
206 * source we get the next interrupt message.
207 */
208 spin_lock(&ihost->scic_lock);
209 if (test_bit(IHOST_IRQ_ENABLED, &ihost->flags)) {
210 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
211 writel(0, &ihost->smu_registers->interrupt_mask);
212 }
213 spin_unlock(&ihost->scic_lock);
214
215 return false;
216 }
217
218 irqreturn_t isci_msix_isr(int vec, void *data)
219 {
220 struct isci_host *ihost = data;
221
222 if (sci_controller_isr(ihost))
223 tasklet_schedule(&ihost->completion_tasklet);
224
225 return IRQ_HANDLED;
226 }
227
228 static bool sci_controller_error_isr(struct isci_host *ihost)
229 {
230 u32 interrupt_status;
231
232 interrupt_status =
233 readl(&ihost->smu_registers->interrupt_status);
234 interrupt_status &= (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND);
235
236 if (interrupt_status != 0) {
237 /*
238 * There is an error interrupt pending so let it through and handle
239 * in the callback */
240 return true;
241 }
242
243 /*
244 * There is a race in the hardware that could cause us not to be notified
245 * of an interrupt completion if we do not take this step. We will mask
246 * then unmask the error interrupts so if there was another interrupt
247 * pending we will be notified.
248 * Could we write the value of (SMU_ISR_QUEUE_ERROR | SMU_ISR_QUEUE_SUSPEND)? */
249 writel(0xff, &ihost->smu_registers->interrupt_mask);
250 writel(0, &ihost->smu_registers->interrupt_mask);
251
252 return false;
253 }
254
255 static void sci_controller_task_completion(struct isci_host *ihost, u32 ent)
256 {
257 u32 index = SCU_GET_COMPLETION_INDEX(ent);
258 struct isci_request *ireq = ihost->reqs[index];
259
260 /* Make sure that we really want to process this IO request */
261 if (test_bit(IREQ_ACTIVE, &ireq->flags) &&
262 ireq->io_tag != SCI_CONTROLLER_INVALID_IO_TAG &&
263 ISCI_TAG_SEQ(ireq->io_tag) == ihost->io_request_sequence[index])
264 /* Yep this is a valid io request pass it along to the
265 * io request handler
266 */
267 sci_io_request_tc_completion(ireq, ent);
268 }
269
270 static void sci_controller_sdma_completion(struct isci_host *ihost, u32 ent)
271 {
272 u32 index;
273 struct isci_request *ireq;
274 struct isci_remote_device *idev;
275
276 index = SCU_GET_COMPLETION_INDEX(ent);
277
278 switch (scu_get_command_request_type(ent)) {
279 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_TC:
280 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_TC:
281 ireq = ihost->reqs[index];
282 dev_warn(&ihost->pdev->dev, "%s: %x for io request %p\n",
283 __func__, ent, ireq);
284 /* @todo For a post TC operation we need to fail the IO
285 * request
286 */
287 break;
288 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_DUMP_RNC:
289 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_OTHER_RNC:
290 case SCU_CONTEXT_COMMAND_REQUEST_TYPE_POST_RNC:
291 idev = ihost->device_table[index];
292 dev_warn(&ihost->pdev->dev, "%s: %x for device %p\n",
293 __func__, ent, idev);
294 /* @todo For a port RNC operation we need to fail the
295 * device
296 */
297 break;
298 default:
299 dev_warn(&ihost->pdev->dev, "%s: unknown completion type %x\n",
300 __func__, ent);
301 break;
302 }
303 }
304
305 static void sci_controller_unsolicited_frame(struct isci_host *ihost, u32 ent)
306 {
307 u32 index;
308 u32 frame_index;
309
310 struct scu_unsolicited_frame_header *frame_header;
311 struct isci_phy *iphy;
312 struct isci_remote_device *idev;
313
314 enum sci_status result = SCI_FAILURE;
315
316 frame_index = SCU_GET_FRAME_INDEX(ent);
317
318 frame_header = ihost->uf_control.buffers.array[frame_index].header;
319 ihost->uf_control.buffers.array[frame_index].state = UNSOLICITED_FRAME_IN_USE;
320
321 if (SCU_GET_FRAME_ERROR(ent)) {
322 /*
323 * / @todo If the IAF frame or SIGNATURE FIS frame has an error will
324 * / this cause a problem? We expect the phy initialization will
325 * / fail if there is an error in the frame. */
326 sci_controller_release_frame(ihost, frame_index);
327 return;
328 }
329
330 if (frame_header->is_address_frame) {
331 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
332 iphy = &ihost->phys[index];
333 result = sci_phy_frame_handler(iphy, frame_index);
334 } else {
335
336 index = SCU_GET_COMPLETION_INDEX(ent);
337
338 if (index == SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
339 /*
340 * This is a signature fis or a frame from a direct attached SATA
341 * device that has not yet been created. In either case forwared
342 * the frame to the PE and let it take care of the frame data. */
343 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
344 iphy = &ihost->phys[index];
345 result = sci_phy_frame_handler(iphy, frame_index);
346 } else {
347 if (index < ihost->remote_node_entries)
348 idev = ihost->device_table[index];
349 else
350 idev = NULL;
351
352 if (idev != NULL)
353 result = sci_remote_device_frame_handler(idev, frame_index);
354 else
355 sci_controller_release_frame(ihost, frame_index);
356 }
357 }
358
359 if (result != SCI_SUCCESS) {
360 /*
361 * / @todo Is there any reason to report some additional error message
362 * / when we get this failure notifiction? */
363 }
364 }
365
366 static void sci_controller_event_completion(struct isci_host *ihost, u32 ent)
367 {
368 struct isci_remote_device *idev;
369 struct isci_request *ireq;
370 struct isci_phy *iphy;
371 u32 index;
372
373 index = SCU_GET_COMPLETION_INDEX(ent);
374
375 switch (scu_get_event_type(ent)) {
376 case SCU_EVENT_TYPE_SMU_COMMAND_ERROR:
377 /* / @todo The driver did something wrong and we need to fix the condtion. */
378 dev_err(&ihost->pdev->dev,
379 "%s: SCIC Controller 0x%p received SMU command error "
380 "0x%x\n",
381 __func__,
382 ihost,
383 ent);
384 break;
385
386 case SCU_EVENT_TYPE_SMU_PCQ_ERROR:
387 case SCU_EVENT_TYPE_SMU_ERROR:
388 case SCU_EVENT_TYPE_FATAL_MEMORY_ERROR:
389 /*
390 * / @todo This is a hardware failure and its likely that we want to
391 * / reset the controller. */
392 dev_err(&ihost->pdev->dev,
393 "%s: SCIC Controller 0x%p received fatal controller "
394 "event 0x%x\n",
395 __func__,
396 ihost,
397 ent);
398 break;
399
400 case SCU_EVENT_TYPE_TRANSPORT_ERROR:
401 ireq = ihost->reqs[index];
402 sci_io_request_event_handler(ireq, ent);
403 break;
404
405 case SCU_EVENT_TYPE_PTX_SCHEDULE_EVENT:
406 switch (scu_get_event_specifier(ent)) {
407 case SCU_EVENT_SPECIFIC_SMP_RESPONSE_NO_PE:
408 case SCU_EVENT_SPECIFIC_TASK_TIMEOUT:
409 ireq = ihost->reqs[index];
410 if (ireq != NULL)
411 sci_io_request_event_handler(ireq, ent);
412 else
413 dev_warn(&ihost->pdev->dev,
414 "%s: SCIC Controller 0x%p received "
415 "event 0x%x for io request object "
416 "that doesn't exist.\n",
417 __func__,
418 ihost,
419 ent);
420
421 break;
422
423 case SCU_EVENT_SPECIFIC_IT_NEXUS_TIMEOUT:
424 idev = ihost->device_table[index];
425 if (idev != NULL)
426 sci_remote_device_event_handler(idev, ent);
427 else
428 dev_warn(&ihost->pdev->dev,
429 "%s: SCIC Controller 0x%p received "
430 "event 0x%x for remote device object "
431 "that doesn't exist.\n",
432 __func__,
433 ihost,
434 ent);
435
436 break;
437 }
438 break;
439
440 case SCU_EVENT_TYPE_BROADCAST_CHANGE:
441 /*
442 * direct the broadcast change event to the phy first and then let
443 * the phy redirect the broadcast change to the port object */
444 case SCU_EVENT_TYPE_ERR_CNT_EVENT:
445 /*
446 * direct error counter event to the phy object since that is where
447 * we get the event notification. This is a type 4 event. */
448 case SCU_EVENT_TYPE_OSSP_EVENT:
449 index = SCU_GET_PROTOCOL_ENGINE_INDEX(ent);
450 iphy = &ihost->phys[index];
451 sci_phy_event_handler(iphy, ent);
452 break;
453
454 case SCU_EVENT_TYPE_RNC_SUSPEND_TX:
455 case SCU_EVENT_TYPE_RNC_SUSPEND_TX_RX:
456 case SCU_EVENT_TYPE_RNC_OPS_MISC:
457 if (index < ihost->remote_node_entries) {
458 idev = ihost->device_table[index];
459
460 if (idev != NULL)
461 sci_remote_device_event_handler(idev, ent);
462 } else
463 dev_err(&ihost->pdev->dev,
464 "%s: SCIC Controller 0x%p received event 0x%x "
465 "for remote device object 0x%0x that doesn't "
466 "exist.\n",
467 __func__,
468 ihost,
469 ent,
470 index);
471
472 break;
473
474 default:
475 dev_warn(&ihost->pdev->dev,
476 "%s: SCIC Controller received unknown event code %x\n",
477 __func__,
478 ent);
479 break;
480 }
481 }
482
483 static void sci_controller_process_completions(struct isci_host *ihost)
484 {
485 u32 completion_count = 0;
486 u32 ent;
487 u32 get_index;
488 u32 get_cycle;
489 u32 event_get;
490 u32 event_cycle;
491
492 dev_dbg(&ihost->pdev->dev,
493 "%s: completion queue beginning get:0x%08x\n",
494 __func__,
495 ihost->completion_queue_get);
496
497 /* Get the component parts of the completion queue */
498 get_index = NORMALIZE_GET_POINTER(ihost->completion_queue_get);
499 get_cycle = SMU_CQGR_CYCLE_BIT & ihost->completion_queue_get;
500
501 event_get = NORMALIZE_EVENT_POINTER(ihost->completion_queue_get);
502 event_cycle = SMU_CQGR_EVENT_CYCLE_BIT & ihost->completion_queue_get;
503
504 while (
505 NORMALIZE_GET_POINTER_CYCLE_BIT(get_cycle)
506 == COMPLETION_QUEUE_CYCLE_BIT(ihost->completion_queue[get_index])
507 ) {
508 completion_count++;
509
510 ent = ihost->completion_queue[get_index];
511
512 /* increment the get pointer and check for rollover to toggle the cycle bit */
513 get_cycle ^= ((get_index+1) & SCU_MAX_COMPLETION_QUEUE_ENTRIES) <<
514 (SMU_COMPLETION_QUEUE_GET_CYCLE_BIT_SHIFT - SCU_MAX_COMPLETION_QUEUE_SHIFT);
515 get_index = (get_index+1) & (SCU_MAX_COMPLETION_QUEUE_ENTRIES-1);
516
517 dev_dbg(&ihost->pdev->dev,
518 "%s: completion queue entry:0x%08x\n",
519 __func__,
520 ent);
521
522 switch (SCU_GET_COMPLETION_TYPE(ent)) {
523 case SCU_COMPLETION_TYPE_TASK:
524 sci_controller_task_completion(ihost, ent);
525 break;
526
527 case SCU_COMPLETION_TYPE_SDMA:
528 sci_controller_sdma_completion(ihost, ent);
529 break;
530
531 case SCU_COMPLETION_TYPE_UFI:
532 sci_controller_unsolicited_frame(ihost, ent);
533 break;
534
535 case SCU_COMPLETION_TYPE_EVENT:
536 sci_controller_event_completion(ihost, ent);
537 break;
538
539 case SCU_COMPLETION_TYPE_NOTIFY: {
540 event_cycle ^= ((event_get+1) & SCU_MAX_EVENTS) <<
541 (SMU_COMPLETION_QUEUE_GET_EVENT_CYCLE_BIT_SHIFT - SCU_MAX_EVENTS_SHIFT);
542 event_get = (event_get+1) & (SCU_MAX_EVENTS-1);
543
544 sci_controller_event_completion(ihost, ent);
545 break;
546 }
547 default:
548 dev_warn(&ihost->pdev->dev,
549 "%s: SCIC Controller received unknown "
550 "completion type %x\n",
551 __func__,
552 ent);
553 break;
554 }
555 }
556
557 /* Update the get register if we completed one or more entries */
558 if (completion_count > 0) {
559 ihost->completion_queue_get =
560 SMU_CQGR_GEN_BIT(ENABLE) |
561 SMU_CQGR_GEN_BIT(EVENT_ENABLE) |
562 event_cycle |
563 SMU_CQGR_GEN_VAL(EVENT_POINTER, event_get) |
564 get_cycle |
565 SMU_CQGR_GEN_VAL(POINTER, get_index);
566
567 writel(ihost->completion_queue_get,
568 &ihost->smu_registers->completion_queue_get);
569
570 }
571
572 dev_dbg(&ihost->pdev->dev,
573 "%s: completion queue ending get:0x%08x\n",
574 __func__,
575 ihost->completion_queue_get);
576
577 }
578
579 static void sci_controller_error_handler(struct isci_host *ihost)
580 {
581 u32 interrupt_status;
582
583 interrupt_status =
584 readl(&ihost->smu_registers->interrupt_status);
585
586 if ((interrupt_status & SMU_ISR_QUEUE_SUSPEND) &&
587 sci_controller_completion_queue_has_entries(ihost)) {
588
589 sci_controller_process_completions(ihost);
590 writel(SMU_ISR_QUEUE_SUSPEND, &ihost->smu_registers->interrupt_status);
591 } else {
592 dev_err(&ihost->pdev->dev, "%s: status: %#x\n", __func__,
593 interrupt_status);
594
595 sci_change_state(&ihost->sm, SCIC_FAILED);
596
597 return;
598 }
599
600 /* If we dont process any completions I am not sure that we want to do this.
601 * We are in the middle of a hardware fault and should probably be reset.
602 */
603 writel(0, &ihost->smu_registers->interrupt_mask);
604 }
605
606 irqreturn_t isci_intx_isr(int vec, void *data)
607 {
608 irqreturn_t ret = IRQ_NONE;
609 struct isci_host *ihost = data;
610
611 if (sci_controller_isr(ihost)) {
612 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
613 tasklet_schedule(&ihost->completion_tasklet);
614 ret = IRQ_HANDLED;
615 } else if (sci_controller_error_isr(ihost)) {
616 spin_lock(&ihost->scic_lock);
617 sci_controller_error_handler(ihost);
618 spin_unlock(&ihost->scic_lock);
619 ret = IRQ_HANDLED;
620 }
621
622 return ret;
623 }
624
625 irqreturn_t isci_error_isr(int vec, void *data)
626 {
627 struct isci_host *ihost = data;
628
629 if (sci_controller_error_isr(ihost))
630 sci_controller_error_handler(ihost);
631
632 return IRQ_HANDLED;
633 }
634
635 /**
636 * isci_host_start_complete() - This function is called by the core library,
637 * through the ISCI Module, to indicate controller start status.
638 * @ihost: This parameter specifies the ISCI host object
639 * @completion_status: This parameter specifies the completion status from the
640 * core library.
641 *
642 */
643 static void isci_host_start_complete(struct isci_host *ihost, enum sci_status completion_status)
644 {
645 if (completion_status != SCI_SUCCESS)
646 dev_info(&ihost->pdev->dev,
647 "controller start timed out, continuing...\n");
648 clear_bit(IHOST_START_PENDING, &ihost->flags);
649 wake_up(&ihost->eventq);
650 }
651
652 int isci_host_scan_finished(struct Scsi_Host *shost, unsigned long time)
653 {
654 struct sas_ha_struct *ha = SHOST_TO_SAS_HA(shost);
655 struct isci_host *ihost = ha->lldd_ha;
656
657 if (test_bit(IHOST_START_PENDING, &ihost->flags))
658 return 0;
659
660 sas_drain_work(ha);
661
662 return 1;
663 }
664
665 /**
666 * sci_controller_get_suggested_start_timeout() - This method returns the
667 * suggested sci_controller_start() timeout amount. The user is free to
668 * use any timeout value, but this method provides the suggested minimum
669 * start timeout value. The returned value is based upon empirical
670 * information determined as a result of interoperability testing.
671 * @ihost: the handle to the controller object for which to return the
672 * suggested start timeout.
673 *
674 * This method returns the number of milliseconds for the suggested start
675 * operation timeout.
676 */
677 static u32 sci_controller_get_suggested_start_timeout(struct isci_host *ihost)
678 {
679 /* Validate the user supplied parameters. */
680 if (!ihost)
681 return 0;
682
683 /*
684 * The suggested minimum timeout value for a controller start operation:
685 *
686 * Signature FIS Timeout
687 * + Phy Start Timeout
688 * + Number of Phy Spin Up Intervals
689 * ---------------------------------
690 * Number of milliseconds for the controller start operation.
691 *
692 * NOTE: The number of phy spin up intervals will be equivalent
693 * to the number of phys divided by the number phys allowed
694 * per interval - 1 (once OEM parameters are supported).
695 * Currently we assume only 1 phy per interval. */
696
697 return SCIC_SDS_SIGNATURE_FIS_TIMEOUT
698 + SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT
699 + ((SCI_MAX_PHYS - 1) * SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
700 }
701
702 static void sci_controller_enable_interrupts(struct isci_host *ihost)
703 {
704 set_bit(IHOST_IRQ_ENABLED, &ihost->flags);
705 writel(0, &ihost->smu_registers->interrupt_mask);
706 }
707
708 void sci_controller_disable_interrupts(struct isci_host *ihost)
709 {
710 clear_bit(IHOST_IRQ_ENABLED, &ihost->flags);
711 writel(0xffffffff, &ihost->smu_registers->interrupt_mask);
712 readl(&ihost->smu_registers->interrupt_mask); /* flush */
713 }
714
715 static void sci_controller_enable_port_task_scheduler(struct isci_host *ihost)
716 {
717 u32 port_task_scheduler_value;
718
719 port_task_scheduler_value =
720 readl(&ihost->scu_registers->peg0.ptsg.control);
721 port_task_scheduler_value |=
722 (SCU_PTSGCR_GEN_BIT(ETM_ENABLE) |
723 SCU_PTSGCR_GEN_BIT(PTSG_ENABLE));
724 writel(port_task_scheduler_value,
725 &ihost->scu_registers->peg0.ptsg.control);
726 }
727
728 static void sci_controller_assign_task_entries(struct isci_host *ihost)
729 {
730 u32 task_assignment;
731
732 /*
733 * Assign all the TCs to function 0
734 * TODO: Do we actually need to read this register to write it back?
735 */
736
737 task_assignment =
738 readl(&ihost->smu_registers->task_context_assignment[0]);
739
740 task_assignment |= (SMU_TCA_GEN_VAL(STARTING, 0)) |
741 (SMU_TCA_GEN_VAL(ENDING, ihost->task_context_entries - 1)) |
742 (SMU_TCA_GEN_BIT(RANGE_CHECK_ENABLE));
743
744 writel(task_assignment,
745 &ihost->smu_registers->task_context_assignment[0]);
746
747 }
748
749 static void sci_controller_initialize_completion_queue(struct isci_host *ihost)
750 {
751 u32 index;
752 u32 completion_queue_control_value;
753 u32 completion_queue_get_value;
754 u32 completion_queue_put_value;
755
756 ihost->completion_queue_get = 0;
757
758 completion_queue_control_value =
759 (SMU_CQC_QUEUE_LIMIT_SET(SCU_MAX_COMPLETION_QUEUE_ENTRIES - 1) |
760 SMU_CQC_EVENT_LIMIT_SET(SCU_MAX_EVENTS - 1));
761
762 writel(completion_queue_control_value,
763 &ihost->smu_registers->completion_queue_control);
764
765
766 /* Set the completion queue get pointer and enable the queue */
767 completion_queue_get_value = (
768 (SMU_CQGR_GEN_VAL(POINTER, 0))
769 | (SMU_CQGR_GEN_VAL(EVENT_POINTER, 0))
770 | (SMU_CQGR_GEN_BIT(ENABLE))
771 | (SMU_CQGR_GEN_BIT(EVENT_ENABLE))
772 );
773
774 writel(completion_queue_get_value,
775 &ihost->smu_registers->completion_queue_get);
776
777 /* Set the completion queue put pointer */
778 completion_queue_put_value = (
779 (SMU_CQPR_GEN_VAL(POINTER, 0))
780 | (SMU_CQPR_GEN_VAL(EVENT_POINTER, 0))
781 );
782
783 writel(completion_queue_put_value,
784 &ihost->smu_registers->completion_queue_put);
785
786 /* Initialize the cycle bit of the completion queue entries */
787 for (index = 0; index < SCU_MAX_COMPLETION_QUEUE_ENTRIES; index++) {
788 /*
789 * If get.cycle_bit != completion_queue.cycle_bit
790 * its not a valid completion queue entry
791 * so at system start all entries are invalid */
792 ihost->completion_queue[index] = 0x80000000;
793 }
794 }
795
796 static void sci_controller_initialize_unsolicited_frame_queue(struct isci_host *ihost)
797 {
798 u32 frame_queue_control_value;
799 u32 frame_queue_get_value;
800 u32 frame_queue_put_value;
801
802 /* Write the queue size */
803 frame_queue_control_value =
804 SCU_UFQC_GEN_VAL(QUEUE_SIZE, SCU_MAX_UNSOLICITED_FRAMES);
805
806 writel(frame_queue_control_value,
807 &ihost->scu_registers->sdma.unsolicited_frame_queue_control);
808
809 /* Setup the get pointer for the unsolicited frame queue */
810 frame_queue_get_value = (
811 SCU_UFQGP_GEN_VAL(POINTER, 0)
812 | SCU_UFQGP_GEN_BIT(ENABLE_BIT)
813 );
814
815 writel(frame_queue_get_value,
816 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
817 /* Setup the put pointer for the unsolicited frame queue */
818 frame_queue_put_value = SCU_UFQPP_GEN_VAL(POINTER, 0);
819 writel(frame_queue_put_value,
820 &ihost->scu_registers->sdma.unsolicited_frame_put_pointer);
821 }
822
823 void sci_controller_transition_to_ready(struct isci_host *ihost, enum sci_status status)
824 {
825 if (ihost->sm.current_state_id == SCIC_STARTING) {
826 /*
827 * We move into the ready state, because some of the phys/ports
828 * may be up and operational.
829 */
830 sci_change_state(&ihost->sm, SCIC_READY);
831
832 isci_host_start_complete(ihost, status);
833 }
834 }
835
836 static bool is_phy_starting(struct isci_phy *iphy)
837 {
838 enum sci_phy_states state;
839
840 state = iphy->sm.current_state_id;
841 switch (state) {
842 case SCI_PHY_STARTING:
843 case SCI_PHY_SUB_INITIAL:
844 case SCI_PHY_SUB_AWAIT_SAS_SPEED_EN:
845 case SCI_PHY_SUB_AWAIT_IAF_UF:
846 case SCI_PHY_SUB_AWAIT_SAS_POWER:
847 case SCI_PHY_SUB_AWAIT_SATA_POWER:
848 case SCI_PHY_SUB_AWAIT_SATA_PHY_EN:
849 case SCI_PHY_SUB_AWAIT_SATA_SPEED_EN:
850 case SCI_PHY_SUB_AWAIT_OSSP_EN:
851 case SCI_PHY_SUB_AWAIT_SIG_FIS_UF:
852 case SCI_PHY_SUB_FINAL:
853 return true;
854 default:
855 return false;
856 }
857 }
858
859 bool is_controller_start_complete(struct isci_host *ihost)
860 {
861 int i;
862
863 for (i = 0; i < SCI_MAX_PHYS; i++) {
864 struct isci_phy *iphy = &ihost->phys[i];
865 u32 state = iphy->sm.current_state_id;
866
867 /* in apc mode we need to check every phy, in
868 * mpc mode we only need to check phys that have
869 * been configured into a port
870 */
871 if (is_port_config_apc(ihost))
872 /* pass */;
873 else if (!phy_get_non_dummy_port(iphy))
874 continue;
875
876 /* The controller start operation is complete iff:
877 * - all links have been given an opportunity to start
878 * - have no indication of a connected device
879 * - have an indication of a connected device and it has
880 * finished the link training process.
881 */
882 if ((iphy->is_in_link_training == false && state == SCI_PHY_INITIAL) ||
883 (iphy->is_in_link_training == false && state == SCI_PHY_STOPPED) ||
884 (iphy->is_in_link_training == true && is_phy_starting(iphy)) ||
885 (ihost->port_agent.phy_ready_mask != ihost->port_agent.phy_configured_mask))
886 return false;
887 }
888
889 return true;
890 }
891
892 /**
893 * sci_controller_start_next_phy - start phy
894 * @ihost: controller
895 *
896 * If all the phys have been started, then attempt to transition the
897 * controller to the READY state and inform the user
898 * (sci_cb_controller_start_complete()).
899 */
900 static enum sci_status sci_controller_start_next_phy(struct isci_host *ihost)
901 {
902 struct sci_oem_params *oem = &ihost->oem_parameters;
903 struct isci_phy *iphy;
904 enum sci_status status;
905
906 status = SCI_SUCCESS;
907
908 if (ihost->phy_startup_timer_pending)
909 return status;
910
911 if (ihost->next_phy_to_start >= SCI_MAX_PHYS) {
912 if (is_controller_start_complete(ihost)) {
913 sci_controller_transition_to_ready(ihost, SCI_SUCCESS);
914 sci_del_timer(&ihost->phy_timer);
915 ihost->phy_startup_timer_pending = false;
916 }
917 } else {
918 iphy = &ihost->phys[ihost->next_phy_to_start];
919
920 if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
921 if (phy_get_non_dummy_port(iphy) == NULL) {
922 ihost->next_phy_to_start++;
923
924 /* Caution recursion ahead be forwarned
925 *
926 * The PHY was never added to a PORT in MPC mode
927 * so start the next phy in sequence This phy
928 * will never go link up and will not draw power
929 * the OEM parameters either configured the phy
930 * incorrectly for the PORT or it was never
931 * assigned to a PORT
932 */
933 return sci_controller_start_next_phy(ihost);
934 }
935 }
936
937 status = sci_phy_start(iphy);
938
939 if (status == SCI_SUCCESS) {
940 sci_mod_timer(&ihost->phy_timer,
941 SCIC_SDS_CONTROLLER_PHY_START_TIMEOUT);
942 ihost->phy_startup_timer_pending = true;
943 } else {
944 dev_warn(&ihost->pdev->dev,
945 "%s: Controller stop operation failed "
946 "to stop phy %d because of status "
947 "%d.\n",
948 __func__,
949 ihost->phys[ihost->next_phy_to_start].phy_index,
950 status);
951 }
952
953 ihost->next_phy_to_start++;
954 }
955
956 return status;
957 }
958
959 static void phy_startup_timeout(struct timer_list *t)
960 {
961 struct sci_timer *tmr = from_timer(tmr, t, timer);
962 struct isci_host *ihost = container_of(tmr, typeof(*ihost), phy_timer);
963 unsigned long flags;
964 enum sci_status status;
965
966 spin_lock_irqsave(&ihost->scic_lock, flags);
967
968 if (tmr->cancel)
969 goto done;
970
971 ihost->phy_startup_timer_pending = false;
972
973 do {
974 status = sci_controller_start_next_phy(ihost);
975 } while (status != SCI_SUCCESS);
976
977 done:
978 spin_unlock_irqrestore(&ihost->scic_lock, flags);
979 }
980
981 static u16 isci_tci_active(struct isci_host *ihost)
982 {
983 return CIRC_CNT(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
984 }
985
986 static enum sci_status sci_controller_start(struct isci_host *ihost,
987 u32 timeout)
988 {
989 enum sci_status result;
990 u16 index;
991
992 if (ihost->sm.current_state_id != SCIC_INITIALIZED) {
993 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
994 __func__, ihost->sm.current_state_id);
995 return SCI_FAILURE_INVALID_STATE;
996 }
997
998 /* Build the TCi free pool */
999 BUILD_BUG_ON(SCI_MAX_IO_REQUESTS > 1 << sizeof(ihost->tci_pool[0]) * 8);
1000 ihost->tci_head = 0;
1001 ihost->tci_tail = 0;
1002 for (index = 0; index < ihost->task_context_entries; index++)
1003 isci_tci_free(ihost, index);
1004
1005 /* Build the RNi free pool */
1006 sci_remote_node_table_initialize(&ihost->available_remote_nodes,
1007 ihost->remote_node_entries);
1008
1009 /*
1010 * Before anything else lets make sure we will not be
1011 * interrupted by the hardware.
1012 */
1013 sci_controller_disable_interrupts(ihost);
1014
1015 /* Enable the port task scheduler */
1016 sci_controller_enable_port_task_scheduler(ihost);
1017
1018 /* Assign all the task entries to ihost physical function */
1019 sci_controller_assign_task_entries(ihost);
1020
1021 /* Now initialize the completion queue */
1022 sci_controller_initialize_completion_queue(ihost);
1023
1024 /* Initialize the unsolicited frame queue for use */
1025 sci_controller_initialize_unsolicited_frame_queue(ihost);
1026
1027 /* Start all of the ports on this controller */
1028 for (index = 0; index < ihost->logical_port_entries; index++) {
1029 struct isci_port *iport = &ihost->ports[index];
1030
1031 result = sci_port_start(iport);
1032 if (result)
1033 return result;
1034 }
1035
1036 sci_controller_start_next_phy(ihost);
1037
1038 sci_mod_timer(&ihost->timer, timeout);
1039
1040 sci_change_state(&ihost->sm, SCIC_STARTING);
1041
1042 return SCI_SUCCESS;
1043 }
1044
1045 void isci_host_start(struct Scsi_Host *shost)
1046 {
1047 struct isci_host *ihost = SHOST_TO_SAS_HA(shost)->lldd_ha;
1048 unsigned long tmo = sci_controller_get_suggested_start_timeout(ihost);
1049
1050 set_bit(IHOST_START_PENDING, &ihost->flags);
1051
1052 spin_lock_irq(&ihost->scic_lock);
1053 sci_controller_start(ihost, tmo);
1054 sci_controller_enable_interrupts(ihost);
1055 spin_unlock_irq(&ihost->scic_lock);
1056 }
1057
1058 static void isci_host_stop_complete(struct isci_host *ihost)
1059 {
1060 sci_controller_disable_interrupts(ihost);
1061 clear_bit(IHOST_STOP_PENDING, &ihost->flags);
1062 wake_up(&ihost->eventq);
1063 }
1064
1065 static void sci_controller_completion_handler(struct isci_host *ihost)
1066 {
1067 /* Empty out the completion queue */
1068 if (sci_controller_completion_queue_has_entries(ihost))
1069 sci_controller_process_completions(ihost);
1070
1071 /* Clear the interrupt and enable all interrupts again */
1072 writel(SMU_ISR_COMPLETION, &ihost->smu_registers->interrupt_status);
1073 /* Could we write the value of SMU_ISR_COMPLETION? */
1074 writel(0xFF000000, &ihost->smu_registers->interrupt_mask);
1075 writel(0, &ihost->smu_registers->interrupt_mask);
1076 }
1077
1078 void ireq_done(struct isci_host *ihost, struct isci_request *ireq, struct sas_task *task)
1079 {
1080 if (!test_bit(IREQ_ABORT_PATH_ACTIVE, &ireq->flags) &&
1081 !(task->task_state_flags & SAS_TASK_STATE_ABORTED)) {
1082 if (test_bit(IREQ_COMPLETE_IN_TARGET, &ireq->flags)) {
1083 /* Normal notification (task_done) */
1084 dev_dbg(&ihost->pdev->dev,
1085 "%s: Normal - ireq/task = %p/%p\n",
1086 __func__, ireq, task);
1087 task->lldd_task = NULL;
1088 task->task_done(task);
1089 } else {
1090 dev_dbg(&ihost->pdev->dev,
1091 "%s: Error - ireq/task = %p/%p\n",
1092 __func__, ireq, task);
1093 if (sas_protocol_ata(task->task_proto))
1094 task->lldd_task = NULL;
1095 sas_task_abort(task);
1096 }
1097 } else
1098 task->lldd_task = NULL;
1099
1100 if (test_and_clear_bit(IREQ_ABORT_PATH_ACTIVE, &ireq->flags))
1101 wake_up_all(&ihost->eventq);
1102
1103 if (!test_bit(IREQ_NO_AUTO_FREE_TAG, &ireq->flags))
1104 isci_free_tag(ihost, ireq->io_tag);
1105 }
1106 /**
1107 * isci_host_completion_routine() - This function is the delayed service
1108 * routine that calls the sci core library's completion handler. It's
1109 * scheduled as a tasklet from the interrupt service routine when interrupts
1110 * in use, or set as the timeout function in polled mode.
1111 * @data: This parameter specifies the ISCI host object
1112 *
1113 */
1114 void isci_host_completion_routine(unsigned long data)
1115 {
1116 struct isci_host *ihost = (struct isci_host *)data;
1117 u16 active;
1118
1119 spin_lock_irq(&ihost->scic_lock);
1120 sci_controller_completion_handler(ihost);
1121 spin_unlock_irq(&ihost->scic_lock);
1122
1123 /*
1124 * we subtract SCI_MAX_PORTS to account for the number of dummy TCs
1125 * issued for hardware issue workaround
1126 */
1127 active = isci_tci_active(ihost) - SCI_MAX_PORTS;
1128
1129 /*
1130 * the coalesence timeout doubles at each encoding step, so
1131 * update it based on the ilog2 value of the outstanding requests
1132 */
1133 writel(SMU_ICC_GEN_VAL(NUMBER, active) |
1134 SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)),
1135 &ihost->smu_registers->interrupt_coalesce_control);
1136 }
1137
1138 /**
1139 * sci_controller_stop() - This method will stop an individual controller
1140 * object.This method will invoke the associated user callback upon
1141 * completion. The completion callback is called when the following
1142 * conditions are met: -# the method return status is SCI_SUCCESS. -# the
1143 * controller has been quiesced. This method will ensure that all IO
1144 * requests are quiesced, phys are stopped, and all additional operation by
1145 * the hardware is halted.
1146 * @ihost: the handle to the controller object to stop.
1147 * @timeout: This parameter specifies the number of milliseconds in which the
1148 * stop operation should complete.
1149 *
1150 * The controller must be in the STARTED or STOPPED state. Indicate if the
1151 * controller stop method succeeded or failed in some way. SCI_SUCCESS if the
1152 * stop operation successfully began. SCI_WARNING_ALREADY_IN_STATE if the
1153 * controller is already in the STOPPED state. SCI_FAILURE_INVALID_STATE if the
1154 * controller is not either in the STARTED or STOPPED states.
1155 */
1156 static enum sci_status sci_controller_stop(struct isci_host *ihost, u32 timeout)
1157 {
1158 if (ihost->sm.current_state_id != SCIC_READY) {
1159 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
1160 __func__, ihost->sm.current_state_id);
1161 return SCI_FAILURE_INVALID_STATE;
1162 }
1163
1164 sci_mod_timer(&ihost->timer, timeout);
1165 sci_change_state(&ihost->sm, SCIC_STOPPING);
1166 return SCI_SUCCESS;
1167 }
1168
1169 /**
1170 * sci_controller_reset() - This method will reset the supplied core
1171 * controller regardless of the state of said controller. This operation is
1172 * considered destructive. In other words, all current operations are wiped
1173 * out. No IO completions for outstanding devices occur. Outstanding IO
1174 * requests are not aborted or completed at the actual remote device.
1175 * @ihost: the handle to the controller object to reset.
1176 *
1177 * Indicate if the controller reset method succeeded or failed in some way.
1178 * SCI_SUCCESS if the reset operation successfully started. SCI_FATAL_ERROR if
1179 * the controller reset operation is unable to complete.
1180 */
1181 static enum sci_status sci_controller_reset(struct isci_host *ihost)
1182 {
1183 switch (ihost->sm.current_state_id) {
1184 case SCIC_RESET:
1185 case SCIC_READY:
1186 case SCIC_STOPPING:
1187 case SCIC_FAILED:
1188 /*
1189 * The reset operation is not a graceful cleanup, just
1190 * perform the state transition.
1191 */
1192 sci_change_state(&ihost->sm, SCIC_RESETTING);
1193 return SCI_SUCCESS;
1194 default:
1195 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
1196 __func__, ihost->sm.current_state_id);
1197 return SCI_FAILURE_INVALID_STATE;
1198 }
1199 }
1200
1201 static enum sci_status sci_controller_stop_phys(struct isci_host *ihost)
1202 {
1203 u32 index;
1204 enum sci_status status;
1205 enum sci_status phy_status;
1206
1207 status = SCI_SUCCESS;
1208
1209 for (index = 0; index < SCI_MAX_PHYS; index++) {
1210 phy_status = sci_phy_stop(&ihost->phys[index]);
1211
1212 if (phy_status != SCI_SUCCESS &&
1213 phy_status != SCI_FAILURE_INVALID_STATE) {
1214 status = SCI_FAILURE;
1215
1216 dev_warn(&ihost->pdev->dev,
1217 "%s: Controller stop operation failed to stop "
1218 "phy %d because of status %d.\n",
1219 __func__,
1220 ihost->phys[index].phy_index, phy_status);
1221 }
1222 }
1223
1224 return status;
1225 }
1226
1227
1228 /**
1229 * isci_host_deinit - shutdown frame reception and dma
1230 * @ihost: host to take down
1231 *
1232 * This is called in either the driver shutdown or the suspend path. In
1233 * the shutdown case libsas went through port teardown and normal device
1234 * removal (i.e. physical links stayed up to service scsi_device removal
1235 * commands). In the suspend case we disable the hardware without
1236 * notifying libsas of the link down events since we want libsas to
1237 * remember the domain across the suspend/resume cycle
1238 */
1239 void isci_host_deinit(struct isci_host *ihost)
1240 {
1241 int i;
1242
1243 /* disable output data selects */
1244 for (i = 0; i < isci_gpio_count(ihost); i++)
1245 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
1246
1247 set_bit(IHOST_STOP_PENDING, &ihost->flags);
1248
1249 spin_lock_irq(&ihost->scic_lock);
1250 sci_controller_stop(ihost, SCIC_CONTROLLER_STOP_TIMEOUT);
1251 spin_unlock_irq(&ihost->scic_lock);
1252
1253 wait_for_stop(ihost);
1254
1255 /* phy stop is after controller stop to allow port and device to
1256 * go idle before shutting down the phys, but the expectation is
1257 * that i/o has been shut off well before we reach this
1258 * function.
1259 */
1260 sci_controller_stop_phys(ihost);
1261
1262 /* disable sgpio: where the above wait should give time for the
1263 * enclosure to sample the gpios going inactive
1264 */
1265 writel(0, &ihost->scu_registers->peg0.sgpio.interface_control);
1266
1267 spin_lock_irq(&ihost->scic_lock);
1268 sci_controller_reset(ihost);
1269 spin_unlock_irq(&ihost->scic_lock);
1270
1271 /* Cancel any/all outstanding port timers */
1272 for (i = 0; i < ihost->logical_port_entries; i++) {
1273 struct isci_port *iport = &ihost->ports[i];
1274 del_timer_sync(&iport->timer.timer);
1275 }
1276
1277 /* Cancel any/all outstanding phy timers */
1278 for (i = 0; i < SCI_MAX_PHYS; i++) {
1279 struct isci_phy *iphy = &ihost->phys[i];
1280 del_timer_sync(&iphy->sata_timer.timer);
1281 }
1282
1283 del_timer_sync(&ihost->port_agent.timer.timer);
1284
1285 del_timer_sync(&ihost->power_control.timer.timer);
1286
1287 del_timer_sync(&ihost->timer.timer);
1288
1289 del_timer_sync(&ihost->phy_timer.timer);
1290 }
1291
1292 static void __iomem *scu_base(struct isci_host *isci_host)
1293 {
1294 struct pci_dev *pdev = isci_host->pdev;
1295 int id = isci_host->id;
1296
1297 return pcim_iomap_table(pdev)[SCI_SCU_BAR * 2] + SCI_SCU_BAR_SIZE * id;
1298 }
1299
1300 static void __iomem *smu_base(struct isci_host *isci_host)
1301 {
1302 struct pci_dev *pdev = isci_host->pdev;
1303 int id = isci_host->id;
1304
1305 return pcim_iomap_table(pdev)[SCI_SMU_BAR * 2] + SCI_SMU_BAR_SIZE * id;
1306 }
1307
1308 static void sci_controller_initial_state_enter(struct sci_base_state_machine *sm)
1309 {
1310 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1311
1312 sci_change_state(&ihost->sm, SCIC_RESET);
1313 }
1314
1315 static inline void sci_controller_starting_state_exit(struct sci_base_state_machine *sm)
1316 {
1317 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1318
1319 sci_del_timer(&ihost->timer);
1320 }
1321
1322 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS 853
1323 #define INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS 1280
1324 #define INTERRUPT_COALESCE_TIMEOUT_MAX_US 2700000
1325 #define INTERRUPT_COALESCE_NUMBER_MAX 256
1326 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN 7
1327 #define INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX 28
1328
1329 /**
1330 * sci_controller_set_interrupt_coalescence() - This method allows the user to
1331 * configure the interrupt coalescence.
1332 * @ihost: This parameter represents the handle to the controller object
1333 * for which its interrupt coalesce register is overridden.
1334 * @coalesce_number: Used to control the number of entries in the Completion
1335 * Queue before an interrupt is generated. If the number of entries exceed
1336 * this number, an interrupt will be generated. The valid range of the input
1337 * is [0, 256]. A setting of 0 results in coalescing being disabled.
1338 * @coalesce_timeout: Timeout value in microseconds. The valid range of the
1339 * input is [0, 2700000] . A setting of 0 is allowed and results in no
1340 * interrupt coalescing timeout.
1341 *
1342 * Indicate if the user successfully set the interrupt coalesce parameters.
1343 * SCI_SUCCESS The user successfully updated the interrutp coalescence.
1344 * SCI_FAILURE_INVALID_PARAMETER_VALUE The user input value is out of range.
1345 */
1346 static enum sci_status
1347 sci_controller_set_interrupt_coalescence(struct isci_host *ihost,
1348 u32 coalesce_number,
1349 u32 coalesce_timeout)
1350 {
1351 u8 timeout_encode = 0;
1352 u32 min = 0;
1353 u32 max = 0;
1354
1355 /* Check if the input parameters fall in the range. */
1356 if (coalesce_number > INTERRUPT_COALESCE_NUMBER_MAX)
1357 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1358
1359 /*
1360 * Defined encoding for interrupt coalescing timeout:
1361 * Value Min Max Units
1362 * ----- --- --- -----
1363 * 0 - - Disabled
1364 * 1 13.3 20.0 ns
1365 * 2 26.7 40.0
1366 * 3 53.3 80.0
1367 * 4 106.7 160.0
1368 * 5 213.3 320.0
1369 * 6 426.7 640.0
1370 * 7 853.3 1280.0
1371 * 8 1.7 2.6 us
1372 * 9 3.4 5.1
1373 * 10 6.8 10.2
1374 * 11 13.7 20.5
1375 * 12 27.3 41.0
1376 * 13 54.6 81.9
1377 * 14 109.2 163.8
1378 * 15 218.5 327.7
1379 * 16 436.9 655.4
1380 * 17 873.8 1310.7
1381 * 18 1.7 2.6 ms
1382 * 19 3.5 5.2
1383 * 20 7.0 10.5
1384 * 21 14.0 21.0
1385 * 22 28.0 41.9
1386 * 23 55.9 83.9
1387 * 24 111.8 167.8
1388 * 25 223.7 335.5
1389 * 26 447.4 671.1
1390 * 27 894.8 1342.2
1391 * 28 1.8 2.7 s
1392 * Others Undefined */
1393
1394 /*
1395 * Use the table above to decide the encode of interrupt coalescing timeout
1396 * value for register writing. */
1397 if (coalesce_timeout == 0)
1398 timeout_encode = 0;
1399 else{
1400 /* make the timeout value in unit of (10 ns). */
1401 coalesce_timeout = coalesce_timeout * 100;
1402 min = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_LOWER_BOUND_NS / 10;
1403 max = INTERRUPT_COALESCE_TIMEOUT_BASE_RANGE_UPPER_BOUND_NS / 10;
1404
1405 /* get the encode of timeout for register writing. */
1406 for (timeout_encode = INTERRUPT_COALESCE_TIMEOUT_ENCODE_MIN;
1407 timeout_encode <= INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX;
1408 timeout_encode++) {
1409 if (min <= coalesce_timeout && max > coalesce_timeout)
1410 break;
1411 else if (coalesce_timeout >= max && coalesce_timeout < min * 2
1412 && coalesce_timeout <= INTERRUPT_COALESCE_TIMEOUT_MAX_US * 100) {
1413 if ((coalesce_timeout - max) < (2 * min - coalesce_timeout))
1414 break;
1415 else{
1416 timeout_encode++;
1417 break;
1418 }
1419 } else {
1420 max = max * 2;
1421 min = min * 2;
1422 }
1423 }
1424
1425 if (timeout_encode == INTERRUPT_COALESCE_TIMEOUT_ENCODE_MAX + 1)
1426 /* the value is out of range. */
1427 return SCI_FAILURE_INVALID_PARAMETER_VALUE;
1428 }
1429
1430 writel(SMU_ICC_GEN_VAL(NUMBER, coalesce_number) |
1431 SMU_ICC_GEN_VAL(TIMER, timeout_encode),
1432 &ihost->smu_registers->interrupt_coalesce_control);
1433
1434
1435 ihost->interrupt_coalesce_number = (u16)coalesce_number;
1436 ihost->interrupt_coalesce_timeout = coalesce_timeout / 100;
1437
1438 return SCI_SUCCESS;
1439 }
1440
1441
1442 static void sci_controller_ready_state_enter(struct sci_base_state_machine *sm)
1443 {
1444 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1445 u32 val;
1446
1447 /* enable clock gating for power control of the scu unit */
1448 val = readl(&ihost->smu_registers->clock_gating_control);
1449 val &= ~(SMU_CGUCR_GEN_BIT(REGCLK_ENABLE) |
1450 SMU_CGUCR_GEN_BIT(TXCLK_ENABLE) |
1451 SMU_CGUCR_GEN_BIT(XCLK_ENABLE));
1452 val |= SMU_CGUCR_GEN_BIT(IDLE_ENABLE);
1453 writel(val, &ihost->smu_registers->clock_gating_control);
1454
1455 /* set the default interrupt coalescence number and timeout value. */
1456 sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1457 }
1458
1459 static void sci_controller_ready_state_exit(struct sci_base_state_machine *sm)
1460 {
1461 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1462
1463 /* disable interrupt coalescence. */
1464 sci_controller_set_interrupt_coalescence(ihost, 0, 0);
1465 }
1466
1467 static enum sci_status sci_controller_stop_ports(struct isci_host *ihost)
1468 {
1469 u32 index;
1470 enum sci_status port_status;
1471 enum sci_status status = SCI_SUCCESS;
1472
1473 for (index = 0; index < ihost->logical_port_entries; index++) {
1474 struct isci_port *iport = &ihost->ports[index];
1475
1476 port_status = sci_port_stop(iport);
1477
1478 if ((port_status != SCI_SUCCESS) &&
1479 (port_status != SCI_FAILURE_INVALID_STATE)) {
1480 status = SCI_FAILURE;
1481
1482 dev_warn(&ihost->pdev->dev,
1483 "%s: Controller stop operation failed to "
1484 "stop port %d because of status %d.\n",
1485 __func__,
1486 iport->logical_port_index,
1487 port_status);
1488 }
1489 }
1490
1491 return status;
1492 }
1493
1494 static enum sci_status sci_controller_stop_devices(struct isci_host *ihost)
1495 {
1496 u32 index;
1497 enum sci_status status;
1498 enum sci_status device_status;
1499
1500 status = SCI_SUCCESS;
1501
1502 for (index = 0; index < ihost->remote_node_entries; index++) {
1503 if (ihost->device_table[index] != NULL) {
1504 /* / @todo What timeout value do we want to provide to this request? */
1505 device_status = sci_remote_device_stop(ihost->device_table[index], 0);
1506
1507 if ((device_status != SCI_SUCCESS) &&
1508 (device_status != SCI_FAILURE_INVALID_STATE)) {
1509 dev_warn(&ihost->pdev->dev,
1510 "%s: Controller stop operation failed "
1511 "to stop device 0x%p because of "
1512 "status %d.\n",
1513 __func__,
1514 ihost->device_table[index], device_status);
1515 }
1516 }
1517 }
1518
1519 return status;
1520 }
1521
1522 static void sci_controller_stopping_state_enter(struct sci_base_state_machine *sm)
1523 {
1524 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1525
1526 sci_controller_stop_devices(ihost);
1527 sci_controller_stop_ports(ihost);
1528
1529 if (!sci_controller_has_remote_devices_stopping(ihost))
1530 isci_host_stop_complete(ihost);
1531 }
1532
1533 static void sci_controller_stopping_state_exit(struct sci_base_state_machine *sm)
1534 {
1535 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1536
1537 sci_del_timer(&ihost->timer);
1538 }
1539
1540 static void sci_controller_reset_hardware(struct isci_host *ihost)
1541 {
1542 /* Disable interrupts so we dont take any spurious interrupts */
1543 sci_controller_disable_interrupts(ihost);
1544
1545 /* Reset the SCU */
1546 writel(0xFFFFFFFF, &ihost->smu_registers->soft_reset_control);
1547
1548 /* Delay for 1ms to before clearing the CQP and UFQPR. */
1549 udelay(1000);
1550
1551 /* The write to the CQGR clears the CQP */
1552 writel(0x00000000, &ihost->smu_registers->completion_queue_get);
1553
1554 /* The write to the UFQGP clears the UFQPR */
1555 writel(0, &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
1556
1557 /* clear all interrupts */
1558 writel(~SMU_INTERRUPT_STATUS_RESERVED_MASK, &ihost->smu_registers->interrupt_status);
1559 }
1560
1561 static void sci_controller_resetting_state_enter(struct sci_base_state_machine *sm)
1562 {
1563 struct isci_host *ihost = container_of(sm, typeof(*ihost), sm);
1564
1565 sci_controller_reset_hardware(ihost);
1566 sci_change_state(&ihost->sm, SCIC_RESET);
1567 }
1568
1569 static const struct sci_base_state sci_controller_state_table[] = {
1570 [SCIC_INITIAL] = {
1571 .enter_state = sci_controller_initial_state_enter,
1572 },
1573 [SCIC_RESET] = {},
1574 [SCIC_INITIALIZING] = {},
1575 [SCIC_INITIALIZED] = {},
1576 [SCIC_STARTING] = {
1577 .exit_state = sci_controller_starting_state_exit,
1578 },
1579 [SCIC_READY] = {
1580 .enter_state = sci_controller_ready_state_enter,
1581 .exit_state = sci_controller_ready_state_exit,
1582 },
1583 [SCIC_RESETTING] = {
1584 .enter_state = sci_controller_resetting_state_enter,
1585 },
1586 [SCIC_STOPPING] = {
1587 .enter_state = sci_controller_stopping_state_enter,
1588 .exit_state = sci_controller_stopping_state_exit,
1589 },
1590 [SCIC_FAILED] = {}
1591 };
1592
1593 static void controller_timeout(struct timer_list *t)
1594 {
1595 struct sci_timer *tmr = from_timer(tmr, t, timer);
1596 struct isci_host *ihost = container_of(tmr, typeof(*ihost), timer);
1597 struct sci_base_state_machine *sm = &ihost->sm;
1598 unsigned long flags;
1599
1600 spin_lock_irqsave(&ihost->scic_lock, flags);
1601
1602 if (tmr->cancel)
1603 goto done;
1604
1605 if (sm->current_state_id == SCIC_STARTING)
1606 sci_controller_transition_to_ready(ihost, SCI_FAILURE_TIMEOUT);
1607 else if (sm->current_state_id == SCIC_STOPPING) {
1608 sci_change_state(sm, SCIC_FAILED);
1609 isci_host_stop_complete(ihost);
1610 } else /* / @todo Now what do we want to do in this case? */
1611 dev_err(&ihost->pdev->dev,
1612 "%s: Controller timer fired when controller was not "
1613 "in a state being timed.\n",
1614 __func__);
1615
1616 done:
1617 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1618 }
1619
1620 static enum sci_status sci_controller_construct(struct isci_host *ihost,
1621 void __iomem *scu_base,
1622 void __iomem *smu_base)
1623 {
1624 u8 i;
1625
1626 sci_init_sm(&ihost->sm, sci_controller_state_table, SCIC_INITIAL);
1627
1628 ihost->scu_registers = scu_base;
1629 ihost->smu_registers = smu_base;
1630
1631 sci_port_configuration_agent_construct(&ihost->port_agent);
1632
1633 /* Construct the ports for this controller */
1634 for (i = 0; i < SCI_MAX_PORTS; i++)
1635 sci_port_construct(&ihost->ports[i], i, ihost);
1636 sci_port_construct(&ihost->ports[i], SCIC_SDS_DUMMY_PORT, ihost);
1637
1638 /* Construct the phys for this controller */
1639 for (i = 0; i < SCI_MAX_PHYS; i++) {
1640 /* Add all the PHYs to the dummy port */
1641 sci_phy_construct(&ihost->phys[i],
1642 &ihost->ports[SCI_MAX_PORTS], i);
1643 }
1644
1645 ihost->invalid_phy_mask = 0;
1646
1647 sci_init_timer(&ihost->timer, controller_timeout);
1648
1649 return sci_controller_reset(ihost);
1650 }
1651
1652 int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version)
1653 {
1654 int i;
1655
1656 for (i = 0; i < SCI_MAX_PORTS; i++)
1657 if (oem->ports[i].phy_mask > SCIC_SDS_PARM_PHY_MASK_MAX)
1658 return -EINVAL;
1659
1660 for (i = 0; i < SCI_MAX_PHYS; i++)
1661 if (oem->phys[i].sas_address.high == 0 &&
1662 oem->phys[i].sas_address.low == 0)
1663 return -EINVAL;
1664
1665 if (oem->controller.mode_type == SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE) {
1666 for (i = 0; i < SCI_MAX_PHYS; i++)
1667 if (oem->ports[i].phy_mask != 0)
1668 return -EINVAL;
1669 } else if (oem->controller.mode_type == SCIC_PORT_MANUAL_CONFIGURATION_MODE) {
1670 u8 phy_mask = 0;
1671
1672 for (i = 0; i < SCI_MAX_PHYS; i++)
1673 phy_mask |= oem->ports[i].phy_mask;
1674
1675 if (phy_mask == 0)
1676 return -EINVAL;
1677 } else
1678 return -EINVAL;
1679
1680 if (oem->controller.max_concurr_spin_up > MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT ||
1681 oem->controller.max_concurr_spin_up < 1)
1682 return -EINVAL;
1683
1684 if (oem->controller.do_enable_ssc) {
1685 if (version < ISCI_ROM_VER_1_1 && oem->controller.do_enable_ssc != 1)
1686 return -EINVAL;
1687
1688 if (version >= ISCI_ROM_VER_1_1) {
1689 u8 test = oem->controller.ssc_sata_tx_spread_level;
1690
1691 switch (test) {
1692 case 0:
1693 case 2:
1694 case 3:
1695 case 6:
1696 case 7:
1697 break;
1698 default:
1699 return -EINVAL;
1700 }
1701
1702 test = oem->controller.ssc_sas_tx_spread_level;
1703 if (oem->controller.ssc_sas_tx_type == 0) {
1704 switch (test) {
1705 case 0:
1706 case 2:
1707 case 3:
1708 break;
1709 default:
1710 return -EINVAL;
1711 }
1712 } else if (oem->controller.ssc_sas_tx_type == 1) {
1713 switch (test) {
1714 case 0:
1715 case 3:
1716 case 6:
1717 break;
1718 default:
1719 return -EINVAL;
1720 }
1721 }
1722 }
1723 }
1724
1725 return 0;
1726 }
1727
1728 static u8 max_spin_up(struct isci_host *ihost)
1729 {
1730 if (ihost->user_parameters.max_concurr_spinup)
1731 return min_t(u8, ihost->user_parameters.max_concurr_spinup,
1732 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1733 else
1734 return min_t(u8, ihost->oem_parameters.controller.max_concurr_spin_up,
1735 MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT);
1736 }
1737
1738 static void power_control_timeout(struct timer_list *t)
1739 {
1740 struct sci_timer *tmr = from_timer(tmr, t, timer);
1741 struct isci_host *ihost = container_of(tmr, typeof(*ihost), power_control.timer);
1742 struct isci_phy *iphy;
1743 unsigned long flags;
1744 u8 i;
1745
1746 spin_lock_irqsave(&ihost->scic_lock, flags);
1747
1748 if (tmr->cancel)
1749 goto done;
1750
1751 ihost->power_control.phys_granted_power = 0;
1752
1753 if (ihost->power_control.phys_waiting == 0) {
1754 ihost->power_control.timer_started = false;
1755 goto done;
1756 }
1757
1758 for (i = 0; i < SCI_MAX_PHYS; i++) {
1759
1760 if (ihost->power_control.phys_waiting == 0)
1761 break;
1762
1763 iphy = ihost->power_control.requesters[i];
1764 if (iphy == NULL)
1765 continue;
1766
1767 if (ihost->power_control.phys_granted_power >= max_spin_up(ihost))
1768 break;
1769
1770 ihost->power_control.requesters[i] = NULL;
1771 ihost->power_control.phys_waiting--;
1772 ihost->power_control.phys_granted_power++;
1773 sci_phy_consume_power_handler(iphy);
1774
1775 if (iphy->protocol == SAS_PROTOCOL_SSP) {
1776 u8 j;
1777
1778 for (j = 0; j < SCI_MAX_PHYS; j++) {
1779 struct isci_phy *requester = ihost->power_control.requesters[j];
1780
1781 /*
1782 * Search the power_control queue to see if there are other phys
1783 * attached to the same remote device. If found, take all of
1784 * them out of await_sas_power state.
1785 */
1786 if (requester != NULL && requester != iphy) {
1787 u8 other = memcmp(requester->frame_rcvd.iaf.sas_addr,
1788 iphy->frame_rcvd.iaf.sas_addr,
1789 sizeof(requester->frame_rcvd.iaf.sas_addr));
1790
1791 if (other == 0) {
1792 ihost->power_control.requesters[j] = NULL;
1793 ihost->power_control.phys_waiting--;
1794 sci_phy_consume_power_handler(requester);
1795 }
1796 }
1797 }
1798 }
1799 }
1800
1801 /*
1802 * It doesn't matter if the power list is empty, we need to start the
1803 * timer in case another phy becomes ready.
1804 */
1805 sci_mod_timer(tmr, SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1806 ihost->power_control.timer_started = true;
1807
1808 done:
1809 spin_unlock_irqrestore(&ihost->scic_lock, flags);
1810 }
1811
1812 void sci_controller_power_control_queue_insert(struct isci_host *ihost,
1813 struct isci_phy *iphy)
1814 {
1815 BUG_ON(iphy == NULL);
1816
1817 if (ihost->power_control.phys_granted_power < max_spin_up(ihost)) {
1818 ihost->power_control.phys_granted_power++;
1819 sci_phy_consume_power_handler(iphy);
1820
1821 /*
1822 * stop and start the power_control timer. When the timer fires, the
1823 * no_of_phys_granted_power will be set to 0
1824 */
1825 if (ihost->power_control.timer_started)
1826 sci_del_timer(&ihost->power_control.timer);
1827
1828 sci_mod_timer(&ihost->power_control.timer,
1829 SCIC_SDS_CONTROLLER_POWER_CONTROL_INTERVAL);
1830 ihost->power_control.timer_started = true;
1831
1832 } else {
1833 /*
1834 * There are phys, attached to the same sas address as this phy, are
1835 * already in READY state, this phy don't need wait.
1836 */
1837 u8 i;
1838 struct isci_phy *current_phy;
1839
1840 for (i = 0; i < SCI_MAX_PHYS; i++) {
1841 u8 other;
1842 current_phy = &ihost->phys[i];
1843
1844 other = memcmp(current_phy->frame_rcvd.iaf.sas_addr,
1845 iphy->frame_rcvd.iaf.sas_addr,
1846 sizeof(current_phy->frame_rcvd.iaf.sas_addr));
1847
1848 if (current_phy->sm.current_state_id == SCI_PHY_READY &&
1849 current_phy->protocol == SAS_PROTOCOL_SSP &&
1850 other == 0) {
1851 sci_phy_consume_power_handler(iphy);
1852 break;
1853 }
1854 }
1855
1856 if (i == SCI_MAX_PHYS) {
1857 /* Add the phy in the waiting list */
1858 ihost->power_control.requesters[iphy->phy_index] = iphy;
1859 ihost->power_control.phys_waiting++;
1860 }
1861 }
1862 }
1863
1864 void sci_controller_power_control_queue_remove(struct isci_host *ihost,
1865 struct isci_phy *iphy)
1866 {
1867 BUG_ON(iphy == NULL);
1868
1869 if (ihost->power_control.requesters[iphy->phy_index])
1870 ihost->power_control.phys_waiting--;
1871
1872 ihost->power_control.requesters[iphy->phy_index] = NULL;
1873 }
1874
1875 static int is_long_cable(int phy, unsigned char selection_byte)
1876 {
1877 return !!(selection_byte & (1 << phy));
1878 }
1879
1880 static int is_medium_cable(int phy, unsigned char selection_byte)
1881 {
1882 return !!(selection_byte & (1 << (phy + 4)));
1883 }
1884
1885 static enum cable_selections decode_selection_byte(
1886 int phy,
1887 unsigned char selection_byte)
1888 {
1889 return ((selection_byte & (1 << phy)) ? 1 : 0)
1890 + (selection_byte & (1 << (phy + 4)) ? 2 : 0);
1891 }
1892
1893 static unsigned char *to_cable_select(struct isci_host *ihost)
1894 {
1895 if (is_cable_select_overridden())
1896 return ((unsigned char *)&cable_selection_override)
1897 + ihost->id;
1898 else
1899 return &ihost->oem_parameters.controller.cable_selection_mask;
1900 }
1901
1902 enum cable_selections decode_cable_selection(struct isci_host *ihost, int phy)
1903 {
1904 return decode_selection_byte(phy, *to_cable_select(ihost));
1905 }
1906
1907 char *lookup_cable_names(enum cable_selections selection)
1908 {
1909 static char *cable_names[] = {
1910 [short_cable] = "short",
1911 [long_cable] = "long",
1912 [medium_cable] = "medium",
1913 [undefined_cable] = "<undefined, assumed long>" /* bit 0==1 */
1914 };
1915 return (selection <= undefined_cable) ? cable_names[selection]
1916 : cable_names[undefined_cable];
1917 }
1918
1919 #define AFE_REGISTER_WRITE_DELAY 10
1920
1921 static void sci_controller_afe_initialization(struct isci_host *ihost)
1922 {
1923 struct scu_afe_registers __iomem *afe = &ihost->scu_registers->afe;
1924 const struct sci_oem_params *oem = &ihost->oem_parameters;
1925 struct pci_dev *pdev = ihost->pdev;
1926 u32 afe_status;
1927 u32 phy_id;
1928 unsigned char cable_selection_mask = *to_cable_select(ihost);
1929
1930 /* Clear DFX Status registers */
1931 writel(0x0081000f, &afe->afe_dfx_master_control0);
1932 udelay(AFE_REGISTER_WRITE_DELAY);
1933
1934 if (is_b0(pdev) || is_c0(pdev) || is_c1(pdev)) {
1935 /* PM Rx Equalization Save, PM SPhy Rx Acknowledgement
1936 * Timer, PM Stagger Timer
1937 */
1938 writel(0x0007FFFF, &afe->afe_pmsn_master_control2);
1939 udelay(AFE_REGISTER_WRITE_DELAY);
1940 }
1941
1942 /* Configure bias currents to normal */
1943 if (is_a2(pdev))
1944 writel(0x00005A00, &afe->afe_bias_control);
1945 else if (is_b0(pdev) || is_c0(pdev))
1946 writel(0x00005F00, &afe->afe_bias_control);
1947 else if (is_c1(pdev))
1948 writel(0x00005500, &afe->afe_bias_control);
1949
1950 udelay(AFE_REGISTER_WRITE_DELAY);
1951
1952 /* Enable PLL */
1953 if (is_a2(pdev))
1954 writel(0x80040908, &afe->afe_pll_control0);
1955 else if (is_b0(pdev) || is_c0(pdev))
1956 writel(0x80040A08, &afe->afe_pll_control0);
1957 else if (is_c1(pdev)) {
1958 writel(0x80000B08, &afe->afe_pll_control0);
1959 udelay(AFE_REGISTER_WRITE_DELAY);
1960 writel(0x00000B08, &afe->afe_pll_control0);
1961 udelay(AFE_REGISTER_WRITE_DELAY);
1962 writel(0x80000B08, &afe->afe_pll_control0);
1963 }
1964
1965 udelay(AFE_REGISTER_WRITE_DELAY);
1966
1967 /* Wait for the PLL to lock */
1968 do {
1969 afe_status = readl(&afe->afe_common_block_status);
1970 udelay(AFE_REGISTER_WRITE_DELAY);
1971 } while ((afe_status & 0x00001000) == 0);
1972
1973 if (is_a2(pdev)) {
1974 /* Shorten SAS SNW lock time (RxLock timer value from 76
1975 * us to 50 us)
1976 */
1977 writel(0x7bcc96ad, &afe->afe_pmsn_master_control0);
1978 udelay(AFE_REGISTER_WRITE_DELAY);
1979 }
1980
1981 for (phy_id = 0; phy_id < SCI_MAX_PHYS; phy_id++) {
1982 struct scu_afe_transceiver __iomem *xcvr = &afe->scu_afe_xcvr[phy_id];
1983 const struct sci_phy_oem_params *oem_phy = &oem->phys[phy_id];
1984 int cable_length_long =
1985 is_long_cable(phy_id, cable_selection_mask);
1986 int cable_length_medium =
1987 is_medium_cable(phy_id, cable_selection_mask);
1988
1989 if (is_a2(pdev)) {
1990 /* All defaults, except the Receive Word
1991 * Alignament/Comma Detect Enable....(0xe800)
1992 */
1993 writel(0x00004512, &xcvr->afe_xcvr_control0);
1994 udelay(AFE_REGISTER_WRITE_DELAY);
1995
1996 writel(0x0050100F, &xcvr->afe_xcvr_control1);
1997 udelay(AFE_REGISTER_WRITE_DELAY);
1998 } else if (is_b0(pdev)) {
1999 /* Configure transmitter SSC parameters */
2000 writel(0x00030000, &xcvr->afe_tx_ssc_control);
2001 udelay(AFE_REGISTER_WRITE_DELAY);
2002 } else if (is_c0(pdev)) {
2003 /* Configure transmitter SSC parameters */
2004 writel(0x00010202, &xcvr->afe_tx_ssc_control);
2005 udelay(AFE_REGISTER_WRITE_DELAY);
2006
2007 /* All defaults, except the Receive Word
2008 * Alignament/Comma Detect Enable....(0xe800)
2009 */
2010 writel(0x00014500, &xcvr->afe_xcvr_control0);
2011 udelay(AFE_REGISTER_WRITE_DELAY);
2012 } else if (is_c1(pdev)) {
2013 /* Configure transmitter SSC parameters */
2014 writel(0x00010202, &xcvr->afe_tx_ssc_control);
2015 udelay(AFE_REGISTER_WRITE_DELAY);
2016
2017 /* All defaults, except the Receive Word
2018 * Alignament/Comma Detect Enable....(0xe800)
2019 */
2020 writel(0x0001C500, &xcvr->afe_xcvr_control0);
2021 udelay(AFE_REGISTER_WRITE_DELAY);
2022 }
2023
2024 /* Power up TX and RX out from power down (PWRDNTX and
2025 * PWRDNRX) & increase TX int & ext bias 20%....(0xe85c)
2026 */
2027 if (is_a2(pdev))
2028 writel(0x000003F0, &xcvr->afe_channel_control);
2029 else if (is_b0(pdev)) {
2030 writel(0x000003D7, &xcvr->afe_channel_control);
2031 udelay(AFE_REGISTER_WRITE_DELAY);
2032
2033 writel(0x000003D4, &xcvr->afe_channel_control);
2034 } else if (is_c0(pdev)) {
2035 writel(0x000001E7, &xcvr->afe_channel_control);
2036 udelay(AFE_REGISTER_WRITE_DELAY);
2037
2038 writel(0x000001E4, &xcvr->afe_channel_control);
2039 } else if (is_c1(pdev)) {
2040 writel(cable_length_long ? 0x000002F7 : 0x000001F7,
2041 &xcvr->afe_channel_control);
2042 udelay(AFE_REGISTER_WRITE_DELAY);
2043
2044 writel(cable_length_long ? 0x000002F4 : 0x000001F4,
2045 &xcvr->afe_channel_control);
2046 }
2047 udelay(AFE_REGISTER_WRITE_DELAY);
2048
2049 if (is_a2(pdev)) {
2050 /* Enable TX equalization (0xe824) */
2051 writel(0x00040000, &xcvr->afe_tx_control);
2052 udelay(AFE_REGISTER_WRITE_DELAY);
2053 }
2054
2055 if (is_a2(pdev) || is_b0(pdev))
2056 /* RDPI=0x0(RX Power On), RXOOBDETPDNC=0x0,
2057 * TPD=0x0(TX Power On), RDD=0x0(RX Detect
2058 * Enabled) ....(0xe800)
2059 */
2060 writel(0x00004100, &xcvr->afe_xcvr_control0);
2061 else if (is_c0(pdev))
2062 writel(0x00014100, &xcvr->afe_xcvr_control0);
2063 else if (is_c1(pdev))
2064 writel(0x0001C100, &xcvr->afe_xcvr_control0);
2065 udelay(AFE_REGISTER_WRITE_DELAY);
2066
2067 /* Leave DFE/FFE on */
2068 if (is_a2(pdev))
2069 writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2070 else if (is_b0(pdev)) {
2071 writel(0x3F11103F, &xcvr->afe_rx_ssc_control0);
2072 udelay(AFE_REGISTER_WRITE_DELAY);
2073 /* Enable TX equalization (0xe824) */
2074 writel(0x00040000, &xcvr->afe_tx_control);
2075 } else if (is_c0(pdev)) {
2076 writel(0x01400C0F, &xcvr->afe_rx_ssc_control1);
2077 udelay(AFE_REGISTER_WRITE_DELAY);
2078
2079 writel(0x3F6F103F, &xcvr->afe_rx_ssc_control0);
2080 udelay(AFE_REGISTER_WRITE_DELAY);
2081
2082 /* Enable TX equalization (0xe824) */
2083 writel(0x00040000, &xcvr->afe_tx_control);
2084 } else if (is_c1(pdev)) {
2085 writel(cable_length_long ? 0x01500C0C :
2086 cable_length_medium ? 0x01400C0D : 0x02400C0D,
2087 &xcvr->afe_xcvr_control1);
2088 udelay(AFE_REGISTER_WRITE_DELAY);
2089
2090 writel(0x000003E0, &xcvr->afe_dfx_rx_control1);
2091 udelay(AFE_REGISTER_WRITE_DELAY);
2092
2093 writel(cable_length_long ? 0x33091C1F :
2094 cable_length_medium ? 0x3315181F : 0x2B17161F,
2095 &xcvr->afe_rx_ssc_control0);
2096 udelay(AFE_REGISTER_WRITE_DELAY);
2097
2098 /* Enable TX equalization (0xe824) */
2099 writel(0x00040000, &xcvr->afe_tx_control);
2100 }
2101
2102 udelay(AFE_REGISTER_WRITE_DELAY);
2103
2104 writel(oem_phy->afe_tx_amp_control0, &xcvr->afe_tx_amp_control0);
2105 udelay(AFE_REGISTER_WRITE_DELAY);
2106
2107 writel(oem_phy->afe_tx_amp_control1, &xcvr->afe_tx_amp_control1);
2108 udelay(AFE_REGISTER_WRITE_DELAY);
2109
2110 writel(oem_phy->afe_tx_amp_control2, &xcvr->afe_tx_amp_control2);
2111 udelay(AFE_REGISTER_WRITE_DELAY);
2112
2113 writel(oem_phy->afe_tx_amp_control3, &xcvr->afe_tx_amp_control3);
2114 udelay(AFE_REGISTER_WRITE_DELAY);
2115 }
2116
2117 /* Transfer control to the PEs */
2118 writel(0x00010f00, &afe->afe_dfx_master_control0);
2119 udelay(AFE_REGISTER_WRITE_DELAY);
2120 }
2121
2122 static void sci_controller_initialize_power_control(struct isci_host *ihost)
2123 {
2124 sci_init_timer(&ihost->power_control.timer, power_control_timeout);
2125
2126 memset(ihost->power_control.requesters, 0,
2127 sizeof(ihost->power_control.requesters));
2128
2129 ihost->power_control.phys_waiting = 0;
2130 ihost->power_control.phys_granted_power = 0;
2131 }
2132
2133 static enum sci_status sci_controller_initialize(struct isci_host *ihost)
2134 {
2135 struct sci_base_state_machine *sm = &ihost->sm;
2136 enum sci_status result = SCI_FAILURE;
2137 unsigned long i, state, val;
2138
2139 if (ihost->sm.current_state_id != SCIC_RESET) {
2140 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2141 __func__, ihost->sm.current_state_id);
2142 return SCI_FAILURE_INVALID_STATE;
2143 }
2144
2145 sci_change_state(sm, SCIC_INITIALIZING);
2146
2147 sci_init_timer(&ihost->phy_timer, phy_startup_timeout);
2148
2149 ihost->next_phy_to_start = 0;
2150 ihost->phy_startup_timer_pending = false;
2151
2152 sci_controller_initialize_power_control(ihost);
2153
2154 /*
2155 * There is nothing to do here for B0 since we do not have to
2156 * program the AFE registers.
2157 * / @todo The AFE settings are supposed to be correct for the B0 but
2158 * / presently they seem to be wrong. */
2159 sci_controller_afe_initialization(ihost);
2160
2161
2162 /* Take the hardware out of reset */
2163 writel(0, &ihost->smu_registers->soft_reset_control);
2164
2165 /*
2166 * / @todo Provide meaningfull error code for hardware failure
2167 * result = SCI_FAILURE_CONTROLLER_HARDWARE; */
2168 for (i = 100; i >= 1; i--) {
2169 u32 status;
2170
2171 /* Loop until the hardware reports success */
2172 udelay(SCU_CONTEXT_RAM_INIT_STALL_TIME);
2173 status = readl(&ihost->smu_registers->control_status);
2174
2175 if ((status & SCU_RAM_INIT_COMPLETED) == SCU_RAM_INIT_COMPLETED)
2176 break;
2177 }
2178 if (i == 0)
2179 goto out;
2180
2181 /*
2182 * Determine what are the actaul device capacities that the
2183 * hardware will support */
2184 val = readl(&ihost->smu_registers->device_context_capacity);
2185
2186 /* Record the smaller of the two capacity values */
2187 ihost->logical_port_entries = min(smu_max_ports(val), SCI_MAX_PORTS);
2188 ihost->task_context_entries = min(smu_max_task_contexts(val), SCI_MAX_IO_REQUESTS);
2189 ihost->remote_node_entries = min(smu_max_rncs(val), SCI_MAX_REMOTE_DEVICES);
2190
2191 /*
2192 * Make all PEs that are unassigned match up with the
2193 * logical ports
2194 */
2195 for (i = 0; i < ihost->logical_port_entries; i++) {
2196 struct scu_port_task_scheduler_group_registers __iomem
2197 *ptsg = &ihost->scu_registers->peg0.ptsg;
2198
2199 writel(i, &ptsg->protocol_engine[i]);
2200 }
2201
2202 /* Initialize hardware PCI Relaxed ordering in DMA engines */
2203 val = readl(&ihost->scu_registers->sdma.pdma_configuration);
2204 val |= SCU_PDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2205 writel(val, &ihost->scu_registers->sdma.pdma_configuration);
2206
2207 val = readl(&ihost->scu_registers->sdma.cdma_configuration);
2208 val |= SCU_CDMACR_GEN_BIT(PCI_RELAXED_ORDERING_ENABLE);
2209 writel(val, &ihost->scu_registers->sdma.cdma_configuration);
2210
2211 /*
2212 * Initialize the PHYs before the PORTs because the PHY registers
2213 * are accessed during the port initialization.
2214 */
2215 for (i = 0; i < SCI_MAX_PHYS; i++) {
2216 result = sci_phy_initialize(&ihost->phys[i],
2217 &ihost->scu_registers->peg0.pe[i].tl,
2218 &ihost->scu_registers->peg0.pe[i].ll);
2219 if (result != SCI_SUCCESS)
2220 goto out;
2221 }
2222
2223 for (i = 0; i < ihost->logical_port_entries; i++) {
2224 struct isci_port *iport = &ihost->ports[i];
2225
2226 iport->port_task_scheduler_registers = &ihost->scu_registers->peg0.ptsg.port[i];
2227 iport->port_pe_configuration_register = &ihost->scu_registers->peg0.ptsg.protocol_engine[0];
2228 iport->viit_registers = &ihost->scu_registers->peg0.viit[i];
2229 }
2230
2231 result = sci_port_configuration_agent_initialize(ihost, &ihost->port_agent);
2232
2233 out:
2234 /* Advance the controller state machine */
2235 if (result == SCI_SUCCESS)
2236 state = SCIC_INITIALIZED;
2237 else
2238 state = SCIC_FAILED;
2239 sci_change_state(sm, state);
2240
2241 return result;
2242 }
2243
2244 static int sci_controller_dma_alloc(struct isci_host *ihost)
2245 {
2246 struct device *dev = &ihost->pdev->dev;
2247 size_t size;
2248 int i;
2249
2250 /* detect re-initialization */
2251 if (ihost->completion_queue)
2252 return 0;
2253
2254 size = SCU_MAX_COMPLETION_QUEUE_ENTRIES * sizeof(u32);
2255 ihost->completion_queue = dmam_alloc_coherent(dev, size, &ihost->cq_dma,
2256 GFP_KERNEL);
2257 if (!ihost->completion_queue)
2258 return -ENOMEM;
2259
2260 size = ihost->remote_node_entries * sizeof(union scu_remote_node_context);
2261 ihost->remote_node_context_table = dmam_alloc_coherent(dev, size, &ihost->rnc_dma,
2262 GFP_KERNEL);
2263
2264 if (!ihost->remote_node_context_table)
2265 return -ENOMEM;
2266
2267 size = ihost->task_context_entries * sizeof(struct scu_task_context),
2268 ihost->task_context_table = dmam_alloc_coherent(dev, size, &ihost->tc_dma,
2269 GFP_KERNEL);
2270 if (!ihost->task_context_table)
2271 return -ENOMEM;
2272
2273 size = SCI_UFI_TOTAL_SIZE;
2274 ihost->ufi_buf = dmam_alloc_coherent(dev, size, &ihost->ufi_dma, GFP_KERNEL);
2275 if (!ihost->ufi_buf)
2276 return -ENOMEM;
2277
2278 for (i = 0; i < SCI_MAX_IO_REQUESTS; i++) {
2279 struct isci_request *ireq;
2280 dma_addr_t dma;
2281
2282 ireq = dmam_alloc_coherent(dev, sizeof(*ireq), &dma, GFP_KERNEL);
2283 if (!ireq)
2284 return -ENOMEM;
2285
2286 ireq->tc = &ihost->task_context_table[i];
2287 ireq->owning_controller = ihost;
2288 ireq->request_daddr = dma;
2289 ireq->isci_host = ihost;
2290 ihost->reqs[i] = ireq;
2291 }
2292
2293 return 0;
2294 }
2295
2296 static int sci_controller_mem_init(struct isci_host *ihost)
2297 {
2298 int err = sci_controller_dma_alloc(ihost);
2299
2300 if (err)
2301 return err;
2302
2303 writel(lower_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_lower);
2304 writel(upper_32_bits(ihost->cq_dma), &ihost->smu_registers->completion_queue_upper);
2305
2306 writel(lower_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_lower);
2307 writel(upper_32_bits(ihost->rnc_dma), &ihost->smu_registers->remote_node_context_upper);
2308
2309 writel(lower_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_lower);
2310 writel(upper_32_bits(ihost->tc_dma), &ihost->smu_registers->host_task_table_upper);
2311
2312 sci_unsolicited_frame_control_construct(ihost);
2313
2314 /*
2315 * Inform the silicon as to the location of the UF headers and
2316 * address table.
2317 */
2318 writel(lower_32_bits(ihost->uf_control.headers.physical_address),
2319 &ihost->scu_registers->sdma.uf_header_base_address_lower);
2320 writel(upper_32_bits(ihost->uf_control.headers.physical_address),
2321 &ihost->scu_registers->sdma.uf_header_base_address_upper);
2322
2323 writel(lower_32_bits(ihost->uf_control.address_table.physical_address),
2324 &ihost->scu_registers->sdma.uf_address_table_lower);
2325 writel(upper_32_bits(ihost->uf_control.address_table.physical_address),
2326 &ihost->scu_registers->sdma.uf_address_table_upper);
2327
2328 return 0;
2329 }
2330
2331 /**
2332 * isci_host_init - (re-)initialize hardware and internal (private) state
2333 * @ihost: host to init
2334 *
2335 * Any public facing objects (like asd_sas_port, and asd_sas_phys), or
2336 * one-time initialization objects like locks and waitqueues, are
2337 * not touched (they are initialized in isci_host_alloc)
2338 */
2339 int isci_host_init(struct isci_host *ihost)
2340 {
2341 int i, err;
2342 enum sci_status status;
2343
2344 spin_lock_irq(&ihost->scic_lock);
2345 status = sci_controller_construct(ihost, scu_base(ihost), smu_base(ihost));
2346 spin_unlock_irq(&ihost->scic_lock);
2347 if (status != SCI_SUCCESS) {
2348 dev_err(&ihost->pdev->dev,
2349 "%s: sci_controller_construct failed - status = %x\n",
2350 __func__,
2351 status);
2352 return -ENODEV;
2353 }
2354
2355 spin_lock_irq(&ihost->scic_lock);
2356 status = sci_controller_initialize(ihost);
2357 spin_unlock_irq(&ihost->scic_lock);
2358 if (status != SCI_SUCCESS) {
2359 dev_warn(&ihost->pdev->dev,
2360 "%s: sci_controller_initialize failed -"
2361 " status = 0x%x\n",
2362 __func__, status);
2363 return -ENODEV;
2364 }
2365
2366 err = sci_controller_mem_init(ihost);
2367 if (err)
2368 return err;
2369
2370 /* enable sgpio */
2371 writel(1, &ihost->scu_registers->peg0.sgpio.interface_control);
2372 for (i = 0; i < isci_gpio_count(ihost); i++)
2373 writel(SGPIO_HW_CONTROL, &ihost->scu_registers->peg0.sgpio.output_data_select[i]);
2374 writel(0, &ihost->scu_registers->peg0.sgpio.vendor_specific_code);
2375
2376 return 0;
2377 }
2378
2379 void sci_controller_link_up(struct isci_host *ihost, struct isci_port *iport,
2380 struct isci_phy *iphy)
2381 {
2382 switch (ihost->sm.current_state_id) {
2383 case SCIC_STARTING:
2384 sci_del_timer(&ihost->phy_timer);
2385 ihost->phy_startup_timer_pending = false;
2386 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2387 iport, iphy);
2388 sci_controller_start_next_phy(ihost);
2389 break;
2390 case SCIC_READY:
2391 ihost->port_agent.link_up_handler(ihost, &ihost->port_agent,
2392 iport, iphy);
2393 break;
2394 default:
2395 dev_dbg(&ihost->pdev->dev,
2396 "%s: SCIC Controller linkup event from phy %d in "
2397 "unexpected state %d\n", __func__, iphy->phy_index,
2398 ihost->sm.current_state_id);
2399 }
2400 }
2401
2402 void sci_controller_link_down(struct isci_host *ihost, struct isci_port *iport,
2403 struct isci_phy *iphy)
2404 {
2405 switch (ihost->sm.current_state_id) {
2406 case SCIC_STARTING:
2407 case SCIC_READY:
2408 ihost->port_agent.link_down_handler(ihost, &ihost->port_agent,
2409 iport, iphy);
2410 break;
2411 default:
2412 dev_dbg(&ihost->pdev->dev,
2413 "%s: SCIC Controller linkdown event from phy %d in "
2414 "unexpected state %d\n",
2415 __func__,
2416 iphy->phy_index,
2417 ihost->sm.current_state_id);
2418 }
2419 }
2420
2421 bool sci_controller_has_remote_devices_stopping(struct isci_host *ihost)
2422 {
2423 u32 index;
2424
2425 for (index = 0; index < ihost->remote_node_entries; index++) {
2426 if ((ihost->device_table[index] != NULL) &&
2427 (ihost->device_table[index]->sm.current_state_id == SCI_DEV_STOPPING))
2428 return true;
2429 }
2430
2431 return false;
2432 }
2433
2434 void sci_controller_remote_device_stopped(struct isci_host *ihost,
2435 struct isci_remote_device *idev)
2436 {
2437 if (ihost->sm.current_state_id != SCIC_STOPPING) {
2438 dev_dbg(&ihost->pdev->dev,
2439 "SCIC Controller 0x%p remote device stopped event "
2440 "from device 0x%p in unexpected state %d\n",
2441 ihost, idev,
2442 ihost->sm.current_state_id);
2443 return;
2444 }
2445
2446 if (!sci_controller_has_remote_devices_stopping(ihost))
2447 isci_host_stop_complete(ihost);
2448 }
2449
2450 void sci_controller_post_request(struct isci_host *ihost, u32 request)
2451 {
2452 dev_dbg(&ihost->pdev->dev, "%s[%d]: %#x\n",
2453 __func__, ihost->id, request);
2454
2455 writel(request, &ihost->smu_registers->post_context_port);
2456 }
2457
2458 struct isci_request *sci_request_by_tag(struct isci_host *ihost, u16 io_tag)
2459 {
2460 u16 task_index;
2461 u16 task_sequence;
2462
2463 task_index = ISCI_TAG_TCI(io_tag);
2464
2465 if (task_index < ihost->task_context_entries) {
2466 struct isci_request *ireq = ihost->reqs[task_index];
2467
2468 if (test_bit(IREQ_ACTIVE, &ireq->flags)) {
2469 task_sequence = ISCI_TAG_SEQ(io_tag);
2470
2471 if (task_sequence == ihost->io_request_sequence[task_index])
2472 return ireq;
2473 }
2474 }
2475
2476 return NULL;
2477 }
2478
2479 /**
2480 * sci_controller_allocate_remote_node_context()
2481 * This method allocates remote node index and the reserves the remote node
2482 * context space for use. This method can fail if there are no more remote
2483 * node index available.
2484 * @ihost: This is the controller object which contains the set of
2485 * free remote node ids
2486 * @idev: This is the device object which is requesting the a remote node
2487 * id
2488 * @node_id: This is the remote node id that is assinged to the device if one
2489 * is available
2490 *
2491 * enum sci_status SCI_FAILURE_OUT_OF_RESOURCES if there are no available remote
2492 * node index available.
2493 */
2494 enum sci_status sci_controller_allocate_remote_node_context(struct isci_host *ihost,
2495 struct isci_remote_device *idev,
2496 u16 *node_id)
2497 {
2498 u16 node_index;
2499 u32 remote_node_count = sci_remote_device_node_count(idev);
2500
2501 node_index = sci_remote_node_table_allocate_remote_node(
2502 &ihost->available_remote_nodes, remote_node_count
2503 );
2504
2505 if (node_index != SCIC_SDS_REMOTE_NODE_CONTEXT_INVALID_INDEX) {
2506 ihost->device_table[node_index] = idev;
2507
2508 *node_id = node_index;
2509
2510 return SCI_SUCCESS;
2511 }
2512
2513 return SCI_FAILURE_INSUFFICIENT_RESOURCES;
2514 }
2515
2516 void sci_controller_free_remote_node_context(struct isci_host *ihost,
2517 struct isci_remote_device *idev,
2518 u16 node_id)
2519 {
2520 u32 remote_node_count = sci_remote_device_node_count(idev);
2521
2522 if (ihost->device_table[node_id] == idev) {
2523 ihost->device_table[node_id] = NULL;
2524
2525 sci_remote_node_table_release_remote_node_index(
2526 &ihost->available_remote_nodes, remote_node_count, node_id
2527 );
2528 }
2529 }
2530
2531 void sci_controller_copy_sata_response(void *response_buffer,
2532 void *frame_header,
2533 void *frame_buffer)
2534 {
2535 /* XXX type safety? */
2536 memcpy(response_buffer, frame_header, sizeof(u32));
2537
2538 memcpy(response_buffer + sizeof(u32),
2539 frame_buffer,
2540 sizeof(struct dev_to_host_fis) - sizeof(u32));
2541 }
2542
2543 void sci_controller_release_frame(struct isci_host *ihost, u32 frame_index)
2544 {
2545 if (sci_unsolicited_frame_control_release_frame(&ihost->uf_control, frame_index))
2546 writel(ihost->uf_control.get,
2547 &ihost->scu_registers->sdma.unsolicited_frame_get_pointer);
2548 }
2549
2550 void isci_tci_free(struct isci_host *ihost, u16 tci)
2551 {
2552 u16 tail = ihost->tci_tail & (SCI_MAX_IO_REQUESTS-1);
2553
2554 ihost->tci_pool[tail] = tci;
2555 ihost->tci_tail = tail + 1;
2556 }
2557
2558 static u16 isci_tci_alloc(struct isci_host *ihost)
2559 {
2560 u16 head = ihost->tci_head & (SCI_MAX_IO_REQUESTS-1);
2561 u16 tci = ihost->tci_pool[head];
2562
2563 ihost->tci_head = head + 1;
2564 return tci;
2565 }
2566
2567 static u16 isci_tci_space(struct isci_host *ihost)
2568 {
2569 return CIRC_SPACE(ihost->tci_head, ihost->tci_tail, SCI_MAX_IO_REQUESTS);
2570 }
2571
2572 u16 isci_alloc_tag(struct isci_host *ihost)
2573 {
2574 if (isci_tci_space(ihost)) {
2575 u16 tci = isci_tci_alloc(ihost);
2576 u8 seq = ihost->io_request_sequence[tci];
2577
2578 return ISCI_TAG(seq, tci);
2579 }
2580
2581 return SCI_CONTROLLER_INVALID_IO_TAG;
2582 }
2583
2584 enum sci_status isci_free_tag(struct isci_host *ihost, u16 io_tag)
2585 {
2586 u16 tci = ISCI_TAG_TCI(io_tag);
2587 u16 seq = ISCI_TAG_SEQ(io_tag);
2588
2589 /* prevent tail from passing head */
2590 if (isci_tci_active(ihost) == 0)
2591 return SCI_FAILURE_INVALID_IO_TAG;
2592
2593 if (seq == ihost->io_request_sequence[tci]) {
2594 ihost->io_request_sequence[tci] = (seq+1) & (SCI_MAX_SEQ-1);
2595
2596 isci_tci_free(ihost, tci);
2597
2598 return SCI_SUCCESS;
2599 }
2600 return SCI_FAILURE_INVALID_IO_TAG;
2601 }
2602
2603 enum sci_status sci_controller_start_io(struct isci_host *ihost,
2604 struct isci_remote_device *idev,
2605 struct isci_request *ireq)
2606 {
2607 enum sci_status status;
2608
2609 if (ihost->sm.current_state_id != SCIC_READY) {
2610 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2611 __func__, ihost->sm.current_state_id);
2612 return SCI_FAILURE_INVALID_STATE;
2613 }
2614
2615 status = sci_remote_device_start_io(ihost, idev, ireq);
2616 if (status != SCI_SUCCESS)
2617 return status;
2618
2619 set_bit(IREQ_ACTIVE, &ireq->flags);
2620 sci_controller_post_request(ihost, ireq->post_context);
2621 return SCI_SUCCESS;
2622 }
2623
2624 enum sci_status sci_controller_terminate_request(struct isci_host *ihost,
2625 struct isci_remote_device *idev,
2626 struct isci_request *ireq)
2627 {
2628 /* terminate an ongoing (i.e. started) core IO request. This does not
2629 * abort the IO request at the target, but rather removes the IO
2630 * request from the host controller.
2631 */
2632 enum sci_status status;
2633
2634 if (ihost->sm.current_state_id != SCIC_READY) {
2635 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2636 __func__, ihost->sm.current_state_id);
2637 return SCI_FAILURE_INVALID_STATE;
2638 }
2639 status = sci_io_request_terminate(ireq);
2640
2641 dev_dbg(&ihost->pdev->dev, "%s: status=%d; ireq=%p; flags=%lx\n",
2642 __func__, status, ireq, ireq->flags);
2643
2644 if ((status == SCI_SUCCESS) &&
2645 !test_bit(IREQ_PENDING_ABORT, &ireq->flags) &&
2646 !test_and_set_bit(IREQ_TC_ABORT_POSTED, &ireq->flags)) {
2647 /* Utilize the original post context command and or in the
2648 * POST_TC_ABORT request sub-type.
2649 */
2650 sci_controller_post_request(
2651 ihost, ireq->post_context |
2652 SCU_CONTEXT_COMMAND_REQUEST_POST_TC_ABORT);
2653 }
2654 return status;
2655 }
2656
2657 /**
2658 * sci_controller_complete_io() - This method will perform core specific
2659 * completion operations for an IO request. After this method is invoked,
2660 * the user should consider the IO request as invalid until it is properly
2661 * reused (i.e. re-constructed).
2662 * @ihost: The handle to the controller object for which to complete the
2663 * IO request.
2664 * @idev: The handle to the remote device object for which to complete
2665 * the IO request.
2666 * @ireq: the handle to the io request object to complete.
2667 */
2668 enum sci_status sci_controller_complete_io(struct isci_host *ihost,
2669 struct isci_remote_device *idev,
2670 struct isci_request *ireq)
2671 {
2672 enum sci_status status;
2673
2674 switch (ihost->sm.current_state_id) {
2675 case SCIC_STOPPING:
2676 /* XXX: Implement this function */
2677 return SCI_FAILURE;
2678 case SCIC_READY:
2679 status = sci_remote_device_complete_io(ihost, idev, ireq);
2680 if (status != SCI_SUCCESS)
2681 return status;
2682
2683 clear_bit(IREQ_ACTIVE, &ireq->flags);
2684 return SCI_SUCCESS;
2685 default:
2686 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2687 __func__, ihost->sm.current_state_id);
2688 return SCI_FAILURE_INVALID_STATE;
2689 }
2690
2691 }
2692
2693 enum sci_status sci_controller_continue_io(struct isci_request *ireq)
2694 {
2695 struct isci_host *ihost = ireq->owning_controller;
2696
2697 if (ihost->sm.current_state_id != SCIC_READY) {
2698 dev_warn(&ihost->pdev->dev, "%s invalid state: %d\n",
2699 __func__, ihost->sm.current_state_id);
2700 return SCI_FAILURE_INVALID_STATE;
2701 }
2702
2703 set_bit(IREQ_ACTIVE, &ireq->flags);
2704 sci_controller_post_request(ihost, ireq->post_context);
2705 return SCI_SUCCESS;
2706 }
2707
2708 /**
2709 * sci_controller_start_task() - This method is called by the SCIC user to
2710 * send/start a framework task management request.
2711 * @ihost: the handle to the controller object for which to start the task
2712 * management request.
2713 * @idev: the handle to the remote device object for which to start
2714 * the task management request.
2715 * @ireq: the handle to the task request object to start.
2716 */
2717 enum sci_status sci_controller_start_task(struct isci_host *ihost,
2718 struct isci_remote_device *idev,
2719 struct isci_request *ireq)
2720 {
2721 enum sci_status status;
2722
2723 if (ihost->sm.current_state_id != SCIC_READY) {
2724 dev_warn(&ihost->pdev->dev,
2725 "%s: SCIC Controller starting task from invalid "
2726 "state\n",
2727 __func__);
2728 return SCI_FAILURE_INVALID_STATE;
2729 }
2730
2731 status = sci_remote_device_start_task(ihost, idev, ireq);
2732 switch (status) {
2733 case SCI_FAILURE_RESET_DEVICE_PARTIAL_SUCCESS:
2734 set_bit(IREQ_ACTIVE, &ireq->flags);
2735
2736 /*
2737 * We will let framework know this task request started successfully,
2738 * although core is still woring on starting the request (to post tc when
2739 * RNC is resumed.)
2740 */
2741 return SCI_SUCCESS;
2742 case SCI_SUCCESS:
2743 set_bit(IREQ_ACTIVE, &ireq->flags);
2744 sci_controller_post_request(ihost, ireq->post_context);
2745 break;
2746 default:
2747 break;
2748 }
2749
2750 return status;
2751 }
2752
2753 static int sci_write_gpio_tx_gp(struct isci_host *ihost, u8 reg_index, u8 reg_count, u8 *write_data)
2754 {
2755 int d;
2756
2757 /* no support for TX_GP_CFG */
2758 if (reg_index == 0)
2759 return -EINVAL;
2760
2761 for (d = 0; d < isci_gpio_count(ihost); d++) {
2762 u32 val = 0x444; /* all ODx.n clear */
2763 int i;
2764
2765 for (i = 0; i < 3; i++) {
2766 int bit;
2767
2768 bit = try_test_sas_gpio_gp_bit(to_sas_gpio_od(d, i),
2769 write_data, reg_index,
2770 reg_count);
2771 if (bit < 0)
2772 break;
2773
2774 /* if od is set, clear the 'invert' bit */
2775 val &= ~(bit << ((i << 2) + 2));
2776 }
2777
2778 if (i < 3)
2779 break;
2780 writel(val, &ihost->scu_registers->peg0.sgpio.output_data_select[d]);
2781 }
2782
2783 /* unless reg_index is > 1, we should always be able to write at
2784 * least one register
2785 */
2786 return d > 0;
2787 }
2788
2789 int isci_gpio_write(struct sas_ha_struct *sas_ha, u8 reg_type, u8 reg_index,
2790 u8 reg_count, u8 *write_data)
2791 {
2792 struct isci_host *ihost = sas_ha->lldd_ha;
2793 int written;
2794
2795 switch (reg_type) {
2796 case SAS_GPIO_REG_TX_GP:
2797 written = sci_write_gpio_tx_gp(ihost, reg_index, reg_count, write_data);
2798 break;
2799 default:
2800 written = -EINVAL;
2801 }
2802
2803 return written;
2804 }
Kernel DRM miscellaneous fixes and cross-tree changes