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drm/modes: Fix drm_mode_vrefres() docs
[drm/drm-misc.git] / drivers / scsi / pm8001 / pm8001_init.c
blobf8c81e53e93f7849bbe7fe9cbc861f22b964bc39
1 /*
2 * PMC-Sierra PM8001/8081/8088/8089 SAS/SATA based host adapters driver
3 *
4 * Copyright (c) 2008-2009 USI Co., Ltd.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
14 * substantially similar to the "NO WARRANTY" disclaimer below
15 * ("Disclaimer") and any redistribution must be conditioned upon
16 * including a substantially similar Disclaimer requirement for further
17 * binary redistribution.
18 * 3. Neither the names of the above-listed copyright holders nor the names
19 * of any contributors may be used to endorse or promote products derived
20 * from this software without specific prior written permission.
21 *
22 * Alternatively, this software may be distributed under the terms of the
23 * GNU General Public License ("GPL") version 2 as published by the Free
24 * Software Foundation.
25 *
26 * NO WARRANTY
27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGES.
38 *
39 */
40
41 #include <linux/slab.h>
42 #include "pm8001_sas.h"
43 #include "pm8001_chips.h"
44 #include "pm80xx_hwi.h"
45
46 static ulong logging_level = PM8001_FAIL_LOGGING | PM8001_IOERR_LOGGING |
47 PM8001_EVENT_LOGGING | PM8001_INIT_LOGGING;
48 module_param(logging_level, ulong, 0644);
49 MODULE_PARM_DESC(logging_level, " bits for enabling logging info.");
50
51 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120;
52 module_param(link_rate, ulong, 0644);
53 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
54 " 1: Link rate 1.5G\n"
55 " 2: Link rate 3.0G\n"
56 " 4: Link rate 6.0G\n"
57 " 8: Link rate 12.0G\n");
58
59 bool pm8001_use_msix = true;
60 module_param_named(use_msix, pm8001_use_msix, bool, 0444);
61 MODULE_PARM_DESC(zoned, "Use MSIX interrupts. Default: true");
62
63 static bool pm8001_use_tasklet = true;
64 module_param_named(use_tasklet, pm8001_use_tasklet, bool, 0444);
65 MODULE_PARM_DESC(zoned, "Use MSIX interrupts. Default: true");
66
67 static bool pm8001_read_wwn = true;
68 module_param_named(read_wwn, pm8001_read_wwn, bool, 0444);
69 MODULE_PARM_DESC(zoned, "Get WWN from the controller. Default: true");
70
71 uint pcs_event_log_severity = 0x03;
72 module_param(pcs_event_log_severity, int, 0644);
73 MODULE_PARM_DESC(pcs_event_log_severity, "PCS event log severity level");
74
75 static struct scsi_transport_template *pm8001_stt;
76 static int pm8001_init_ccb_tag(struct pm8001_hba_info *);
77
78 /*
79 * chip info structure to identify chip key functionality as
80 * encryption available/not, no of ports, hw specific function ref
81 */
82 static const struct pm8001_chip_info pm8001_chips[] = {
83 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
84 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
85 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
86 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
87 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
88 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
89 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
90 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
91 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
92 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
93 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
94 };
95 static int pm8001_id;
96
97 LIST_HEAD(hba_list);
98
99 struct workqueue_struct *pm8001_wq;
100
101 static void pm8001_map_queues(struct Scsi_Host *shost)
102 {
103 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
104 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
105 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
106
107 if (pm8001_ha->number_of_intr > 1) {
108 blk_mq_pci_map_queues(qmap, pm8001_ha->pdev, 1);
109 return;
110 }
111
112 blk_mq_map_queues(qmap);
113 }
114
115 /*
116 * The main structure which LLDD must register for scsi core.
117 */
118 static const struct scsi_host_template pm8001_sht = {
119 LIBSAS_SHT_BASE
120 .scan_finished = pm8001_scan_finished,
121 .scan_start = pm8001_scan_start,
122 .can_queue = 1,
123 .sg_tablesize = PM8001_MAX_DMA_SG,
124 .max_sectors = PM8001_MAX_SECTORS,
125 .shost_groups = pm8001_host_groups,
126 .sdev_groups = pm8001_sdev_groups,
127 .track_queue_depth = 1,
128 .cmd_per_lun = 32,
129 .map_queues = pm8001_map_queues,
130 };
131
132 /*
133 * Sas layer call this function to execute specific task.
134 */
135 static struct sas_domain_function_template pm8001_transport_ops = {
136 .lldd_dev_found = pm8001_dev_found,
137 .lldd_dev_gone = pm8001_dev_gone,
138
139 .lldd_execute_task = pm8001_queue_command,
140 .lldd_control_phy = pm8001_phy_control,
141
142 .lldd_abort_task = pm8001_abort_task,
143 .lldd_abort_task_set = sas_abort_task_set,
144 .lldd_clear_task_set = pm8001_clear_task_set,
145 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
146 .lldd_lu_reset = pm8001_lu_reset,
147 .lldd_query_task = pm8001_query_task,
148 .lldd_port_formed = pm8001_port_formed,
149 .lldd_tmf_exec_complete = pm8001_setds_completion,
150 .lldd_tmf_aborted = pm8001_tmf_aborted,
151 };
152
153 /**
154 * pm8001_phy_init - initiate our adapter phys
155 * @pm8001_ha: our hba structure.
156 * @phy_id: phy id.
157 */
158 static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
159 {
160 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
161 struct asd_sas_phy *sas_phy = &phy->sas_phy;
162 phy->phy_state = PHY_LINK_DISABLE;
163 phy->pm8001_ha = pm8001_ha;
164 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
165 phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
166 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
167 sas_phy->iproto = SAS_PROTOCOL_ALL;
168 sas_phy->tproto = 0;
169 sas_phy->role = PHY_ROLE_INITIATOR;
170 sas_phy->oob_mode = OOB_NOT_CONNECTED;
171 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
172 sas_phy->id = phy_id;
173 sas_phy->sas_addr = (u8 *)&phy->dev_sas_addr;
174 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
175 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
176 sas_phy->lldd_phy = phy;
177 }
178
179 /**
180 * pm8001_free - free hba
181 * @pm8001_ha: our hba structure.
182 */
183 static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
184 {
185 int i;
186
187 if (!pm8001_ha)
188 return;
189
190 for (i = 0; i < USI_MAX_MEMCNT; i++) {
191 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
192 dma_free_coherent(&pm8001_ha->pdev->dev,
193 (pm8001_ha->memoryMap.region[i].total_len +
194 pm8001_ha->memoryMap.region[i].alignment),
195 pm8001_ha->memoryMap.region[i].virt_ptr,
196 pm8001_ha->memoryMap.region[i].phys_addr);
197 }
198 }
199 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
200 flush_workqueue(pm8001_wq);
201 bitmap_free(pm8001_ha->rsvd_tags);
202 kfree(pm8001_ha);
203 }
204
205 /**
206 * pm8001_tasklet() - tasklet for 64 msi-x interrupt handler
207 * @opaque: the passed general host adapter struct
208 * Note: pm8001_tasklet is common for pm8001 & pm80xx
209 */
210 static void pm8001_tasklet(unsigned long opaque)
211 {
212 struct isr_param *irq_vector = (struct isr_param *)opaque;
213 struct pm8001_hba_info *pm8001_ha = irq_vector->drv_inst;
214
215 if (WARN_ON_ONCE(!pm8001_ha))
216 return;
217
218 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
219 }
220
221 static void pm8001_init_tasklet(struct pm8001_hba_info *pm8001_ha)
222 {
223 int i;
224
225 if (!pm8001_use_tasklet)
226 return;
227
228 /* Tasklet for non msi-x interrupt handler */
229 if ((!pm8001_ha->pdev->msix_cap || !pci_msi_enabled()) ||
230 (pm8001_ha->chip_id == chip_8001)) {
231 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
232 (unsigned long)&(pm8001_ha->irq_vector[0]));
233 return;
234 }
235 for (i = 0; i < PM8001_MAX_MSIX_VEC; i++)
236 tasklet_init(&pm8001_ha->tasklet[i], pm8001_tasklet,
237 (unsigned long)&(pm8001_ha->irq_vector[i]));
238 }
239
240 static void pm8001_kill_tasklet(struct pm8001_hba_info *pm8001_ha)
241 {
242 int i;
243
244 if (!pm8001_use_tasklet)
245 return;
246
247 /* For non-msix and msix interrupts */
248 if ((!pm8001_ha->pdev->msix_cap || !pci_msi_enabled()) ||
249 (pm8001_ha->chip_id == chip_8001)) {
250 tasklet_kill(&pm8001_ha->tasklet[0]);
251 return;
252 }
253
254 for (i = 0; i < PM8001_MAX_MSIX_VEC; i++)
255 tasklet_kill(&pm8001_ha->tasklet[i]);
256 }
257
258 static irqreturn_t pm8001_handle_irq(struct pm8001_hba_info *pm8001_ha,
259 int irq)
260 {
261 if (unlikely(!pm8001_ha))
262 return IRQ_NONE;
263
264 if (!PM8001_CHIP_DISP->is_our_interrupt(pm8001_ha))
265 return IRQ_NONE;
266
267 if (!pm8001_use_tasklet)
268 return PM8001_CHIP_DISP->isr(pm8001_ha, irq);
269
270 tasklet_schedule(&pm8001_ha->tasklet[irq]);
271 return IRQ_HANDLED;
272 }
273
274 /**
275 * pm8001_interrupt_handler_msix - main MSIX interrupt handler.
276 * It obtains the vector number and calls the equivalent bottom
277 * half or services directly.
278 * @irq: interrupt number
279 * @opaque: the passed outbound queue/vector. Host structure is
280 * retrieved from the same.
281 */
282 static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
283 {
284 struct isr_param *irq_vector = (struct isr_param *)opaque;
285 struct pm8001_hba_info *pm8001_ha = irq_vector->drv_inst;
286
287 return pm8001_handle_irq(pm8001_ha, irq_vector->irq_id);
288 }
289
290 /**
291 * pm8001_interrupt_handler_intx - main INTx interrupt handler.
292 * @irq: interrupt number
293 * @dev_id: sas_ha structure. The HBA is retrieved from sas_ha structure.
294 */
295
296 static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
297 {
298 struct sas_ha_struct *sha = dev_id;
299 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
300
301 return pm8001_handle_irq(pm8001_ha, 0);
302 }
303
304 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha);
305 static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha);
306
307 /**
308 * pm8001_alloc - initiate our hba structure and 6 DMAs area.
309 * @pm8001_ha: our hba structure.
310 * @ent: PCI device ID structure to match on
311 */
312 static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
313 const struct pci_device_id *ent)
314 {
315 int i, count = 0, rc = 0;
316 u32 ci_offset, ib_offset, ob_offset, pi_offset;
317 struct inbound_queue_table *ibq;
318 struct outbound_queue_table *obq;
319
320 spin_lock_init(&pm8001_ha->lock);
321 spin_lock_init(&pm8001_ha->bitmap_lock);
322 pm8001_dbg(pm8001_ha, INIT, "pm8001_alloc: PHY:%x\n",
323 pm8001_ha->chip->n_phy);
324
325 /* Request Interrupt */
326 rc = pm8001_request_irq(pm8001_ha);
327 if (rc)
328 goto err_out;
329
330 count = pm8001_ha->max_q_num;
331 /* Queues are chosen based on the number of cores/msix availability */
332 ib_offset = pm8001_ha->ib_offset = USI_MAX_MEMCNT_BASE;
333 ci_offset = pm8001_ha->ci_offset = ib_offset + count;
334 ob_offset = pm8001_ha->ob_offset = ci_offset + count;
335 pi_offset = pm8001_ha->pi_offset = ob_offset + count;
336 pm8001_ha->max_memcnt = pi_offset + count;
337
338 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
339 pm8001_phy_init(pm8001_ha, i);
340 pm8001_ha->port[i].wide_port_phymap = 0;
341 pm8001_ha->port[i].port_attached = 0;
342 pm8001_ha->port[i].port_state = 0;
343 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
344 }
345
346 /* MPI Memory region 1 for AAP Event Log for fw */
347 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
348 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
349 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
350 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
351
352 /* MPI Memory region 2 for IOP Event Log for fw */
353 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
354 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
355 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
356 pm8001_ha->memoryMap.region[IOP].alignment = 32;
357
358 for (i = 0; i < count; i++) {
359 ibq = &pm8001_ha->inbnd_q_tbl[i];
360 spin_lock_init(&ibq->iq_lock);
361 /* MPI Memory region 3 for consumer Index of inbound queues */
362 pm8001_ha->memoryMap.region[ci_offset+i].num_elements = 1;
363 pm8001_ha->memoryMap.region[ci_offset+i].element_size = 4;
364 pm8001_ha->memoryMap.region[ci_offset+i].total_len = 4;
365 pm8001_ha->memoryMap.region[ci_offset+i].alignment = 4;
366
367 if ((ent->driver_data) != chip_8001) {
368 /* MPI Memory region 5 inbound queues */
369 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
370 PM8001_MPI_QUEUE;
371 pm8001_ha->memoryMap.region[ib_offset+i].element_size
372 = 128;
373 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
374 PM8001_MPI_QUEUE * 128;
375 pm8001_ha->memoryMap.region[ib_offset+i].alignment
376 = 128;
377 } else {
378 pm8001_ha->memoryMap.region[ib_offset+i].num_elements =
379 PM8001_MPI_QUEUE;
380 pm8001_ha->memoryMap.region[ib_offset+i].element_size
381 = 64;
382 pm8001_ha->memoryMap.region[ib_offset+i].total_len =
383 PM8001_MPI_QUEUE * 64;
384 pm8001_ha->memoryMap.region[ib_offset+i].alignment = 64;
385 }
386 }
387
388 for (i = 0; i < count; i++) {
389 obq = &pm8001_ha->outbnd_q_tbl[i];
390 spin_lock_init(&obq->oq_lock);
391 /* MPI Memory region 4 for producer Index of outbound queues */
392 pm8001_ha->memoryMap.region[pi_offset+i].num_elements = 1;
393 pm8001_ha->memoryMap.region[pi_offset+i].element_size = 4;
394 pm8001_ha->memoryMap.region[pi_offset+i].total_len = 4;
395 pm8001_ha->memoryMap.region[pi_offset+i].alignment = 4;
396
397 if (ent->driver_data != chip_8001) {
398 /* MPI Memory region 6 Outbound queues */
399 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
400 PM8001_MPI_QUEUE;
401 pm8001_ha->memoryMap.region[ob_offset+i].element_size
402 = 128;
403 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
404 PM8001_MPI_QUEUE * 128;
405 pm8001_ha->memoryMap.region[ob_offset+i].alignment
406 = 128;
407 } else {
408 /* MPI Memory region 6 Outbound queues */
409 pm8001_ha->memoryMap.region[ob_offset+i].num_elements =
410 PM8001_MPI_QUEUE;
411 pm8001_ha->memoryMap.region[ob_offset+i].element_size
412 = 64;
413 pm8001_ha->memoryMap.region[ob_offset+i].total_len =
414 PM8001_MPI_QUEUE * 64;
415 pm8001_ha->memoryMap.region[ob_offset+i].alignment = 64;
416 }
417
418 }
419 /* Memory region write DMA*/
420 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
421 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
422 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
423
424 /* Memory region for fw flash */
425 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
426
427 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
428 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
429 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
430 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
431 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
432 struct mpi_mem *region = &pm8001_ha->memoryMap.region[i];
433
434 if (pm8001_mem_alloc(pm8001_ha->pdev,
435 &region->virt_ptr,
436 &region->phys_addr,
437 &region->phys_addr_hi,
438 &region->phys_addr_lo,
439 region->total_len,
440 region->alignment) != 0) {
441 pm8001_dbg(pm8001_ha, FAIL, "Mem%d alloc failed\n", i);
442 goto err_out;
443 }
444 }
445
446 /* Memory region for devices*/
447 pm8001_ha->devices = kzalloc(PM8001_MAX_DEVICES
448 * sizeof(struct pm8001_device), GFP_KERNEL);
449 if (!pm8001_ha->devices) {
450 rc = -ENOMEM;
451 goto err_out_nodev;
452 }
453 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
454 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
455 }
456 pm8001_ha->flags = PM8001F_INIT_TIME;
457 return 0;
458
459 err_out_nodev:
460 for (i = 0; i < pm8001_ha->max_memcnt; i++) {
461 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
462 dma_free_coherent(&pm8001_ha->pdev->dev,
463 (pm8001_ha->memoryMap.region[i].total_len +
464 pm8001_ha->memoryMap.region[i].alignment),
465 pm8001_ha->memoryMap.region[i].virt_ptr,
466 pm8001_ha->memoryMap.region[i].phys_addr);
467 }
468 }
469 err_out:
470 return 1;
471 }
472
473 /**
474 * pm8001_ioremap - remap the pci high physical address to kernel virtual
475 * address so that we can access them.
476 * @pm8001_ha: our hba structure.
477 */
478 static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
479 {
480 u32 bar;
481 u32 logicalBar = 0;
482 struct pci_dev *pdev;
483
484 pdev = pm8001_ha->pdev;
485 /* map pci mem (PMC pci base 0-3)*/
486 for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
487 /*
488 ** logical BARs for SPC:
489 ** bar 0 and 1 - logical BAR0
490 ** bar 2 and 3 - logical BAR1
491 ** bar4 - logical BAR2
492 ** bar5 - logical BAR3
493 ** Skip the appropriate assignments:
494 */
495 if ((bar == 1) || (bar == 3))
496 continue;
497 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
498 pm8001_ha->io_mem[logicalBar].membase =
499 pci_resource_start(pdev, bar);
500 pm8001_ha->io_mem[logicalBar].memsize =
501 pci_resource_len(pdev, bar);
502 pm8001_ha->io_mem[logicalBar].memvirtaddr =
503 ioremap(pm8001_ha->io_mem[logicalBar].membase,
504 pm8001_ha->io_mem[logicalBar].memsize);
505 if (!pm8001_ha->io_mem[logicalBar].memvirtaddr) {
506 pm8001_dbg(pm8001_ha, INIT,
507 "Failed to ioremap bar %d, logicalBar %d",
508 bar, logicalBar);
509 return -ENOMEM;
510 }
511 pm8001_dbg(pm8001_ha, INIT,
512 "base addr %llx virt_addr=%llx len=%d\n",
513 (u64)pm8001_ha->io_mem[logicalBar].membase,
514 (u64)(unsigned long)
515 pm8001_ha->io_mem[logicalBar].memvirtaddr,
516 pm8001_ha->io_mem[logicalBar].memsize);
517 } else {
518 pm8001_ha->io_mem[logicalBar].membase = 0;
519 pm8001_ha->io_mem[logicalBar].memsize = 0;
520 pm8001_ha->io_mem[logicalBar].memvirtaddr = NULL;
521 }
522 logicalBar++;
523 }
524 return 0;
525 }
526
527 /**
528 * pm8001_pci_alloc - initialize our ha card structure
529 * @pdev: pci device.
530 * @ent: ent
531 * @shost: scsi host struct which has been initialized before.
532 */
533 static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
534 const struct pci_device_id *ent,
535 struct Scsi_Host *shost)
536
537 {
538 struct pm8001_hba_info *pm8001_ha;
539 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
540
541 pm8001_ha = sha->lldd_ha;
542 if (!pm8001_ha)
543 return NULL;
544
545 pm8001_ha->pdev = pdev;
546 pm8001_ha->dev = &pdev->dev;
547 pm8001_ha->chip_id = ent->driver_data;
548 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
549 pm8001_ha->irq = pdev->irq;
550 pm8001_ha->sas = sha;
551 pm8001_ha->shost = shost;
552 pm8001_ha->id = pm8001_id++;
553 pm8001_ha->logging_level = logging_level;
554 pm8001_ha->non_fatal_count = 0;
555 if (link_rate >= 1 && link_rate <= 15)
556 pm8001_ha->link_rate = (link_rate << 8);
557 else {
558 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 |
559 LINKRATE_60 | LINKRATE_120;
560 pm8001_dbg(pm8001_ha, FAIL,
561 "Setting link rate to default value\n");
562 }
563 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
564 /* IOMB size is 128 for 8088/89 controllers */
565 if (pm8001_ha->chip_id != chip_8001)
566 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
567 else
568 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
569
570 pm8001_init_tasklet(pm8001_ha);
571
572 if (pm8001_ioremap(pm8001_ha))
573 goto failed_pci_alloc;
574 if (!pm8001_alloc(pm8001_ha, ent))
575 return pm8001_ha;
576 failed_pci_alloc:
577 pm8001_free(pm8001_ha);
578 return NULL;
579 }
580
581 /**
582 * pci_go_44 - pm8001 specified, its DMA is 44 bit rather than 64 bit
583 * @pdev: pci device.
584 */
585 static int pci_go_44(struct pci_dev *pdev)
586 {
587 int rc;
588
589 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
590 if (rc) {
591 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
592 if (rc)
593 dev_printk(KERN_ERR, &pdev->dev,
594 "32-bit DMA enable failed\n");
595 }
596 return rc;
597 }
598
599 /**
600 * pm8001_prep_sas_ha_init - allocate memory in general hba struct && init them.
601 * @shost: scsi host which has been allocated outside.
602 * @chip_info: our ha struct.
603 */
604 static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
605 const struct pm8001_chip_info *chip_info)
606 {
607 int phy_nr, port_nr;
608 struct asd_sas_phy **arr_phy;
609 struct asd_sas_port **arr_port;
610 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
611
612 phy_nr = chip_info->n_phy;
613 port_nr = phy_nr;
614 memset(sha, 0x00, sizeof(*sha));
615 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
616 if (!arr_phy)
617 goto exit;
618 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
619 if (!arr_port)
620 goto exit_free2;
621
622 sha->sas_phy = arr_phy;
623 sha->sas_port = arr_port;
624 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
625 if (!sha->lldd_ha)
626 goto exit_free1;
627
628 shost->transportt = pm8001_stt;
629 shost->max_id = PM8001_MAX_DEVICES;
630 shost->unique_id = pm8001_id;
631 shost->max_cmd_len = 16;
632 return 0;
633 exit_free1:
634 kfree(arr_port);
635 exit_free2:
636 kfree(arr_phy);
637 exit:
638 return -1;
639 }
640
641 /**
642 * pm8001_post_sas_ha_init - initialize general hba struct defined in libsas
643 * @shost: scsi host which has been allocated outside
644 * @chip_info: our ha struct.
645 */
646 static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
647 const struct pm8001_chip_info *chip_info)
648 {
649 int i = 0;
650 struct pm8001_hba_info *pm8001_ha;
651 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
652
653 pm8001_ha = sha->lldd_ha;
654 for (i = 0; i < chip_info->n_phy; i++) {
655 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
656 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
657 sha->sas_phy[i]->sas_addr =
658 (u8 *)&pm8001_ha->phy[i].dev_sas_addr;
659 }
660 sha->sas_ha_name = DRV_NAME;
661 sha->dev = pm8001_ha->dev;
662 sha->strict_wide_ports = 1;
663 sha->sas_addr = &pm8001_ha->sas_addr[0];
664 sha->num_phys = chip_info->n_phy;
665 sha->shost = shost;
666 }
667
668 /**
669 * pm8001_init_sas_add - initialize sas address
670 * @pm8001_ha: our ha struct.
671 *
672 * Currently we just set the fixed SAS address to our HBA, for manufacture,
673 * it should read from the EEPROM
674 */
675 static int pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
676 {
677 DECLARE_COMPLETION_ONSTACK(completion);
678 struct pm8001_ioctl_payload payload;
679 unsigned long time_remaining;
680 u8 sas_add[8];
681 u16 deviceid;
682 int rc;
683 u8 i, j;
684
685 if (!pm8001_read_wwn) {
686 __be64 dev_sas_addr = cpu_to_be64(0x50010c600047f9d0ULL);
687
688 for (i = 0; i < pm8001_ha->chip->n_phy; i++)
689 memcpy(&pm8001_ha->phy[i].dev_sas_addr, &dev_sas_addr,
690 SAS_ADDR_SIZE);
691 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
692 SAS_ADDR_SIZE);
693 return 0;
694 }
695
696 /*
697 * For new SPC controllers WWN is stored in flash vpd. For SPC/SPCve
698 * controllers WWN is stored in EEPROM. And for Older SPC WWN is stored
699 * in NVMD.
700 */
701 if (PM8001_CHIP_DISP->fatal_errors(pm8001_ha)) {
702 pm8001_dbg(pm8001_ha, FAIL, "controller is in fatal error state\n");
703 return -EIO;
704 }
705
706 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
707 pm8001_ha->nvmd_completion = &completion;
708
709 if (pm8001_ha->chip_id == chip_8001) {
710 if (deviceid == 0x8081 || deviceid == 0x0042) {
711 payload.minor_function = 4;
712 payload.rd_length = 4096;
713 } else {
714 payload.minor_function = 0;
715 payload.rd_length = 128;
716 }
717 } else if ((pm8001_ha->chip_id == chip_8070 ||
718 pm8001_ha->chip_id == chip_8072) &&
719 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
720 payload.minor_function = 4;
721 payload.rd_length = 4096;
722 } else {
723 payload.minor_function = 1;
724 payload.rd_length = 4096;
725 }
726 payload.offset = 0;
727 payload.func_specific = kzalloc(payload.rd_length, GFP_KERNEL);
728 if (!payload.func_specific) {
729 pm8001_dbg(pm8001_ha, FAIL, "mem alloc fail\n");
730 return -ENOMEM;
731 }
732 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
733 if (rc) {
734 kfree(payload.func_specific);
735 pm8001_dbg(pm8001_ha, FAIL, "nvmd failed\n");
736 return -EIO;
737 }
738 time_remaining = wait_for_completion_timeout(&completion,
739 msecs_to_jiffies(60*1000)); // 1 min
740 if (!time_remaining) {
741 kfree(payload.func_specific);
742 pm8001_dbg(pm8001_ha, FAIL, "get_nvmd_req timeout\n");
743 return -EIO;
744 }
745
746
747 for (i = 0, j = 0; i <= 7; i++, j++) {
748 if (pm8001_ha->chip_id == chip_8001) {
749 if (deviceid == 0x8081)
750 pm8001_ha->sas_addr[j] =
751 payload.func_specific[0x704 + i];
752 else if (deviceid == 0x0042)
753 pm8001_ha->sas_addr[j] =
754 payload.func_specific[0x010 + i];
755 } else if ((pm8001_ha->chip_id == chip_8070 ||
756 pm8001_ha->chip_id == chip_8072) &&
757 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
758 pm8001_ha->sas_addr[j] =
759 payload.func_specific[0x010 + i];
760 } else
761 pm8001_ha->sas_addr[j] =
762 payload.func_specific[0x804 + i];
763 }
764 memcpy(sas_add, pm8001_ha->sas_addr, SAS_ADDR_SIZE);
765 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
766 if (i && ((i % 4) == 0))
767 sas_add[7] = sas_add[7] + 4;
768 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
769 sas_add, SAS_ADDR_SIZE);
770 pm8001_dbg(pm8001_ha, INIT, "phy %d sas_addr = %016llx\n", i,
771 pm8001_ha->phy[i].dev_sas_addr);
772 }
773 kfree(payload.func_specific);
774
775 return 0;
776 }
777
778 /*
779 * pm8001_get_phy_settings_info : Read phy setting values.
780 * @pm8001_ha : our hba.
781 */
782 static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
783 {
784 DECLARE_COMPLETION_ONSTACK(completion);
785 struct pm8001_ioctl_payload payload;
786 int rc;
787
788 if (!pm8001_read_wwn)
789 return 0;
790
791 pm8001_ha->nvmd_completion = &completion;
792 /* SAS ADDRESS read from flash / EEPROM */
793 payload.minor_function = 6;
794 payload.offset = 0;
795 payload.rd_length = 4096;
796 payload.func_specific = kzalloc(4096, GFP_KERNEL);
797 if (!payload.func_specific)
798 return -ENOMEM;
799 /* Read phy setting values from flash */
800 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
801 if (rc) {
802 kfree(payload.func_specific);
803 pm8001_dbg(pm8001_ha, INIT, "nvmd failed\n");
804 return -ENOMEM;
805 }
806 wait_for_completion(&completion);
807 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
808 kfree(payload.func_specific);
809
810 return 0;
811 }
812
813 struct pm8001_mpi3_phy_pg_trx_config {
814 u32 LaneLosCfg;
815 u32 LanePgaCfg1;
816 u32 LanePisoCfg1;
817 u32 LanePisoCfg2;
818 u32 LanePisoCfg3;
819 u32 LanePisoCfg4;
820 u32 LanePisoCfg5;
821 u32 LanePisoCfg6;
822 u32 LaneBctCtrl;
823 };
824
825 /**
826 * pm8001_get_internal_phy_settings - Retrieves the internal PHY settings
827 * @pm8001_ha : our adapter
828 * @phycfg : PHY config page to populate
829 */
830 static
831 void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
832 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
833 {
834 phycfg->LaneLosCfg = 0x00000132;
835 phycfg->LanePgaCfg1 = 0x00203949;
836 phycfg->LanePisoCfg1 = 0x000000FF;
837 phycfg->LanePisoCfg2 = 0xFF000001;
838 phycfg->LanePisoCfg3 = 0xE7011300;
839 phycfg->LanePisoCfg4 = 0x631C40C0;
840 phycfg->LanePisoCfg5 = 0xF8102036;
841 phycfg->LanePisoCfg6 = 0xF74A1000;
842 phycfg->LaneBctCtrl = 0x00FB33F8;
843 }
844
845 /**
846 * pm8001_get_external_phy_settings - Retrieves the external PHY settings
847 * @pm8001_ha : our adapter
848 * @phycfg : PHY config page to populate
849 */
850 static
851 void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
852 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
853 {
854 phycfg->LaneLosCfg = 0x00000132;
855 phycfg->LanePgaCfg1 = 0x00203949;
856 phycfg->LanePisoCfg1 = 0x000000FF;
857 phycfg->LanePisoCfg2 = 0xFF000001;
858 phycfg->LanePisoCfg3 = 0xE7011300;
859 phycfg->LanePisoCfg4 = 0x63349140;
860 phycfg->LanePisoCfg5 = 0xF8102036;
861 phycfg->LanePisoCfg6 = 0xF80D9300;
862 phycfg->LaneBctCtrl = 0x00FB33F8;
863 }
864
865 /**
866 * pm8001_get_phy_mask - Retrieves the mask that denotes if a PHY is int/ext
867 * @pm8001_ha : our adapter
868 * @phymask : The PHY mask
869 */
870 static
871 void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
872 {
873 switch (pm8001_ha->pdev->subsystem_device) {
874 case 0x0070: /* H1280 - 8 external 0 internal */
875 case 0x0072: /* H12F0 - 16 external 0 internal */
876 *phymask = 0x0000;
877 break;
878
879 case 0x0071: /* H1208 - 0 external 8 internal */
880 case 0x0073: /* H120F - 0 external 16 internal */
881 *phymask = 0xFFFF;
882 break;
883
884 case 0x0080: /* H1244 - 4 external 4 internal */
885 *phymask = 0x00F0;
886 break;
887
888 case 0x0081: /* H1248 - 4 external 8 internal */
889 *phymask = 0x0FF0;
890 break;
891
892 case 0x0082: /* H1288 - 8 external 8 internal */
893 *phymask = 0xFF00;
894 break;
895
896 default:
897 pm8001_dbg(pm8001_ha, INIT,
898 "Unknown subsystem device=0x%.04x\n",
899 pm8001_ha->pdev->subsystem_device);
900 }
901 }
902
903 /**
904 * pm8001_set_phy_settings_ven_117c_12G() - Configure ATTO 12Gb PHY settings
905 * @pm8001_ha : our adapter
906 */
907 static
908 int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
909 {
910 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
911 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
912 int phymask = 0;
913 int i = 0;
914
915 memset(&phycfg_int, 0, sizeof(phycfg_int));
916 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
917
918 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
919 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
920 pm8001_get_phy_mask(pm8001_ha, &phymask);
921
922 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
923 if (phymask & (1 << i)) {/* Internal PHY */
924 pm8001_set_phy_profile_single(pm8001_ha, i,
925 sizeof(phycfg_int) / sizeof(u32),
926 (u32 *)&phycfg_int);
927
928 } else { /* External PHY */
929 pm8001_set_phy_profile_single(pm8001_ha, i,
930 sizeof(phycfg_ext) / sizeof(u32),
931 (u32 *)&phycfg_ext);
932 }
933 }
934
935 return 0;
936 }
937
938 /**
939 * pm8001_configure_phy_settings - Configures PHY settings based on vendor ID.
940 * @pm8001_ha : our hba.
941 */
942 static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
943 {
944 switch (pm8001_ha->pdev->subsystem_vendor) {
945 case PCI_VENDOR_ID_ATTO:
946 if (pm8001_ha->pdev->device == 0x0042) /* 6Gb */
947 return 0;
948 else
949 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
950
951 case PCI_VENDOR_ID_ADAPTEC2:
952 case 0:
953 return 0;
954
955 default:
956 return pm8001_get_phy_settings_info(pm8001_ha);
957 }
958 }
959
960 /**
961 * pm8001_setup_msix - enable MSI-X interrupt
962 * @pm8001_ha: our ha struct.
963 */
964 static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
965 {
966 unsigned int allocated_irq_vectors;
967 int rc;
968
969 /* SPCv controllers supports 64 msi-x */
970 if (pm8001_ha->chip_id == chip_8001) {
971 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, 1, 1,
972 PCI_IRQ_MSIX);
973 } else {
974 /*
975 * Queue index #0 is used always for housekeeping, so don't
976 * include in the affinity spreading.
977 */
978 struct irq_affinity desc = {
979 .pre_vectors = 1,
980 };
981 rc = pci_alloc_irq_vectors_affinity(
982 pm8001_ha->pdev, 2, PM8001_MAX_MSIX_VEC,
983 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY, &desc);
984 }
985
986 allocated_irq_vectors = rc;
987 if (rc < 0)
988 return rc;
989
990 /* Assigns the number of interrupts */
991 pm8001_ha->number_of_intr = allocated_irq_vectors;
992
993 /* Maximum queue number updating in HBA structure */
994 pm8001_ha->max_q_num = allocated_irq_vectors;
995
996 pm8001_dbg(pm8001_ha, INIT,
997 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
998 rc, pm8001_ha->number_of_intr);
999 return 0;
1000 }
1001
1002 static u32 pm8001_request_msix(struct pm8001_hba_info *pm8001_ha)
1003 {
1004 u32 i = 0, j = 0;
1005 int flag = 0, rc = 0;
1006 int nr_irqs = pm8001_ha->number_of_intr;
1007
1008 if (pm8001_ha->chip_id != chip_8001)
1009 flag &= ~IRQF_SHARED;
1010
1011 pm8001_dbg(pm8001_ha, INIT,
1012 "pci_enable_msix request number of intr %d\n",
1013 pm8001_ha->number_of_intr);
1014
1015 if (nr_irqs > ARRAY_SIZE(pm8001_ha->intr_drvname))
1016 nr_irqs = ARRAY_SIZE(pm8001_ha->intr_drvname);
1017
1018 for (i = 0; i < nr_irqs; i++) {
1019 snprintf(pm8001_ha->intr_drvname[i],
1020 sizeof(pm8001_ha->intr_drvname[0]),
1021 "%s-%d", pm8001_ha->name, i);
1022 pm8001_ha->irq_vector[i].irq_id = i;
1023 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
1024
1025 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
1026 pm8001_interrupt_handler_msix, flag,
1027 pm8001_ha->intr_drvname[i],
1028 &(pm8001_ha->irq_vector[i]));
1029 if (rc) {
1030 for (j = 0; j < i; j++) {
1031 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
1032 &(pm8001_ha->irq_vector[i]));
1033 }
1034 pci_free_irq_vectors(pm8001_ha->pdev);
1035 break;
1036 }
1037 }
1038
1039 return rc;
1040 }
1041
1042 /**
1043 * pm8001_request_irq - register interrupt
1044 * @pm8001_ha: our ha struct.
1045 */
1046 static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
1047 {
1048 struct pci_dev *pdev = pm8001_ha->pdev;
1049 int rc;
1050
1051 if (pm8001_use_msix && pci_find_capability(pdev, PCI_CAP_ID_MSIX)) {
1052 rc = pm8001_setup_msix(pm8001_ha);
1053 if (rc) {
1054 pm8001_dbg(pm8001_ha, FAIL,
1055 "pm8001_setup_irq failed [ret: %d]\n", rc);
1056 return rc;
1057 }
1058
1059 if (!pdev->msix_cap || !pci_msi_enabled())
1060 goto use_intx;
1061
1062 rc = pm8001_request_msix(pm8001_ha);
1063 if (rc)
1064 return rc;
1065
1066 pm8001_ha->use_msix = true;
1067
1068 return 0;
1069 }
1070
1071 use_intx:
1072 /* Initialize the INT-X interrupt */
1073 pm8001_dbg(pm8001_ha, INIT, "MSIX not supported!!!\n");
1074 pm8001_ha->use_msix = false;
1075 pm8001_ha->irq_vector[0].irq_id = 0;
1076 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
1077
1078 return request_irq(pdev->irq, pm8001_interrupt_handler_intx,
1079 IRQF_SHARED, pm8001_ha->name,
1080 SHOST_TO_SAS_HA(pm8001_ha->shost));
1081 }
1082
1083 static void pm8001_free_irq(struct pm8001_hba_info *pm8001_ha)
1084 {
1085 struct pci_dev *pdev = pm8001_ha->pdev;
1086 int i;
1087
1088 if (pm8001_ha->use_msix) {
1089 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1090 synchronize_irq(pci_irq_vector(pdev, i));
1091
1092 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1093 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1094
1095 pci_free_irq_vectors(pdev);
1096 return;
1097 }
1098
1099 /* INT-X */
1100 free_irq(pm8001_ha->irq, pm8001_ha->sas);
1101 }
1102
1103 /**
1104 * pm8001_pci_probe - probe supported device
1105 * @pdev: pci device which kernel has been prepared for.
1106 * @ent: pci device id
1107 *
1108 * This function is the main initialization function, when register a new
1109 * pci driver it is invoked, all struct and hardware initialization should be
1110 * done here, also, register interrupt.
1111 */
1112 static int pm8001_pci_probe(struct pci_dev *pdev,
1113 const struct pci_device_id *ent)
1114 {
1115 unsigned int rc;
1116 u32 pci_reg;
1117 u8 i = 0;
1118 struct pm8001_hba_info *pm8001_ha;
1119 struct Scsi_Host *shost = NULL;
1120 const struct pm8001_chip_info *chip;
1121 struct sas_ha_struct *sha;
1122
1123 dev_printk(KERN_INFO, &pdev->dev,
1124 "pm80xx: driver version %s\n", DRV_VERSION);
1125 rc = pci_enable_device(pdev);
1126 if (rc)
1127 goto err_out_enable;
1128 pci_set_master(pdev);
1129 /*
1130 * Enable pci slot busmaster by setting pci command register.
1131 * This is required by FW for Cyclone card.
1132 */
1133
1134 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
1135 pci_reg |= 0x157;
1136 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
1137 rc = pci_request_regions(pdev, DRV_NAME);
1138 if (rc)
1139 goto err_out_disable;
1140 rc = pci_go_44(pdev);
1141 if (rc)
1142 goto err_out_regions;
1143
1144 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1145 if (!shost) {
1146 rc = -ENOMEM;
1147 goto err_out_regions;
1148 }
1149 chip = &pm8001_chips[ent->driver_data];
1150 sha = kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1151 if (!sha) {
1152 rc = -ENOMEM;
1153 goto err_out_free_host;
1154 }
1155 SHOST_TO_SAS_HA(shost) = sha;
1156
1157 rc = pm8001_prep_sas_ha_init(shost, chip);
1158 if (rc) {
1159 rc = -ENOMEM;
1160 goto err_out_free;
1161 }
1162 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1163 /* ent->driver variable is used to differentiate between controllers */
1164 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1165 if (!pm8001_ha) {
1166 rc = -ENOMEM;
1167 goto err_out_free;
1168 }
1169
1170 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1171 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1172 if (rc) {
1173 pm8001_dbg(pm8001_ha, FAIL,
1174 "chip_init failed [ret: %d]\n", rc);
1175 goto err_out_ha_free;
1176 }
1177
1178 rc = pm8001_init_ccb_tag(pm8001_ha);
1179 if (rc)
1180 goto err_out_enable;
1181
1182
1183 PM8001_CHIP_DISP->chip_post_init(pm8001_ha);
1184
1185 if (pm8001_ha->number_of_intr > 1) {
1186 shost->nr_hw_queues = pm8001_ha->number_of_intr - 1;
1187 /*
1188 * For now, ensure we're not sent too many commands by setting
1189 * host_tagset. This is also required if we start using request
1190 * tag.
1191 */
1192 shost->host_tagset = 1;
1193 }
1194
1195 rc = scsi_add_host(shost, &pdev->dev);
1196 if (rc)
1197 goto err_out_ha_free;
1198
1199 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1200 if (pm8001_ha->chip_id != chip_8001) {
1201 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1202 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1203 /* setup thermal configuration. */
1204 pm80xx_set_thermal_config(pm8001_ha);
1205 }
1206
1207 rc = pm8001_init_sas_add(pm8001_ha);
1208 if (rc)
1209 goto err_out_shost;
1210 /* phy setting support for motherboard controller */
1211 rc = pm8001_configure_phy_settings(pm8001_ha);
1212 if (rc)
1213 goto err_out_shost;
1214
1215 pm8001_post_sas_ha_init(shost, chip);
1216 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1217 if (rc) {
1218 pm8001_dbg(pm8001_ha, FAIL,
1219 "sas_register_ha failed [ret: %d]\n", rc);
1220 goto err_out_shost;
1221 }
1222 list_add_tail(&pm8001_ha->list, &hba_list);
1223 pm8001_ha->flags = PM8001F_RUN_TIME;
1224 scsi_scan_host(pm8001_ha->shost);
1225 return 0;
1226
1227 err_out_shost:
1228 scsi_remove_host(pm8001_ha->shost);
1229 err_out_ha_free:
1230 pm8001_free(pm8001_ha);
1231 err_out_free:
1232 kfree(sha);
1233 err_out_free_host:
1234 scsi_host_put(shost);
1235 err_out_regions:
1236 pci_release_regions(pdev);
1237 err_out_disable:
1238 pci_disable_device(pdev);
1239 err_out_enable:
1240 return rc;
1241 }
1242
1243 /**
1244 * pm8001_init_ccb_tag - allocate memory to CCB and tag.
1245 * @pm8001_ha: our hba card information.
1246 */
1247 static int pm8001_init_ccb_tag(struct pm8001_hba_info *pm8001_ha)
1248 {
1249 struct Scsi_Host *shost = pm8001_ha->shost;
1250 struct device *dev = pm8001_ha->dev;
1251 u32 max_out_io, ccb_count;
1252 int i;
1253
1254 max_out_io = pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io;
1255 ccb_count = min_t(int, PM8001_MAX_CCB, max_out_io);
1256
1257 shost->can_queue = ccb_count - PM8001_RESERVE_SLOT;
1258
1259 pm8001_ha->rsvd_tags = bitmap_zalloc(PM8001_RESERVE_SLOT, GFP_KERNEL);
1260 if (!pm8001_ha->rsvd_tags)
1261 goto err_out;
1262
1263 /* Memory region for ccb_info*/
1264 pm8001_ha->ccb_count = ccb_count;
1265 pm8001_ha->ccb_info =
1266 kcalloc(ccb_count, sizeof(struct pm8001_ccb_info), GFP_KERNEL);
1267 if (!pm8001_ha->ccb_info) {
1268 pm8001_dbg(pm8001_ha, FAIL,
1269 "Unable to allocate memory for ccb\n");
1270 goto err_out_noccb;
1271 }
1272 for (i = 0; i < ccb_count; i++) {
1273 pm8001_ha->ccb_info[i].buf_prd = dma_alloc_coherent(dev,
1274 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1275 &pm8001_ha->ccb_info[i].ccb_dma_handle,
1276 GFP_KERNEL);
1277 if (!pm8001_ha->ccb_info[i].buf_prd) {
1278 pm8001_dbg(pm8001_ha, FAIL,
1279 "ccb prd memory allocation error\n");
1280 goto err_out;
1281 }
1282 pm8001_ha->ccb_info[i].task = NULL;
1283 pm8001_ha->ccb_info[i].ccb_tag = PM8001_INVALID_TAG;
1284 pm8001_ha->ccb_info[i].device = NULL;
1285 }
1286
1287 return 0;
1288
1289 err_out_noccb:
1290 kfree(pm8001_ha->devices);
1291 err_out:
1292 return -ENOMEM;
1293 }
1294
1295 static void pm8001_pci_remove(struct pci_dev *pdev)
1296 {
1297 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1298 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1299 int i;
1300
1301 sas_unregister_ha(sha);
1302 sas_remove_host(pm8001_ha->shost);
1303 list_del(&pm8001_ha->list);
1304 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1305 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1306
1307 pm8001_free_irq(pm8001_ha);
1308 pm8001_kill_tasklet(pm8001_ha);
1309 scsi_host_put(pm8001_ha->shost);
1310
1311 for (i = 0; i < pm8001_ha->ccb_count; i++) {
1312 dma_free_coherent(&pm8001_ha->pdev->dev,
1313 sizeof(struct pm8001_prd) * PM8001_MAX_DMA_SG,
1314 pm8001_ha->ccb_info[i].buf_prd,
1315 pm8001_ha->ccb_info[i].ccb_dma_handle);
1316 }
1317 kfree(pm8001_ha->ccb_info);
1318 kfree(pm8001_ha->devices);
1319
1320 pm8001_free(pm8001_ha);
1321 kfree(sha->sas_phy);
1322 kfree(sha->sas_port);
1323 kfree(sha);
1324 pci_release_regions(pdev);
1325 pci_disable_device(pdev);
1326 }
1327
1328 /**
1329 * pm8001_pci_suspend - power management suspend main entry point
1330 * @dev: Device struct
1331 *
1332 * Return: 0 on success, anything else on error.
1333 */
1334 static int __maybe_unused pm8001_pci_suspend(struct device *dev)
1335 {
1336 struct pci_dev *pdev = to_pci_dev(dev);
1337 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1338 struct pm8001_hba_info *pm8001_ha = sha->lldd_ha;
1339
1340 sas_suspend_ha(sha);
1341 flush_workqueue(pm8001_wq);
1342 scsi_block_requests(pm8001_ha->shost);
1343 if (!pdev->pm_cap) {
1344 dev_err(dev, " PCI PM not supported\n");
1345 return -ENODEV;
1346 }
1347 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1348 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1349
1350 pm8001_free_irq(pm8001_ha);
1351 pm8001_kill_tasklet(pm8001_ha);
1352
1353 pm8001_info(pm8001_ha, "pdev=0x%p, slot=%s, entering "
1354 "suspended state\n", pdev,
1355 pm8001_ha->name);
1356 return 0;
1357 }
1358
1359 /**
1360 * pm8001_pci_resume - power management resume main entry point
1361 * @dev: Device struct
1362 *
1363 * Return: 0 on success, anything else on error.
1364 */
1365 static int __maybe_unused pm8001_pci_resume(struct device *dev)
1366 {
1367 struct pci_dev *pdev = to_pci_dev(dev);
1368 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1369 struct pm8001_hba_info *pm8001_ha;
1370 int rc;
1371 u8 i = 0;
1372 DECLARE_COMPLETION_ONSTACK(completion);
1373
1374 pm8001_ha = sha->lldd_ha;
1375
1376 pm8001_info(pm8001_ha,
1377 "pdev=0x%p, slot=%s, resuming from previous operating state [D%d]\n",
1378 pdev, pm8001_ha->name, pdev->current_state);
1379
1380 rc = pci_go_44(pdev);
1381 if (rc)
1382 goto err_out_disable;
1383 sas_prep_resume_ha(sha);
1384 /* chip soft rst only for spc */
1385 if (pm8001_ha->chip_id == chip_8001) {
1386 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1387 pm8001_dbg(pm8001_ha, INIT, "chip soft reset successful\n");
1388 }
1389 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1390 if (rc)
1391 goto err_out_disable;
1392
1393 /* disable all the interrupt bits */
1394 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1395
1396 rc = pm8001_request_irq(pm8001_ha);
1397 if (rc)
1398 goto err_out_disable;
1399
1400 pm8001_init_tasklet(pm8001_ha);
1401
1402 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1403 if (pm8001_ha->chip_id != chip_8001) {
1404 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1405 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1406 }
1407
1408 /* Chip documentation for the 8070 and 8072 SPCv */
1409 /* states that a 500ms minimum delay is required */
1410 /* before issuing commands. Otherwise, the firmware */
1411 /* will enter an unrecoverable state. */
1412
1413 if (pm8001_ha->chip_id == chip_8070 ||
1414 pm8001_ha->chip_id == chip_8072) {
1415 mdelay(500);
1416 }
1417
1418 /* Spin up the PHYs */
1419
1420 pm8001_ha->flags = PM8001F_RUN_TIME;
1421 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1422 pm8001_ha->phy[i].enable_completion = &completion;
1423 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1424 wait_for_completion(&completion);
1425 }
1426 sas_resume_ha(sha);
1427 return 0;
1428
1429 err_out_disable:
1430 scsi_remove_host(pm8001_ha->shost);
1431
1432 return rc;
1433 }
1434
1435 /* update of pci device, vendor id and driver data with
1436 * unique value for each of the controller
1437 */
1438 static struct pci_device_id pm8001_pci_table[] = {
1439 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1440 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1441 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1442 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1443 /* Support for SPC/SPCv/SPCve controllers */
1444 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1445 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1446 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1447 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1448 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1449 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1450 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1451 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1452 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1453 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1454 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1455 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1456 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1457 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1458 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1459 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1460 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1461 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1462 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1463 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1464 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1465 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1466 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1467 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1468 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1469 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1470 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1471 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1472 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1473 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1474 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1475 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1476 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1477 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1478 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1479 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1480 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1481 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1482 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1483 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1484 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1485 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1486 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1487 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1488 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1489 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1490 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1491 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1492 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1493 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1494 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1495 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1496 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1497 { PCI_VENDOR_ID_ATTO, 0x8070,
1498 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1499 { PCI_VENDOR_ID_ATTO, 0x8070,
1500 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1501 { PCI_VENDOR_ID_ATTO, 0x8072,
1502 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1503 { PCI_VENDOR_ID_ATTO, 0x8072,
1504 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1505 { PCI_VENDOR_ID_ATTO, 0x8070,
1506 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1507 { PCI_VENDOR_ID_ATTO, 0x8072,
1508 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1509 { PCI_VENDOR_ID_ATTO, 0x8072,
1510 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1511 {} /* terminate list */
1512 };
1513
1514 static SIMPLE_DEV_PM_OPS(pm8001_pci_pm_ops,
1515 pm8001_pci_suspend,
1516 pm8001_pci_resume);
1517
1518 static struct pci_driver pm8001_pci_driver = {
1519 .name = DRV_NAME,
1520 .id_table = pm8001_pci_table,
1521 .probe = pm8001_pci_probe,
1522 .remove = pm8001_pci_remove,
1523 .driver.pm = &pm8001_pci_pm_ops,
1524 };
1525
1526 /**
1527 * pm8001_init - initialize scsi transport template
1528 */
1529 static int __init pm8001_init(void)
1530 {
1531 int rc = -ENOMEM;
1532
1533 if (pm8001_use_tasklet && !pm8001_use_msix)
1534 pm8001_use_tasklet = false;
1535
1536 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1537 if (!pm8001_wq)
1538 goto err;
1539
1540 pm8001_id = 0;
1541 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1542 if (!pm8001_stt)
1543 goto err_wq;
1544 rc = pci_register_driver(&pm8001_pci_driver);
1545 if (rc)
1546 goto err_tp;
1547 return 0;
1548
1549 err_tp:
1550 sas_release_transport(pm8001_stt);
1551 err_wq:
1552 destroy_workqueue(pm8001_wq);
1553 err:
1554 return rc;
1555 }
1556
1557 static void __exit pm8001_exit(void)
1558 {
1559 pci_unregister_driver(&pm8001_pci_driver);
1560 sas_release_transport(pm8001_stt);
1561 destroy_workqueue(pm8001_wq);
1562 }
1563
1564 module_init(pm8001_init);
1565 module_exit(pm8001_exit);
1566
1567 MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1568 MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1569 MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1570 MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1571 MODULE_DESCRIPTION(
1572 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1573 "SAS/SATA controller driver");
1574 MODULE_VERSION(DRV_VERSION);
1575 MODULE_LICENSE("GPL");
1576 MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1577
Kernel DRM miscellaneous fixes and cross-tree changes