1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
4 * Copyright (C) 2013, 2021 Intel Corporation
10 #include <linux/dmaengine.h>
11 #include <linux/irqreturn.h>
12 #include <linux/types.h>
13 #include <linux/sizes.h>
15 #include <linux/pxa2xx_ssp.h>
21 * The platform data for SSP controller devices
22 * (resides in device.platform_data).
24 struct pxa2xx_spi_controller
{
30 /* DMA engine specific config */
31 dma_filter_fn dma_filter
;
35 /* For non-PXA arches */
36 struct ssp_device ssp
;
39 struct spi_controller
;
45 struct ssp_device
*ssp
;
47 /* SPI framework hookup */
48 enum pxa_ssp_type ssp_type
;
49 struct spi_controller
*controller
;
52 struct pxa2xx_spi_controller
*controller_info
;
60 /* DMA engine support */
63 /* Current transfer state info */
69 int (*write
)(struct driver_data
*drv_data
);
70 int (*read
)(struct driver_data
*drv_data
);
71 irqreturn_t (*transfer_handler
)(struct driver_data
*drv_data
);
73 void __iomem
*lpss_base
;
75 /* Optional slave FIFO ready signal */
76 struct gpio_desc
*gpiod_ready
;
79 static inline u32
pxa2xx_spi_read(const struct driver_data
*drv_data
, u32 reg
)
81 return pxa_ssp_read_reg(drv_data
->ssp
, reg
);
84 static inline void pxa2xx_spi_write(const struct driver_data
*drv_data
, u32 reg
, u32 val
)
86 pxa_ssp_write_reg(drv_data
->ssp
, reg
, val
);
89 #define DMA_ALIGNMENT 8
91 static inline int pxa25x_ssp_comp(const struct driver_data
*drv_data
)
93 switch (drv_data
->ssp_type
) {
103 static inline void clear_SSCR1_bits(const struct driver_data
*drv_data
, u32 bits
)
105 pxa2xx_spi_write(drv_data
, SSCR1
, pxa2xx_spi_read(drv_data
, SSCR1
) & ~bits
);
108 static inline u32
read_SSSR_bits(const struct driver_data
*drv_data
, u32 bits
)
110 return pxa2xx_spi_read(drv_data
, SSSR
) & bits
;
113 static inline void write_SSSR_CS(const struct driver_data
*drv_data
, u32 val
)
115 if (drv_data
->ssp_type
== CE4100_SSP
||
116 drv_data
->ssp_type
== QUARK_X1000_SSP
)
117 val
|= read_SSSR_bits(drv_data
, SSSR_ALT_FRM_MASK
);
119 pxa2xx_spi_write(drv_data
, SSSR
, val
);
122 extern int pxa2xx_spi_flush(struct driver_data
*drv_data
);
124 #define MAX_DMA_LEN SZ_64K
125 #define DEFAULT_DMA_CR1 (SSCR1_TSRE | SSCR1_RSRE | SSCR1_TRAIL)
127 extern irqreturn_t
pxa2xx_spi_dma_transfer(struct driver_data
*drv_data
);
128 extern int pxa2xx_spi_dma_prepare(struct driver_data
*drv_data
,
129 struct spi_transfer
*xfer
);
130 extern void pxa2xx_spi_dma_start(struct driver_data
*drv_data
);
131 extern void pxa2xx_spi_dma_stop(struct driver_data
*drv_data
);
132 extern int pxa2xx_spi_dma_setup(struct driver_data
*drv_data
);
133 extern void pxa2xx_spi_dma_release(struct driver_data
*drv_data
);
135 int pxa2xx_spi_probe(struct device
*dev
, struct ssp_device
*ssp
,
136 struct pxa2xx_spi_controller
*platform_info
);
137 void pxa2xx_spi_remove(struct device
*dev
);
139 extern const struct dev_pm_ops pxa2xx_spi_pm_ops
;
141 #endif /* SPI_PXA2XX_H */