drivers/thermal/qcom/tsens-v2.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015, The Linux Foundation. All rights reserved.
   4  * Copyright (c) 2018, Linaro Limited
   5  */
   6
   7 #include <linux/bitops.h>
   8 #include <linux/regmap.h>
   9 #include "tsens.h"
  10
  11 /* ----- SROT ------ */
  12 #define SROT_HW_VER_OFF 0x0000
  13 #define SROT_CTRL_OFF           0x0004
  14
  15 /* ----- TM ------ */
  16 #define TM_INT_EN_OFF                   0x0004
  17 #define TM_UPPER_LOWER_INT_STATUS_OFF   0x0008
  18 #define TM_UPPER_LOWER_INT_CLEAR_OFF    0x000c
  19 #define TM_UPPER_LOWER_INT_MASK_OFF     0x0010
  20 #define TM_CRITICAL_INT_STATUS_OFF      0x0014
  21 #define TM_CRITICAL_INT_CLEAR_OFF       0x0018
  22 #define TM_CRITICAL_INT_MASK_OFF        0x001c
  23 #define TM_Sn_UPPER_LOWER_THRESHOLD_OFF 0x0020
  24 #define TM_Sn_CRITICAL_THRESHOLD_OFF    0x0060
  25 #define TM_Sn_STATUS_OFF                0x00a0
  26 #define TM_TRDY_OFF                     0x00e4
  27 #define TM_WDOG_LOG_OFF         0x013c
  28
  29 /* v2.x: 8996, 8998, sdm845 */
  30
  31 static struct tsens_features tsens_v2_feat = {
  32         .ver_major      = VER_2_X,
  33         .crit_int       = 1,
  34         .combo_int      = 0,
  35         .adc            = 0,
  36         .srot_split     = 1,
  37         .max_sensors    = 16,
  38         .trip_min_temp  = -40000,
  39         .trip_max_temp  = 120000,
  40 };
  41
  42 static struct tsens_features ipq8074_feat = {
  43         .ver_major      = VER_2_X,
  44         .crit_int       = 1,
  45         .combo_int      = 1,
  46         .adc            = 0,
  47         .srot_split     = 1,
  48         .max_sensors    = 16,
  49         .trip_min_temp  = 0,
  50         .trip_max_temp  = 204000,
  51 };
  52
  53 static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = {
  54         /* ----- SROT ------ */
  55         /* VERSION */
  56         [VER_MAJOR] = REG_FIELD(SROT_HW_VER_OFF, 28, 31),
  57         [VER_MINOR] = REG_FIELD(SROT_HW_VER_OFF, 16, 27),
  58         [VER_STEP]  = REG_FIELD(SROT_HW_VER_OFF,  0, 15),
  59         /* CTRL_OFF */
  60         [TSENS_EN]     = REG_FIELD(SROT_CTRL_OFF,    0,  0),
  61         [TSENS_SW_RST] = REG_FIELD(SROT_CTRL_OFF,    1,  1),
  62
  63         /* ----- TM ------ */
  64         /* INTERRUPT ENABLE */
  65         /* v2 has separate enables for UPPER/LOWER/CRITICAL interrupts */
  66         [INT_EN]  = REG_FIELD(TM_INT_EN_OFF, 0, 2),
  67
  68         /* TEMPERATURE THRESHOLDS */
  69         REG_FIELD_FOR_EACH_SENSOR16(LOW_THRESH,  TM_Sn_UPPER_LOWER_THRESHOLD_OFF,  0,  11),
  70         REG_FIELD_FOR_EACH_SENSOR16(UP_THRESH,   TM_Sn_UPPER_LOWER_THRESHOLD_OFF, 12,  23),
  71         REG_FIELD_FOR_EACH_SENSOR16(CRIT_THRESH, TM_Sn_CRITICAL_THRESHOLD_OFF,     0,  11),
  72
  73         /* INTERRUPTS [CLEAR/STATUS/MASK] */
  74         REG_FIELD_SPLIT_BITS_0_15(LOW_INT_STATUS,  TM_UPPER_LOWER_INT_STATUS_OFF),
  75         REG_FIELD_SPLIT_BITS_0_15(LOW_INT_CLEAR,   TM_UPPER_LOWER_INT_CLEAR_OFF),
  76         REG_FIELD_SPLIT_BITS_0_15(LOW_INT_MASK,    TM_UPPER_LOWER_INT_MASK_OFF),
  77         REG_FIELD_SPLIT_BITS_16_31(UP_INT_STATUS,  TM_UPPER_LOWER_INT_STATUS_OFF),
  78         REG_FIELD_SPLIT_BITS_16_31(UP_INT_CLEAR,   TM_UPPER_LOWER_INT_CLEAR_OFF),
  79         REG_FIELD_SPLIT_BITS_16_31(UP_INT_MASK,    TM_UPPER_LOWER_INT_MASK_OFF),
  80         REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_STATUS, TM_CRITICAL_INT_STATUS_OFF),
  81         REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_CLEAR,  TM_CRITICAL_INT_CLEAR_OFF),
  82         REG_FIELD_SPLIT_BITS_0_15(CRIT_INT_MASK,   TM_CRITICAL_INT_MASK_OFF),
  83
  84         /* WATCHDOG on v2.3 or later */
  85         [WDOG_BARK_STATUS] = REG_FIELD(TM_CRITICAL_INT_STATUS_OFF, 31, 31),
  86         [WDOG_BARK_CLEAR]  = REG_FIELD(TM_CRITICAL_INT_CLEAR_OFF,  31, 31),
  87         [WDOG_BARK_MASK]   = REG_FIELD(TM_CRITICAL_INT_MASK_OFF,   31, 31),
  88         [CC_MON_STATUS]    = REG_FIELD(TM_CRITICAL_INT_STATUS_OFF, 30, 30),
  89         [CC_MON_CLEAR]     = REG_FIELD(TM_CRITICAL_INT_CLEAR_OFF,  30, 30),
  90         [CC_MON_MASK]      = REG_FIELD(TM_CRITICAL_INT_MASK_OFF,   30, 30),
  91         [WDOG_BARK_COUNT]  = REG_FIELD(TM_WDOG_LOG_OFF,             0,  7),
  92
  93         /* Sn_STATUS */
  94         REG_FIELD_FOR_EACH_SENSOR16(LAST_TEMP,       TM_Sn_STATUS_OFF,  0,  11),
  95         REG_FIELD_FOR_EACH_SENSOR16(VALID,           TM_Sn_STATUS_OFF, 21,  21),
  96         /* xxx_STATUS bits: 1 == threshold violated */
  97         REG_FIELD_FOR_EACH_SENSOR16(MIN_STATUS,      TM_Sn_STATUS_OFF, 16,  16),
  98         REG_FIELD_FOR_EACH_SENSOR16(LOWER_STATUS,    TM_Sn_STATUS_OFF, 17,  17),
  99         REG_FIELD_FOR_EACH_SENSOR16(UPPER_STATUS,    TM_Sn_STATUS_OFF, 18,  18),
 100         REG_FIELD_FOR_EACH_SENSOR16(CRITICAL_STATUS, TM_Sn_STATUS_OFF, 19,  19),
 101         REG_FIELD_FOR_EACH_SENSOR16(MAX_STATUS,      TM_Sn_STATUS_OFF, 20,  20),
 102
 103         /* TRDY: 1=ready, 0=in progress */
 104         [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0),
 105 };
 106
 107 static const struct tsens_ops ops_generic_v2 = {
 108         .init           = init_common,
 109         .get_temp       = get_temp_tsens_valid,
 110         .resume         = tsens_resume_common,
 111 };
 112
 113 struct tsens_plat_data data_tsens_v2 = {
 114         .ops            = &ops_generic_v2,
 115         .feat           = &tsens_v2_feat,
 116         .fields = tsens_v2_regfields,
 117 };
 118
 119 struct tsens_plat_data data_ipq8074 = {
 120         .ops            = &ops_generic_v2,
 121         .feat           = &ipq8074_feat,
 122         .fields = tsens_v2_regfields,
 123 };
 124
 125 /* Kept around for backward compatibility with old msm8996.dtsi */
 126 struct tsens_plat_data data_8996 = {
 127         .num_sensors    = 13,
 128         .ops            = &ops_generic_v2,
 129         .feat           = &tsens_v2_feat,
 130         .fields = tsens_v2_regfields,
 131 };