| blob | cb54390e7de488344e97658c8d9cea8fbaa56632 |
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3 * hcd.c - DesignWare HS OTG Controller host-mode routines
4 *
5 * Copyright (C) 2004-2013 Synopsys, Inc.
6 */
8 /*
9 * This file contains the core HCD code, and implements the Linux hc_driver
10 * API
11 */
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/spinlock.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/delay.h>
19 #include <linux/io.h>
20 #include <linux/slab.h>
21 #include <linux/usb.h>
23 #include <linux/usb/hcd.h>
24 #include <linux/usb/ch11.h>
25 #include <linux/usb/of.h>
30 /*
31 * =========================================================================
32 * Host Core Layer Functions
33 * =========================================================================
34 */
36 /**
37 * dwc2_enable_common_interrupts() - Initializes the commmon interrupts,
38 * used in both device and host modes
39 *
40 * @hsotg: Programming view of the DWC_otg controller
41 */
43 {
44 u32 intmsk;
46 /* Clear any pending OTG Interrupts */
49 /* Clear any pending interrupts */
52 /* Enable the interrupts in the GINTMSK */
61 GINTSTS_SESSREQINT;
67 }
70 {
84 }
91 }
95 else
101 }
104 {
105 u32 usbcfg;
115 fallthrough;
129 }
132 }
135 {
140 }
143 {
148 }
150 /**
151 * dwc2_enable_host_interrupts() - Enables the Host mode interrupts
152 *
153 * @hsotg: Programming view of DWC_otg controller
154 */
156 {
157 u32 intmsk;
161 /* Disable all interrupts */
165 /* Enable the common interrupts */
168 /* Enable host mode interrupts without disturbing common interrupts */
172 }
174 /**
175 * dwc2_disable_host_interrupts() - Disables the Host Mode interrupts
176 *
177 * @hsotg: Programming view of DWC_otg controller
178 */
180 {
183 /* Disable host mode interrupts without disturbing common interrupts */
187 }
189 /*
190 * dwc2_calculate_dynamic_fifo() - Calculates the default fifo size
191 * For system that have a total fifo depth that is smaller than the default
192 * RX + TX fifo size.
193 *
194 * @hsotg: Programming view of DWC_otg controller
195 */
197 {
207 /*
208 * Will use Method 2 defined in the DWC2 spec: minimum FIFO depth
209 * allocation with support for high bandwidth endpoints. Synopsys
210 * defines MPS(Max Packet size) for a periodic EP=1024, and for
211 * non-periodic as 512.
212 */
214 /*
215 * For Buffer DMA mode/Scatter Gather DMA mode
216 * 2 * ((Largest Packet size / 4) + 1 + 1) + n
217 * with n = number of host channel.
218 * 2 * ((1024/4) + 2) = 516
219 */
222 /*
223 * min non-periodic tx fifo depth
224 * 2 * (largest non-periodic USB packet used / 4)
225 * 2 * (512/4) = 256
226 */
229 /*
230 * min periodic tx fifo depth
231 * (largest packet size*MC)/4
232 * (1024 * 3)/4 = 768
233 */
239 }
241 /*
242 * If the summation of RX, NPTX and PTX fifo sizes is still
243 * bigger than the total_fifo_size, then we have a problem.
244 *
245 * We won't be able to allocate as many endpoints. Right now,
246 * we're just printing an error message, but ideally this FIFO
247 * allocation algorithm would be improved in the future.
248 *
249 * FIXME improve this FIFO allocation algorithm.
250 */
253 }
256 {
265 /* Rx FIFO */
275 /* Non-periodic Tx FIFO */
286 /* Periodic Tx FIFO */
300 /*
301 * This feature was implemented in 2.91a version
302 * Global DFIFOCFG calculation for Host mode -
303 * include RxFIFO, NPTXFIFO and HPTXFIFO
304 */
310 GDFIFOCFG_EPINFOBASE_SHIFT &
311 GDFIFOCFG_EPINFOBASE_MASK;
313 }
314 }
316 /**
317 * dwc2_calc_frame_interval() - Calculates the correct frame Interval value for
318 * the HFIR register according to PHY type and speed
319 *
320 * @hsotg: Programming view of DWC_otg controller
321 *
322 * NOTE: The caller can modify the value of the HFIR register only after the
323 * Port Enable bit of the Host Port Control and Status register (HPRT.EnaPort)
324 * has been set
325 */
327 {
328 u32 usbcfg;
329 u32 hprt0;
339 GHWCFG2_FS_PHY_TYPE_SHARED_ULPI)
358 /* High speed case */
361 /* FS/LS case */
363 }
365 /**
366 * dwc2_read_packet() - Reads a packet from the Rx FIFO into the destination
367 * buffer
368 *
369 * @hsotg: Programming view of DWC_otg controller
370 * @dest: Destination buffer for the packet
371 * @bytes: Number of bytes to copy to the destination
372 */
374 {
379 /*
380 * Todo: Account for the case where dest is not dword aligned. This
381 * requires reading data from the FIFO into a u32 temp buffer, then
382 * moving it into the data buffer.
383 */
389 }
391 /**
392 * dwc2_dump_channel_info() - Prints the state of a host channel
393 *
394 * @hsotg: Programming view of DWC_otg controller
395 * @chan: Pointer to the channel to dump
396 *
397 * Must be called with interrupt disabled and spinlock held
398 *
399 * NOTE: This function will be removed once the peripheral controller code
400 * is integrated and the driver is stable
401 */
404 {
405 #ifdef VERBOSE_DEBUG
408 u32 hcchar;
409 u32 hcsplt;
410 u32 hctsiz;
411 u32 hc_dma;
441 qh_list_entry)
445 qh_list_entry)
449 qh_list_entry)
456 }
458 }
463 {
468 }
471 {
475 }
479 {
484 else
487 }
489 /*
490 * =========================================================================
491 * Low Level Host Channel Access Functions
492 * =========================================================================
493 */
497 {
515 }
521 else
523 }
546 else
548 }
561 }
566 }
571 }
575 {
578 /*
579 * For Descriptor DMA mode core halts the channel on AHB error.
580 * Interrupt is not required.
581 */
591 }
602 }
603 }
608 }
612 {
613 u32 intmsk;
623 }
625 /* Enable the top level host channel interrupt */
632 /* Make sure host channel interrupts are enabled */
638 }
640 /**
641 * dwc2_hc_init() - Prepares a host channel for transferring packets to/from
642 * a specific endpoint
643 *
644 * @hsotg: Programming view of DWC_otg controller
645 * @chan: Information needed to initialize the host channel
646 *
647 * The HCCHARn register is set up with the characteristics specified in chan.
648 * Host channel interrupts that may need to be serviced while this transfer is
649 * in progress are enabled.
650 */
652 {
654 u32 hcintmsk;
655 u32 hcchar;
661 /* Clear old interrupt conditions for this host channel */
666 /* Enable channel interrupts required for this transfer */
669 /*
670 * Program the HCCHARn register with the endpoint characteristics for
671 * the current transfer
672 */
700 }
702 /* Program the HCSPLT register for SPLITs */
707 hc_num,
712 HCSPLT_XACTPOS_MASK;
714 HCSPLT_HUBADDR_MASK;
716 HCSPLT_PRTADDR_MASK;
732 }
733 }
736 }
738 /**
739 * dwc2_hc_halt() - Attempts to halt a host channel
740 *
741 * @hsotg: Controller register interface
742 * @chan: Host channel to halt
743 * @halt_status: Reason for halting the channel
744 *
745 * This function should only be called in Slave mode or to abort a transfer in
746 * either Slave mode or DMA mode. Under normal circumstances in DMA mode, the
747 * controller halts the channel when the transfer is complete or a condition
748 * occurs that requires application intervention.
749 *
750 * In slave mode, checks for a free request queue entry, then sets the Channel
751 * Enable and Channel Disable bits of the Host Channel Characteristics
752 * register of the specified channel to intiate the halt. If there is no free
753 * request queue entry, sets only the Channel Disable bit of the HCCHARn
754 * register to flush requests for this channel. In the latter case, sets a
755 * flag to indicate that the host channel needs to be halted when a request
756 * queue slot is open.
757 *
758 * In DMA mode, always sets the Channel Enable and Channel Disable bits of the
759 * HCCHARn register. The controller ensures there is space in the request
760 * queue before submitting the halt request.
761 *
762 * Some time may elapse before the core flushes any posted requests for this
763 * host channel and halts. The Channel Halted interrupt handler completes the
764 * deactivation of the host channel.
765 */
768 {
774 /*
775 * In buffer DMA or external DMA mode channel can't be halted
776 * for non-split periodic channels. At the end of the next
777 * uframe/frame (in the worst case), the core generates a channel
778 * halted and disables the channel automatically.
779 */
786 __func__);
788 }
789 }
796 /*
797 * Disable all channel interrupts except Ch Halted. The QTD
798 * and QH state associated with this transfer has been cleared
799 * (in the case of URB_DEQUEUE), so the channel needs to be
800 * shut down carefully to prevent crashes.
801 */
807 /*
808 * Make sure no other interrupts besides halt are currently
809 * pending. Handling another interrupt could cause a crash due
810 * to the QTD and QH state.
811 */
814 /*
815 * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR
816 * even if the channel was already halted for some other
817 * reason
818 */
823 /*
824 * The channel is either already halted or it hasn't
825 * started yet. In DMA mode, the transfer may halt if
826 * it finishes normally or a condition occurs that
827 * requires driver intervention. Don't want to halt
828 * the channel again. In either Slave or DMA mode,
829 * it's possible that the transfer has been assigned
830 * to a channel, but not started yet when an URB is
831 * dequeued. Don't want to halt a channel that hasn't
832 * started yet.
833 */
835 }
836 }
838 /*
839 * A halt has already been issued for this channel. This might
840 * happen when a transfer is aborted by a higher level in
841 * the stack.
842 */
847 }
851 /* No need to set the bit in DDMA for disabling the channel */
852 /* TODO check it everywhere channel is disabled */
860 }
868 /* Check for space in the request queue to issue the halt */
876 }
886 }
887 }
891 }
905 }
911 hcchar);
918 }
919 }
921 /**
922 * dwc2_hc_cleanup() - Clears the transfer state for a host channel
923 *
924 * @hsotg: Programming view of DWC_otg controller
925 * @chan: Identifies the host channel to clean up
926 *
927 * This function is normally called after a transfer is done and the host
928 * channel is being released
929 */
931 {
932 u32 hcintmsk;
938 /*
939 * Clear channel interrupt enables and any unhandled channel interrupt
940 * conditions
941 */
946 }
948 /**
949 * dwc2_hc_set_even_odd_frame() - Sets the channel property that indicates in
950 * which frame a periodic transfer should occur
951 *
952 * @hsotg: Programming view of DWC_otg controller
953 * @chan: Identifies the host channel to set up and its properties
954 * @hcchar: Current value of the HCCHAR register for the specified host channel
955 *
956 * This function has no effect on non-periodic transfers
957 */
960 {
967 u16 fifo_space;
968 u16 frame_number;
969 u16 wire_frame;
971 /*
972 * Try to figure out if we're an even or odd frame. If we set
973 * even and the current frame number is even the transfer
974 * will happen immediately. Similar if both are odd. If one is
975 * even and the other is odd then the transfer will happen when
976 * the frame number ticks.
977 *
978 * There's a bit of a balancing act to get this right.
979 * Sometimes we may want to send data in the current frame (AK
980 * right away). We might want to do this if the frame number
981 * _just_ ticked, but we might also want to do this in order
982 * to continue a split transaction that happened late in a
983 * microframe (so we didn't know to queue the next transfer
984 * until the frame number had ticked). The problem is that we
985 * need a lot of knowledge to know if there's actually still
986 * time to send things or if it would be better to wait until
987 * the next frame.
988 *
989 * We can look at how much time is left in the current frame
990 * and make a guess about whether we'll have time to transfer.
991 * We'll do that.
992 */
994 /* Get speed host is running at */
998 /* See how many bytes are in the periodic FIFO right now */
1003 fifo_space);
1005 /*
1006 * Roughly estimate bus time for everything in the periodic
1007 * queue + our new transfer. This is "rough" because we're
1008 * using a function that makes takes into account IN/OUT
1009 * and INT/ISO and we're just slamming in one value for all
1010 * transfers. This should be an over-estimate and that should
1011 * be OK, but we can probably tighten it.
1012 */
1017 /* See what frame number we'll be at by the time we finish */
1020 /* This is when we were scheduled to be on the wire */
1023 /*
1024 * If we'd finish _after_ the frame we're scheduled in then
1025 * it's hopeless. Just schedule right away and hope for the
1026 * best. Note that it _might_ be wise to call back into the
1027 * scheduler to pick a better frame, but this is better than
1028 * nothing.
1029 */
1035 wire_frame));
1038 /*
1039 * We picked a different frame number; communicate this
1040 * back to the scheduler so it doesn't try to schedule
1041 * another in the same frame.
1042 *
1043 * Remember that next_active_frame is 1 before the wire
1044 * frame.
1045 */
1048 }
1052 else
1054 }
1055 }
1058 {
1059 /* Set up the initial PID for the transfer */
1066 else
1071 else
1073 }
1076 }
1077 }
1079 /**
1080 * dwc2_hc_write_packet() - Writes a packet into the Tx FIFO associated with
1081 * the Host Channel
1082 *
1083 * @hsotg: Programming view of DWC_otg controller
1084 * @chan: Information needed to initialize the host channel
1085 *
1086 * This function should only be called in Slave mode. For a channel associated
1087 * with a non-periodic EP, the non-periodic Tx FIFO is written. For a channel
1088 * associated with a periodic EP, the periodic Tx FIFO is written.
1089 *
1090 * Upon return the xfer_buf and xfer_count fields in chan are incremented by
1091 * the number of bytes written to the Tx FIFO.
1092 */
1095 {
1096 u32 i;
1097 u32 remaining_count;
1098 u32 byte_count;
1099 u32 dword_count;
1108 else
1114 /* xfer_buf is DWORD aligned */
1118 /* xfer_buf is not DWORD aligned */
1123 }
1124 }
1128 }
1130 /**
1131 * dwc2_hc_do_ping() - Starts a PING transfer
1132 *
1133 * @hsotg: Programming view of DWC_otg controller
1134 * @chan: Information needed to initialize the host channel
1135 *
1136 * This function should only be called in Slave mode. The Do Ping bit is set in
1137 * the HCTSIZ register, then the channel is enabled.
1138 */
1141 {
1142 u32 hcchar;
1143 u32 hctsiz;
1157 }
1159 /**
1160 * dwc2_hc_start_transfer() - Does the setup for a data transfer for a host
1161 * channel and starts the transfer
1162 *
1163 * @hsotg: Programming view of DWC_otg controller
1164 * @chan: Information needed to initialize the host channel. The xfer_len value
1165 * may be reduced to accommodate the max widths of the XferSize and
1166 * PktCnt fields in the HCTSIZn register. The multi_count value may be
1167 * changed to reflect the final xfer_len value.
1168 *
1169 * This function may be called in either Slave mode or DMA mode. In Slave mode,
1170 * the caller must ensure that there is sufficient space in the request queue
1171 * and Tx Data FIFO.
1172 *
1173 * For an OUT transfer in Slave mode, it loads a data packet into the
1174 * appropriate FIFO. If necessary, additional data packets are loaded in the
1175 * Host ISR.
1176 *
1177 * For an IN transfer in Slave mode, a data packet is requested. The data
1178 * packets are unloaded from the Rx FIFO in the Host ISR. If necessary,
1179 * additional data packets are requested in the Host ISR.
1180 *
1181 * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ
1182 * register along with a packet count of 1 and the channel is enabled. This
1183 * causes a single PING transaction to occur. Other fields in HCTSIZ are
1184 * simply set to 0 since no data transfer occurs in this case.
1185 *
1186 * For a PING transfer in DMA mode, the HCTSIZ register is initialized with
1187 * all the information required to perform the subsequent data transfer. In
1188 * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the
1189 * controller performs the entire PING protocol, then starts the data
1190 * transfer.
1191 */
1194 {
1197 u32 hcchar;
1199 u16 num_packets;
1200 u32 ec_mc;
1212 }
1218 }
1226 /*
1227 * For CSPLIT OUT Transfer, set the size to 0 so the
1228 * core doesn't expect any data written to the FIFO
1229 */
1237 TSIZ_XFERSIZE_MASK;
1239 /* For split set ec_mc for immediate retries */
1243 else
1248 /*
1249 * Ensure that the transfer length and packet count will fit
1250 * in the widths allocated for them in the HCTSIZn register
1251 */
1254 /*
1255 * Make sure the transfer size is no larger than one
1256 * (micro)frame's worth of data. (A check was done
1257 * when the periodic transfer was accepted to ensure
1258 * that a (micro)frame's worth of data can be
1259 * programmed into a channel.)
1260 */
1261 u32 max_periodic_len =
1267 /*
1268 * Make sure that xfer_len is a multiple of max packet
1269 * size
1270 */
1273 }
1282 /*
1283 * Always program an integral # of max packets
1284 * for IN transfers.
1285 * Note: This assumes that the input buffer is
1286 * aligned and sized accordingly.
1287 */
1289 }
1291 /* Need 1 packet for transfer length of 0 */
1293 }
1297 /*
1298 * Make sure that the multi_count field matches the
1299 * actual transfer length
1300 */
1307 TSIZ_XFERSIZE_MASK;
1309 /* The ec_mc gets the multi_count for non-split */
1311 }
1316 TSIZ_SC_MC_PID_MASK;
1326 TSIZ_XFERSIZE_SHIFT);
1329 TSIZ_PKTCNT_SHIFT);
1332 TSIZ_SC_MC_PID_SHIFT);
1333 }
1336 dma_addr_t dma_addr;
1344 }
1350 }
1352 /* Start the split */
1358 }
1370 /* Set host channel enable after all other setup is complete */
1377 HCCHAR_MULTICNT_SHIFT);
1389 /* Load OUT packet into the appropriate Tx FIFO */
1391 }
1393 /**
1394 * dwc2_hc_start_transfer_ddma() - Does the setup for a data transfer for a
1395 * host channel and starts the transfer in Descriptor DMA mode
1396 *
1397 * @hsotg: Programming view of DWC_otg controller
1398 * @chan: Information needed to initialize the host channel
1399 *
1400 * Initializes HCTSIZ register. For a PING transfer the Do Ping bit is set.
1401 * Sets PID and NTD values. For periodic transfers initializes SCHED_INFO field
1402 * with micro-frame bitmap.
1403 *
1404 * Initializes HCDMA register with descriptor list address and CTD value then
1405 * starts the transfer via enabling the channel.
1406 */
1409 {
1410 u32 hcchar;
1419 /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
1421 TSIZ_SC_MC_PID_MASK;
1423 /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
1426 /* Non-zero only for high-speed interrupt endpoints */
1435 }
1451 HCCHAR_MULTICNT_MASK;
1458 /* Set host channel enable after all other setup is complete */
1465 HCCHAR_MULTICNT_SHIFT);
1474 }
1476 /**
1477 * dwc2_hc_continue_transfer() - Continues a data transfer that was started by
1478 * a previous call to dwc2_hc_start_transfer()
1479 *
1480 * @hsotg: Programming view of DWC_otg controller
1481 * @chan: Information needed to initialize the host channel
1482 *
1483 * The caller must ensure there is sufficient space in the request queue and Tx
1484 * Data FIFO. This function should only be called in Slave mode. In DMA mode,
1485 * the controller acts autonomously to complete transfers programmed to a host
1486 * channel.
1487 *
1488 * For an OUT transfer, a new data packet is loaded into the appropriate FIFO
1489 * if there is any data remaining to be queued. For an IN transfer, another
1490 * data packet is always requested. For the SETUP phase of a control transfer,
1491 * this function does nothing.
1492 *
1493 * Return: 1 if a new request is queued, 0 if no more requests are required
1494 * for this transfer
1495 */
1498 {
1504 /* SPLITs always queue just once per channel */
1508 /* SETUPs are queued only once since they can't be NAK'd */
1512 /*
1513 * Always queue another request for other IN transfers. If
1514 * back-to-back INs are issued and NAKs are received for both,
1515 * the driver may still be processing the first NAK when the
1516 * second NAK is received. When the interrupt handler clears
1517 * the NAK interrupt for the first NAK, the second NAK will
1518 * not be seen. So we can't depend on the NAK interrupt
1519 * handler to requeue a NAK'd request. Instead, IN requests
1520 * are issued each time this function is called. When the
1521 * transfer completes, the extra requests for the channel will
1522 * be flushed.
1523 */
1531 hcchar);
1535 }
1537 /* OUT transfers */
1547 }
1549 /* Load OUT packet into the appropriate Tx FIFO */
1553 }
1556 }
1558 /*
1559 * =========================================================================
1560 * HCD
1561 * =========================================================================
1562 */
1564 /*
1565 * Processes all the URBs in a single list of QHs. Completes them with
1566 * -ETIMEDOUT and frees the QTD.
1567 *
1568 * Must be called with interrupt disabled and spinlock held
1569 */
1572 {
1578 qtd_list_entry) {
1581 }
1582 }
1583 }
1587 {
1593 /* The list hasn't been initialized yet */
1598 /* Ensure there are no QTDs or URBs left */
1604 /* Free each QTD in the QH's QTD list */
1606 qtd_list_entry)
1615 }
1618 }
1620 /*
1621 * Responds with an error status of -ETIMEDOUT to all URBs in the non-periodic
1622 * and periodic schedules. The QTD associated with each URB is removed from
1623 * the schedule and freed. This function may be called when a disconnect is
1624 * detected or when the HCD is being stopped.
1625 *
1626 * Must be called with interrupt disabled and spinlock held
1627 */
1629 {
1637 }
1639 /**
1640 * dwc2_hcd_start() - Starts the HCD when switching to Host mode
1641 *
1642 * @hsotg: Pointer to struct dwc2_hsotg
1643 */
1645 {
1646 u32 hprt0;
1649 /*
1650 * Reset the port. During a HNP mode switch the reset
1651 * needs to occur within 1ms and have a duration of at
1652 * least 50ms.
1653 */
1657 }
1661 }
1663 /* Must be called with interrupt disabled and spinlock held */
1665 {
1668 u32 hcchar;
1672 /* Flush out any channel requests in slave mode */
1682 }
1683 }
1684 }
1692 /* Halt the channel */
1695 }
1699 /*
1700 * Added for Descriptor DMA to prevent channel double cleanup in
1701 * release_channel_ddma(), which is called from ep_disable when
1702 * device disconnects
1703 */
1705 }
1706 /* All channels have been freed, mark them available */
1713 }
1714 }
1716 /**
1717 * dwc2_hcd_connect() - Handles connect of the HCD
1718 *
1719 * @hsotg: Pointer to struct dwc2_hsotg
1720 *
1721 * Must be called with interrupt disabled and spinlock held
1722 */
1724 {
1730 }
1732 /**
1733 * dwc2_hcd_disconnect() - Handles disconnect of the HCD
1734 *
1735 * @hsotg: Pointer to struct dwc2_hsotg
1736 * @force: If true, we won't try to reconnect even if we see device connected.
1737 *
1738 * Must be called with interrupt disabled and spinlock held
1739 */
1741 {
1742 u32 intr;
1743 u32 hprt0;
1745 /* Set status flags for the hub driver */
1749 /*
1750 * Shutdown any transfers in process by clearing the Tx FIFO Empty
1751 * interrupt mask and status bits and disabling subsequent host
1752 * channel interrupts.
1753 */
1760 /*
1761 * Turn off the vbus power only if the core has transitioned to device
1762 * mode. If still in host mode, need to keep power on to detect a
1763 * reconnection.
1764 */
1769 }
1772 }
1774 /* Respond with an error status to all URBs in the schedule */
1778 /* Clean up any host channels that were in use */
1783 /*
1784 * Add an extra check here to see if we're actually connected but
1785 * we don't have a detection interrupt pending. This can happen if:
1786 * 1. hardware sees connect
1787 * 2. hardware sees disconnect
1788 * 3. hardware sees connect
1789 * 4. dwc2_port_intr() - clears connect interrupt
1790 * 5. dwc2_handle_common_intr() - calls here
1791 *
1792 * Without the extra check here we will end calling disconnect
1793 * and won't get any future interrupts to handle the connect.
1794 */
1799 }
1800 }
1802 /**
1803 * dwc2_hcd_rem_wakeup() - Handles Remote Wakeup
1804 *
1805 * @hsotg: Pointer to struct dwc2_hsotg
1806 */
1808 {
1812 }
1816 }
1818 /**
1819 * dwc2_hcd_stop() - Halts the DWC_otg host mode operations in a clean manner
1820 *
1821 * @hsotg: Pointer to struct dwc2_hsotg
1822 *
1823 * Must be called with interrupt disabled and spinlock held
1824 */
1826 {
1829 /*
1830 * The root hub should be disconnected before this function is called.
1831 * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue)
1832 * and the QH lists (via ..._hcd_endpoint_disable).
1833 */
1835 /* Turn off all host-specific interrupts */
1838 /* Turn off the vbus power */
1841 }
1843 /* Caller must hold driver lock */
1847 {
1848 u32 intr_mask;
1853 /* No longer connected */
1856 }
1860 /* Some configurations cannot support LS traffic on a FS root port */
1869 }
1879 retval);
1881 }
1889 /*
1890 * Do not schedule SG transactions until qtd has
1891 * URB_GIVEBACK_ASAP set
1892 */
1898 }
1901 }
1903 /* Must be called with interrupt disabled and spinlock held */
1906 {
1914 }
1920 }
1927 /* The QTD is in process (it has been assigned to a channel) */
1929 /*
1930 * If still connected (i.e. in host mode), halt the
1931 * channel so it can be used for other transfers. If
1932 * no longer connected, the host registers can't be
1933 * written to halt the channel since the core is in
1934 * device mode.
1935 */
1937 DWC2_HC_XFER_URB_DEQUEUE);
1938 }
1940 /*
1941 * Free the QTD and clean up the associated QH. Leave the QH in the
1942 * schedule if it has any remaining QTDs.
1943 */
1953 }
1956 }
1959 }
1961 /* Must NOT be called with interrupt disabled or spinlock held */
1964 {
1976 }
1984 }
1993 }
1994 }
1998 /* Free each QTD in the QH's QTD list */
2013 err:
2018 }
2020 /* Must be called with interrupt disabled and spinlock held */
2023 {
2032 }
2034 /**
2035 * dwc2_core_init() - Initializes the DWC_otg controller registers and
2036 * prepares the core for device mode or host mode operation
2037 *
2038 * @hsotg: Programming view of the DWC_otg controller
2039 * @initial_setup: If true then this is the first init for this instance.
2040 */
2042 {
2050 /* Set ULPI External VBUS bit if needed */
2055 /* Set external TS Dline pulsing bit if needed */
2062 /*
2063 * Reset the Controller
2064 *
2065 * We only need to reset the controller if this is a re-init.
2066 * For the first init we know for sure that earlier code reset us (it
2067 * needed to in order to properly detect various parameters).
2068 */
2073 __func__);
2075 }
2076 }
2078 /*
2079 * This needs to happen in FS mode before any other programming occurs
2080 */
2085 /* Program the GAHBCFG Register */
2090 /* Program the GUSBCFG register */
2093 /* Program the GOTGCTL register */
2098 /* Clear the SRP success bit for FS-I2c */
2101 /* Enable common interrupts */
2104 /*
2105 * Do device or host initialization based on mode during PCD and
2106 * HCD initialization
2107 */
2114 }
2117 }
2119 /**
2120 * dwc2_core_host_init() - Initializes the DWC_otg controller registers for
2121 * Host mode
2122 *
2123 * @hsotg: Programming view of DWC_otg controller
2124 *
2125 * This function flushes the Tx and Rx FIFOs and flushes any entries in the
2126 * request queues. Host channels are reset to ensure that they are ready for
2127 * performing transfers.
2128 */
2130 {
2135 /* Set HS/FS Timeout Calibration to 7 (max available value).
2136 * The number of PHY clocks that the application programs in
2137 * this field is added to the high/full speed interpacket timeout
2138 * duration in the core to account for any additional delays
2139 * introduced by the PHY. This can be required, because the delay
2140 * introduced by the PHY in generating the linestate condition
2141 * can vary from one PHY to another.
2142 */
2147 /* Restart the Phy Clock */
2150 /* Initialize Host Configuration Register */
2157 }
2159 /*
2160 * This bit allows dynamic reloading of the HFIR register during
2161 * runtime. This bit needs to be programmed during initial configuration
2162 * and its value must not be changed during runtime.
2163 */
2168 }
2187 }
2188 }
2190 /* Configure data FIFO sizes */
2193 /* TODO - check this */
2194 /* Clear Host Set HNP Enable in the OTG Control Register */
2199 /* Make sure the FIFOs are flushed */
2203 /* Clear Host Set HNP Enable in the OTG Control Register */
2210 u32 hcchar;
2212 /* Flush out any leftover queued requests */
2221 }
2222 }
2224 /* Halt all channels to put them into a known state */
2235 HCCHAR_CHENA,
2239 i);
2240 }
2241 }
2242 }
2243 }
2245 /* Enable ACG feature in host mode, if supported */
2248 /* Turn on the vbus power */
2258 }
2259 }
2262 }
2264 /*
2265 * Initializes dynamic portions of the DWC_otg HCD state
2266 *
2267 * Must be called with interrupt disabled and spinlock held
2268 */
2270 {
2284 }
2286 /*
2287 * Put all channels in the free channel list and clean up channel
2288 * states
2289 */
2291 hc_list_entry)
2299 }
2301 /* Initialize the DWC core for host mode operation */
2303 }
2308 {
2317 }
2322 {
2338 else
2349 /*
2350 * Direction is opposite of data direction or IN if no
2351 * data
2352 */
2356 else
2365 else
2368 }
2395 }
2402 else
2404 }
2406 }
2407 }
2412 {
2422 }
2425 DWC2_KMEM_UNALIGNED_BUF_SIZE,
2426 DMA_FROM_DEVICE);
2432 }
2436 }
2438 #define DWC2_USB_DMA_ALIGN 4
2441 {
2448 /* Restore urb->transfer_buffer from the end of the allocated area */
2457 else
2461 }
2466 }
2469 {
2478 /*
2479 * Allocate a buffer with enough padding for original transfer_buffer
2480 * pointer. This allocation is guaranteed to be aligned properly for
2481 * DMA
2482 */
2491 /*
2492 * Position value of original urb->transfer_buffer pointer to the end
2493 * of allocation for later referencing
2494 */
2507 }
2510 gfp_t mem_flags)
2511 {
2514 /* We assume setup_dma is always aligned; warn if not */
2527 }
2530 {
2533 }
2535 /**
2536 * dwc2_assign_and_init_hc() - Assigns transactions from a QTD to a free host
2537 * channel and initializes the host channel to perform the transactions. The
2538 * host channel is removed from the free list.
2539 *
2540 * @hsotg: The HCD state structure
2541 * @qh: Transactions from the first QTD for this QH are selected and assigned
2542 * to a free host channel
2543 */
2545 {
2556 }
2561 }
2564 hc_list_entry);
2566 /* Remove host channel from free list */
2574 /*
2575 * Use usb_pipedevice to determine device address. This address is
2576 * 0 before the SET_ADDRESS command and the correct address afterward.
2577 */
2590 /*
2591 * The following values may be modified in the transfer type section
2592 * below. The xfer_len value may be reduced when the transfer is
2593 * started to accommodate the max widths of the XferSize and PktCnt
2594 * fields in the HCTSIZn register.
2595 */
2600 else
2612 else
2618 /* Set the split attributes if required */
2621 else
2624 /* Set the transfer attributes */
2627 /* For non-dword aligned buffers */
2634 /* Add channel back to free list */
2642 }
2644 /*
2645 * We assume that DMA is always aligned in non-split
2646 * case or split out case. Warn if not.
2647 */
2651 }
2655 /*
2656 * This value may be modified when the transfer is started
2657 * to reflect the actual transfer length
2658 */
2664 }
2670 }
2672 /**
2673 * dwc2_hcd_select_transactions() - Selects transactions from the HCD transfer
2674 * schedule and assigns them to available host channels. Called from the HCD
2675 * interrupt handler functions.
2676 *
2677 * @hsotg: The HCD state structure
2678 *
2679 * Return: The types of new transactions that were assigned to host channels
2680 */
2683 {
2689 #ifdef DWC2_DEBUG_SOF
2691 #endif
2693 /* Process entries in the periodic ready list */
2702 }
2708 }
2710 /*
2711 * Move the QH from the periodic ready schedule to the
2712 * periodic assigned schedule
2713 */
2718 }
2720 /*
2721 * Process entries in the inactive portion of the non-periodic
2722 * schedule. Some free host channels may not be used if they are
2723 * reserved for periodic transfers.
2724 */
2739 }
2745 }
2747 /*
2748 * Move the QH from the non-periodic inactive schedule to the
2749 * non-periodic active schedule
2750 */
2757 else
2762 }
2765 }
2767 /**
2768 * dwc2_queue_transaction() - Attempts to queue a single transaction request for
2769 * a host channel associated with either a periodic or non-periodic transfer
2770 *
2771 * @hsotg: The HCD state structure
2772 * @chan: Host channel descriptor associated with either a periodic or
2773 * non-periodic transfer
2774 * @fifo_dwords_avail: Number of DWORDs available in the periodic Tx FIFO
2775 * for periodic transfers or the non-periodic Tx FIFO
2776 * for non-periodic transfers
2777 *
2778 * Return: 1 if a request is queued and more requests may be needed to
2779 * complete the transfer, 0 if no more requests are required for this
2780 * transfer, -1 if there is insufficient space in the Tx FIFO
2781 *
2782 * This function assumes that there is space available in the appropriate
2783 * request queue. For an OUT transfer or SETUP transaction in Slave mode,
2784 * it checks whether space is available in the appropriate Tx FIFO.
2785 *
2786 * Must be called with interrupt disabled and spinlock held
2787 */
2790 u16 fifo_dwords_avail)
2791 {
2795 /* Put ourselves on the list to keep order straight */
2805 }
2809 }
2811 /* Don't queue a request if the channel has been halted */
2825 }
2828 }
2835 }
2836 }
2839 }
2841 /*
2842 * Processes periodic channels for the next frame and queues transactions for
2843 * these channels to the DWC_otg controller. After queueing transactions, the
2844 * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions
2845 * to queue as Periodic Tx FIFO or request queue space becomes available.
2846 * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled.
2847 *
2848 * Must be called with interrupt disabled and spinlock held
2849 */
2851 {
2854 u32 tx_status;
2855 u32 fspcavail;
2856 u32 gintmsk;
2860 u32 qspcavail;
2862 /* If empty list then just adjust interrupt enables */
2871 TXSTS_QSPCAVAIL_SHIFT;
2873 TXSTS_FSPCAVAIL_SHIFT;
2877 qspcavail);
2879 fspcavail);
2880 }
2886 TXSTS_QSPCAVAIL_SHIFT;
2890 }
2896 }
2898 /* Make sure EP's TT buffer is clean before queueing qtds */
2902 }
2904 /*
2905 * Set a flag if we're queuing high-bandwidth in slave mode.
2906 * The flag prevents any halts to get into the request queue in
2907 * the middle of multiple high-bandwidth packets getting queued.
2908 */
2914 TXSTS_FSPCAVAIL_SHIFT;
2919 }
2921 /*
2922 * In Slave mode, stay on the current transfer until there is
2923 * nothing more to do or the high-bandwidth request count is
2924 * reached. In DMA mode, only need to queue one request. The
2925 * controller automatically handles multiple packets for
2926 * high-bandwidth transfers.
2927 */
2931 /*
2932 * Move the QH from the periodic assigned schedule to
2933 * the periodic queued schedule
2934 */
2938 /* done queuing high bandwidth */
2940 }
2941 }
2943 exit:
2947 /*
2948 * May need to queue more transactions as the request
2949 * queue or Tx FIFO empties. Enable the periodic Tx
2950 * FIFO empty interrupt. (Always use the half-empty
2951 * level to ensure that new requests are loaded as
2952 * soon as possible.)
2953 */
2958 }
2960 /*
2961 * Disable the Tx FIFO empty interrupt since there are
2962 * no more transactions that need to be queued right
2963 * now. This function is called from interrupt
2964 * handlers to queue more transactions as transfer
2965 * states change.
2966 */
2971 }
2972 }
2973 }
2975 /*
2976 * Processes active non-periodic channels and queues transactions for these
2977 * channels to the DWC_otg controller. After queueing transactions, the NP Tx
2978 * FIFO Empty interrupt is enabled if there are more transactions to queue as
2979 * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx
2980 * FIFO Empty interrupt is disabled.
2981 *
2982 * Must be called with interrupt disabled and spinlock held
2983 */
2985 {
2988 u32 tx_status;
2989 u32 qspcavail;
2990 u32 fspcavail;
2991 u32 gintmsk;
3001 TXSTS_QSPCAVAIL_SHIFT;
3003 TXSTS_FSPCAVAIL_SHIFT;
3005 qspcavail);
3007 fspcavail);
3009 /*
3010 * Keep track of the starting point. Skip over the start-of-list
3011 * entry.
3012 */
3017 /*
3018 * Process once through the active list or until no more space is
3019 * available in the request queue or the Tx FIFO
3020 */
3024 TXSTS_QSPCAVAIL_SHIFT;
3028 }
3031 qh_list_entry);
3035 /* Make sure EP's TT buffer is clean before queueing qtds */
3040 TXSTS_FSPCAVAIL_SHIFT;
3048 }
3049 next:
3050 /* Advance to next QH, skipping start-of-list entry */
3061 TXSTS_QSPCAVAIL_SHIFT;
3063 TXSTS_FSPCAVAIL_SHIFT;
3066 qspcavail);
3069 fspcavail);
3072 /*
3073 * May need to queue more transactions as the request
3074 * queue or Tx FIFO empties. Enable the non-periodic
3075 * Tx FIFO empty interrupt. (Always use the half-empty
3076 * level to ensure that new requests are loaded as
3077 * soon as possible.)
3078 */
3083 /*
3084 * Disable the Tx FIFO empty interrupt since there are
3085 * no more transactions that need to be queued right
3086 * now. This function is called from interrupt
3087 * handlers to queue more transactions as transfer
3088 * states change.
3089 */
3093 }
3094 }
3095 }
3097 /**
3098 * dwc2_hcd_queue_transactions() - Processes the currently active host channels
3099 * and queues transactions for these channels to the DWC_otg controller. Called
3100 * from the HCD interrupt handler functions.
3101 *
3102 * @hsotg: The HCD state structure
3103 * @tr_type: The type(s) of transactions to queue (non-periodic, periodic,
3104 * or both)
3105 *
3106 * Must be called with interrupt disabled and spinlock held
3107 */
3110 {
3111 #ifdef DWC2_DEBUG_SOF
3113 #endif
3114 /* Process host channels associated with periodic transfers */
3119 /* Process host channels associated with non-periodic transfers */
3125 /*
3126 * Ensure NP Tx FIFO empty interrupt is disabled when
3127 * there are no non-periodic transfers to process
3128 */
3133 }
3134 }
3135 }
3138 {
3140 wf_otg);
3142 u32 gotgctl;
3152 /* B-Device connector (Device Mode) */
3155 /* Wait for switch to device mode */
3161 }
3168 /*
3169 * Sometimes the initial GOTGCTRL read is wrong, so
3170 * check it again and jump to host mode if that was
3171 * the case.
3172 */
3178 }
3183 /*
3184 * Exit Partial Power Down without restoring registers.
3185 * No need to check the return value as registers
3186 * are not being restored.
3187 */
3197 /* Enable ACG feature in device mode,if supported */
3201 host:
3202 /* A-Device connector (Host Mode) */
3211 }
3221 /* Initialize the Core for Host mode */
3225 }
3226 }
3229 {
3231 u32 hprt0;
3235 /*
3236 * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms
3237 * so that OPT tests pass with all PHYs.)
3238 */
3249 /* Change to L0 state */
3251 }
3254 {
3258 }
3260 /**
3261 * dwc2_port_suspend() - Put controller in suspend mode for host.
3262 *
3263 * @hsotg: Programming view of the DWC_otg controller
3264 * @windex: The control request wIndex field
3265 *
3266 * Return: non-zero if failed to enter suspend mode for host.
3267 *
3268 * This function is for entering Host mode suspend.
3269 * Must NOT be called with interrupt disabled or spinlock held.
3270 */
3272 {
3274 u32 pcgctl;
3275 u32 gotgctl;
3287 }
3297 /*
3298 * Perform spin unlock and lock because in
3299 * "dwc2_host_enter_hibernation()" function there is a spinlock
3300 * logic which prevents servicing of any IRQ during entering
3301 * hibernation.
3302 */
3310 /*
3311 * If not hibernation nor partial power down are supported,
3312 * clock gating is used to save power.
3313 */
3317 }
3319 /* For HNP the bus must be suspended for at least 200ms */
3330 }
3333 }
3335 /**
3336 * dwc2_port_resume() - Exit controller from suspend mode for host.
3337 *
3338 * @hsotg: Programming view of the DWC_otg controller
3339 *
3340 * Return: non-zero if failed to exit suspend mode for host.
3341 *
3342 * This function is for exiting Host mode suspend.
3343 * Must NOT be called with interrupt disabled or spinlock held.
3344 */
3346 {
3360 /* Exit host hibernation. */
3366 /*
3367 * If not hibernation nor partial power down are supported,
3368 * port resume is done using the clock gating programming flow.
3369 */
3374 }
3379 }
3381 /* Handles hub class-specific requests */
3384 {
3387 u32 hprt0;
3388 u32 port_status;
3389 u32 speed;
3390 u32 pcgctl;
3391 u32 pwr;
3400 /* Nothing required here */
3407 wvalue);
3408 }
3446 /* Port indicator not supported */
3450 /*
3451 * Clears driver's internal Connect Status Change flag
3452 */
3459 /* Clears driver's internal Port Reset Change flag */
3466 /*
3467 * Clears the driver's internal Port Enable/Disable
3468 * Change flag
3469 */
3476 /*
3477 * Clears the driver's internal Port Suspend Change
3478 * flag, which is set when resume signaling on the host
3479 * port is complete
3480 */
3502 wvalue);
3503 }
3514 HUB_CHAR_INDV_PORT_OCPM);
3547 }
3550 /*
3551 * The port is disconnected, which means the core is
3552 * either in device mode or it soon will be. Just
3553 * return 0's for the remainder of the port status
3554 * since the port register can't be read if the core
3555 * is in device mode.
3556 */
3559 }
3585 /* USB_PORT_FEAT_INDICATOR unsupported always 0 */
3588 /*
3589 * Enable descriptor DMA only if a full speed
3590 * device is connected.
3591 */
3595 USB_PORT_STAT_HIGH_SPEED |
3596 USB_PORT_STAT_LOW_SPEED)) ==
3597 USB_PORT_STAT_CONNECTION)) {
3598 u32 hcfg;
3606 }
3607 }
3615 /* No HUB features supported */
3624 /*
3625 * The port is disconnected, which means the core is
3626 * either in device mode or it soon will be. Just
3627 * return without doing anything since the port
3628 * register can't be written if the core is in device
3629 * mode.
3630 */
3632 }
3666 }
3674 }
3683 /* ??? Original driver does this */
3688 /* Clear suspend bit if resetting from suspend state */
3691 /*
3692 * When B-Host the Port reset bit is set in the Start
3693 * HCD Callback function, so that the reset is started
3694 * within 1ms of the HNP success interrupt
3695 */
3703 }
3705 /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */
3715 /* Not supported */
3731 wvalue);
3733 }
3737 error:
3743 }
3746 }
3749 {
3774 }
3777 }
3780 {
3783 #ifdef DWC2_DEBUG_SOF
3786 #endif
3788 }
3791 {
3801 /* High speed has 125 us per (micro) frame; others are 1 ms per */
3804 /* Extract fields */
3809 /*
3810 * Number of phy clocks since the last tick of the frame number after
3811 * "us" has passed.
3812 */
3817 }
3820 {
3822 }
3826 gfp_t mem_flags)
3827 {
3834 }
3840 {
3853 }
3855 /*
3856 * NOTE: This function will be removed once the peripheral controller code
3857 * is integrated and the driver is stable
3858 */
3860 {
3861 #ifdef DEBUG
3866 u32 np_tx_status;
3867 u32 p_tx_status;
3923 }
3957 }
3958 }
3959 }
3981 #endif
3982 }
3986 };
3988 /* Gets the dwc2_hsotg from a usb_hcd */
3990 {
3995 }
3997 /**
3998 * dwc2_host_get_tt_info() - Get the dwc2_tt associated with context
3999 *
4000 * This will get the dwc2_tt structure (and ttport) associated with the given
4001 * context (which is really just a struct urb pointer).
4002 *
4003 * The first time this is called for a given TT we allocate memory for our
4004 * structure. When everyone is done and has called dwc2_host_put_tt_info()
4005 * then the refcount for the structure will go to 0 and we'll free it.
4006 *
4007 * @hsotg: The HCD state structure for the DWC OTG controller.
4008 * @context: The priv pointer from a struct dwc2_hcd_urb.
4009 * @mem_flags: Flags for allocating memory.
4010 * @ttport: We'll return this device's port number here. That's used to
4011 * reference into the bitmap if we're on a multi_tt hub.
4012 *
4013 * Return: a pointer to a struct dwc2_tt. Don't forget to call
4014 * dwc2_host_put_tt_info()! Returns NULL upon memory alloc failure.
4015 */
4019 {
4030 /*
4031 * For single_tt we need one schedule. For multi_tt
4032 * we need one per port.
4033 */
4040 mem_flags);
4046 }
4049 }
4052 }
4054 /**
4055 * dwc2_host_put_tt_info() - Put the dwc2_tt from dwc2_host_get_tt_info()
4056 *
4057 * Frees resources allocated by dwc2_host_get_tt_info() if all current holders
4058 * of the structure are done.
4059 *
4060 * It's OK to call this with NULL.
4061 *
4062 * @hsotg: The HCD state structure for the DWC OTG controller.
4063 * @dwc_tt: The pointer returned by dwc2_host_get_tt_info.
4064 */
4066 {
4067 /* Model kfree and make put of NULL a no-op */
4077 }
4078 }
4081 {
4085 }
4089 {
4096 else
4098 }
4102 {
4109 else
4111 }
4113 /*
4114 * Sets the final status of an URB and returns it to the upper layer. Any
4115 * required cleanup of the URB is performed.
4116 *
4117 * Must be called with interrupt disabled and spinlock held
4118 */
4121 {
4128 }
4133 }
4139 }
4161 }
4162 }
4168 }
4175 }
4184 urb);
4185 }
4193 }
4195 /*
4196 * Work queue function for starting the HCD when A-Cable is connected
4197 */
4199 {
4205 }
4207 /*
4208 * Reset work queue function
4209 */
4211 {
4215 u32 hprt0;
4227 }
4230 {
4232 phy_reset_work);
4238 }
4240 /*
4241 * =========================================================================
4242 * Linux HC Driver Functions
4243 * =========================================================================
4244 */
4246 /*
4247 * Initializes the DWC_otg controller and its root hub and prepares it for host
4248 * mode operation. Activates the root port. Returns 0 on success and a negative
4249 * error code on failure.
4250 */
4252 {
4256 u32 hprt0;
4269 }
4274 /* Has vbus power been turned on in dwc2_core_host_init ? */
4276 /* Enable external vbus supply before resuming root hub */
4282 }
4284 /* Initialize and connect root hub if one is not already attached */
4287 /* Inform the HUB driver to resume */
4289 }
4294 }
4296 /*
4297 * Halts the DWC_otg host mode operations in a clean manner. USB transfers are
4298 * stopped.
4299 */
4301 {
4304 u32 hprt0;
4306 /* Turn off all host-specific interrupts */
4309 /* Wait for interrupt processing to finish */
4314 /* Ensure hcd is disconnected */
4322 /* keep balanced supply init/exit by checking HPRT0_PWR */
4327 }
4330 {
4357 /* Enter partial_power_down */
4362 /* After entering suspend, hardware is not accessible */
4366 /* Enter hibernation */
4373 /* After entering suspend, hardware is not accessible */
4377 /*
4378 * If not hibernation nor partial power down are supported,
4379 * clock gating is used to save power.
4380 */
4384 /* After entering suspend, hardware is not accessible */
4386 }
4390 }
4396 /* Ask phy to be suspended */
4401 }
4403 skip_power_saving:
4405 unlock:
4409 }
4412 {
4415 u32 hprt0;
4428 /*
4429 * Added port connection status checking which prevents exiting from
4430 * Partial Power Down mode from _dwc2_hcd_resume() if not in Partial
4431 * Power Down mode.
4432 */
4436 }
4444 /*
4445 * Set HW accessible bit before powering on the controller
4446 * since an interrupt may rise.
4447 */
4455 /*
4456 * Set HW accessible bit before powering on the controller
4457 * since an interrupt may rise.
4458 */
4462 /*
4463 * If not hibernation nor partial power down are supported,
4464 * port resume is done using the clock gating programming flow.
4465 */
4469 /*
4470 * Initialize the Core for Host mode, as after system resume
4471 * the global interrupts are disabled.
4472 */
4478 /*
4479 * Set HW accessible bit before powering on the controller
4480 * since an interrupt may rise.
4481 */
4487 }
4489 /* Change Root port status, as port status change occurred after resume.*/
4492 /*
4493 * Enable power if not already done.
4494 * This must not be spinlocked since duration
4495 * of this call is unknown.
4496 */
4501 }
4503 /* Enable external vbus supply after resuming the port. */
4507 /* Wait for controller to correctly update D+/D- level */
4511 /*
4512 * Clear Port Enable and Port Status changes.
4513 * Enable Port Power.
4514 */
4518 /* Wait for controller to detect Port Connect */
4522 unlock:
4526 }
4528 /* Returns the current frame number */
4530 {
4534 }
4538 {
4539 #ifdef VERBOSE_DEBUG
4564 }
4583 }
4606 }
4607 }
4608 #endif
4609 }
4611 /*
4612 * Starts processing a USB transfer request specified by a USB Request Block
4613 * (URB). mem_flags indicates the type of memory allocation to use while
4614 * processing this URB.
4615 */
4617 gfp_t mem_flags)
4618 {
4639 }
4644 else
4650 }
4657 }
4663 else
4665 }
4676 }
4691 }
4694 mem_flags);
4710 __func__);
4713 }
4714 }
4738 /* Create QH for the endpoint if it doesn't exist */
4744 }
4747 }
4753 }
4767 urb);
4768 }
4774 fail3:
4779 fail2:
4783 fail1:
4789 /* Free each QTD in the QH's QTD list */
4791 qtd_list_entry)
4794 }
4795 fail0:
4799 }
4801 /*
4802 * Aborts/cancels a USB transfer request. Always returns 0 to indicate success.
4803 */
4806 {
4823 }
4832 /* Higher layer software sets URB status */
4839 out:
4843 }
4845 /*
4846 * Frees resources in the DWC_otg controller related to a given endpoint. Also
4847 * clears state in the HCD related to the endpoint. Any URBs for the endpoint
4848 * must already be dequeued.
4849 */
4852 {
4859 }
4861 /*
4862 * Resets endpoint specific parameter values, in current version used to reset
4863 * the data toggle (as a WA). This function can be called from usb_clear_halt
4864 * routine.
4865 */
4868 {
4879 }
4881 /*
4882 * Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if
4883 * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid
4884 * interrupt.
4885 *
4886 * This function is called by the USB core when an interrupt occurs
4887 */
4889 {
4893 }
4895 /*
4896 * Creates Status Change bitmap for the root hub and root port. The bitmap is
4897 * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1
4898 * is the status change indicator for the single root port. Returns 1 if either
4899 * change indicator is 1, otherwise returns 0.
4900 */
4902 {
4907 }
4909 /* Handles hub class-specific requests */
4912 {
4916 }
4918 /* Handles hub TT buffer clear completions */
4921 {
4937 }
4939 /*
4940 * HPRT0_SPD_HIGH_SPEED: high speed
4941 * HPRT0_SPD_FULL_SPEED: full speed
4942 */
4944 {
4952 }
4955 {
4961 /*
4962 * On removal, set speed to default high-speed.
4963 */
4968 }
4969 }
4972 {
4983 /*
4984 * Change speed setting to full-speed if there's
4985 * a full-speed or low-speed device plugged in.
4986 */
4989 }
4992 }
5019 };
5021 /*
5022 * Frees secondary storage associated with the dwc2_hsotg structure contained
5023 * in the struct usb_hcd field
5024 */
5026 {
5027 u32 ahbcfg;
5028 u32 dctl;
5033 /* Free memory for QH/QTD lists */
5042 /* Free memory for the host channels */
5051 }
5052 }
5060 }
5064 }
5068 /* Disable all interrupts */
5077 }
5083 }
5088 }
5091 {
5092 /* Turn off all host-specific interrupts */
5096 }
5098 /*
5099 * Initializes the HCD. This function allocates memory for and initializes the
5100 * static parts of the usb_hcd and dwc2_hsotg structures. It also registers the
5101 * USB bus with the core and calls the hc_driver->start() function. It returns
5102 * a negative error on failure.
5103 */
5105 {
5110 u32 hcfg;
5124 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5127 GFP_KERNEL);
5135 #endif
5138 /* Check if the bus driver or platform code has setup a dma_mask */
5145 }
5147 /* Set device flags indicating whether the HCD supports DMA */
5153 }
5158 }
5173 }
5180 /*
5181 * Disable the global interrupt until all the interrupt handlers are
5182 * installed
5183 */
5186 /* Initialize the DWC_otg core, and select the Phy type */
5191 /* Create new workqueue and init work */
5197 }
5202 /* Initialize the non-periodic schedule */
5207 /* Initialize the periodic schedule */
5215 /*
5216 * Create a host channel descriptor for each host channel implemented
5217 * in the controller. Initialize the channel descriptor array.
5218 */
5230 }
5232 /* Initialize work */
5237 /*
5238 * Allocate space for storing data on status transactions. Normally no
5239 * data is sent, but this space acts as a bit bucket. This must be
5240 * done after usb_add_hcd since that function allocates the DMA buffer
5241 * pool.
5242 */
5245 DWC2_HCD_STATUS_BUF_SIZE,
5247 else
5249 GFP_KERNEL);
5254 /*
5255 * Create kmem caches to handle descriptor buffers in descriptor
5256 * DMA mode.
5257 * Alignment must be set to 512 bytes.
5258 */
5264 NULL);
5269 /*
5270 * Disable descriptor dma mode since it will not be
5271 * usable.
5272 */
5275 }
5286 /*
5287 * Disable descriptor dma mode since it will not be
5288 * usable.
5289 */
5292 }
5293 }
5296 /*
5297 * Create kmem caches to handle non-aligned buffer
5298 * in Buffer DMA mode.
5299 */
5306 }
5313 /* Initiate lx_state to L3 disconnected state */
5318 /* Don't support SG list at this point */
5326 /*
5327 * Finish generic HCD initialization and start the HCD. This function
5328 * allocates the DMA buffer pool, registers the USB bus, requests the
5329 * IRQ line, and calls hcd_start method.
5330 */
5343 error4:
5347 error3:
5349 error2:
5351 error1:
5353 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5356 #endif
5360 }
5362 /*
5363 * Removes the HCD.
5364 * Frees memory and resources associated with the HCD and deregisters the bus.
5365 */
5367 {
5377 __func__);
5379 }
5394 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
5397 #endif
5398 }
5400 /**
5401 * dwc2_backup_host_registers() - Backup controller host registers.
5402 * When suspending usb bus, registers needs to be backuped
5403 * if controller power is disabled once suspended.
5404 *
5405 * @hsotg: Programming view of the DWC_otg controller
5406 */
5408 {
5414 /* Backup Host regs */
5426 }
5434 }
5436 /**
5437 * dwc2_restore_host_registers() - Restore controller host registers.
5438 * When resuming usb bus, device registers needs to be restored
5439 * if controller power were disabled.
5440 *
5441 * @hsotg: Programming view of the DWC_otg controller
5442 */
5444 {
5450 /* Restore host regs */
5454 __func__);
5456 }
5470 }
5478 }
5480 /**
5481 * dwc2_host_enter_hibernation() - Put controller in Hibernation.
5482 *
5483 * @hsotg: Programming view of the DWC_otg controller
5484 */
5486 {
5489 u32 hprt0;
5490 u32 pcgcctl;
5491 u32 gusbcfg;
5492 u32 gpwrdn;
5498 __func__);
5500 }
5504 __func__);
5506 }
5508 /* Enter USB Suspend Mode */
5514 /* Wait for the HPRT0.PrtSusp register field to be set */
5518 /*
5519 * We need to disable interrupts to prevent servicing of any IRQ
5520 * during going to hibernation
5521 */
5527 /* ULPI interface */
5533 /* Suspend the Phy Clock */
5544 /* UTMI+ Interface */
5554 }
5556 /* Enable interrupts from wake up logic */
5562 /* Unmask host mode interrupts in GPWRDN */
5570 /* Enable Power Down Clamp */
5576 /* Switch off VDD */
5586 }
5588 /*
5589 * dwc2_host_exit_hibernation()
5590 *
5591 * @hsotg: Programming view of the DWC_otg controller
5592 * @rem_wakeup: indicates whether resume is initiated by Device or Host.
5593 * @param reset: indicates whether resume is initiated by Reset.
5594 *
5595 * Return: non-zero if failed to enter to hibernation.
5596 *
5597 * This function is for exiting from Host mode hibernation by
5598 * Host Initiated Resume/Reset and Device Initiated Remote-Wakeup.
5599 */
5602 {
5603 u32 gpwrdn;
5604 u32 hprt0;
5619 /*
5620 * This step is not described in functional spec but if not wait for
5621 * this delay, mismatch interrupts occurred because just after restore
5622 * core is in Device mode(gintsts.curmode == 0)
5623 */
5626 /* Clear all pending interupts */
5629 /* De-assert Restore */
5635 /* Restore GUSBCFG, HCFG */
5639 /* Reset ULPI latch */
5644 /* De-assert Wakeup Logic */
5650 }
5667 /* Wait for Resume time and then program HPRT again */
5675 /* De-assert Wakeup Logic */
5681 }
5682 /* Wait for Resume time and then program HPRT again */
5686 }
5687 /* Clear all interrupt status */
5696 /* Clear all pending interupts */
5699 /* Restore global registers */
5703 __func__);
5705 }
5707 /* Restore host registers */
5711 __func__);
5713 }
5717 /*
5718 * Change "port_connect_status_change" flag to re-enumerate,
5719 * because after exit from hibernation port connection status
5720 * is not detected.
5721 */
5723 }
5730 }
5733 {
5736 /* If the controller isn't allowed to wakeup then we can power off. */
5740 /*
5741 * We don't want to power off the PHY if something under the
5742 * root hub has wakeup enabled.
5743 */
5747 /* No reason to keep the PHY powered, so allow poweroff */
5749 }
5751 /**
5752 * dwc2_host_enter_partial_power_down() - Put controller in partial
5753 * power down.
5754 *
5755 * @hsotg: Programming view of the DWC_otg controller
5756 *
5757 * Return: non-zero if failed to enter host partial power down.
5758 *
5759 * This function is for entering Host mode partial power down.
5760 */
5762 {
5763 u32 pcgcctl;
5764 u32 hprt0;
5769 /* Put this port in suspend mode. */
5775 /* Wait for the HPRT0.PrtSusp register field to be set */
5779 /* Backup all registers */
5783 __func__);
5785 }
5790 __func__);
5792 }
5794 /*
5795 * Clear any pending interrupts since dwc2 will not be able to
5796 * clear them after entering partial_power_down.
5797 */
5800 /* Put the controller in low power state */
5814 /* Set in_ppd flag to 1 as here core enters suspend. */
5822 }
5824 /*
5825 * dwc2_host_exit_partial_power_down() - Exit controller from host partial
5826 * power down.
5827 *
5828 * @hsotg: Programming view of the DWC_otg controller
5829 * @rem_wakeup: indicates whether resume is initiated by Reset.
5830 * @restore: indicates whether need to restore the registers or not.
5831 *
5832 * Return: non-zero if failed to exit host partial power down.
5833 *
5834 * This function is for exiting from Host mode partial power down.
5835 */
5838 {
5839 u32 pcgcctl;
5841 u32 hprt0;
5864 __func__);
5866 }
5871 __func__);
5873 }
5874 }
5876 /* Drive resume signaling and exit suspend mode on the port. */
5884 /* Stop driveing resume signaling on the port. */
5891 /* Turn on the port power bit. */
5896 /* Connect hcd. */
5901 }
5903 /* Set lx_state to and in_ppd to 0 as here core exits from suspend. */
5909 }
5911 /**
5912 * dwc2_host_enter_clock_gating() - Put controller in clock gating.
5913 *
5914 * @hsotg: Programming view of the DWC_otg controller
5915 *
5916 * This function is for entering Host mode clock gating.
5917 */
5919 {
5920 u32 hprt0;
5921 u32 pcgctl;
5925 /* Put this port in suspend mode. */
5930 /* Set the Phy Clock bit as suspend is received. */
5936 /* Set the Gate hclk as suspend is received. */
5944 }
5946 /**
5947 * dwc2_host_exit_clock_gating() - Exit controller from clock gating.
5948 *
5949 * @hsotg: Programming view of the DWC_otg controller
5950 * @rem_wakeup: indicates whether resume is initiated by remote wakeup
5951 *
5952 * This function is for exiting Host mode clock gating.
5953 */
5955 {
5956 u32 hprt0;
5957 u32 pcgctl;
5961 /* Clear the Gate hclk. */
5967 /* Phy Clock bit. */
5973 /* Drive resume signaling and exit suspend mode on the port. */
5981 /* In case of port resume need to wait for 40 ms */
5984 /* Stop driveing resume signaling on the port. */
5994 }
5995 }