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drm/rockchip: Don't change hdmi reference clock rate
[drm/drm-misc.git] / drivers / video / fbdev / matrox / matroxfb_misc.c
blob8f159a2ad8d050c80c8df4de4c92d325e48ab492
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 *
4 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
5 *
6 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
7 *
8 * Portions Copyright (c) 2001 Matrox Graphics Inc.
9 *
10 * Version: 1.65 2002/08/14
11 *
12 * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
13 *
14 * Contributors: "menion?" <menion@mindless.com>
15 * Betatesting, fixes, ideas
16 *
17 * "Kurt Garloff" <garloff@suse.de>
18 * Betatesting, fixes, ideas, videomodes, videomodes timmings
19 *
20 * "Tom Rini" <trini@kernel.crashing.org>
21 * MTRR stuff, PPC cleanups, betatesting, fixes, ideas
22 *
23 * "Bibek Sahu" <scorpio@dodds.net>
24 * Access device through readb|w|l and write b|w|l
25 * Extensive debugging stuff
26 *
27 * "Daniel Haun" <haund@usa.net>
28 * Testing, hardware cursor fixes
29 *
30 * "Scott Wood" <sawst46+@pitt.edu>
31 * Fixes
32 *
33 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
34 * Betatesting
35 *
36 * "Kelly French" <targon@hazmat.com>
37 * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
38 * Betatesting, bug reporting
39 *
40 * "Pablo Bianucci" <pbian@pccp.com.ar>
41 * Fixes, ideas, betatesting
42 *
43 * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
44 * Fixes, enhandcements, ideas, betatesting
45 *
46 * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
47 * PPC betatesting, PPC support, backward compatibility
48 *
49 * "Paul Womar" <Paul@pwomar.demon.co.uk>
50 * "Owen Waller" <O.Waller@ee.qub.ac.uk>
51 * PPC betatesting
52 *
53 * "Thomas Pornin" <pornin@bolet.ens.fr>
54 * Alpha betatesting
55 *
56 * "Pieter van Leuven" <pvl@iae.nl>
57 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
58 * G100 testing
59 *
60 * "H. Peter Arvin" <hpa@transmeta.com>
61 * Ideas
62 *
63 * "Cort Dougan" <cort@cs.nmt.edu>
64 * CHRP fixes and PReP cleanup
65 *
66 * "Mark Vojkovich" <mvojkovi@ucsd.edu>
67 * G400 support
68 *
69 * "David C. Hansen" <haveblue@us.ibm.com>
70 * Fixes
71 *
72 * "Ian Romanick" <idr@us.ibm.com>
73 * Find PInS data in BIOS on PowerPC systems.
74 *
75 * (following author is not in any relation with this code, but his code
76 * is included in this driver)
77 *
78 * Based on framebuffer driver for VBE 2.0 compliant graphic boards
79 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
80 *
81 * (following author is not in any relation with this code, but his ideas
82 * were used when writing this driver)
83 *
84 * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
85 *
86 */
87
88
89 #include "matroxfb_misc.h"
90 #include <linux/interrupt.h>
91 #include <linux/matroxfb.h>
92
93 void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val)
94 {
95 DBG_REG(__func__)
96 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
97 mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val);
98 }
99
100 int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg)
101 {
102 DBG_REG(__func__)
103 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
104 return mga_inb(M_RAMDAC_BASE+M_X_DATAREG);
105 }
106
107 void matroxfb_var2my(struct fb_var_screeninfo* var, struct my_timming* mt) {
108 unsigned int pixclock = var->pixclock;
109
110 DBG(__func__)
111
112 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
113 mt->pixclock = 1000000000 / pixclock;
114 if (mt->pixclock < 1) mt->pixclock = 1;
115 mt->mnp = -1;
116 mt->dblscan = var->vmode & FB_VMODE_DOUBLE;
117 mt->interlaced = var->vmode & FB_VMODE_INTERLACED;
118 mt->HDisplay = var->xres;
119 mt->HSyncStart = mt->HDisplay + var->right_margin;
120 mt->HSyncEnd = mt->HSyncStart + var->hsync_len;
121 mt->HTotal = mt->HSyncEnd + var->left_margin;
122 mt->VDisplay = var->yres;
123 mt->VSyncStart = mt->VDisplay + var->lower_margin;
124 mt->VSyncEnd = mt->VSyncStart + var->vsync_len;
125 mt->VTotal = mt->VSyncEnd + var->upper_margin;
126 mt->sync = var->sync;
127 }
128
129 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
130 unsigned int* in, unsigned int* feed, unsigned int* post) {
131 unsigned int bestdiff = ~0;
132 unsigned int bestvco = 0;
133 unsigned int fxtal = pll->ref_freq;
134 unsigned int fwant;
135 unsigned int p;
136
137 DBG(__func__)
138
139 fwant = freq;
140
141 #ifdef DEBUG
142 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
143 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
144 printk(KERN_ERR "freq: %d\n", freq);
145 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
146 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
147 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
148 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
149 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
150 printk(KERN_ERR "fmax: %d\n", fmax);
151 #endif
152 for (p = 1; p <= pll->post_shift_max; p++) {
153 if (fwant * 2 > fmax)
154 break;
155 fwant *= 2;
156 }
157 if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min;
158 if (fwant > fmax) fwant = fmax;
159 for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) {
160 unsigned int m;
161
162 if (fwant < pll->vco_freq_min) break;
163 for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
164 unsigned int diff, fvco;
165 unsigned int n;
166
167 n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1;
168 if (n > pll->feed_div_max)
169 break;
170 if (n < pll->feed_div_min)
171 n = pll->feed_div_min;
172 fvco = (fxtal * (n + 1)) / (m + 1);
173 if (fvco < fwant)
174 diff = fwant - fvco;
175 else
176 diff = fvco - fwant;
177 if (diff < bestdiff) {
178 bestdiff = diff;
179 *post = p;
180 *in = m;
181 *feed = n;
182 bestvco = fvco;
183 }
184 }
185 }
186 dprintk(KERN_ERR "clk: %02X %02X %02X %d %d %d\n", *in, *feed, *post, fxtal, bestvco, fwant);
187 return bestvco;
188 }
189
190 int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m)
191 {
192 unsigned int hd, hs, he, hbe, ht;
193 unsigned int vd, vs, ve, vt, lc;
194 unsigned int wd;
195 unsigned int divider;
196 int i;
197 struct matrox_hw_state * const hw = &minfo->hw;
198
199 DBG(__func__)
200
201 hw->SEQ[0] = 0x00;
202 hw->SEQ[1] = 0x01; /* or 0x09 */
203 hw->SEQ[2] = 0x0F; /* bitplanes */
204 hw->SEQ[3] = 0x00;
205 hw->SEQ[4] = 0x0E;
206 /* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */
207 if (m->dblscan) {
208 m->VTotal <<= 1;
209 m->VDisplay <<= 1;
210 m->VSyncStart <<= 1;
211 m->VSyncEnd <<= 1;
212 }
213 if (m->interlaced) {
214 m->VTotal >>= 1;
215 m->VDisplay >>= 1;
216 m->VSyncStart >>= 1;
217 m->VSyncEnd >>= 1;
218 }
219
220 /* GCTL is ignored when not using 0xA0000 aperture */
221 hw->GCTL[0] = 0x00;
222 hw->GCTL[1] = 0x00;
223 hw->GCTL[2] = 0x00;
224 hw->GCTL[3] = 0x00;
225 hw->GCTL[4] = 0x00;
226 hw->GCTL[5] = 0x40;
227 hw->GCTL[6] = 0x05;
228 hw->GCTL[7] = 0x0F;
229 hw->GCTL[8] = 0xFF;
230
231 /* Whole ATTR is ignored in PowerGraphics mode */
232 for (i = 0; i < 16; i++)
233 hw->ATTR[i] = i;
234 hw->ATTR[16] = 0x41;
235 hw->ATTR[17] = 0xFF;
236 hw->ATTR[18] = 0x0F;
237 hw->ATTR[19] = 0x00;
238 hw->ATTR[20] = 0x00;
239
240 hd = m->HDisplay >> 3;
241 hs = m->HSyncStart >> 3;
242 he = m->HSyncEnd >> 3;
243 ht = m->HTotal >> 3;
244 /* standard timmings are in 8pixels, but for interleaved we cannot */
245 /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
246 /* using 16 or more pixels per unit can save us */
247 divider = minfo->curr.final_bppShift;
248 while (divider & 3) {
249 hd >>= 1;
250 hs >>= 1;
251 he >>= 1;
252 ht >>= 1;
253 divider <<= 1;
254 }
255 divider = divider / 4;
256 /* divider can be from 1 to 8 */
257 while (divider > 8) {
258 hd <<= 1;
259 hs <<= 1;
260 he <<= 1;
261 ht <<= 1;
262 divider >>= 1;
263 }
264 hd = hd - 1;
265 hs = hs - 1;
266 he = he - 1;
267 ht = ht - 1;
268 vd = m->VDisplay - 1;
269 vs = m->VSyncStart - 1;
270 ve = m->VSyncEnd - 1;
271 vt = m->VTotal - 2;
272 lc = vd;
273 /* G200 cannot work with (ht & 7) == 6 */
274 if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
275 ht++;
276 hbe = ht;
277 wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64;
278
279 hw->CRTCEXT[0] = 0;
280 hw->CRTCEXT[5] = 0;
281 if (m->interlaced) {
282 hw->CRTCEXT[0] = 0x80;
283 hw->CRTCEXT[5] = (hs + he - ht) >> 1;
284 if (!m->dblscan)
285 wd <<= 1;
286 vt &= ~1;
287 }
288 hw->CRTCEXT[0] |= (wd & 0x300) >> 4;
289 hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) |
290 ((hd & 0x100) >> 7) | /* blanking */
291 ((hs & 0x100) >> 6) | /* sync start */
292 (hbe & 0x040); /* end hor. blanking */
293 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */
294 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1)
295 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
296 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
297 ((vd & 0x400) >> 8) | /* disp end */
298 ((vd & 0xC00) >> 7) | /* vblanking start */
299 ((vs & 0xC00) >> 5) |
300 ((lc & 0x400) >> 3);
301 hw->CRTCEXT[3] = (divider - 1) | 0x80;
302 hw->CRTCEXT[4] = 0;
303
304 hw->CRTC[0] = ht-4;
305 hw->CRTC[1] = hd;
306 hw->CRTC[2] = hd;
307 hw->CRTC[3] = (hbe & 0x1F) | 0x80;
308 hw->CRTC[4] = hs;
309 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F);
310 hw->CRTC[6] = vt & 0xFF;
311 hw->CRTC[7] = ((vt & 0x100) >> 8) |
312 ((vd & 0x100) >> 7) |
313 ((vs & 0x100) >> 6) |
314 ((vd & 0x100) >> 5) |
315 ((lc & 0x100) >> 4) |
316 ((vt & 0x200) >> 4) |
317 ((vd & 0x200) >> 3) |
318 ((vs & 0x200) >> 2);
319 hw->CRTC[8] = 0x00;
320 hw->CRTC[9] = ((vd & 0x200) >> 4) |
321 ((lc & 0x200) >> 3);
322 if (m->dblscan && !m->interlaced)
323 hw->CRTC[9] |= 0x80;
324 for (i = 10; i < 16; i++)
325 hw->CRTC[i] = 0x00;
326 hw->CRTC[16] = vs /* & 0xFF */;
327 hw->CRTC[17] = (ve & 0x0F) | 0x20;
328 hw->CRTC[18] = vd /* & 0xFF */;
329 hw->CRTC[19] = wd /* & 0xFF */;
330 hw->CRTC[20] = 0x00;
331 hw->CRTC[21] = vd /* & 0xFF */;
332 hw->CRTC[22] = (vt + 1) /* & 0xFF */;
333 hw->CRTC[23] = 0xC3;
334 hw->CRTC[24] = lc;
335 return 0;
336 };
337
338 void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo)
339 {
340 int i;
341 struct matrox_hw_state * const hw = &minfo->hw;
342 CRITFLAGS
343
344 DBG(__func__)
345
346 dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg);
347 dprintk(KERN_INFO "SEQ regs: ");
348 for (i = 0; i < 5; i++)
349 dprintk("%02X:", hw->SEQ[i]);
350 dprintk("\n");
351 dprintk(KERN_INFO "GDC regs: ");
352 for (i = 0; i < 9; i++)
353 dprintk("%02X:", hw->GCTL[i]);
354 dprintk("\n");
355 dprintk(KERN_INFO "CRTC regs: ");
356 for (i = 0; i < 25; i++)
357 dprintk("%02X:", hw->CRTC[i]);
358 dprintk("\n");
359 dprintk(KERN_INFO "ATTR regs: ");
360 for (i = 0; i < 21; i++)
361 dprintk("%02X:", hw->ATTR[i]);
362 dprintk("\n");
363
364 CRITBEGIN
365
366 mga_inb(M_ATTR_RESET);
367 mga_outb(M_ATTR_INDEX, 0);
368 mga_outb(M_MISC_REG, hw->MiscOutReg);
369 for (i = 1; i < 5; i++)
370 mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]);
371 mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F);
372 for (i = 0; i < 25; i++)
373 mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]);
374 for (i = 0; i < 9; i++)
375 mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]);
376 for (i = 0; i < 21; i++) {
377 mga_inb(M_ATTR_RESET);
378 mga_outb(M_ATTR_INDEX, i);
379 mga_outb(M_ATTR_INDEX, hw->ATTR[i]);
380 }
381 mga_outb(M_PALETTE_MASK, 0xFF);
382 mga_outb(M_DAC_REG, 0x00);
383 for (i = 0; i < 768; i++)
384 mga_outb(M_DAC_VAL, hw->DACpal[i]);
385 mga_inb(M_ATTR_RESET);
386 mga_outb(M_ATTR_INDEX, 0x20);
387
388 CRITEND
389 }
390
391 static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) {
392 unsigned int b0 = readb(pins);
393
394 if (b0 == 0x2E && readb(pins+1) == 0x41) {
395 unsigned int pins_len = readb(pins+2);
396 unsigned int i;
397 unsigned char cksum;
398 unsigned char* dst = bd->pins;
399
400 if (pins_len < 3 || pins_len > 128) {
401 return;
402 }
403 *dst++ = 0x2E;
404 *dst++ = 0x41;
405 *dst++ = pins_len;
406 cksum = 0x2E + 0x41 + pins_len;
407 for (i = 3; i < pins_len; i++) {
408 cksum += *dst++ = readb(pins+i);
409 }
410 if (cksum) {
411 return;
412 }
413 bd->pins_len = pins_len;
414 } else if (b0 == 0x40 && readb(pins+1) == 0x00) {
415 unsigned int i;
416 unsigned char* dst = bd->pins;
417
418 *dst++ = 0x40;
419 *dst++ = 0;
420 for (i = 2; i < 0x40; i++) {
421 *dst++ = readb(pins+i);
422 }
423 bd->pins_len = 0x40;
424 }
425 }
426
427 static void get_bios_version(unsigned char __iomem * vbios, struct matrox_bios* bd) {
428 unsigned int pcir_offset;
429
430 pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8);
431 if (pcir_offset >= 26 && pcir_offset < 0xFFE0 &&
432 readb(vbios + pcir_offset ) == 'P' &&
433 readb(vbios + pcir_offset + 1) == 'C' &&
434 readb(vbios + pcir_offset + 2) == 'I' &&
435 readb(vbios + pcir_offset + 3) == 'R') {
436 unsigned char h;
437
438 h = readb(vbios + pcir_offset + 0x12);
439 bd->version.vMaj = (h >> 4) & 0xF;
440 bd->version.vMin = h & 0xF;
441 bd->version.vRev = readb(vbios + pcir_offset + 0x13);
442 } else {
443 unsigned char h;
444
445 h = readb(vbios + 5);
446 bd->version.vMaj = (h >> 4) & 0xF;
447 bd->version.vMin = h & 0xF;
448 bd->version.vRev = 0;
449 }
450 }
451
452 static void get_bios_output(unsigned char __iomem* vbios, struct matrox_bios* bd) {
453 unsigned char b;
454
455 b = readb(vbios + 0x7FF1);
456 if (b == 0xFF) {
457 b = 0;
458 }
459 bd->output.state = b;
460 }
461
462 static void get_bios_tvout(unsigned char __iomem* vbios, struct matrox_bios* bd) {
463 unsigned int i;
464
465 /* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */
466 bd->output.tvout = 0;
467 if (readb(vbios + 0x1D) != 'I' ||
468 readb(vbios + 0x1E) != 'B' ||
469 readb(vbios + 0x1F) != 'M' ||
470 readb(vbios + 0x20) != ' ') {
471 return;
472 }
473 for (i = 0x2D; i < 0x2D + 128; i++) {
474 unsigned char b = readb(vbios + i);
475
476 if (b == '(' && readb(vbios + i + 1) == 'V') {
477 if (readb(vbios + i + 6) == 'T' &&
478 readb(vbios + i + 7) == 'V' &&
479 readb(vbios + i + 8) == 'O') {
480 bd->output.tvout = 1;
481 }
482 return;
483 }
484 if (b == 0)
485 break;
486 }
487 }
488
489 static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) {
490 unsigned int pins_offset;
491
492 if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) {
493 return;
494 }
495 bd->bios_valid = 1;
496 get_bios_version(vbios, bd);
497 get_bios_output(vbios, bd);
498 get_bios_tvout(vbios, bd);
499 #if defined(__powerpc__)
500 /* On PowerPC cards, the PInS offset isn't stored at the end of the
501 * BIOS image. Instead, you must search the entire BIOS image for
502 * the magic PInS signature.
503 *
504 * This actually applies to all OpenFirmware base cards. Since these
505 * cards could be put in a MIPS or SPARC system, should the condition
506 * be something different?
507 */
508 for ( pins_offset = 0 ; pins_offset <= 0xFF80 ; pins_offset++ ) {
509 unsigned char header[3];
510
511 header[0] = readb(vbios + pins_offset);
512 header[1] = readb(vbios + pins_offset + 1);
513 header[2] = readb(vbios + pins_offset + 2);
514 if ( (header[0] == 0x2E) && (header[1] == 0x41)
515 && ((header[2] == 0x40) || (header[2] == 0x80)) ) {
516 printk(KERN_INFO "PInS data found at offset %u\n",
517 pins_offset);
518 get_pins(vbios + pins_offset, bd);
519 break;
520 }
521 }
522 #else
523 pins_offset = readb(vbios + 0x7FFC) | (readb(vbios + 0x7FFD) << 8);
524 if (pins_offset <= 0xFF80) {
525 get_pins(vbios + pins_offset, bd);
526 }
527 #endif
528 }
529
530 static int parse_pins1(struct matrox_fb_info *minfo,
531 const struct matrox_bios *bd)
532 {
533 unsigned int maxdac;
534
535 switch (bd->pins[22]) {
536 case 0: maxdac = 175000; break;
537 case 1: maxdac = 220000; break;
538 default: maxdac = 240000; break;
539 }
540 if (get_unaligned_le16(bd->pins + 24)) {
541 maxdac = get_unaligned_le16(bd->pins + 24) * 10;
542 }
543 minfo->limits.pixel.vcomax = maxdac;
544 minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ?
545 get_unaligned_le16(bd->pins + 28) * 10 : 50000;
546 /* ignore 4MB, 8MB, module clocks */
547 minfo->features.pll.ref_freq = 14318;
548 minfo->values.reg.mctlwtst = 0x00030101;
549 return 0;
550 }
551
552 static void default_pins1(struct matrox_fb_info *minfo)
553 {
554 /* Millennium */
555 minfo->limits.pixel.vcomax = 220000;
556 minfo->values.pll.system = 50000;
557 minfo->features.pll.ref_freq = 14318;
558 minfo->values.reg.mctlwtst = 0x00030101;
559 }
560
561 static int parse_pins2(struct matrox_fb_info *minfo,
562 const struct matrox_bios *bd)
563 {
564 minfo->limits.pixel.vcomax =
565 minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
566 minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
567 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
568 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
569 ((bd->pins[51] & 0x08) ? 0x00020000 : 0);
570 minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
571 minfo->features.pll.ref_freq = 14318;
572 return 0;
573 }
574
575 static void default_pins2(struct matrox_fb_info *minfo)
576 {
577 /* Millennium II, Mystique */
578 minfo->limits.pixel.vcomax =
579 minfo->limits.system.vcomax = 230000;
580 minfo->values.reg.mctlwtst = 0x00030101;
581 minfo->values.pll.system = 50000;
582 minfo->features.pll.ref_freq = 14318;
583 }
584
585 static int parse_pins3(struct matrox_fb_info *minfo,
586 const struct matrox_bios *bd)
587 {
588 minfo->limits.pixel.vcomax =
589 minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
590 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ?
591 0x01250A21 : get_unaligned_le32(bd->pins + 48);
592 /* memory config */
593 minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
594 ((bd->pins[57] << 22) & 0x00C00000) |
595 ((bd->pins[56] << 1) & 0x000001E0) |
596 ( bd->pins[56] & 0x0000000F);
597 minfo->values.reg.opt = (bd->pins[54] & 7) << 10;
598 minfo->values.reg.opt2 = bd->pins[58] << 12;
599 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
600 return 0;
601 }
602
603 static void default_pins3(struct matrox_fb_info *minfo)
604 {
605 /* G100, G200 */
606 minfo->limits.pixel.vcomax =
607 minfo->limits.system.vcomax = 230000;
608 minfo->values.reg.mctlwtst = 0x01250A21;
609 minfo->values.reg.memrdbk = 0x00000000;
610 minfo->values.reg.opt = 0x00000C00;
611 minfo->values.reg.opt2 = 0x00000000;
612 minfo->features.pll.ref_freq = 27000;
613 }
614
615 static int parse_pins4(struct matrox_fb_info *minfo,
616 const struct matrox_bios *bd)
617 {
618 minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
619 minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38] * 4000;
620 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71);
621 minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
622 ((bd->pins[87] << 22) & 0x00C00000) |
623 ((bd->pins[86] << 1) & 0x000001E0) |
624 ( bd->pins[86] & 0x0000000F);
625 minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
626 ((bd->pins[53] << 22) & 0x10000000) |
627 ((bd->pins[53] << 7) & 0x00001C00);
628 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67);
629 minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
630 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
631 return 0;
632 }
633
634 static void default_pins4(struct matrox_fb_info *minfo)
635 {
636 /* G400 */
637 minfo->limits.pixel.vcomax =
638 minfo->limits.system.vcomax = 252000;
639 minfo->values.reg.mctlwtst = 0x04A450A1;
640 minfo->values.reg.memrdbk = 0x000000E7;
641 minfo->values.reg.opt = 0x10000400;
642 minfo->values.reg.opt3 = 0x0190A419;
643 minfo->values.pll.system = 200000;
644 minfo->features.pll.ref_freq = 27000;
645 }
646
647 static int parse_pins5(struct matrox_fb_info *minfo,
648 const struct matrox_bios *bd)
649 {
650 unsigned int mult;
651
652 mult = bd->pins[4]?8000:6000;
653
654 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
655 minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36] * mult;
656 minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37] * mult;
657 minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
658 minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121] * mult;
659 minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122] * mult;
660 minfo->values.pll.system =
661 minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
662 minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48);
663 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52);
664 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94);
665 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98);
666 minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102);
667 minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106);
668 minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
669 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
670 minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0;
671 minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
672 minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000;
673 if (bd->pins[115] & 4) {
674 minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst;
675 } else {
676 static const u8 wtst_xlat[] = {
677 0, 1, 5, 6, 7, 5, 2, 3
678 };
679
680 minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) |
681 wtst_xlat[minfo->values.reg.mctlwtst & 7];
682 }
683 minfo->max_pixel_clock_panellink = bd->pins[47] * 4000;
684 return 0;
685 }
686
687 static void default_pins5(struct matrox_fb_info *minfo)
688 {
689 /* Mine 16MB G450 with SDRAM DDR */
690 minfo->limits.pixel.vcomax =
691 minfo->limits.system.vcomax =
692 minfo->limits.video.vcomax = 600000;
693 minfo->limits.pixel.vcomin =
694 minfo->limits.system.vcomin =
695 minfo->limits.video.vcomin = 256000;
696 minfo->values.pll.system =
697 minfo->values.pll.video = 284000;
698 minfo->values.reg.opt = 0x404A1160;
699 minfo->values.reg.opt2 = 0x0000AC00;
700 minfo->values.reg.opt3 = 0x0090A409;
701 minfo->values.reg.mctlwtst_core =
702 minfo->values.reg.mctlwtst = 0x0C81462B;
703 minfo->values.reg.memmisc = 0x80000004;
704 minfo->values.reg.memrdbk = 0x01001103;
705 minfo->features.pll.ref_freq = 27000;
706 minfo->values.memory.ddr = 1;
707 minfo->values.memory.dll = 1;
708 minfo->values.memory.emrswen = 1;
709 minfo->values.reg.maccess = 0x00004000;
710 }
711
712 static int matroxfb_set_limits(struct matrox_fb_info *minfo,
713 const struct matrox_bios *bd)
714 {
715 unsigned int pins_version;
716 static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
717
718 switch (minfo->chip) {
719 case MGA_2064: default_pins1(minfo); break;
720 case MGA_2164:
721 case MGA_1064:
722 case MGA_1164: default_pins2(minfo); break;
723 case MGA_G100:
724 case MGA_G200: default_pins3(minfo); break;
725 case MGA_G400: default_pins4(minfo); break;
726 case MGA_G450:
727 case MGA_G550: default_pins5(minfo); break;
728 }
729 if (!bd->bios_valid) {
730 printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n");
731 return -1;
732 }
733 if (bd->pins_len < 64) {
734 printk(KERN_INFO "matroxfb: BIOS on your Matrox device does not contain powerup info\n");
735 return -1;
736 }
737 if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) {
738 pins_version = bd->pins[5];
739 if (pins_version < 2 || pins_version > 5) {
740 printk(KERN_INFO "matroxfb: Unknown version (%u) of powerup info\n", pins_version);
741 return -1;
742 }
743 } else {
744 pins_version = 1;
745 }
746 if (bd->pins_len != pinslen[pins_version - 1]) {
747 printk(KERN_INFO "matroxfb: Invalid powerup info\n");
748 return -1;
749 }
750 switch (pins_version) {
751 case 1:
752 return parse_pins1(minfo, bd);
753 case 2:
754 return parse_pins2(minfo, bd);
755 case 3:
756 return parse_pins3(minfo, bd);
757 case 4:
758 return parse_pins4(minfo, bd);
759 case 5:
760 return parse_pins5(minfo, bd);
761 default:
762 printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version);
763 return -1;
764 }
765 }
766
767 void matroxfb_read_pins(struct matrox_fb_info *minfo)
768 {
769 u32 opt;
770 u32 biosbase;
771 u32 fbbase;
772 struct pci_dev *pdev = minfo->pcidev;
773
774 memset(&minfo->bios, 0, sizeof(minfo->bios));
775 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
776 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
777 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
778 pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase);
779 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
780 parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios);
781 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
782 pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
783 #ifdef CONFIG_X86
784 if (!minfo->bios.bios_valid) {
785 unsigned char __iomem* b;
786
787 b = ioremap(0x000C0000, 65536);
788 if (!b) {
789 printk(KERN_INFO "matroxfb: Unable to map legacy BIOS\n");
790 } else {
791 unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8);
792 unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8);
793
794 if (ven != pdev->vendor || dev != pdev->device) {
795 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
796 ven, dev, pdev->vendor, pdev->device);
797 } else {
798 parse_bios(b, &minfo->bios);
799 }
800 iounmap(b);
801 }
802 }
803 #endif
804 matroxfb_set_limits(minfo, &minfo->bios);
805 printk(KERN_INFO "PInS memtype = %u\n",
806 (minfo->values.reg.opt & 0x1C00) >> 10);
807 }
808
809 EXPORT_SYMBOL(matroxfb_DAC_in);
810 EXPORT_SYMBOL(matroxfb_DAC_out);
811 EXPORT_SYMBOL(matroxfb_var2my);
812 EXPORT_SYMBOL(matroxfb_PLL_calcclock);
813 EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */
814 EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */
815 EXPORT_SYMBOL(matroxfb_read_pins);
816
817 MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
818 MODULE_DESCRIPTION("Miscellaneous support for Matrox video cards");
819 MODULE_LICENSE("GPL");
Kernel DRM miscellaneous fixes and cross-tree changes