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drm/rockchip: Don't change hdmi reference clock rate
[drm/drm-misc.git] / drivers / video / fbdev / omap2 / omapfb / dss / dispc.c
blobc3329c8b4c169b09e77fd5c5077fabdc619a137a
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * linux/drivers/video/omap2/dss/dispc.c
4 *
5 * Copyright (C) 2009 Nokia Corporation
6 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 *
8 * Some code and ideas taken from drivers/video/omap/ driver
9 * by Imre Deak.
10 */
11
12 #define DSS_SUBSYS_NAME "DISPC"
13
14 #include <linux/kernel.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/vmalloc.h>
17 #include <linux/export.h>
18 #include <linux/clk.h>
19 #include <linux/io.h>
20 #include <linux/jiffies.h>
21 #include <linux/seq_file.h>
22 #include <linux/delay.h>
23 #include <linux/workqueue.h>
24 #include <linux/hardirq.h>
25 #include <linux/platform_device.h>
26 #include <linux/pm_runtime.h>
27 #include <linux/sizes.h>
28 #include <linux/mfd/syscon.h>
29 #include <linux/regmap.h>
30 #include <linux/of.h>
31 #include <linux/component.h>
32
33 #include <video/omapfb_dss.h>
34
35 #include "dss.h"
36 #include "dss_features.h"
37 #include "dispc.h"
38
39 /* DISPC */
40 #define DISPC_SZ_REGS SZ_4K
41
42 enum omap_burst_size {
43 BURST_SIZE_X2 = 0,
44 BURST_SIZE_X4 = 1,
45 BURST_SIZE_X8 = 2,
46 };
47
48 #define REG_GET(idx, start, end) \
49 FLD_GET(dispc_read_reg(idx), start, end)
50
51 #define REG_FLD_MOD(idx, val, start, end) \
52 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
53
54 struct dispc_features {
55 u8 sw_start;
56 u8 fp_start;
57 u8 bp_start;
58 u16 sw_max;
59 u16 vp_max;
60 u16 hp_max;
61 u8 mgr_width_start;
62 u8 mgr_height_start;
63 u16 mgr_width_max;
64 u16 mgr_height_max;
65 unsigned long max_lcd_pclk;
66 unsigned long max_tv_pclk;
67 int (*calc_scaling) (unsigned long pclk, unsigned long lclk,
68 const struct omap_video_timings *mgr_timings,
69 u16 width, u16 height, u16 out_width, u16 out_height,
70 enum omap_color_mode color_mode, bool *five_taps,
71 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
72 u16 pos_x, unsigned long *core_clk, bool mem_to_mem);
73 unsigned long (*calc_core_clk) (unsigned long pclk,
74 u16 width, u16 height, u16 out_width, u16 out_height,
75 bool mem_to_mem);
76 u8 num_fifos;
77
78 /* swap GFX & WB fifos */
79 bool gfx_fifo_workaround:1;
80
81 /* no DISPC_IRQ_FRAMEDONETV on this SoC */
82 bool no_framedone_tv:1;
83
84 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
85 bool mstandby_workaround:1;
86
87 bool set_max_preload:1;
88
89 /* PIXEL_INC is not added to the last pixel of a line */
90 bool last_pixel_inc_missing:1;
91
92 /* POL_FREQ has ALIGN bit */
93 bool supports_sync_align:1;
94
95 bool has_writeback:1;
96 };
97
98 #define DISPC_MAX_NR_FIFOS 5
99
100 static struct {
101 struct platform_device *pdev;
102 void __iomem *base;
103
104 int irq;
105 irq_handler_t user_handler;
106 void *user_data;
107
108 unsigned long core_clk_rate;
109 unsigned long tv_pclk_rate;
110
111 u32 fifo_size[DISPC_MAX_NR_FIFOS];
112 /* maps which plane is using a fifo. fifo-id -> plane-id */
113 int fifo_assignment[DISPC_MAX_NR_FIFOS];
114
115 bool ctx_valid;
116 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
117
118 const struct dispc_features *feat;
119
120 bool is_enabled;
121
122 struct regmap *syscon_pol;
123 u32 syscon_pol_offset;
124
125 /* DISPC_CONTROL & DISPC_CONFIG lock*/
126 spinlock_t control_lock;
127 } dispc;
128
129 enum omap_color_component {
130 /* used for all color formats for OMAP3 and earlier
131 * and for RGB and Y color component on OMAP4
132 */
133 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
134 /* used for UV component for
135 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
136 * color formats on OMAP4
137 */
138 DISPC_COLOR_COMPONENT_UV = 1 << 1,
139 };
140
141 enum mgr_reg_fields {
142 DISPC_MGR_FLD_ENABLE,
143 DISPC_MGR_FLD_STNTFT,
144 DISPC_MGR_FLD_GO,
145 DISPC_MGR_FLD_TFTDATALINES,
146 DISPC_MGR_FLD_STALLMODE,
147 DISPC_MGR_FLD_TCKENABLE,
148 DISPC_MGR_FLD_TCKSELECTION,
149 DISPC_MGR_FLD_CPR,
150 DISPC_MGR_FLD_FIFOHANDCHECK,
151 /* used to maintain a count of the above fields */
152 DISPC_MGR_FLD_NUM,
153 };
154
155 struct dispc_reg_field {
156 u16 reg;
157 u8 high;
158 u8 low;
159 };
160
161 static const struct {
162 const char *name;
163 u32 vsync_irq;
164 u32 framedone_irq;
165 u32 sync_lost_irq;
166 struct dispc_reg_field reg_desc[DISPC_MGR_FLD_NUM];
167 } mgr_desc[] = {
168 [OMAP_DSS_CHANNEL_LCD] = {
169 .name = "LCD",
170 .vsync_irq = DISPC_IRQ_VSYNC,
171 .framedone_irq = DISPC_IRQ_FRAMEDONE,
172 .sync_lost_irq = DISPC_IRQ_SYNC_LOST,
173 .reg_desc = {
174 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 0, 0 },
175 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL, 3, 3 },
176 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 5, 5 },
177 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL, 9, 8 },
178 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL, 11, 11 },
179 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 10, 10 },
180 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 11, 11 },
181 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG, 15, 15 },
182 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
183 },
184 },
185 [OMAP_DSS_CHANNEL_DIGIT] = {
186 .name = "DIGIT",
187 .vsync_irq = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
188 .framedone_irq = DISPC_IRQ_FRAMEDONETV,
189 .sync_lost_irq = DISPC_IRQ_SYNC_LOST_DIGIT,
190 .reg_desc = {
191 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL, 1, 1 },
192 [DISPC_MGR_FLD_STNTFT] = { },
193 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL, 6, 6 },
194 [DISPC_MGR_FLD_TFTDATALINES] = { },
195 [DISPC_MGR_FLD_STALLMODE] = { },
196 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG, 12, 12 },
197 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG, 13, 13 },
198 [DISPC_MGR_FLD_CPR] = { },
199 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG, 16, 16 },
200 },
201 },
202 [OMAP_DSS_CHANNEL_LCD2] = {
203 .name = "LCD2",
204 .vsync_irq = DISPC_IRQ_VSYNC2,
205 .framedone_irq = DISPC_IRQ_FRAMEDONE2,
206 .sync_lost_irq = DISPC_IRQ_SYNC_LOST2,
207 .reg_desc = {
208 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL2, 0, 0 },
209 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL2, 3, 3 },
210 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL2, 5, 5 },
211 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL2, 9, 8 },
212 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL2, 11, 11 },
213 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG2, 10, 10 },
214 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG2, 11, 11 },
215 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG2, 15, 15 },
216 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG2, 16, 16 },
217 },
218 },
219 [OMAP_DSS_CHANNEL_LCD3] = {
220 .name = "LCD3",
221 .vsync_irq = DISPC_IRQ_VSYNC3,
222 .framedone_irq = DISPC_IRQ_FRAMEDONE3,
223 .sync_lost_irq = DISPC_IRQ_SYNC_LOST3,
224 .reg_desc = {
225 [DISPC_MGR_FLD_ENABLE] = { DISPC_CONTROL3, 0, 0 },
226 [DISPC_MGR_FLD_STNTFT] = { DISPC_CONTROL3, 3, 3 },
227 [DISPC_MGR_FLD_GO] = { DISPC_CONTROL3, 5, 5 },
228 [DISPC_MGR_FLD_TFTDATALINES] = { DISPC_CONTROL3, 9, 8 },
229 [DISPC_MGR_FLD_STALLMODE] = { DISPC_CONTROL3, 11, 11 },
230 [DISPC_MGR_FLD_TCKENABLE] = { DISPC_CONFIG3, 10, 10 },
231 [DISPC_MGR_FLD_TCKSELECTION] = { DISPC_CONFIG3, 11, 11 },
232 [DISPC_MGR_FLD_CPR] = { DISPC_CONFIG3, 15, 15 },
233 [DISPC_MGR_FLD_FIFOHANDCHECK] = { DISPC_CONFIG3, 16, 16 },
234 },
235 },
236 };
237
238 struct color_conv_coef {
239 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
240 int full_range;
241 };
242
243 static unsigned long dispc_fclk_rate(void);
244 static unsigned long dispc_core_clk_rate(void);
245 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
246 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
247
248 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane);
249 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane);
250
251 static inline void dispc_write_reg(const u16 idx, u32 val)
252 {
253 __raw_writel(val, dispc.base + idx);
254 }
255
256 static inline u32 dispc_read_reg(const u16 idx)
257 {
258 return __raw_readl(dispc.base + idx);
259 }
260
261 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
262 {
263 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
264 return REG_GET(rfld.reg, rfld.high, rfld.low);
265 }
266
267 static void mgr_fld_write(enum omap_channel channel,
268 enum mgr_reg_fields regfld, int val) {
269 const struct dispc_reg_field rfld = mgr_desc[channel].reg_desc[regfld];
270 const bool need_lock = rfld.reg == DISPC_CONTROL || rfld.reg == DISPC_CONFIG;
271 unsigned long flags;
272
273 if (need_lock)
274 spin_lock_irqsave(&dispc.control_lock, flags);
275
276 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
277
278 if (need_lock)
279 spin_unlock_irqrestore(&dispc.control_lock, flags);
280 }
281
282 #define SR(reg) \
283 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
284 #define RR(reg) \
285 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
286
287 static void dispc_save_context(void)
288 {
289 int i, j;
290
291 DSSDBG("dispc_save_context\n");
292
293 SR(IRQENABLE);
294 SR(CONTROL);
295 SR(CONFIG);
296 SR(LINE_NUMBER);
297 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
298 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
299 SR(GLOBAL_ALPHA);
300 if (dss_has_feature(FEAT_MGR_LCD2)) {
301 SR(CONTROL2);
302 SR(CONFIG2);
303 }
304 if (dss_has_feature(FEAT_MGR_LCD3)) {
305 SR(CONTROL3);
306 SR(CONFIG3);
307 }
308
309 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
310 SR(DEFAULT_COLOR(i));
311 SR(TRANS_COLOR(i));
312 SR(SIZE_MGR(i));
313 if (i == OMAP_DSS_CHANNEL_DIGIT)
314 continue;
315 SR(TIMING_H(i));
316 SR(TIMING_V(i));
317 SR(POL_FREQ(i));
318 SR(DIVISORo(i));
319
320 SR(DATA_CYCLE1(i));
321 SR(DATA_CYCLE2(i));
322 SR(DATA_CYCLE3(i));
323
324 if (dss_has_feature(FEAT_CPR)) {
325 SR(CPR_COEF_R(i));
326 SR(CPR_COEF_G(i));
327 SR(CPR_COEF_B(i));
328 }
329 }
330
331 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
332 SR(OVL_BA0(i));
333 SR(OVL_BA1(i));
334 SR(OVL_POSITION(i));
335 SR(OVL_SIZE(i));
336 SR(OVL_ATTRIBUTES(i));
337 SR(OVL_FIFO_THRESHOLD(i));
338 SR(OVL_ROW_INC(i));
339 SR(OVL_PIXEL_INC(i));
340 if (dss_has_feature(FEAT_PRELOAD))
341 SR(OVL_PRELOAD(i));
342 if (i == OMAP_DSS_GFX) {
343 SR(OVL_WINDOW_SKIP(i));
344 SR(OVL_TABLE_BA(i));
345 continue;
346 }
347 SR(OVL_FIR(i));
348 SR(OVL_PICTURE_SIZE(i));
349 SR(OVL_ACCU0(i));
350 SR(OVL_ACCU1(i));
351
352 for (j = 0; j < 8; j++)
353 SR(OVL_FIR_COEF_H(i, j));
354
355 for (j = 0; j < 8; j++)
356 SR(OVL_FIR_COEF_HV(i, j));
357
358 for (j = 0; j < 5; j++)
359 SR(OVL_CONV_COEF(i, j));
360
361 if (dss_has_feature(FEAT_FIR_COEF_V)) {
362 for (j = 0; j < 8; j++)
363 SR(OVL_FIR_COEF_V(i, j));
364 }
365
366 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
367 SR(OVL_BA0_UV(i));
368 SR(OVL_BA1_UV(i));
369 SR(OVL_FIR2(i));
370 SR(OVL_ACCU2_0(i));
371 SR(OVL_ACCU2_1(i));
372
373 for (j = 0; j < 8; j++)
374 SR(OVL_FIR_COEF_H2(i, j));
375
376 for (j = 0; j < 8; j++)
377 SR(OVL_FIR_COEF_HV2(i, j));
378
379 for (j = 0; j < 8; j++)
380 SR(OVL_FIR_COEF_V2(i, j));
381 }
382 if (dss_has_feature(FEAT_ATTR2))
383 SR(OVL_ATTRIBUTES2(i));
384 }
385
386 if (dss_has_feature(FEAT_CORE_CLK_DIV))
387 SR(DIVISOR);
388
389 dispc.ctx_valid = true;
390
391 DSSDBG("context saved\n");
392 }
393
394 static void dispc_restore_context(void)
395 {
396 int i, j;
397
398 DSSDBG("dispc_restore_context\n");
399
400 if (!dispc.ctx_valid)
401 return;
402
403 /*RR(IRQENABLE);*/
404 /*RR(CONTROL);*/
405 RR(CONFIG);
406 RR(LINE_NUMBER);
407 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
408 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
409 RR(GLOBAL_ALPHA);
410 if (dss_has_feature(FEAT_MGR_LCD2))
411 RR(CONFIG2);
412 if (dss_has_feature(FEAT_MGR_LCD3))
413 RR(CONFIG3);
414
415 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
416 RR(DEFAULT_COLOR(i));
417 RR(TRANS_COLOR(i));
418 RR(SIZE_MGR(i));
419 if (i == OMAP_DSS_CHANNEL_DIGIT)
420 continue;
421 RR(TIMING_H(i));
422 RR(TIMING_V(i));
423 RR(POL_FREQ(i));
424 RR(DIVISORo(i));
425
426 RR(DATA_CYCLE1(i));
427 RR(DATA_CYCLE2(i));
428 RR(DATA_CYCLE3(i));
429
430 if (dss_has_feature(FEAT_CPR)) {
431 RR(CPR_COEF_R(i));
432 RR(CPR_COEF_G(i));
433 RR(CPR_COEF_B(i));
434 }
435 }
436
437 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
438 RR(OVL_BA0(i));
439 RR(OVL_BA1(i));
440 RR(OVL_POSITION(i));
441 RR(OVL_SIZE(i));
442 RR(OVL_ATTRIBUTES(i));
443 RR(OVL_FIFO_THRESHOLD(i));
444 RR(OVL_ROW_INC(i));
445 RR(OVL_PIXEL_INC(i));
446 if (dss_has_feature(FEAT_PRELOAD))
447 RR(OVL_PRELOAD(i));
448 if (i == OMAP_DSS_GFX) {
449 RR(OVL_WINDOW_SKIP(i));
450 RR(OVL_TABLE_BA(i));
451 continue;
452 }
453 RR(OVL_FIR(i));
454 RR(OVL_PICTURE_SIZE(i));
455 RR(OVL_ACCU0(i));
456 RR(OVL_ACCU1(i));
457
458 for (j = 0; j < 8; j++)
459 RR(OVL_FIR_COEF_H(i, j));
460
461 for (j = 0; j < 8; j++)
462 RR(OVL_FIR_COEF_HV(i, j));
463
464 for (j = 0; j < 5; j++)
465 RR(OVL_CONV_COEF(i, j));
466
467 if (dss_has_feature(FEAT_FIR_COEF_V)) {
468 for (j = 0; j < 8; j++)
469 RR(OVL_FIR_COEF_V(i, j));
470 }
471
472 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
473 RR(OVL_BA0_UV(i));
474 RR(OVL_BA1_UV(i));
475 RR(OVL_FIR2(i));
476 RR(OVL_ACCU2_0(i));
477 RR(OVL_ACCU2_1(i));
478
479 for (j = 0; j < 8; j++)
480 RR(OVL_FIR_COEF_H2(i, j));
481
482 for (j = 0; j < 8; j++)
483 RR(OVL_FIR_COEF_HV2(i, j));
484
485 for (j = 0; j < 8; j++)
486 RR(OVL_FIR_COEF_V2(i, j));
487 }
488 if (dss_has_feature(FEAT_ATTR2))
489 RR(OVL_ATTRIBUTES2(i));
490 }
491
492 if (dss_has_feature(FEAT_CORE_CLK_DIV))
493 RR(DIVISOR);
494
495 /* enable last, because LCD & DIGIT enable are here */
496 RR(CONTROL);
497 if (dss_has_feature(FEAT_MGR_LCD2))
498 RR(CONTROL2);
499 if (dss_has_feature(FEAT_MGR_LCD3))
500 RR(CONTROL3);
501 /* clear spurious SYNC_LOST_DIGIT interrupts */
502 dispc_clear_irqstatus(DISPC_IRQ_SYNC_LOST_DIGIT);
503
504 /*
505 * enable last so IRQs won't trigger before
506 * the context is fully restored
507 */
508 RR(IRQENABLE);
509
510 DSSDBG("context restored\n");
511 }
512
513 #undef SR
514 #undef RR
515
516 int dispc_runtime_get(void)
517 {
518 int r;
519
520 DSSDBG("dispc_runtime_get\n");
521
522 r = pm_runtime_resume_and_get(&dispc.pdev->dev);
523 if (WARN_ON(r < 0))
524 return r;
525 return 0;
526 }
527 EXPORT_SYMBOL(dispc_runtime_get);
528
529 void dispc_runtime_put(void)
530 {
531 int r;
532
533 DSSDBG("dispc_runtime_put\n");
534
535 r = pm_runtime_put_sync(&dispc.pdev->dev);
536 WARN_ON(r < 0 && r != -ENOSYS);
537 }
538 EXPORT_SYMBOL(dispc_runtime_put);
539
540 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
541 {
542 return mgr_desc[channel].vsync_irq;
543 }
544 EXPORT_SYMBOL(dispc_mgr_get_vsync_irq);
545
546 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
547 {
548 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc.feat->no_framedone_tv)
549 return 0;
550
551 return mgr_desc[channel].framedone_irq;
552 }
553 EXPORT_SYMBOL(dispc_mgr_get_framedone_irq);
554
555 u32 dispc_mgr_get_sync_lost_irq(enum omap_channel channel)
556 {
557 return mgr_desc[channel].sync_lost_irq;
558 }
559 EXPORT_SYMBOL(dispc_mgr_get_sync_lost_irq);
560
561 bool dispc_mgr_go_busy(enum omap_channel channel)
562 {
563 return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
564 }
565 EXPORT_SYMBOL(dispc_mgr_go_busy);
566
567 void dispc_mgr_go(enum omap_channel channel)
568 {
569 WARN_ON(!dispc_mgr_is_enabled(channel));
570 WARN_ON(dispc_mgr_go_busy(channel));
571
572 DSSDBG("GO %s\n", mgr_desc[channel].name);
573
574 mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
575 }
576 EXPORT_SYMBOL(dispc_mgr_go);
577
578 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
579 {
580 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
581 }
582
583 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
584 {
585 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
586 }
587
588 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
589 {
590 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
591 }
592
593 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
594 {
595 BUG_ON(plane == OMAP_DSS_GFX);
596
597 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
598 }
599
600 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
601 u32 value)
602 {
603 BUG_ON(plane == OMAP_DSS_GFX);
604
605 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
606 }
607
608 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
609 {
610 BUG_ON(plane == OMAP_DSS_GFX);
611
612 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
613 }
614
615 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
616 int fir_vinc, int five_taps,
617 enum omap_color_component color_comp)
618 {
619 const struct dispc_coef *h_coef, *v_coef;
620 int i;
621
622 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
623 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
624
625 for (i = 0; i < 8; i++) {
626 u32 h, hv;
627
628 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
629 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
630 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
631 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
632 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
633 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
634 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
635 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
636
637 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
638 dispc_ovl_write_firh_reg(plane, i, h);
639 dispc_ovl_write_firhv_reg(plane, i, hv);
640 } else {
641 dispc_ovl_write_firh2_reg(plane, i, h);
642 dispc_ovl_write_firhv2_reg(plane, i, hv);
643 }
644
645 }
646
647 if (five_taps) {
648 for (i = 0; i < 8; i++) {
649 u32 v;
650 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
651 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
652 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
653 dispc_ovl_write_firv_reg(plane, i, v);
654 else
655 dispc_ovl_write_firv2_reg(plane, i, v);
656 }
657 }
658 }
659
660
661 static void dispc_ovl_write_color_conv_coef(enum omap_plane plane,
662 const struct color_conv_coef *ct)
663 {
664 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
665
666 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
667 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
668 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
669 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
670 dispc_write_reg(DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
671
672 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
673
674 #undef CVAL
675 }
676
677 static void dispc_setup_color_conv_coef(void)
678 {
679 int i;
680 int num_ovl = dss_feat_get_num_ovls();
681 const struct color_conv_coef ctbl_bt601_5_ovl = {
682 /* YUV -> RGB */
683 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
684 };
685 const struct color_conv_coef ctbl_bt601_5_wb = {
686 /* RGB -> YUV */
687 66, 129, 25, 112, -94, -18, -38, -74, 112, 0,
688 };
689
690 for (i = 1; i < num_ovl; i++)
691 dispc_ovl_write_color_conv_coef(i, &ctbl_bt601_5_ovl);
692
693 if (dispc.feat->has_writeback)
694 dispc_ovl_write_color_conv_coef(OMAP_DSS_WB, &ctbl_bt601_5_wb);
695 }
696
697 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
698 {
699 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
700 }
701
702 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
703 {
704 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
705 }
706
707 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
708 {
709 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
710 }
711
712 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
713 {
714 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
715 }
716
717 static void dispc_ovl_set_pos(enum omap_plane plane,
718 enum omap_overlay_caps caps, int x, int y)
719 {
720 u32 val;
721
722 if ((caps & OMAP_DSS_OVL_CAP_POS) == 0)
723 return;
724
725 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
726
727 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
728 }
729
730 static void dispc_ovl_set_input_size(enum omap_plane plane, int width,
731 int height)
732 {
733 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
734
735 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
736 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
737 else
738 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
739 }
740
741 static void dispc_ovl_set_output_size(enum omap_plane plane, int width,
742 int height)
743 {
744 u32 val;
745
746 BUG_ON(plane == OMAP_DSS_GFX);
747
748 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
749
750 if (plane == OMAP_DSS_WB)
751 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
752 else
753 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
754 }
755
756 static void dispc_ovl_set_zorder(enum omap_plane plane,
757 enum omap_overlay_caps caps, u8 zorder)
758 {
759 if ((caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
760 return;
761
762 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
763 }
764
765 static void dispc_ovl_enable_zorder_planes(void)
766 {
767 int i;
768
769 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
770 return;
771
772 for (i = 0; i < dss_feat_get_num_ovls(); i++)
773 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
774 }
775
776 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane,
777 enum omap_overlay_caps caps, bool enable)
778 {
779 if ((caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
780 return;
781
782 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
783 }
784
785 static void dispc_ovl_setup_global_alpha(enum omap_plane plane,
786 enum omap_overlay_caps caps, u8 global_alpha)
787 {
788 static const unsigned shifts[] = { 0, 8, 16, 24, };
789 int shift;
790
791 if ((caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
792 return;
793
794 shift = shifts[plane];
795 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
796 }
797
798 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
799 {
800 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
801 }
802
803 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
804 {
805 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
806 }
807
808 static void dispc_ovl_set_color_mode(enum omap_plane plane,
809 enum omap_color_mode color_mode)
810 {
811 u32 m = 0;
812 if (plane != OMAP_DSS_GFX) {
813 switch (color_mode) {
814 case OMAP_DSS_COLOR_NV12:
815 m = 0x0; break;
816 case OMAP_DSS_COLOR_RGBX16:
817 m = 0x1; break;
818 case OMAP_DSS_COLOR_RGBA16:
819 m = 0x2; break;
820 case OMAP_DSS_COLOR_RGB12U:
821 m = 0x4; break;
822 case OMAP_DSS_COLOR_ARGB16:
823 m = 0x5; break;
824 case OMAP_DSS_COLOR_RGB16:
825 m = 0x6; break;
826 case OMAP_DSS_COLOR_ARGB16_1555:
827 m = 0x7; break;
828 case OMAP_DSS_COLOR_RGB24U:
829 m = 0x8; break;
830 case OMAP_DSS_COLOR_RGB24P:
831 m = 0x9; break;
832 case OMAP_DSS_COLOR_YUV2:
833 m = 0xa; break;
834 case OMAP_DSS_COLOR_UYVY:
835 m = 0xb; break;
836 case OMAP_DSS_COLOR_ARGB32:
837 m = 0xc; break;
838 case OMAP_DSS_COLOR_RGBA32:
839 m = 0xd; break;
840 case OMAP_DSS_COLOR_RGBX32:
841 m = 0xe; break;
842 case OMAP_DSS_COLOR_XRGB16_1555:
843 m = 0xf; break;
844 default:
845 BUG(); return;
846 }
847 } else {
848 switch (color_mode) {
849 case OMAP_DSS_COLOR_CLUT1:
850 m = 0x0; break;
851 case OMAP_DSS_COLOR_CLUT2:
852 m = 0x1; break;
853 case OMAP_DSS_COLOR_CLUT4:
854 m = 0x2; break;
855 case OMAP_DSS_COLOR_CLUT8:
856 m = 0x3; break;
857 case OMAP_DSS_COLOR_RGB12U:
858 m = 0x4; break;
859 case OMAP_DSS_COLOR_ARGB16:
860 m = 0x5; break;
861 case OMAP_DSS_COLOR_RGB16:
862 m = 0x6; break;
863 case OMAP_DSS_COLOR_ARGB16_1555:
864 m = 0x7; break;
865 case OMAP_DSS_COLOR_RGB24U:
866 m = 0x8; break;
867 case OMAP_DSS_COLOR_RGB24P:
868 m = 0x9; break;
869 case OMAP_DSS_COLOR_RGBX16:
870 m = 0xa; break;
871 case OMAP_DSS_COLOR_RGBA16:
872 m = 0xb; break;
873 case OMAP_DSS_COLOR_ARGB32:
874 m = 0xc; break;
875 case OMAP_DSS_COLOR_RGBA32:
876 m = 0xd; break;
877 case OMAP_DSS_COLOR_RGBX32:
878 m = 0xe; break;
879 case OMAP_DSS_COLOR_XRGB16_1555:
880 m = 0xf; break;
881 default:
882 BUG(); return;
883 }
884 }
885
886 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
887 }
888
889 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
890 enum omap_dss_rotation_type rotation_type)
891 {
892 if (!dss_has_feature(FEAT_BURST_2D))
893 return;
894
895 if (rotation_type == OMAP_DSS_ROT_TILER)
896 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
897 else
898 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
899 }
900
901 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
902 {
903 int shift;
904 u32 val;
905 int chan = 0, chan2 = 0;
906
907 switch (plane) {
908 case OMAP_DSS_GFX:
909 shift = 8;
910 break;
911 case OMAP_DSS_VIDEO1:
912 case OMAP_DSS_VIDEO2:
913 case OMAP_DSS_VIDEO3:
914 shift = 16;
915 break;
916 default:
917 BUG();
918 return;
919 }
920
921 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
922 if (dss_has_feature(FEAT_MGR_LCD2)) {
923 switch (channel) {
924 case OMAP_DSS_CHANNEL_LCD:
925 chan = 0;
926 chan2 = 0;
927 break;
928 case OMAP_DSS_CHANNEL_DIGIT:
929 chan = 1;
930 chan2 = 0;
931 break;
932 case OMAP_DSS_CHANNEL_LCD2:
933 chan = 0;
934 chan2 = 1;
935 break;
936 case OMAP_DSS_CHANNEL_LCD3:
937 if (dss_has_feature(FEAT_MGR_LCD3)) {
938 chan = 0;
939 chan2 = 2;
940 } else {
941 BUG();
942 return;
943 }
944 break;
945 case OMAP_DSS_CHANNEL_WB:
946 chan = 0;
947 chan2 = 3;
948 break;
949 default:
950 BUG();
951 return;
952 }
953
954 val = FLD_MOD(val, chan, shift, shift);
955 val = FLD_MOD(val, chan2, 31, 30);
956 } else {
957 val = FLD_MOD(val, channel, shift, shift);
958 }
959 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
960 }
961 EXPORT_SYMBOL(dispc_ovl_set_channel_out);
962
963 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
964 {
965 int shift;
966 u32 val;
967
968 switch (plane) {
969 case OMAP_DSS_GFX:
970 shift = 8;
971 break;
972 case OMAP_DSS_VIDEO1:
973 case OMAP_DSS_VIDEO2:
974 case OMAP_DSS_VIDEO3:
975 shift = 16;
976 break;
977 default:
978 BUG();
979 return 0;
980 }
981
982 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
983
984 if (FLD_GET(val, shift, shift) == 1)
985 return OMAP_DSS_CHANNEL_DIGIT;
986
987 if (!dss_has_feature(FEAT_MGR_LCD2))
988 return OMAP_DSS_CHANNEL_LCD;
989
990 switch (FLD_GET(val, 31, 30)) {
991 case 0:
992 default:
993 return OMAP_DSS_CHANNEL_LCD;
994 case 1:
995 return OMAP_DSS_CHANNEL_LCD2;
996 case 2:
997 return OMAP_DSS_CHANNEL_LCD3;
998 case 3:
999 return OMAP_DSS_CHANNEL_WB;
1000 }
1001 }
1002
1003 static void dispc_ovl_set_burst_size(enum omap_plane plane,
1004 enum omap_burst_size burst_size)
1005 {
1006 static const unsigned shifts[] = { 6, 14, 14, 14, 14, };
1007 int shift;
1008
1009 shift = shifts[plane];
1010 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
1011 }
1012
1013 static void dispc_configure_burst_sizes(void)
1014 {
1015 int i;
1016 const int burst_size = BURST_SIZE_X8;
1017
1018 /* Configure burst size always to maximum size */
1019 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1020 dispc_ovl_set_burst_size(i, burst_size);
1021 if (dispc.feat->has_writeback)
1022 dispc_ovl_set_burst_size(OMAP_DSS_WB, burst_size);
1023 }
1024
1025 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
1026 {
1027 unsigned unit = dss_feat_get_burst_size_unit();
1028 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
1029 return unit * 8;
1030 }
1031
1032 void dispc_enable_gamma_table(bool enable)
1033 {
1034 /*
1035 * This is partially implemented to support only disabling of
1036 * the gamma table.
1037 */
1038 if (enable) {
1039 DSSWARN("Gamma table enabling for TV not yet supported");
1040 return;
1041 }
1042
1043 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1044 }
1045
1046 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1047 {
1048 if (channel == OMAP_DSS_CHANNEL_DIGIT)
1049 return;
1050
1051 mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1052 }
1053
1054 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1055 const struct omap_dss_cpr_coefs *coefs)
1056 {
1057 u32 coef_r, coef_g, coef_b;
1058
1059 if (!dss_mgr_is_lcd(channel))
1060 return;
1061
1062 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1063 FLD_VAL(coefs->rb, 9, 0);
1064 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1065 FLD_VAL(coefs->gb, 9, 0);
1066 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1067 FLD_VAL(coefs->bb, 9, 0);
1068
1069 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1070 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1071 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1072 }
1073
1074 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1075 {
1076 u32 val;
1077
1078 BUG_ON(plane == OMAP_DSS_GFX);
1079
1080 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1081 val = FLD_MOD(val, enable, 9, 9);
1082 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1083 }
1084
1085 static void dispc_ovl_enable_replication(enum omap_plane plane,
1086 enum omap_overlay_caps caps, bool enable)
1087 {
1088 static const unsigned shifts[] = { 5, 10, 10, 10 };
1089 int shift;
1090
1091 if ((caps & OMAP_DSS_OVL_CAP_REPLICATION) == 0)
1092 return;
1093
1094 shift = shifts[plane];
1095 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1096 }
1097
1098 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1099 u16 height)
1100 {
1101 u32 val;
1102
1103 val = FLD_VAL(height - 1, dispc.feat->mgr_height_start, 16) |
1104 FLD_VAL(width - 1, dispc.feat->mgr_width_start, 0);
1105
1106 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1107 }
1108
1109 static void dispc_init_fifos(void)
1110 {
1111 u32 size;
1112 int fifo;
1113 u8 start, end;
1114 u32 unit;
1115 int i;
1116
1117 unit = dss_feat_get_buffer_size_unit();
1118
1119 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1120
1121 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1122 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end);
1123 size *= unit;
1124 dispc.fifo_size[fifo] = size;
1125
1126 /*
1127 * By default fifos are mapped directly to overlays, fifo 0 to
1128 * ovl 0, fifo 1 to ovl 1, etc.
1129 */
1130 dispc.fifo_assignment[fifo] = fifo;
1131 }
1132
1133 /*
1134 * The GFX fifo on OMAP4 is smaller than the other fifos. The small fifo
1135 * causes problems with certain use cases, like using the tiler in 2D
1136 * mode. The below hack swaps the fifos of GFX and WB planes, thus
1137 * giving GFX plane a larger fifo. WB but should work fine with a
1138 * smaller fifo.
1139 */
1140 if (dispc.feat->gfx_fifo_workaround) {
1141 u32 v;
1142
1143 v = dispc_read_reg(DISPC_GLOBAL_BUFFER);
1144
1145 v = FLD_MOD(v, 4, 2, 0); /* GFX BUF top to WB */
1146 v = FLD_MOD(v, 4, 5, 3); /* GFX BUF bottom to WB */
1147 v = FLD_MOD(v, 0, 26, 24); /* WB BUF top to GFX */
1148 v = FLD_MOD(v, 0, 29, 27); /* WB BUF bottom to GFX */
1149
1150 dispc_write_reg(DISPC_GLOBAL_BUFFER, v);
1151
1152 dispc.fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB;
1153 dispc.fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX;
1154 }
1155
1156 /*
1157 * Setup default fifo thresholds.
1158 */
1159 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1160 u32 low, high;
1161 const bool use_fifomerge = false;
1162 const bool manual_update = false;
1163
1164 dispc_ovl_compute_fifo_thresholds(i, &low, &high,
1165 use_fifomerge, manual_update);
1166
1167 dispc_ovl_set_fifo_threshold(i, low, high);
1168 }
1169
1170 if (dispc.feat->has_writeback) {
1171 u32 low, high;
1172 const bool use_fifomerge = false;
1173 const bool manual_update = false;
1174
1175 dispc_ovl_compute_fifo_thresholds(OMAP_DSS_WB, &low, &high,
1176 use_fifomerge, manual_update);
1177
1178 dispc_ovl_set_fifo_threshold(OMAP_DSS_WB, low, high);
1179 }
1180 }
1181
1182 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1183 {
1184 int fifo;
1185 u32 size = 0;
1186
1187 for (fifo = 0; fifo < dispc.feat->num_fifos; ++fifo) {
1188 if (dispc.fifo_assignment[fifo] == plane)
1189 size += dispc.fifo_size[fifo];
1190 }
1191
1192 return size;
1193 }
1194
1195 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1196 {
1197 u8 hi_start, hi_end, lo_start, lo_end;
1198 u32 unit;
1199
1200 unit = dss_feat_get_buffer_size_unit();
1201
1202 WARN_ON(low % unit != 0);
1203 WARN_ON(high % unit != 0);
1204
1205 low /= unit;
1206 high /= unit;
1207
1208 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1209 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1210
1211 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1212 plane,
1213 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1214 lo_start, lo_end) * unit,
1215 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1216 hi_start, hi_end) * unit,
1217 low * unit, high * unit);
1218
1219 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1220 FLD_VAL(high, hi_start, hi_end) |
1221 FLD_VAL(low, lo_start, lo_end));
1222
1223 /*
1224 * configure the preload to the pipeline's high threhold, if HT it's too
1225 * large for the preload field, set the threshold to the maximum value
1226 * that can be held by the preload register
1227 */
1228 if (dss_has_feature(FEAT_PRELOAD) && dispc.feat->set_max_preload &&
1229 plane != OMAP_DSS_WB)
1230 dispc_write_reg(DISPC_OVL_PRELOAD(plane), min(high, 0xfffu));
1231 }
1232
1233 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1234 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1235 bool manual_update)
1236 {
1237 /*
1238 * All sizes are in bytes. Both the buffer and burst are made of
1239 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1240 */
1241
1242 unsigned buf_unit = dss_feat_get_buffer_size_unit();
1243 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1244 int i;
1245
1246 burst_size = dispc_ovl_get_burst_size(plane);
1247 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1248
1249 if (use_fifomerge) {
1250 total_fifo_size = 0;
1251 for (i = 0; i < dss_feat_get_num_ovls(); ++i)
1252 total_fifo_size += dispc_ovl_get_fifo_size(i);
1253 } else {
1254 total_fifo_size = ovl_fifo_size;
1255 }
1256
1257 /*
1258 * We use the same low threshold for both fifomerge and non-fifomerge
1259 * cases, but for fifomerge we calculate the high threshold using the
1260 * combined fifo size
1261 */
1262
1263 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1264 *fifo_low = ovl_fifo_size - burst_size * 2;
1265 *fifo_high = total_fifo_size - burst_size;
1266 } else if (plane == OMAP_DSS_WB) {
1267 /*
1268 * Most optimal configuration for writeback is to push out data
1269 * to the interconnect the moment writeback pushes enough pixels
1270 * in the FIFO to form a burst
1271 */
1272 *fifo_low = 0;
1273 *fifo_high = burst_size;
1274 } else {
1275 *fifo_low = ovl_fifo_size - burst_size;
1276 *fifo_high = total_fifo_size - buf_unit;
1277 }
1278 }
1279
1280 static void dispc_ovl_set_mflag(enum omap_plane plane, bool enable)
1281 {
1282 int bit;
1283
1284 if (plane == OMAP_DSS_GFX)
1285 bit = 14;
1286 else
1287 bit = 23;
1288
1289 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1290 }
1291
1292 static void dispc_ovl_set_mflag_threshold(enum omap_plane plane,
1293 int low, int high)
1294 {
1295 dispc_write_reg(DISPC_OVL_MFLAG_THRESHOLD(plane),
1296 FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0));
1297 }
1298
1299 static void dispc_init_mflag(void)
1300 {
1301 int i;
1302
1303 /*
1304 * HACK: NV12 color format and MFLAG seem to have problems working
1305 * together: using two displays, and having an NV12 overlay on one of
1306 * the displays will cause underflows/synclosts when MFLAG_CTRL=2.
1307 * Changing MFLAG thresholds and PRELOAD to certain values seem to
1308 * remove the errors, but there doesn't seem to be a clear logic on
1309 * which values work and which not.
1310 *
1311 * As a work-around, set force MFLAG to always on.
1312 */
1313 dispc_write_reg(DISPC_GLOBAL_MFLAG_ATTRIBUTE,
1314 (1 << 0) | /* MFLAG_CTRL = force always on */
1315 (0 << 2)); /* MFLAG_START = disable */
1316
1317 for (i = 0; i < dss_feat_get_num_ovls(); ++i) {
1318 u32 size = dispc_ovl_get_fifo_size(i);
1319 u32 unit = dss_feat_get_buffer_size_unit();
1320 u32 low, high;
1321
1322 dispc_ovl_set_mflag(i, true);
1323
1324 /*
1325 * Simulation team suggests below thesholds:
1326 * HT = fifosize * 5 / 8;
1327 * LT = fifosize * 4 / 8;
1328 */
1329
1330 low = size * 4 / 8 / unit;
1331 high = size * 5 / 8 / unit;
1332
1333 dispc_ovl_set_mflag_threshold(i, low, high);
1334 }
1335
1336 if (dispc.feat->has_writeback) {
1337 u32 size = dispc_ovl_get_fifo_size(OMAP_DSS_WB);
1338 u32 unit = dss_feat_get_buffer_size_unit();
1339 u32 low, high;
1340
1341 dispc_ovl_set_mflag(OMAP_DSS_WB, true);
1342
1343 /*
1344 * Simulation team suggests below thesholds:
1345 * HT = fifosize * 5 / 8;
1346 * LT = fifosize * 4 / 8;
1347 */
1348
1349 low = size * 4 / 8 / unit;
1350 high = size * 5 / 8 / unit;
1351
1352 dispc_ovl_set_mflag_threshold(OMAP_DSS_WB, low, high);
1353 }
1354 }
1355
1356 static void dispc_ovl_set_fir(enum omap_plane plane,
1357 int hinc, int vinc,
1358 enum omap_color_component color_comp)
1359 {
1360 u32 val;
1361
1362 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1363 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1364
1365 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1366 &hinc_start, &hinc_end);
1367 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1368 &vinc_start, &vinc_end);
1369 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1370 FLD_VAL(hinc, hinc_start, hinc_end);
1371
1372 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1373 } else {
1374 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1375 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1376 }
1377 }
1378
1379 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1380 {
1381 u32 val;
1382 u8 hor_start, hor_end, vert_start, vert_end;
1383
1384 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1385 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1386
1387 val = FLD_VAL(vaccu, vert_start, vert_end) |
1388 FLD_VAL(haccu, hor_start, hor_end);
1389
1390 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1391 }
1392
1393 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1394 {
1395 u32 val;
1396 u8 hor_start, hor_end, vert_start, vert_end;
1397
1398 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1399 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1400
1401 val = FLD_VAL(vaccu, vert_start, vert_end) |
1402 FLD_VAL(haccu, hor_start, hor_end);
1403
1404 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1405 }
1406
1407 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1408 int vaccu)
1409 {
1410 u32 val;
1411
1412 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1413 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1414 }
1415
1416 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1417 int vaccu)
1418 {
1419 u32 val;
1420
1421 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1422 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1423 }
1424
1425 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1426 u16 orig_width, u16 orig_height,
1427 u16 out_width, u16 out_height,
1428 bool five_taps, u8 rotation,
1429 enum omap_color_component color_comp)
1430 {
1431 int fir_hinc, fir_vinc;
1432
1433 fir_hinc = 1024 * orig_width / out_width;
1434 fir_vinc = 1024 * orig_height / out_height;
1435
1436 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1437 color_comp);
1438 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1439 }
1440
1441 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1442 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1443 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1444 {
1445 int h_accu2_0, h_accu2_1;
1446 int v_accu2_0, v_accu2_1;
1447 int chroma_hinc, chroma_vinc;
1448 int idx;
1449
1450 struct accu {
1451 s8 h0_m, h0_n;
1452 s8 h1_m, h1_n;
1453 s8 v0_m, v0_n;
1454 s8 v1_m, v1_n;
1455 };
1456
1457 const struct accu *accu_table;
1458 const struct accu *accu_val;
1459
1460 static const struct accu accu_nv12[4] = {
1461 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1462 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1463 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1464 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1465 };
1466
1467 static const struct accu accu_nv12_ilace[4] = {
1468 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1469 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1470 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1471 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1472 };
1473
1474 static const struct accu accu_yuv[4] = {
1475 { 0, 1, 0, 1, 0, 1, 0, 1 },
1476 { 0, 1, 0, 1, 0, 1, 0, 1 },
1477 { -1, 1, 0, 1, 0, 1, 0, 1 },
1478 { 0, 1, 0, 1, -1, 1, 0, 1 },
1479 };
1480
1481 switch (rotation) {
1482 case OMAP_DSS_ROT_0:
1483 idx = 0;
1484 break;
1485 case OMAP_DSS_ROT_90:
1486 idx = 1;
1487 break;
1488 case OMAP_DSS_ROT_180:
1489 idx = 2;
1490 break;
1491 case OMAP_DSS_ROT_270:
1492 idx = 3;
1493 break;
1494 default:
1495 BUG();
1496 return;
1497 }
1498
1499 switch (color_mode) {
1500 case OMAP_DSS_COLOR_NV12:
1501 if (ilace)
1502 accu_table = accu_nv12_ilace;
1503 else
1504 accu_table = accu_nv12;
1505 break;
1506 case OMAP_DSS_COLOR_YUV2:
1507 case OMAP_DSS_COLOR_UYVY:
1508 accu_table = accu_yuv;
1509 break;
1510 default:
1511 BUG();
1512 return;
1513 }
1514
1515 accu_val = &accu_table[idx];
1516
1517 chroma_hinc = 1024 * orig_width / out_width;
1518 chroma_vinc = 1024 * orig_height / out_height;
1519
1520 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1521 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1522 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1523 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1524
1525 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1526 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1527 }
1528
1529 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1530 u16 orig_width, u16 orig_height,
1531 u16 out_width, u16 out_height,
1532 bool ilace, bool five_taps,
1533 bool fieldmode, enum omap_color_mode color_mode,
1534 u8 rotation)
1535 {
1536 int accu0 = 0;
1537 int accu1 = 0;
1538 u32 l;
1539
1540 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1541 out_width, out_height, five_taps,
1542 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1543 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1544
1545 /* RESIZEENABLE and VERTICALTAPS */
1546 l &= ~((0x3 << 5) | (0x1 << 21));
1547 l |= (orig_width != out_width) ? (1 << 5) : 0;
1548 l |= (orig_height != out_height) ? (1 << 6) : 0;
1549 l |= five_taps ? (1 << 21) : 0;
1550
1551 /* VRESIZECONF and HRESIZECONF */
1552 if (dss_has_feature(FEAT_RESIZECONF)) {
1553 l &= ~(0x3 << 7);
1554 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1555 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1556 }
1557
1558 /* LINEBUFFERSPLIT */
1559 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1560 l &= ~(0x1 << 22);
1561 l |= five_taps ? (1 << 22) : 0;
1562 }
1563
1564 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1565
1566 /*
1567 * field 0 = even field = bottom field
1568 * field 1 = odd field = top field
1569 */
1570 if (ilace && !fieldmode) {
1571 accu1 = 0;
1572 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1573 if (accu0 >= 1024/2) {
1574 accu1 = 1024/2;
1575 accu0 -= accu1;
1576 }
1577 }
1578
1579 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1580 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1581 }
1582
1583 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1584 u16 orig_width, u16 orig_height,
1585 u16 out_width, u16 out_height,
1586 bool ilace, bool five_taps,
1587 bool fieldmode, enum omap_color_mode color_mode,
1588 u8 rotation)
1589 {
1590 int scale_x = out_width != orig_width;
1591 int scale_y = out_height != orig_height;
1592 bool chroma_upscale = plane != OMAP_DSS_WB;
1593
1594 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1595 return;
1596 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1597 color_mode != OMAP_DSS_COLOR_UYVY &&
1598 color_mode != OMAP_DSS_COLOR_NV12)) {
1599 /* reset chroma resampling for RGB formats */
1600 if (plane != OMAP_DSS_WB)
1601 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1602 return;
1603 }
1604
1605 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1606 out_height, ilace, color_mode, rotation);
1607
1608 switch (color_mode) {
1609 case OMAP_DSS_COLOR_NV12:
1610 if (chroma_upscale) {
1611 /* UV is subsampled by 2 horizontally and vertically */
1612 orig_height >>= 1;
1613 orig_width >>= 1;
1614 } else {
1615 /* UV is downsampled by 2 horizontally and vertically */
1616 orig_height <<= 1;
1617 orig_width <<= 1;
1618 }
1619
1620 break;
1621 case OMAP_DSS_COLOR_YUV2:
1622 case OMAP_DSS_COLOR_UYVY:
1623 /* For YUV422 with 90/270 rotation, we don't upsample chroma */
1624 if (rotation == OMAP_DSS_ROT_0 ||
1625 rotation == OMAP_DSS_ROT_180) {
1626 if (chroma_upscale)
1627 /* UV is subsampled by 2 horizontally */
1628 orig_width >>= 1;
1629 else
1630 /* UV is downsampled by 2 horizontally */
1631 orig_width <<= 1;
1632 }
1633
1634 /* must use FIR for YUV422 if rotated */
1635 if (rotation != OMAP_DSS_ROT_0)
1636 scale_x = scale_y = true;
1637
1638 break;
1639 default:
1640 BUG();
1641 return;
1642 }
1643
1644 if (out_width != orig_width)
1645 scale_x = true;
1646 if (out_height != orig_height)
1647 scale_y = true;
1648
1649 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1650 out_width, out_height, five_taps,
1651 rotation, DISPC_COLOR_COMPONENT_UV);
1652
1653 if (plane != OMAP_DSS_WB)
1654 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1655 (scale_x || scale_y) ? 1 : 0, 8, 8);
1656
1657 /* set H scaling */
1658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1659 /* set V scaling */
1660 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1661 }
1662
1663 static void dispc_ovl_set_scaling(enum omap_plane plane,
1664 u16 orig_width, u16 orig_height,
1665 u16 out_width, u16 out_height,
1666 bool ilace, bool five_taps,
1667 bool fieldmode, enum omap_color_mode color_mode,
1668 u8 rotation)
1669 {
1670 BUG_ON(plane == OMAP_DSS_GFX);
1671
1672 dispc_ovl_set_scaling_common(plane,
1673 orig_width, orig_height,
1674 out_width, out_height,
1675 ilace, five_taps,
1676 fieldmode, color_mode,
1677 rotation);
1678
1679 dispc_ovl_set_scaling_uv(plane,
1680 orig_width, orig_height,
1681 out_width, out_height,
1682 ilace, five_taps,
1683 fieldmode, color_mode,
1684 rotation);
1685 }
1686
1687 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1688 enum omap_dss_rotation_type rotation_type,
1689 bool mirroring, enum omap_color_mode color_mode)
1690 {
1691 bool row_repeat = false;
1692 int vidrot = 0;
1693
1694 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1695 color_mode == OMAP_DSS_COLOR_UYVY) {
1696
1697 if (mirroring) {
1698 switch (rotation) {
1699 case OMAP_DSS_ROT_0:
1700 vidrot = 2;
1701 break;
1702 case OMAP_DSS_ROT_90:
1703 vidrot = 1;
1704 break;
1705 case OMAP_DSS_ROT_180:
1706 vidrot = 0;
1707 break;
1708 case OMAP_DSS_ROT_270:
1709 vidrot = 3;
1710 break;
1711 }
1712 } else {
1713 switch (rotation) {
1714 case OMAP_DSS_ROT_0:
1715 vidrot = 0;
1716 break;
1717 case OMAP_DSS_ROT_90:
1718 vidrot = 1;
1719 break;
1720 case OMAP_DSS_ROT_180:
1721 vidrot = 2;
1722 break;
1723 case OMAP_DSS_ROT_270:
1724 vidrot = 3;
1725 break;
1726 }
1727 }
1728
1729 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1730 row_repeat = true;
1731 else
1732 row_repeat = false;
1733 }
1734
1735 /*
1736 * OMAP4/5 Errata i631:
1737 * NV12 in 1D mode must use ROTATION=1. Otherwise DSS will fetch extra
1738 * rows beyond the framebuffer, which may cause OCP error.
1739 */
1740 if (color_mode == OMAP_DSS_COLOR_NV12 &&
1741 rotation_type != OMAP_DSS_ROT_TILER)
1742 vidrot = 1;
1743
1744 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1745 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1746 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1747 row_repeat ? 1 : 0, 18, 18);
1748
1749 if (color_mode == OMAP_DSS_COLOR_NV12) {
1750 bool doublestride = (rotation_type == OMAP_DSS_ROT_TILER) &&
1751 (rotation == OMAP_DSS_ROT_0 ||
1752 rotation == OMAP_DSS_ROT_180);
1753 /* DOUBLESTRIDE */
1754 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), doublestride, 22, 22);
1755 }
1756
1757 }
1758
1759 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1760 {
1761 switch (color_mode) {
1762 case OMAP_DSS_COLOR_CLUT1:
1763 return 1;
1764 case OMAP_DSS_COLOR_CLUT2:
1765 return 2;
1766 case OMAP_DSS_COLOR_CLUT4:
1767 return 4;
1768 case OMAP_DSS_COLOR_CLUT8:
1769 case OMAP_DSS_COLOR_NV12:
1770 return 8;
1771 case OMAP_DSS_COLOR_RGB12U:
1772 case OMAP_DSS_COLOR_RGB16:
1773 case OMAP_DSS_COLOR_ARGB16:
1774 case OMAP_DSS_COLOR_YUV2:
1775 case OMAP_DSS_COLOR_UYVY:
1776 case OMAP_DSS_COLOR_RGBA16:
1777 case OMAP_DSS_COLOR_RGBX16:
1778 case OMAP_DSS_COLOR_ARGB16_1555:
1779 case OMAP_DSS_COLOR_XRGB16_1555:
1780 return 16;
1781 case OMAP_DSS_COLOR_RGB24P:
1782 return 24;
1783 case OMAP_DSS_COLOR_RGB24U:
1784 case OMAP_DSS_COLOR_ARGB32:
1785 case OMAP_DSS_COLOR_RGBA32:
1786 case OMAP_DSS_COLOR_RGBX32:
1787 return 32;
1788 default:
1789 BUG();
1790 return 0;
1791 }
1792 }
1793
1794 static s32 pixinc(int pixels, u8 ps)
1795 {
1796 if (pixels == 1)
1797 return 1;
1798 else if (pixels > 1)
1799 return 1 + (pixels - 1) * ps;
1800 else if (pixels < 0)
1801 return 1 - (-pixels + 1) * ps;
1802 else
1803 BUG();
1804 return 0;
1805 }
1806
1807 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1808 u16 screen_width,
1809 u16 width, u16 height,
1810 enum omap_color_mode color_mode, bool fieldmode,
1811 unsigned int field_offset,
1812 unsigned *offset0, unsigned *offset1,
1813 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1814 {
1815 u8 ps;
1816
1817 /* FIXME CLUT formats */
1818 switch (color_mode) {
1819 case OMAP_DSS_COLOR_CLUT1:
1820 case OMAP_DSS_COLOR_CLUT2:
1821 case OMAP_DSS_COLOR_CLUT4:
1822 case OMAP_DSS_COLOR_CLUT8:
1823 BUG();
1824 return;
1825 case OMAP_DSS_COLOR_YUV2:
1826 case OMAP_DSS_COLOR_UYVY:
1827 ps = 4;
1828 break;
1829 default:
1830 ps = color_mode_to_bpp(color_mode) / 8;
1831 break;
1832 }
1833
1834 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1835 width, height);
1836
1837 /*
1838 * field 0 = even field = bottom field
1839 * field 1 = odd field = top field
1840 */
1841 switch (rotation + mirror * 4) {
1842 case OMAP_DSS_ROT_0:
1843 case OMAP_DSS_ROT_180:
1844 /*
1845 * If the pixel format is YUV or UYVY divide the width
1846 * of the image by 2 for 0 and 180 degree rotation.
1847 */
1848 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1849 color_mode == OMAP_DSS_COLOR_UYVY)
1850 width = width >> 1;
1851 fallthrough;
1852 case OMAP_DSS_ROT_90:
1853 case OMAP_DSS_ROT_270:
1854 *offset1 = 0;
1855 if (field_offset)
1856 *offset0 = field_offset * screen_width * ps;
1857 else
1858 *offset0 = 0;
1859
1860 *row_inc = pixinc(1 +
1861 (y_predecim * screen_width - x_predecim * width) +
1862 (fieldmode ? screen_width : 0), ps);
1863 *pix_inc = pixinc(x_predecim, ps);
1864 break;
1865
1866 case OMAP_DSS_ROT_0 + 4:
1867 case OMAP_DSS_ROT_180 + 4:
1868 /* If the pixel format is YUV or UYVY divide the width
1869 * of the image by 2 for 0 degree and 180 degree
1870 */
1871 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1872 color_mode == OMAP_DSS_COLOR_UYVY)
1873 width = width >> 1;
1874 fallthrough;
1875 case OMAP_DSS_ROT_90 + 4:
1876 case OMAP_DSS_ROT_270 + 4:
1877 *offset1 = 0;
1878 if (field_offset)
1879 *offset0 = field_offset * screen_width * ps;
1880 else
1881 *offset0 = 0;
1882 *row_inc = pixinc(1 -
1883 (y_predecim * screen_width + x_predecim * width) -
1884 (fieldmode ? screen_width : 0), ps);
1885 *pix_inc = pixinc(x_predecim, ps);
1886 break;
1887
1888 default:
1889 BUG();
1890 return;
1891 }
1892 }
1893
1894 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1895 u16 screen_width,
1896 u16 width, u16 height,
1897 enum omap_color_mode color_mode, bool fieldmode,
1898 unsigned int field_offset,
1899 unsigned *offset0, unsigned *offset1,
1900 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1901 {
1902 u8 ps;
1903 u16 fbw, fbh;
1904
1905 /* FIXME CLUT formats */
1906 switch (color_mode) {
1907 case OMAP_DSS_COLOR_CLUT1:
1908 case OMAP_DSS_COLOR_CLUT2:
1909 case OMAP_DSS_COLOR_CLUT4:
1910 case OMAP_DSS_COLOR_CLUT8:
1911 BUG();
1912 return;
1913 default:
1914 ps = color_mode_to_bpp(color_mode) / 8;
1915 break;
1916 }
1917
1918 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1919 width, height);
1920
1921 /* width & height are overlay sizes, convert to fb sizes */
1922
1923 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1924 fbw = width;
1925 fbh = height;
1926 } else {
1927 fbw = height;
1928 fbh = width;
1929 }
1930
1931 /*
1932 * field 0 = even field = bottom field
1933 * field 1 = odd field = top field
1934 */
1935 switch (rotation + mirror * 4) {
1936 case OMAP_DSS_ROT_0:
1937 *offset1 = 0;
1938 if (field_offset)
1939 *offset0 = *offset1 + field_offset * screen_width * ps;
1940 else
1941 *offset0 = *offset1;
1942 *row_inc = pixinc(1 +
1943 (y_predecim * screen_width - fbw * x_predecim) +
1944 (fieldmode ? screen_width : 0), ps);
1945 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1946 color_mode == OMAP_DSS_COLOR_UYVY)
1947 *pix_inc = pixinc(x_predecim, 2 * ps);
1948 else
1949 *pix_inc = pixinc(x_predecim, ps);
1950 break;
1951 case OMAP_DSS_ROT_90:
1952 *offset1 = screen_width * (fbh - 1) * ps;
1953 if (field_offset)
1954 *offset0 = *offset1 + field_offset * ps;
1955 else
1956 *offset0 = *offset1;
1957 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1958 y_predecim + (fieldmode ? 1 : 0), ps);
1959 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1960 break;
1961 case OMAP_DSS_ROT_180:
1962 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1963 if (field_offset)
1964 *offset0 = *offset1 - field_offset * screen_width * ps;
1965 else
1966 *offset0 = *offset1;
1967 *row_inc = pixinc(-1 -
1968 (y_predecim * screen_width - fbw * x_predecim) -
1969 (fieldmode ? screen_width : 0), ps);
1970 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1971 color_mode == OMAP_DSS_COLOR_UYVY)
1972 *pix_inc = pixinc(-x_predecim, 2 * ps);
1973 else
1974 *pix_inc = pixinc(-x_predecim, ps);
1975 break;
1976 case OMAP_DSS_ROT_270:
1977 *offset1 = (fbw - 1) * ps;
1978 if (field_offset)
1979 *offset0 = *offset1 - field_offset * ps;
1980 else
1981 *offset0 = *offset1;
1982 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1983 y_predecim - (fieldmode ? 1 : 0), ps);
1984 *pix_inc = pixinc(x_predecim * screen_width, ps);
1985 break;
1986
1987 /* mirroring */
1988 case OMAP_DSS_ROT_0 + 4:
1989 *offset1 = (fbw - 1) * ps;
1990 if (field_offset)
1991 *offset0 = *offset1 + field_offset * screen_width * ps;
1992 else
1993 *offset0 = *offset1;
1994 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1995 (fieldmode ? screen_width : 0),
1996 ps);
1997 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1998 color_mode == OMAP_DSS_COLOR_UYVY)
1999 *pix_inc = pixinc(-x_predecim, 2 * ps);
2000 else
2001 *pix_inc = pixinc(-x_predecim, ps);
2002 break;
2003
2004 case OMAP_DSS_ROT_90 + 4:
2005 *offset1 = 0;
2006 if (field_offset)
2007 *offset0 = *offset1 + field_offset * ps;
2008 else
2009 *offset0 = *offset1;
2010 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
2011 y_predecim + (fieldmode ? 1 : 0),
2012 ps);
2013 *pix_inc = pixinc(x_predecim * screen_width, ps);
2014 break;
2015
2016 case OMAP_DSS_ROT_180 + 4:
2017 *offset1 = screen_width * (fbh - 1) * ps;
2018 if (field_offset)
2019 *offset0 = *offset1 - field_offset * screen_width * ps;
2020 else
2021 *offset0 = *offset1;
2022 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
2023 (fieldmode ? screen_width : 0),
2024 ps);
2025 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2026 color_mode == OMAP_DSS_COLOR_UYVY)
2027 *pix_inc = pixinc(x_predecim, 2 * ps);
2028 else
2029 *pix_inc = pixinc(x_predecim, ps);
2030 break;
2031
2032 case OMAP_DSS_ROT_270 + 4:
2033 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
2034 if (field_offset)
2035 *offset0 = *offset1 - field_offset * ps;
2036 else
2037 *offset0 = *offset1;
2038 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
2039 y_predecim - (fieldmode ? 1 : 0),
2040 ps);
2041 *pix_inc = pixinc(-x_predecim * screen_width, ps);
2042 break;
2043
2044 default:
2045 BUG();
2046 return;
2047 }
2048 }
2049
2050 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
2051 enum omap_color_mode color_mode, bool fieldmode,
2052 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
2053 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
2054 {
2055 u8 ps;
2056
2057 switch (color_mode) {
2058 case OMAP_DSS_COLOR_CLUT1:
2059 case OMAP_DSS_COLOR_CLUT2:
2060 case OMAP_DSS_COLOR_CLUT4:
2061 case OMAP_DSS_COLOR_CLUT8:
2062 BUG();
2063 return;
2064 default:
2065 ps = color_mode_to_bpp(color_mode) / 8;
2066 break;
2067 }
2068
2069 DSSDBG("scrw %d, width %d\n", screen_width, width);
2070
2071 /*
2072 * field 0 = even field = bottom field
2073 * field 1 = odd field = top field
2074 */
2075 *offset1 = 0;
2076 if (field_offset)
2077 *offset0 = *offset1 + field_offset * screen_width * ps;
2078 else
2079 *offset0 = *offset1;
2080 *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
2081 (fieldmode ? screen_width : 0), ps);
2082 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2083 color_mode == OMAP_DSS_COLOR_UYVY)
2084 *pix_inc = pixinc(x_predecim, 2 * ps);
2085 else
2086 *pix_inc = pixinc(x_predecim, ps);
2087 }
2088
2089 /*
2090 * This function is used to avoid synclosts in OMAP3, because of some
2091 * undocumented horizontal position and timing related limitations.
2092 */
2093 static int check_horiz_timing_omap3(unsigned long pclk, unsigned long lclk,
2094 const struct omap_video_timings *t, u16 pos_x,
2095 u16 width, u16 height, u16 out_width, u16 out_height,
2096 bool five_taps)
2097 {
2098 const int ds = DIV_ROUND_UP(height, out_height);
2099 unsigned long nonactive;
2100 static const u8 limits[3] = { 8, 10, 20 };
2101 u64 val, blank;
2102 int i;
2103
2104 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
2105
2106 i = 0;
2107 if (out_height < height)
2108 i++;
2109 if (out_width < width)
2110 i++;
2111 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
2112 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
2113 if (blank <= limits[i])
2114 return -EINVAL;
2115
2116 /* FIXME add checks for 3-tap filter once the limitations are known */
2117 if (!five_taps)
2118 return 0;
2119
2120 /*
2121 * Pixel data should be prepared before visible display point starts.
2122 * So, atleast DS-2 lines must have already been fetched by DISPC
2123 * during nonactive - pos_x period.
2124 */
2125 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
2126 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
2127 val, max(0, ds - 2) * width);
2128 if (val < max(0, ds - 2) * width)
2129 return -EINVAL;
2130
2131 /*
2132 * All lines need to be refilled during the nonactive period of which
2133 * only one line can be loaded during the active period. So, atleast
2134 * DS - 1 lines should be loaded during nonactive period.
2135 */
2136 val = div_u64((u64)nonactive * lclk, pclk);
2137 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
2138 val, max(0, ds - 1) * width);
2139 if (val < max(0, ds - 1) * width)
2140 return -EINVAL;
2141
2142 return 0;
2143 }
2144
2145 static unsigned long calc_core_clk_five_taps(unsigned long pclk,
2146 const struct omap_video_timings *mgr_timings, u16 width,
2147 u16 height, u16 out_width, u16 out_height,
2148 enum omap_color_mode color_mode)
2149 {
2150 u32 core_clk = 0;
2151 u64 tmp;
2152
2153 if (height <= out_height && width <= out_width)
2154 return (unsigned long) pclk;
2155
2156 if (height > out_height) {
2157 unsigned int ppl = mgr_timings->x_res;
2158
2159 tmp = (u64)pclk * height * out_width;
2160 do_div(tmp, 2 * out_height * ppl);
2161 core_clk = tmp;
2162
2163 if (height > 2 * out_height) {
2164 if (ppl == out_width)
2165 return 0;
2166
2167 tmp = (u64)pclk * (height - 2 * out_height) * out_width;
2168 do_div(tmp, 2 * out_height * (ppl - out_width));
2169 core_clk = max_t(u32, core_clk, tmp);
2170 }
2171 }
2172
2173 if (width > out_width) {
2174 tmp = (u64)pclk * width;
2175 do_div(tmp, out_width);
2176 core_clk = max_t(u32, core_clk, tmp);
2177
2178 if (color_mode == OMAP_DSS_COLOR_RGB24U)
2179 core_clk <<= 1;
2180 }
2181
2182 return core_clk;
2183 }
2184
2185 static unsigned long calc_core_clk_24xx(unsigned long pclk, u16 width,
2186 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2187 {
2188 if (height > out_height && width > out_width)
2189 return pclk * 4;
2190 else
2191 return pclk * 2;
2192 }
2193
2194 static unsigned long calc_core_clk_34xx(unsigned long pclk, u16 width,
2195 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2196 {
2197 unsigned int hf, vf;
2198
2199 /*
2200 * FIXME how to determine the 'A' factor
2201 * for the no downscaling case ?
2202 */
2203
2204 if (width > 3 * out_width)
2205 hf = 4;
2206 else if (width > 2 * out_width)
2207 hf = 3;
2208 else if (width > out_width)
2209 hf = 2;
2210 else
2211 hf = 1;
2212 if (height > out_height)
2213 vf = 2;
2214 else
2215 vf = 1;
2216
2217 return pclk * vf * hf;
2218 }
2219
2220 static unsigned long calc_core_clk_44xx(unsigned long pclk, u16 width,
2221 u16 height, u16 out_width, u16 out_height, bool mem_to_mem)
2222 {
2223 /*
2224 * If the overlay/writeback is in mem to mem mode, there are no
2225 * downscaling limitations with respect to pixel clock, return 1 as
2226 * required core clock to represent that we have sufficient enough
2227 * core clock to do maximum downscaling
2228 */
2229 if (mem_to_mem)
2230 return 1;
2231
2232 if (width > out_width)
2233 return DIV_ROUND_UP(pclk, out_width) * width;
2234 else
2235 return pclk;
2236 }
2237
2238 static int dispc_ovl_calc_scaling_24xx(unsigned long pclk, unsigned long lclk,
2239 const struct omap_video_timings *mgr_timings,
2240 u16 width, u16 height, u16 out_width, u16 out_height,
2241 enum omap_color_mode color_mode, bool *five_taps,
2242 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2243 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2244 {
2245 int error;
2246 u16 in_width, in_height;
2247 int min_factor = min(*decim_x, *decim_y);
2248 const int maxsinglelinewidth =
2249 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2250
2251 *five_taps = false;
2252
2253 do {
2254 in_height = height / *decim_y;
2255 in_width = width / *decim_x;
2256 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2257 in_height, out_width, out_height, mem_to_mem);
2258 error = (in_width > maxsinglelinewidth || !*core_clk ||
2259 *core_clk > dispc_core_clk_rate());
2260 if (error) {
2261 if (*decim_x == *decim_y) {
2262 *decim_x = min_factor;
2263 ++*decim_y;
2264 } else {
2265 swap(*decim_x, *decim_y);
2266 if (*decim_x < *decim_y)
2267 ++*decim_x;
2268 }
2269 }
2270 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2271
2272 if (error) {
2273 DSSERR("failed to find scaling settings\n");
2274 return -EINVAL;
2275 }
2276
2277 if (in_width > maxsinglelinewidth) {
2278 DSSERR("Cannot scale max input width exceeded");
2279 return -EINVAL;
2280 }
2281 return 0;
2282 }
2283
2284 static int dispc_ovl_calc_scaling_34xx(unsigned long pclk, unsigned long lclk,
2285 const struct omap_video_timings *mgr_timings,
2286 u16 width, u16 height, u16 out_width, u16 out_height,
2287 enum omap_color_mode color_mode, bool *five_taps,
2288 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2289 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2290 {
2291 int error;
2292 u16 in_width, in_height;
2293 const int maxsinglelinewidth =
2294 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2295
2296 do {
2297 in_height = height / *decim_y;
2298 in_width = width / *decim_x;
2299 *five_taps = in_height > out_height;
2300
2301 if (in_width > maxsinglelinewidth)
2302 if (in_height > out_height &&
2303 in_height < out_height * 2)
2304 *five_taps = false;
2305 again:
2306 if (*five_taps)
2307 *core_clk = calc_core_clk_five_taps(pclk, mgr_timings,
2308 in_width, in_height, out_width,
2309 out_height, color_mode);
2310 else
2311 *core_clk = dispc.feat->calc_core_clk(pclk, in_width,
2312 in_height, out_width, out_height,
2313 mem_to_mem);
2314
2315 error = check_horiz_timing_omap3(pclk, lclk, mgr_timings,
2316 pos_x, in_width, in_height, out_width,
2317 out_height, *five_taps);
2318 if (error && *five_taps) {
2319 *five_taps = false;
2320 goto again;
2321 }
2322
2323 error = (error || in_width > maxsinglelinewidth * 2 ||
2324 (in_width > maxsinglelinewidth && *five_taps) ||
2325 !*core_clk || *core_clk > dispc_core_clk_rate());
2326
2327 if (!error) {
2328 /* verify that we're inside the limits of scaler */
2329 if (in_width / 4 > out_width)
2330 error = 1;
2331
2332 if (*five_taps) {
2333 if (in_height / 4 > out_height)
2334 error = 1;
2335 } else {
2336 if (in_height / 2 > out_height)
2337 error = 1;
2338 }
2339 }
2340
2341 if (error)
2342 ++*decim_y;
2343 } while (*decim_x <= *x_predecim && *decim_y <= *y_predecim && error);
2344
2345 if (error) {
2346 DSSERR("failed to find scaling settings\n");
2347 return -EINVAL;
2348 }
2349
2350 if (check_horiz_timing_omap3(pclk, lclk, mgr_timings, pos_x, in_width,
2351 in_height, out_width, out_height, *five_taps)) {
2352 DSSERR("horizontal timing too tight\n");
2353 return -EINVAL;
2354 }
2355
2356 if (in_width > (maxsinglelinewidth * 2)) {
2357 DSSERR("Cannot setup scaling");
2358 DSSERR("width exceeds maximum width possible");
2359 return -EINVAL;
2360 }
2361
2362 if (in_width > maxsinglelinewidth && *five_taps) {
2363 DSSERR("cannot setup scaling with five taps");
2364 return -EINVAL;
2365 }
2366 return 0;
2367 }
2368
2369 static int dispc_ovl_calc_scaling_44xx(unsigned long pclk, unsigned long lclk,
2370 const struct omap_video_timings *mgr_timings,
2371 u16 width, u16 height, u16 out_width, u16 out_height,
2372 enum omap_color_mode color_mode, bool *five_taps,
2373 int *x_predecim, int *y_predecim, int *decim_x, int *decim_y,
2374 u16 pos_x, unsigned long *core_clk, bool mem_to_mem)
2375 {
2376 u16 in_width, in_width_max;
2377 int decim_x_min = *decim_x;
2378 u16 in_height = height / *decim_y;
2379 const int maxsinglelinewidth =
2380 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2381 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2382
2383 if (mem_to_mem) {
2384 in_width_max = out_width * maxdownscale;
2385 } else {
2386 in_width_max = dispc_core_clk_rate() /
2387 DIV_ROUND_UP(pclk, out_width);
2388 }
2389
2390 *decim_x = DIV_ROUND_UP(width, in_width_max);
2391
2392 *decim_x = *decim_x > decim_x_min ? *decim_x : decim_x_min;
2393 if (*decim_x > *x_predecim)
2394 return -EINVAL;
2395
2396 do {
2397 in_width = width / *decim_x;
2398 } while (*decim_x <= *x_predecim &&
2399 in_width > maxsinglelinewidth && ++*decim_x);
2400
2401 if (in_width > maxsinglelinewidth) {
2402 DSSERR("Cannot scale width exceeds max line width");
2403 return -EINVAL;
2404 }
2405
2406 *core_clk = dispc.feat->calc_core_clk(pclk, in_width, in_height,
2407 out_width, out_height, mem_to_mem);
2408 return 0;
2409 }
2410
2411 #define DIV_FRAC(dividend, divisor) \
2412 ((dividend) * 100 / (divisor) - ((dividend) / (divisor) * 100))
2413
2414 static int dispc_ovl_calc_scaling(unsigned long pclk, unsigned long lclk,
2415 enum omap_overlay_caps caps,
2416 const struct omap_video_timings *mgr_timings,
2417 u16 width, u16 height, u16 out_width, u16 out_height,
2418 enum omap_color_mode color_mode, bool *five_taps,
2419 int *x_predecim, int *y_predecim, u16 pos_x,
2420 enum omap_dss_rotation_type rotation_type, bool mem_to_mem)
2421 {
2422 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2423 const int max_decim_limit = 16;
2424 unsigned long core_clk = 0;
2425 int decim_x, decim_y, ret;
2426
2427 if (width == out_width && height == out_height)
2428 return 0;
2429
2430 if (!mem_to_mem && (pclk == 0 || mgr_timings->pixelclock == 0)) {
2431 DSSERR("cannot calculate scaling settings: pclk is zero\n");
2432 return -EINVAL;
2433 }
2434
2435 if ((caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2436 return -EINVAL;
2437
2438 if (mem_to_mem) {
2439 *x_predecim = *y_predecim = 1;
2440 } else {
2441 *x_predecim = max_decim_limit;
2442 *y_predecim = (rotation_type == OMAP_DSS_ROT_TILER &&
2443 dss_has_feature(FEAT_BURST_2D)) ?
2444 2 : max_decim_limit;
2445 }
2446
2447 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2448 color_mode == OMAP_DSS_COLOR_CLUT2 ||
2449 color_mode == OMAP_DSS_COLOR_CLUT4 ||
2450 color_mode == OMAP_DSS_COLOR_CLUT8) {
2451 *x_predecim = 1;
2452 *y_predecim = 1;
2453 *five_taps = false;
2454 return 0;
2455 }
2456
2457 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2458 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2459
2460 if (decim_x > *x_predecim || out_width > width * 8)
2461 return -EINVAL;
2462
2463 if (decim_y > *y_predecim || out_height > height * 8)
2464 return -EINVAL;
2465
2466 ret = dispc.feat->calc_scaling(pclk, lclk, mgr_timings, width, height,
2467 out_width, out_height, color_mode, five_taps,
2468 x_predecim, y_predecim, &decim_x, &decim_y, pos_x, &core_clk,
2469 mem_to_mem);
2470 if (ret)
2471 return ret;
2472
2473 DSSDBG("%dx%d -> %dx%d (%d.%02d x %d.%02d), decim %dx%d %dx%d (%d.%02d x %d.%02d), taps %d, req clk %lu, cur clk %lu\n",
2474 width, height,
2475 out_width, out_height,
2476 out_width / width, DIV_FRAC(out_width, width),
2477 out_height / height, DIV_FRAC(out_height, height),
2478
2479 decim_x, decim_y,
2480 width / decim_x, height / decim_y,
2481 out_width / (width / decim_x), DIV_FRAC(out_width, width / decim_x),
2482 out_height / (height / decim_y), DIV_FRAC(out_height, height / decim_y),
2483
2484 *five_taps ? 5 : 3,
2485 core_clk, dispc_core_clk_rate());
2486
2487 if (!core_clk || core_clk > dispc_core_clk_rate()) {
2488 DSSERR("failed to set up scaling, "
2489 "required core clk rate = %lu Hz, "
2490 "current core clk rate = %lu Hz\n",
2491 core_clk, dispc_core_clk_rate());
2492 return -EINVAL;
2493 }
2494
2495 *x_predecim = decim_x;
2496 *y_predecim = decim_y;
2497 return 0;
2498 }
2499
2500 int dispc_ovl_check(enum omap_plane plane, enum omap_channel channel,
2501 const struct omap_overlay_info *oi,
2502 const struct omap_video_timings *timings,
2503 int *x_predecim, int *y_predecim)
2504 {
2505 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2506 bool five_taps = true;
2507 bool fieldmode = false;
2508 u16 in_height = oi->height;
2509 u16 in_width = oi->width;
2510 bool ilace = timings->interlace;
2511 u16 out_width, out_height;
2512 int pos_x = oi->pos_x;
2513 unsigned long pclk = dispc_mgr_pclk_rate(channel);
2514 unsigned long lclk = dispc_mgr_lclk_rate(channel);
2515
2516 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2517 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2518
2519 if (ilace && oi->height == out_height)
2520 fieldmode = true;
2521
2522 if (ilace) {
2523 if (fieldmode)
2524 in_height /= 2;
2525 out_height /= 2;
2526
2527 DSSDBG("adjusting for ilace: height %d, out_height %d\n",
2528 in_height, out_height);
2529 }
2530
2531 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2532 return -EINVAL;
2533
2534 return dispc_ovl_calc_scaling(pclk, lclk, caps, timings, in_width,
2535 in_height, out_width, out_height, oi->color_mode,
2536 &five_taps, x_predecim, y_predecim, pos_x,
2537 oi->rotation_type, false);
2538 }
2539 EXPORT_SYMBOL(dispc_ovl_check);
2540
2541 static int dispc_ovl_setup_common(enum omap_plane plane,
2542 enum omap_overlay_caps caps, u32 paddr, u32 p_uv_addr,
2543 u16 screen_width, int pos_x, int pos_y, u16 width, u16 height,
2544 u16 out_width, u16 out_height, enum omap_color_mode color_mode,
2545 u8 rotation, bool mirror, u8 zorder, u8 pre_mult_alpha,
2546 u8 global_alpha, enum omap_dss_rotation_type rotation_type,
2547 bool replication, const struct omap_video_timings *mgr_timings,
2548 bool mem_to_mem)
2549 {
2550 bool five_taps = true;
2551 bool fieldmode = false;
2552 int r, cconv = 0;
2553 unsigned offset0, offset1;
2554 s32 row_inc;
2555 s32 pix_inc;
2556 u16 frame_width, frame_height;
2557 unsigned int field_offset = 0;
2558 u16 in_height = height;
2559 u16 in_width = width;
2560 int x_predecim = 1, y_predecim = 1;
2561 bool ilace = mgr_timings->interlace;
2562 unsigned long pclk = dispc_plane_pclk_rate(plane);
2563 unsigned long lclk = dispc_plane_lclk_rate(plane);
2564
2565 if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER)
2566 return -EINVAL;
2567
2568 switch (color_mode) {
2569 case OMAP_DSS_COLOR_YUV2:
2570 case OMAP_DSS_COLOR_UYVY:
2571 case OMAP_DSS_COLOR_NV12:
2572 if (in_width & 1) {
2573 DSSERR("input width %d is not even for YUV format\n",
2574 in_width);
2575 return -EINVAL;
2576 }
2577 break;
2578
2579 default:
2580 break;
2581 }
2582
2583 out_width = out_width == 0 ? width : out_width;
2584 out_height = out_height == 0 ? height : out_height;
2585
2586 if (ilace && height == out_height)
2587 fieldmode = true;
2588
2589 if (ilace) {
2590 if (fieldmode)
2591 in_height /= 2;
2592 pos_y /= 2;
2593 out_height /= 2;
2594
2595 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2596 "out_height %d\n", in_height, pos_y,
2597 out_height);
2598 }
2599
2600 if (!dss_feat_color_mode_supported(plane, color_mode))
2601 return -EINVAL;
2602
2603 r = dispc_ovl_calc_scaling(pclk, lclk, caps, mgr_timings, in_width,
2604 in_height, out_width, out_height, color_mode,
2605 &five_taps, &x_predecim, &y_predecim, pos_x,
2606 rotation_type, mem_to_mem);
2607 if (r)
2608 return r;
2609
2610 in_width = in_width / x_predecim;
2611 in_height = in_height / y_predecim;
2612
2613 if (x_predecim > 1 || y_predecim > 1)
2614 DSSDBG("predecimation %d x %x, new input size %d x %d\n",
2615 x_predecim, y_predecim, in_width, in_height);
2616
2617 switch (color_mode) {
2618 case OMAP_DSS_COLOR_YUV2:
2619 case OMAP_DSS_COLOR_UYVY:
2620 case OMAP_DSS_COLOR_NV12:
2621 if (in_width & 1) {
2622 DSSDBG("predecimated input width is not even for YUV format\n");
2623 DSSDBG("adjusting input width %d -> %d\n",
2624 in_width, in_width & ~1);
2625
2626 in_width &= ~1;
2627 }
2628 break;
2629
2630 default:
2631 break;
2632 }
2633
2634 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
2635 color_mode == OMAP_DSS_COLOR_UYVY ||
2636 color_mode == OMAP_DSS_COLOR_NV12)
2637 cconv = 1;
2638
2639 if (ilace && !fieldmode) {
2640 /*
2641 * when downscaling the bottom field may have to start several
2642 * source lines below the top field. Unfortunately ACCUI
2643 * registers will only hold the fractional part of the offset
2644 * so the integer part must be added to the base address of the
2645 * bottom field.
2646 */
2647 if (!in_height || in_height == out_height)
2648 field_offset = 0;
2649 else
2650 field_offset = in_height / out_height / 2;
2651 }
2652
2653 /* Fields are independent but interleaved in memory. */
2654 if (fieldmode)
2655 field_offset = 1;
2656
2657 offset0 = 0;
2658 offset1 = 0;
2659 row_inc = 0;
2660 pix_inc = 0;
2661
2662 if (plane == OMAP_DSS_WB) {
2663 frame_width = out_width;
2664 frame_height = out_height;
2665 } else {
2666 frame_width = in_width;
2667 frame_height = height;
2668 }
2669
2670 if (rotation_type == OMAP_DSS_ROT_TILER)
2671 calc_tiler_rotation_offset(screen_width, frame_width,
2672 color_mode, fieldmode, field_offset,
2673 &offset0, &offset1, &row_inc, &pix_inc,
2674 x_predecim, y_predecim);
2675 else if (rotation_type == OMAP_DSS_ROT_DMA)
2676 calc_dma_rotation_offset(rotation, mirror, screen_width,
2677 frame_width, frame_height,
2678 color_mode, fieldmode, field_offset,
2679 &offset0, &offset1, &row_inc, &pix_inc,
2680 x_predecim, y_predecim);
2681 else
2682 calc_vrfb_rotation_offset(rotation, mirror,
2683 screen_width, frame_width, frame_height,
2684 color_mode, fieldmode, field_offset,
2685 &offset0, &offset1, &row_inc, &pix_inc,
2686 x_predecim, y_predecim);
2687
2688 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2689 offset0, offset1, row_inc, pix_inc);
2690
2691 dispc_ovl_set_color_mode(plane, color_mode);
2692
2693 dispc_ovl_configure_burst_type(plane, rotation_type);
2694
2695 dispc_ovl_set_ba0(plane, paddr + offset0);
2696 dispc_ovl_set_ba1(plane, paddr + offset1);
2697
2698 if (OMAP_DSS_COLOR_NV12 == color_mode) {
2699 dispc_ovl_set_ba0_uv(plane, p_uv_addr + offset0);
2700 dispc_ovl_set_ba1_uv(plane, p_uv_addr + offset1);
2701 }
2702
2703 if (dispc.feat->last_pixel_inc_missing)
2704 row_inc += pix_inc - 1;
2705
2706 dispc_ovl_set_row_inc(plane, row_inc);
2707 dispc_ovl_set_pix_inc(plane, pix_inc);
2708
2709 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, in_width,
2710 in_height, out_width, out_height);
2711
2712 dispc_ovl_set_pos(plane, caps, pos_x, pos_y);
2713
2714 dispc_ovl_set_input_size(plane, in_width, in_height);
2715
2716 if (caps & OMAP_DSS_OVL_CAP_SCALE) {
2717 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2718 out_height, ilace, five_taps, fieldmode,
2719 color_mode, rotation);
2720 dispc_ovl_set_output_size(plane, out_width, out_height);
2721 dispc_ovl_set_vid_color_conv(plane, cconv);
2722 }
2723
2724 dispc_ovl_set_rotation_attrs(plane, rotation, rotation_type, mirror,
2725 color_mode);
2726
2727 dispc_ovl_set_zorder(plane, caps, zorder);
2728 dispc_ovl_set_pre_mult_alpha(plane, caps, pre_mult_alpha);
2729 dispc_ovl_setup_global_alpha(plane, caps, global_alpha);
2730
2731 dispc_ovl_enable_replication(plane, caps, replication);
2732
2733 return 0;
2734 }
2735
2736 int dispc_ovl_setup(enum omap_plane plane, const struct omap_overlay_info *oi,
2737 bool replication, const struct omap_video_timings *mgr_timings,
2738 bool mem_to_mem)
2739 {
2740 int r;
2741 enum omap_overlay_caps caps = dss_feat_get_overlay_caps(plane);
2742 enum omap_channel channel;
2743
2744 channel = dispc_ovl_get_channel_out(plane);
2745
2746 DSSDBG("dispc_ovl_setup %d, pa %pad, pa_uv %pad, sw %d, %d,%d, %dx%d ->"
2747 " %dx%d, cmode %x, rot %d, mir %d, chan %d repl %d\n",
2748 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2749 oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
2750 oi->color_mode, oi->rotation, oi->mirror, channel, replication);
2751
2752 r = dispc_ovl_setup_common(plane, caps, oi->paddr, oi->p_uv_addr,
2753 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2754 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2755 oi->mirror, oi->zorder, oi->pre_mult_alpha, oi->global_alpha,
2756 oi->rotation_type, replication, mgr_timings, mem_to_mem);
2757
2758 return r;
2759 }
2760 EXPORT_SYMBOL(dispc_ovl_setup);
2761
2762 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2763 {
2764 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2765
2766 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2767
2768 return 0;
2769 }
2770 EXPORT_SYMBOL(dispc_ovl_enable);
2771
2772 bool dispc_ovl_enabled(enum omap_plane plane)
2773 {
2774 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0);
2775 }
2776 EXPORT_SYMBOL(dispc_ovl_enabled);
2777
2778 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2779 {
2780 mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2781 /* flush posted write */
2782 mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2783 }
2784 EXPORT_SYMBOL(dispc_mgr_enable);
2785
2786 bool dispc_mgr_is_enabled(enum omap_channel channel)
2787 {
2788 return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2789 }
2790 EXPORT_SYMBOL(dispc_mgr_is_enabled);
2791
2792 static void dispc_lcd_enable_signal_polarity(bool act_high)
2793 {
2794 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2795 return;
2796
2797 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2798 }
2799
2800 void dispc_lcd_enable_signal(bool enable)
2801 {
2802 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2803 return;
2804
2805 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2806 }
2807
2808 void dispc_pck_free_enable(bool enable)
2809 {
2810 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2811 return;
2812
2813 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2814 }
2815
2816 static void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2817 {
2818 mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2819 }
2820
2821
2822 static void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2823 {
2824 mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2825 }
2826
2827 static void dispc_set_loadmode(enum omap_dss_load_mode mode)
2828 {
2829 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2830 }
2831
2832
2833 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2834 {
2835 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2836 }
2837
2838 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2839 enum omap_dss_trans_key_type type,
2840 u32 trans_key)
2841 {
2842 mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2843
2844 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2845 }
2846
2847 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2848 {
2849 mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2850 }
2851
2852 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2853 bool enable)
2854 {
2855 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2856 return;
2857
2858 if (ch == OMAP_DSS_CHANNEL_LCD)
2859 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2860 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2861 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2862 }
2863
2864 void dispc_mgr_setup(enum omap_channel channel,
2865 const struct omap_overlay_manager_info *info)
2866 {
2867 dispc_mgr_set_default_color(channel, info->default_color);
2868 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2869 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2870 dispc_mgr_enable_alpha_fixed_zorder(channel,
2871 info->partial_alpha_enabled);
2872 if (dss_has_feature(FEAT_CPR)) {
2873 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2874 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2875 }
2876 }
2877 EXPORT_SYMBOL(dispc_mgr_setup);
2878
2879 static void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2880 {
2881 int code;
2882
2883 switch (data_lines) {
2884 case 12:
2885 code = 0;
2886 break;
2887 case 16:
2888 code = 1;
2889 break;
2890 case 18:
2891 code = 2;
2892 break;
2893 case 24:
2894 code = 3;
2895 break;
2896 default:
2897 BUG();
2898 return;
2899 }
2900
2901 mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2902 }
2903
2904 static void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2905 {
2906 u32 l;
2907 int gpout0, gpout1;
2908
2909 switch (mode) {
2910 case DSS_IO_PAD_MODE_RESET:
2911 gpout0 = 0;
2912 gpout1 = 0;
2913 break;
2914 case DSS_IO_PAD_MODE_RFBI:
2915 gpout0 = 1;
2916 gpout1 = 0;
2917 break;
2918 case DSS_IO_PAD_MODE_BYPASS:
2919 gpout0 = 1;
2920 gpout1 = 1;
2921 break;
2922 default:
2923 BUG();
2924 return;
2925 }
2926
2927 l = dispc_read_reg(DISPC_CONTROL);
2928 l = FLD_MOD(l, gpout0, 15, 15);
2929 l = FLD_MOD(l, gpout1, 16, 16);
2930 dispc_write_reg(DISPC_CONTROL, l);
2931 }
2932
2933 static void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2934 {
2935 mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2936 }
2937
2938 void dispc_mgr_set_lcd_config(enum omap_channel channel,
2939 const struct dss_lcd_mgr_config *config)
2940 {
2941 dispc_mgr_set_io_pad_mode(config->io_pad_mode);
2942
2943 dispc_mgr_enable_stallmode(channel, config->stallmode);
2944 dispc_mgr_enable_fifohandcheck(channel, config->fifohandcheck);
2945
2946 dispc_mgr_set_clock_div(channel, &config->clock_info);
2947
2948 dispc_mgr_set_tft_data_lines(channel, config->video_port_width);
2949
2950 dispc_lcd_enable_signal_polarity(config->lcden_sig_polarity);
2951
2952 dispc_mgr_set_lcd_type_tft(channel);
2953 }
2954 EXPORT_SYMBOL(dispc_mgr_set_lcd_config);
2955
2956 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2957 {
2958 return width <= dispc.feat->mgr_width_max &&
2959 height <= dispc.feat->mgr_height_max;
2960 }
2961
2962 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2963 int vsw, int vfp, int vbp)
2964 {
2965 if (hsw < 1 || hsw > dispc.feat->sw_max ||
2966 hfp < 1 || hfp > dispc.feat->hp_max ||
2967 hbp < 1 || hbp > dispc.feat->hp_max ||
2968 vsw < 1 || vsw > dispc.feat->sw_max ||
2969 vfp < 0 || vfp > dispc.feat->vp_max ||
2970 vbp < 0 || vbp > dispc.feat->vp_max)
2971 return false;
2972 return true;
2973 }
2974
2975 static bool _dispc_mgr_pclk_ok(enum omap_channel channel,
2976 unsigned long pclk)
2977 {
2978 if (dss_mgr_is_lcd(channel))
2979 return pclk <= dispc.feat->max_lcd_pclk;
2980 else
2981 return pclk <= dispc.feat->max_tv_pclk;
2982 }
2983
2984 bool dispc_mgr_timings_ok(enum omap_channel channel,
2985 const struct omap_video_timings *timings)
2986 {
2987 if (!_dispc_mgr_size_ok(timings->x_res, timings->y_res))
2988 return false;
2989
2990 if (!_dispc_mgr_pclk_ok(channel, timings->pixelclock))
2991 return false;
2992
2993 if (dss_mgr_is_lcd(channel)) {
2994 /* TODO: OMAP4+ supports interlace for LCD outputs */
2995 if (timings->interlace)
2996 return false;
2997
2998 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2999 timings->hbp, timings->vsw, timings->vfp,
3000 timings->vbp))
3001 return false;
3002 }
3003
3004 return true;
3005 }
3006
3007 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
3008 int hfp, int hbp, int vsw, int vfp, int vbp,
3009 enum omap_dss_signal_level vsync_level,
3010 enum omap_dss_signal_level hsync_level,
3011 enum omap_dss_signal_edge data_pclk_edge,
3012 enum omap_dss_signal_level de_level,
3013 enum omap_dss_signal_edge sync_pclk_edge)
3014
3015 {
3016 u32 timing_h, timing_v, l;
3017 bool onoff, rf, ipc, vs, hs, de;
3018
3019 timing_h = FLD_VAL(hsw-1, dispc.feat->sw_start, 0) |
3020 FLD_VAL(hfp-1, dispc.feat->fp_start, 8) |
3021 FLD_VAL(hbp-1, dispc.feat->bp_start, 20);
3022 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) |
3023 FLD_VAL(vfp, dispc.feat->fp_start, 8) |
3024 FLD_VAL(vbp, dispc.feat->bp_start, 20);
3025
3026 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
3027 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
3028
3029 switch (vsync_level) {
3030 case OMAPDSS_SIG_ACTIVE_LOW:
3031 vs = true;
3032 break;
3033 case OMAPDSS_SIG_ACTIVE_HIGH:
3034 vs = false;
3035 break;
3036 default:
3037 BUG();
3038 }
3039
3040 switch (hsync_level) {
3041 case OMAPDSS_SIG_ACTIVE_LOW:
3042 hs = true;
3043 break;
3044 case OMAPDSS_SIG_ACTIVE_HIGH:
3045 hs = false;
3046 break;
3047 default:
3048 BUG();
3049 }
3050
3051 switch (de_level) {
3052 case OMAPDSS_SIG_ACTIVE_LOW:
3053 de = true;
3054 break;
3055 case OMAPDSS_SIG_ACTIVE_HIGH:
3056 de = false;
3057 break;
3058 default:
3059 BUG();
3060 }
3061
3062 switch (data_pclk_edge) {
3063 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3064 ipc = false;
3065 break;
3066 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3067 ipc = true;
3068 break;
3069 default:
3070 BUG();
3071 }
3072
3073 /* always use the 'rf' setting */
3074 onoff = true;
3075
3076 switch (sync_pclk_edge) {
3077 case OMAPDSS_DRIVE_SIG_FALLING_EDGE:
3078 rf = false;
3079 break;
3080 case OMAPDSS_DRIVE_SIG_RISING_EDGE:
3081 rf = true;
3082 break;
3083 default:
3084 BUG();
3085 }
3086
3087 l = FLD_VAL(onoff, 17, 17) |
3088 FLD_VAL(rf, 16, 16) |
3089 FLD_VAL(de, 15, 15) |
3090 FLD_VAL(ipc, 14, 14) |
3091 FLD_VAL(hs, 13, 13) |
3092 FLD_VAL(vs, 12, 12);
3093
3094 /* always set ALIGN bit when available */
3095 if (dispc.feat->supports_sync_align)
3096 l |= (1 << 18);
3097
3098 dispc_write_reg(DISPC_POL_FREQ(channel), l);
3099
3100 if (dispc.syscon_pol) {
3101 const int shifts[] = {
3102 [OMAP_DSS_CHANNEL_LCD] = 0,
3103 [OMAP_DSS_CHANNEL_LCD2] = 1,
3104 [OMAP_DSS_CHANNEL_LCD3] = 2,
3105 };
3106
3107 u32 mask, val;
3108
3109 mask = (1 << 0) | (1 << 3) | (1 << 6);
3110 val = (rf << 0) | (ipc << 3) | (onoff << 6);
3111
3112 mask <<= 16 + shifts[channel];
3113 val <<= 16 + shifts[channel];
3114
3115 regmap_update_bits(dispc.syscon_pol, dispc.syscon_pol_offset,
3116 mask, val);
3117 }
3118 }
3119
3120 /* change name to mode? */
3121 void dispc_mgr_set_timings(enum omap_channel channel,
3122 const struct omap_video_timings *timings)
3123 {
3124 unsigned xtot, ytot;
3125 unsigned long ht, vt;
3126 struct omap_video_timings t = *timings;
3127
3128 DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
3129
3130 if (!dispc_mgr_timings_ok(channel, &t)) {
3131 BUG();
3132 return;
3133 }
3134
3135 if (dss_mgr_is_lcd(channel)) {
3136 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
3137 t.vfp, t.vbp, t.vsync_level, t.hsync_level,
3138 t.data_pclk_edge, t.de_level, t.sync_pclk_edge);
3139
3140 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
3141 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
3142
3143 ht = timings->pixelclock / xtot;
3144 vt = timings->pixelclock / xtot / ytot;
3145
3146 DSSDBG("pck %u\n", timings->pixelclock);
3147 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
3148 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
3149 DSSDBG("vsync_level %d hsync_level %d data_pclk_edge %d de_level %d sync_pclk_edge %d\n",
3150 t.vsync_level, t.hsync_level, t.data_pclk_edge,
3151 t.de_level, t.sync_pclk_edge);
3152
3153 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
3154 } else {
3155 if (t.interlace)
3156 t.y_res /= 2;
3157 }
3158
3159 dispc_mgr_set_size(channel, t.x_res, t.y_res);
3160 }
3161 EXPORT_SYMBOL(dispc_mgr_set_timings);
3162
3163 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
3164 u16 pck_div)
3165 {
3166 BUG_ON(lck_div < 1);
3167 BUG_ON(pck_div < 1);
3168
3169 dispc_write_reg(DISPC_DIVISORo(channel),
3170 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
3171
3172 if (!dss_has_feature(FEAT_CORE_CLK_DIV) &&
3173 channel == OMAP_DSS_CHANNEL_LCD)
3174 dispc.core_clk_rate = dispc_fclk_rate() / lck_div;
3175 }
3176
3177 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
3178 int *pck_div)
3179 {
3180 u32 l;
3181 l = dispc_read_reg(DISPC_DIVISORo(channel));
3182 *lck_div = FLD_GET(l, 23, 16);
3183 *pck_div = FLD_GET(l, 7, 0);
3184 }
3185
3186 static unsigned long dispc_fclk_rate(void)
3187 {
3188 struct dss_pll *pll;
3189 unsigned long r = 0;
3190
3191 switch (dss_get_dispc_clk_source()) {
3192 case OMAP_DSS_CLK_SRC_FCK:
3193 r = dss_get_dispc_clk_rate();
3194 break;
3195 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3196 pll = dss_pll_find("dsi0");
3197 if (!pll)
3198 pll = dss_pll_find("video0");
3199
3200 r = pll->cinfo.clkout[0];
3201 break;
3202 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3203 pll = dss_pll_find("dsi1");
3204 if (!pll)
3205 pll = dss_pll_find("video1");
3206
3207 r = pll->cinfo.clkout[0];
3208 break;
3209 default:
3210 BUG();
3211 return 0;
3212 }
3213
3214 return r;
3215 }
3216
3217 static unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
3218 {
3219 struct dss_pll *pll;
3220 int lcd;
3221 unsigned long r;
3222 u32 l;
3223
3224 if (dss_mgr_is_lcd(channel)) {
3225 l = dispc_read_reg(DISPC_DIVISORo(channel));
3226
3227 lcd = FLD_GET(l, 23, 16);
3228
3229 switch (dss_get_lcd_clk_source(channel)) {
3230 case OMAP_DSS_CLK_SRC_FCK:
3231 r = dss_get_dispc_clk_rate();
3232 break;
3233 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
3234 pll = dss_pll_find("dsi0");
3235 if (!pll)
3236 pll = dss_pll_find("video0");
3237
3238 r = pll->cinfo.clkout[0];
3239 break;
3240 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
3241 pll = dss_pll_find("dsi1");
3242 if (!pll)
3243 pll = dss_pll_find("video1");
3244
3245 r = pll->cinfo.clkout[0];
3246 break;
3247 default:
3248 BUG();
3249 return 0;
3250 }
3251
3252 return r / lcd;
3253 } else {
3254 return dispc_fclk_rate();
3255 }
3256 }
3257
3258 static unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
3259 {
3260 unsigned long r;
3261
3262 if (dss_mgr_is_lcd(channel)) {
3263 int pcd;
3264 u32 l;
3265
3266 l = dispc_read_reg(DISPC_DIVISORo(channel));
3267
3268 pcd = FLD_GET(l, 7, 0);
3269
3270 r = dispc_mgr_lclk_rate(channel);
3271
3272 return r / pcd;
3273 } else {
3274 return dispc.tv_pclk_rate;
3275 }
3276 }
3277
3278 void dispc_set_tv_pclk(unsigned long pclk)
3279 {
3280 dispc.tv_pclk_rate = pclk;
3281 }
3282
3283 static unsigned long dispc_core_clk_rate(void)
3284 {
3285 return dispc.core_clk_rate;
3286 }
3287
3288 static unsigned long dispc_plane_pclk_rate(enum omap_plane plane)
3289 {
3290 enum omap_channel channel;
3291
3292 if (plane == OMAP_DSS_WB)
3293 return 0;
3294
3295 channel = dispc_ovl_get_channel_out(plane);
3296
3297 return dispc_mgr_pclk_rate(channel);
3298 }
3299
3300 static unsigned long dispc_plane_lclk_rate(enum omap_plane plane)
3301 {
3302 enum omap_channel channel;
3303
3304 if (plane == OMAP_DSS_WB)
3305 return 0;
3306
3307 channel = dispc_ovl_get_channel_out(plane);
3308
3309 return dispc_mgr_lclk_rate(channel);
3310 }
3311
3312 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
3313 {
3314 int lcd, pcd;
3315 enum omap_dss_clk_source lcd_clk_src;
3316
3317 seq_printf(s, "- %s -\n", mgr_desc[channel].name);
3318
3319 lcd_clk_src = dss_get_lcd_clk_source(channel);
3320
3321 seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
3322 dss_get_generic_clk_source_name(lcd_clk_src),
3323 dss_feat_get_clk_source_name(lcd_clk_src));
3324
3325 dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
3326
3327 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3328 dispc_mgr_lclk_rate(channel), lcd);
3329 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
3330 dispc_mgr_pclk_rate(channel), pcd);
3331 }
3332
3333 void dispc_dump_clocks(struct seq_file *s)
3334 {
3335 int lcd;
3336 u32 l;
3337 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
3338
3339 if (dispc_runtime_get())
3340 return;
3341
3342 seq_printf(s, "- DISPC -\n");
3343
3344 seq_printf(s, "dispc fclk source = %s (%s)\n",
3345 dss_get_generic_clk_source_name(dispc_clk_src),
3346 dss_feat_get_clk_source_name(dispc_clk_src));
3347
3348 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
3349
3350 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3351 seq_printf(s, "- DISPC-CORE-CLK -\n");
3352 l = dispc_read_reg(DISPC_DIVISOR);
3353 lcd = FLD_GET(l, 23, 16);
3354
3355 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
3356 (dispc_fclk_rate()/lcd), lcd);
3357 }
3358
3359 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
3360
3361 if (dss_has_feature(FEAT_MGR_LCD2))
3362 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
3363 if (dss_has_feature(FEAT_MGR_LCD3))
3364 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
3365
3366 dispc_runtime_put();
3367 }
3368
3369 static void dispc_dump_regs(struct seq_file *s)
3370 {
3371 int i, j;
3372 const char *mgr_names[] = {
3373 [OMAP_DSS_CHANNEL_LCD] = "LCD",
3374 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
3375 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
3376 [OMAP_DSS_CHANNEL_LCD3] = "LCD3",
3377 };
3378 const char *ovl_names[] = {
3379 [OMAP_DSS_GFX] = "GFX",
3380 [OMAP_DSS_VIDEO1] = "VID1",
3381 [OMAP_DSS_VIDEO2] = "VID2",
3382 [OMAP_DSS_VIDEO3] = "VID3",
3383 [OMAP_DSS_WB] = "WB",
3384 };
3385 const char **p_names;
3386
3387 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
3388
3389 if (dispc_runtime_get())
3390 return;
3391
3392 /* DISPC common registers */
3393 DUMPREG(DISPC_REVISION);
3394 DUMPREG(DISPC_SYSCONFIG);
3395 DUMPREG(DISPC_SYSSTATUS);
3396 DUMPREG(DISPC_IRQSTATUS);
3397 DUMPREG(DISPC_IRQENABLE);
3398 DUMPREG(DISPC_CONTROL);
3399 DUMPREG(DISPC_CONFIG);
3400 DUMPREG(DISPC_CAPABLE);
3401 DUMPREG(DISPC_LINE_STATUS);
3402 DUMPREG(DISPC_LINE_NUMBER);
3403 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
3404 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
3405 DUMPREG(DISPC_GLOBAL_ALPHA);
3406 if (dss_has_feature(FEAT_MGR_LCD2)) {
3407 DUMPREG(DISPC_CONTROL2);
3408 DUMPREG(DISPC_CONFIG2);
3409 }
3410 if (dss_has_feature(FEAT_MGR_LCD3)) {
3411 DUMPREG(DISPC_CONTROL3);
3412 DUMPREG(DISPC_CONFIG3);
3413 }
3414 if (dss_has_feature(FEAT_MFLAG))
3415 DUMPREG(DISPC_GLOBAL_MFLAG_ATTRIBUTE);
3416
3417 #undef DUMPREG
3418
3419 #define DISPC_REG(i, name) name(i)
3420 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3421 (int)(48 - strlen(#r) - strlen(p_names[i])), " ", \
3422 dispc_read_reg(DISPC_REG(i, r)))
3423
3424 p_names = mgr_names;
3425
3426 /* DISPC channel specific registers */
3427 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3428 DUMPREG(i, DISPC_DEFAULT_COLOR);
3429 DUMPREG(i, DISPC_TRANS_COLOR);
3430 DUMPREG(i, DISPC_SIZE_MGR);
3431
3432 if (i == OMAP_DSS_CHANNEL_DIGIT)
3433 continue;
3434
3435 DUMPREG(i, DISPC_TIMING_H);
3436 DUMPREG(i, DISPC_TIMING_V);
3437 DUMPREG(i, DISPC_POL_FREQ);
3438 DUMPREG(i, DISPC_DIVISORo);
3439
3440 DUMPREG(i, DISPC_DATA_CYCLE1);
3441 DUMPREG(i, DISPC_DATA_CYCLE2);
3442 DUMPREG(i, DISPC_DATA_CYCLE3);
3443
3444 if (dss_has_feature(FEAT_CPR)) {
3445 DUMPREG(i, DISPC_CPR_COEF_R);
3446 DUMPREG(i, DISPC_CPR_COEF_G);
3447 DUMPREG(i, DISPC_CPR_COEF_B);
3448 }
3449 }
3450
3451 p_names = ovl_names;
3452
3453 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3454 DUMPREG(i, DISPC_OVL_BA0);
3455 DUMPREG(i, DISPC_OVL_BA1);
3456 DUMPREG(i, DISPC_OVL_POSITION);
3457 DUMPREG(i, DISPC_OVL_SIZE);
3458 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3459 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3460 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3461 DUMPREG(i, DISPC_OVL_ROW_INC);
3462 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3463
3464 if (dss_has_feature(FEAT_PRELOAD))
3465 DUMPREG(i, DISPC_OVL_PRELOAD);
3466 if (dss_has_feature(FEAT_MFLAG))
3467 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3468
3469 if (i == OMAP_DSS_GFX) {
3470 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3471 DUMPREG(i, DISPC_OVL_TABLE_BA);
3472 continue;
3473 }
3474
3475 DUMPREG(i, DISPC_OVL_FIR);
3476 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3477 DUMPREG(i, DISPC_OVL_ACCU0);
3478 DUMPREG(i, DISPC_OVL_ACCU1);
3479 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3480 DUMPREG(i, DISPC_OVL_BA0_UV);
3481 DUMPREG(i, DISPC_OVL_BA1_UV);
3482 DUMPREG(i, DISPC_OVL_FIR2);
3483 DUMPREG(i, DISPC_OVL_ACCU2_0);
3484 DUMPREG(i, DISPC_OVL_ACCU2_1);
3485 }
3486 if (dss_has_feature(FEAT_ATTR2))
3487 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3488 }
3489
3490 if (dispc.feat->has_writeback) {
3491 i = OMAP_DSS_WB;
3492 DUMPREG(i, DISPC_OVL_BA0);
3493 DUMPREG(i, DISPC_OVL_BA1);
3494 DUMPREG(i, DISPC_OVL_SIZE);
3495 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3496 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3497 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3498 DUMPREG(i, DISPC_OVL_ROW_INC);
3499 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3500
3501 if (dss_has_feature(FEAT_MFLAG))
3502 DUMPREG(i, DISPC_OVL_MFLAG_THRESHOLD);
3503
3504 DUMPREG(i, DISPC_OVL_FIR);
3505 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3506 DUMPREG(i, DISPC_OVL_ACCU0);
3507 DUMPREG(i, DISPC_OVL_ACCU1);
3508 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3509 DUMPREG(i, DISPC_OVL_BA0_UV);
3510 DUMPREG(i, DISPC_OVL_BA1_UV);
3511 DUMPREG(i, DISPC_OVL_FIR2);
3512 DUMPREG(i, DISPC_OVL_ACCU2_0);
3513 DUMPREG(i, DISPC_OVL_ACCU2_1);
3514 }
3515 if (dss_has_feature(FEAT_ATTR2))
3516 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3517 }
3518
3519 #undef DISPC_REG
3520 #undef DUMPREG
3521
3522 #define DISPC_REG(plane, name, i) name(plane, i)
3523 #define DUMPREG(plane, name, i) \
3524 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3525 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3526 dispc_read_reg(DISPC_REG(plane, name, i)))
3527
3528 /* Video pipeline coefficient registers */
3529
3530 /* start from OMAP_DSS_VIDEO1 */
3531 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3532 for (j = 0; j < 8; j++)
3533 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3534
3535 for (j = 0; j < 8; j++)
3536 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3537
3538 for (j = 0; j < 5; j++)
3539 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3540
3541 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3542 for (j = 0; j < 8; j++)
3543 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3544 }
3545
3546 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3547 for (j = 0; j < 8; j++)
3548 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3549
3550 for (j = 0; j < 8; j++)
3551 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3552
3553 for (j = 0; j < 8; j++)
3554 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3555 }
3556 }
3557
3558 dispc_runtime_put();
3559
3560 #undef DISPC_REG
3561 #undef DUMPREG
3562 }
3563
3564 /* calculate clock rates using dividers in cinfo */
3565 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3566 struct dispc_clock_info *cinfo)
3567 {
3568 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3569 return -EINVAL;
3570 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3571 return -EINVAL;
3572
3573 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3574 cinfo->pck = cinfo->lck / cinfo->pck_div;
3575
3576 return 0;
3577 }
3578
3579 bool dispc_div_calc(unsigned long dispc,
3580 unsigned long pck_min, unsigned long pck_max,
3581 dispc_div_calc_func func, void *data)
3582 {
3583 int lckd, lckd_start, lckd_stop;
3584 int pckd, pckd_start, pckd_stop;
3585 unsigned long pck, lck;
3586 unsigned long lck_max;
3587 unsigned long pckd_hw_min, pckd_hw_max;
3588 unsigned min_fck_per_pck;
3589 unsigned long fck;
3590
3591 #ifdef CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK
3592 min_fck_per_pck = CONFIG_FB_OMAP2_DSS_MIN_FCK_PER_PCK;
3593 #else
3594 min_fck_per_pck = 0;
3595 #endif
3596
3597 pckd_hw_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3598 pckd_hw_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3599
3600 lck_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
3601
3602 pck_min = pck_min ? pck_min : 1;
3603 pck_max = pck_max ? pck_max : ULONG_MAX;
3604
3605 lckd_start = max(DIV_ROUND_UP(dispc, lck_max), 1ul);
3606 lckd_stop = min(dispc / pck_min, 255ul);
3607
3608 for (lckd = lckd_start; lckd <= lckd_stop; ++lckd) {
3609 lck = dispc / lckd;
3610
3611 pckd_start = max(DIV_ROUND_UP(lck, pck_max), pckd_hw_min);
3612 pckd_stop = min(lck / pck_min, pckd_hw_max);
3613
3614 for (pckd = pckd_start; pckd <= pckd_stop; ++pckd) {
3615 pck = lck / pckd;
3616
3617 /*
3618 * For OMAP2/3 the DISPC fclk is the same as LCD's logic
3619 * clock, which means we're configuring DISPC fclk here
3620 * also. Thus we need to use the calculated lck. For
3621 * OMAP4+ the DISPC fclk is a separate clock.
3622 */
3623 if (dss_has_feature(FEAT_CORE_CLK_DIV))
3624 fck = dispc_core_clk_rate();
3625 else
3626 fck = lck;
3627
3628 if (fck < pck * min_fck_per_pck)
3629 continue;
3630
3631 if (func(lckd, pckd, lck, pck, data))
3632 return true;
3633 }
3634 }
3635
3636 return false;
3637 }
3638
3639 void dispc_mgr_set_clock_div(enum omap_channel channel,
3640 const struct dispc_clock_info *cinfo)
3641 {
3642 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3643 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3644
3645 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3646 }
3647
3648 u32 dispc_read_irqstatus(void)
3649 {
3650 return dispc_read_reg(DISPC_IRQSTATUS);
3651 }
3652 EXPORT_SYMBOL(dispc_read_irqstatus);
3653
3654 void dispc_clear_irqstatus(u32 mask)
3655 {
3656 dispc_write_reg(DISPC_IRQSTATUS, mask);
3657 }
3658 EXPORT_SYMBOL(dispc_clear_irqstatus);
3659
3660 u32 dispc_read_irqenable(void)
3661 {
3662 return dispc_read_reg(DISPC_IRQENABLE);
3663 }
3664 EXPORT_SYMBOL(dispc_read_irqenable);
3665
3666 void dispc_write_irqenable(u32 mask)
3667 {
3668 u32 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3669
3670 /* clear the irqstatus for newly enabled irqs */
3671 dispc_clear_irqstatus((mask ^ old_mask) & mask);
3672
3673 dispc_write_reg(DISPC_IRQENABLE, mask);
3674 }
3675 EXPORT_SYMBOL(dispc_write_irqenable);
3676
3677 void dispc_enable_sidle(void)
3678 {
3679 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3680 }
3681
3682 void dispc_disable_sidle(void)
3683 {
3684 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3685 }
3686
3687 static void _omap_dispc_initial_config(void)
3688 {
3689 u32 l;
3690
3691 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3692 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3693 l = dispc_read_reg(DISPC_DIVISOR);
3694 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3695 l = FLD_MOD(l, 1, 0, 0);
3696 l = FLD_MOD(l, 1, 23, 16);
3697 dispc_write_reg(DISPC_DIVISOR, l);
3698
3699 dispc.core_clk_rate = dispc_fclk_rate();
3700 }
3701
3702 /* FUNCGATED */
3703 if (dss_has_feature(FEAT_FUNCGATED))
3704 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3705
3706 dispc_setup_color_conv_coef();
3707
3708 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3709
3710 dispc_init_fifos();
3711
3712 dispc_configure_burst_sizes();
3713
3714 dispc_ovl_enable_zorder_planes();
3715
3716 if (dispc.feat->mstandby_workaround)
3717 REG_FLD_MOD(DISPC_MSTANDBY_CTRL, 1, 0, 0);
3718
3719 if (dss_has_feature(FEAT_MFLAG))
3720 dispc_init_mflag();
3721 }
3722
3723 static const struct dispc_features omap24xx_dispc_feats = {
3724 .sw_start = 5,
3725 .fp_start = 15,
3726 .bp_start = 27,
3727 .sw_max = 64,
3728 .vp_max = 255,
3729 .hp_max = 256,
3730 .mgr_width_start = 10,
3731 .mgr_height_start = 26,
3732 .mgr_width_max = 2048,
3733 .mgr_height_max = 2048,
3734 .max_lcd_pclk = 66500000,
3735 .calc_scaling = dispc_ovl_calc_scaling_24xx,
3736 .calc_core_clk = calc_core_clk_24xx,
3737 .num_fifos = 3,
3738 .no_framedone_tv = true,
3739 .set_max_preload = false,
3740 .last_pixel_inc_missing = true,
3741 };
3742
3743 static const struct dispc_features omap34xx_rev1_0_dispc_feats = {
3744 .sw_start = 5,
3745 .fp_start = 15,
3746 .bp_start = 27,
3747 .sw_max = 64,
3748 .vp_max = 255,
3749 .hp_max = 256,
3750 .mgr_width_start = 10,
3751 .mgr_height_start = 26,
3752 .mgr_width_max = 2048,
3753 .mgr_height_max = 2048,
3754 .max_lcd_pclk = 173000000,
3755 .max_tv_pclk = 59000000,
3756 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3757 .calc_core_clk = calc_core_clk_34xx,
3758 .num_fifos = 3,
3759 .no_framedone_tv = true,
3760 .set_max_preload = false,
3761 .last_pixel_inc_missing = true,
3762 };
3763
3764 static const struct dispc_features omap34xx_rev3_0_dispc_feats = {
3765 .sw_start = 7,
3766 .fp_start = 19,
3767 .bp_start = 31,
3768 .sw_max = 256,
3769 .vp_max = 4095,
3770 .hp_max = 4096,
3771 .mgr_width_start = 10,
3772 .mgr_height_start = 26,
3773 .mgr_width_max = 2048,
3774 .mgr_height_max = 2048,
3775 .max_lcd_pclk = 173000000,
3776 .max_tv_pclk = 59000000,
3777 .calc_scaling = dispc_ovl_calc_scaling_34xx,
3778 .calc_core_clk = calc_core_clk_34xx,
3779 .num_fifos = 3,
3780 .no_framedone_tv = true,
3781 .set_max_preload = false,
3782 .last_pixel_inc_missing = true,
3783 };
3784
3785 static const struct dispc_features omap44xx_dispc_feats = {
3786 .sw_start = 7,
3787 .fp_start = 19,
3788 .bp_start = 31,
3789 .sw_max = 256,
3790 .vp_max = 4095,
3791 .hp_max = 4096,
3792 .mgr_width_start = 10,
3793 .mgr_height_start = 26,
3794 .mgr_width_max = 2048,
3795 .mgr_height_max = 2048,
3796 .max_lcd_pclk = 170000000,
3797 .max_tv_pclk = 185625000,
3798 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3799 .calc_core_clk = calc_core_clk_44xx,
3800 .num_fifos = 5,
3801 .gfx_fifo_workaround = true,
3802 .set_max_preload = true,
3803 .supports_sync_align = true,
3804 .has_writeback = true,
3805 };
3806
3807 static const struct dispc_features omap54xx_dispc_feats = {
3808 .sw_start = 7,
3809 .fp_start = 19,
3810 .bp_start = 31,
3811 .sw_max = 256,
3812 .vp_max = 4095,
3813 .hp_max = 4096,
3814 .mgr_width_start = 11,
3815 .mgr_height_start = 27,
3816 .mgr_width_max = 4096,
3817 .mgr_height_max = 4096,
3818 .max_lcd_pclk = 170000000,
3819 .max_tv_pclk = 186000000,
3820 .calc_scaling = dispc_ovl_calc_scaling_44xx,
3821 .calc_core_clk = calc_core_clk_44xx,
3822 .num_fifos = 5,
3823 .gfx_fifo_workaround = true,
3824 .mstandby_workaround = true,
3825 .set_max_preload = true,
3826 .supports_sync_align = true,
3827 .has_writeback = true,
3828 };
3829
3830 static const struct dispc_features *dispc_get_features(void)
3831 {
3832 switch (omapdss_get_version()) {
3833 case OMAPDSS_VER_OMAP24xx:
3834 return &omap24xx_dispc_feats;
3835
3836 case OMAPDSS_VER_OMAP34xx_ES1:
3837 return &omap34xx_rev1_0_dispc_feats;
3838
3839 case OMAPDSS_VER_OMAP34xx_ES3:
3840 case OMAPDSS_VER_OMAP3630:
3841 case OMAPDSS_VER_AM35xx:
3842 case OMAPDSS_VER_AM43xx:
3843 return &omap34xx_rev3_0_dispc_feats;
3844
3845 case OMAPDSS_VER_OMAP4430_ES1:
3846 case OMAPDSS_VER_OMAP4430_ES2:
3847 case OMAPDSS_VER_OMAP4:
3848 return &omap44xx_dispc_feats;
3849
3850 case OMAPDSS_VER_OMAP5:
3851 case OMAPDSS_VER_DRA7xx:
3852 return &omap54xx_dispc_feats;
3853
3854 default:
3855 return NULL;
3856 }
3857 }
3858
3859 static irqreturn_t dispc_irq_handler(int irq, void *arg)
3860 {
3861 if (!dispc.is_enabled)
3862 return IRQ_NONE;
3863
3864 return dispc.user_handler(irq, dispc.user_data);
3865 }
3866
3867 int dispc_request_irq(irq_handler_t handler, void *dev_id)
3868 {
3869 int r;
3870
3871 if (dispc.user_handler != NULL)
3872 return -EBUSY;
3873
3874 dispc.user_handler = handler;
3875 dispc.user_data = dev_id;
3876
3877 /* ensure the dispc_irq_handler sees the values above */
3878 smp_wmb();
3879
3880 r = devm_request_irq(&dispc.pdev->dev, dispc.irq, dispc_irq_handler,
3881 IRQF_SHARED, "OMAP DISPC", &dispc);
3882 if (r) {
3883 dispc.user_handler = NULL;
3884 dispc.user_data = NULL;
3885 }
3886
3887 return r;
3888 }
3889 EXPORT_SYMBOL(dispc_request_irq);
3890
3891 void dispc_free_irq(void *dev_id)
3892 {
3893 devm_free_irq(&dispc.pdev->dev, dispc.irq, &dispc);
3894
3895 dispc.user_handler = NULL;
3896 dispc.user_data = NULL;
3897 }
3898 EXPORT_SYMBOL(dispc_free_irq);
3899
3900 /* DISPC HW IP initialisation */
3901 static int dispc_bind(struct device *dev, struct device *master, void *data)
3902 {
3903 struct platform_device *pdev = to_platform_device(dev);
3904 u32 rev;
3905 int r = 0;
3906 struct resource *dispc_mem;
3907 struct device_node *np = pdev->dev.of_node;
3908
3909 dispc.pdev = pdev;
3910
3911 spin_lock_init(&dispc.control_lock);
3912
3913 dispc.feat = dispc_get_features();
3914 if (!dispc.feat)
3915 return -ENODEV;
3916
3917 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3918 if (!dispc_mem) {
3919 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3920 return -EINVAL;
3921 }
3922
3923 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3924 resource_size(dispc_mem));
3925 if (!dispc.base) {
3926 DSSERR("can't ioremap DISPC\n");
3927 return -ENOMEM;
3928 }
3929
3930 dispc.irq = platform_get_irq(dispc.pdev, 0);
3931 if (dispc.irq < 0) {
3932 DSSERR("platform_get_irq failed\n");
3933 return -ENODEV;
3934 }
3935
3936 if (np && of_property_read_bool(np, "syscon-pol")) {
3937 dispc.syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol");
3938 if (IS_ERR(dispc.syscon_pol)) {
3939 dev_err(&pdev->dev, "failed to get syscon-pol regmap\n");
3940 return PTR_ERR(dispc.syscon_pol);
3941 }
3942
3943 if (of_property_read_u32_index(np, "syscon-pol", 1,
3944 &dispc.syscon_pol_offset)) {
3945 dev_err(&pdev->dev, "failed to get syscon-pol offset\n");
3946 return -EINVAL;
3947 }
3948 }
3949
3950 pm_runtime_enable(&pdev->dev);
3951
3952 r = dispc_runtime_get();
3953 if (r)
3954 goto err_runtime_get;
3955
3956 _omap_dispc_initial_config();
3957
3958 rev = dispc_read_reg(DISPC_REVISION);
3959 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3960 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3961
3962 dispc_runtime_put();
3963
3964 dss_init_overlay_managers();
3965
3966 dss_debugfs_create_file("dispc", dispc_dump_regs);
3967
3968 return 0;
3969
3970 err_runtime_get:
3971 pm_runtime_disable(&pdev->dev);
3972 return r;
3973 }
3974
3975 static void dispc_unbind(struct device *dev, struct device *master,
3976 void *data)
3977 {
3978 pm_runtime_disable(dev);
3979
3980 dss_uninit_overlay_managers();
3981 }
3982
3983 static const struct component_ops dispc_component_ops = {
3984 .bind = dispc_bind,
3985 .unbind = dispc_unbind,
3986 };
3987
3988 static int dispc_probe(struct platform_device *pdev)
3989 {
3990 return component_add(&pdev->dev, &dispc_component_ops);
3991 }
3992
3993 static void dispc_remove(struct platform_device *pdev)
3994 {
3995 component_del(&pdev->dev, &dispc_component_ops);
3996 }
3997
3998 static int dispc_runtime_suspend(struct device *dev)
3999 {
4000 dispc.is_enabled = false;
4001 /* ensure the dispc_irq_handler sees the is_enabled value */
4002 smp_wmb();
4003 /* wait for current handler to finish before turning the DISPC off */
4004 synchronize_irq(dispc.irq);
4005
4006 dispc_save_context();
4007
4008 return 0;
4009 }
4010
4011 static int dispc_runtime_resume(struct device *dev)
4012 {
4013 /*
4014 * The reset value for load mode is 0 (OMAP_DSS_LOAD_CLUT_AND_FRAME)
4015 * but we always initialize it to 2 (OMAP_DSS_LOAD_FRAME_ONLY) in
4016 * _omap_dispc_initial_config(). We can thus use it to detect if
4017 * we have lost register context.
4018 */
4019 if (REG_GET(DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) {
4020 _omap_dispc_initial_config();
4021
4022 dispc_restore_context();
4023 }
4024
4025 dispc.is_enabled = true;
4026 /* ensure the dispc_irq_handler sees the is_enabled value */
4027 smp_wmb();
4028
4029 return 0;
4030 }
4031
4032 static const struct dev_pm_ops dispc_pm_ops = {
4033 .runtime_suspend = dispc_runtime_suspend,
4034 .runtime_resume = dispc_runtime_resume,
4035 };
4036
4037 static const struct of_device_id dispc_of_match[] = {
4038 { .compatible = "ti,omap2-dispc", },
4039 { .compatible = "ti,omap3-dispc", },
4040 { .compatible = "ti,omap4-dispc", },
4041 { .compatible = "ti,omap5-dispc", },
4042 { .compatible = "ti,dra7-dispc", },
4043 {},
4044 };
4045
4046 static struct platform_driver omap_dispchw_driver = {
4047 .probe = dispc_probe,
4048 .remove = dispc_remove,
4049 .driver = {
4050 .name = "omapdss_dispc",
4051 .pm = &dispc_pm_ops,
4052 .of_match_table = dispc_of_match,
4053 .suppress_bind_attrs = true,
4054 },
4055 };
4056
4057 int __init dispc_init_platform_driver(void)
4058 {
4059 return platform_driver_register(&omap_dispchw_driver);
4060 }
4061
4062 void dispc_uninit_platform_driver(void)
4063 {
4064 platform_driver_unregister(&omap_dispchw_driver);
4065 }
Kernel DRM miscellaneous fixes and cross-tree changes