drivers/watchdog/mtk_wdt.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Mediatek Watchdog Driver
   4  *
   5  * Copyright (C) 2014 Matthias Brugger
   6  *
   7  * Matthias Brugger <matthias.bgg@gmail.com>
   8  *
   9  * Based on sunxi_wdt.c
  10  */
  11
  12 #include <dt-bindings/reset/mt2712-resets.h>
  13 #include <dt-bindings/reset/mediatek,mt6735-wdt.h>
  14 #include <dt-bindings/reset/mediatek,mt6795-resets.h>
  15 #include <dt-bindings/reset/mt7986-resets.h>
  16 #include <dt-bindings/reset/mt8183-resets.h>
  17 #include <dt-bindings/reset/mt8186-resets.h>
  18 #include <dt-bindings/reset/mt8188-resets.h>
  19 #include <dt-bindings/reset/mt8192-resets.h>
  20 #include <dt-bindings/reset/mt8195-resets.h>
  21 #include <linux/delay.h>
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/of.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/reset-controller.h>
  31 #include <linux/types.h>
  32 #include <linux/watchdog.h>
  33 #include <linux/interrupt.h>
  34
  35 #define WDT_MAX_TIMEOUT         31
  36 #define WDT_MIN_TIMEOUT         2
  37 #define WDT_LENGTH_TIMEOUT(n)   ((n) << 5)
  38
  39 #define WDT_LENGTH              0x04
  40 #define WDT_LENGTH_KEY          0x8
  41
  42 #define WDT_RST                 0x08
  43 #define WDT_RST_RELOAD          0x1971
  44
  45 #define WDT_MODE                0x00
  46 #define WDT_MODE_EN             (1 << 0)
  47 #define WDT_MODE_EXT_POL_LOW    (0 << 1)
  48 #define WDT_MODE_EXT_POL_HIGH   (1 << 1)
  49 #define WDT_MODE_EXRST_EN       (1 << 2)
  50 #define WDT_MODE_IRQ_EN         (1 << 3)
  51 #define WDT_MODE_AUTO_START     (1 << 4)
  52 #define WDT_MODE_DUAL_EN        (1 << 6)
  53 #define WDT_MODE_CNT_SEL        (1 << 8)
  54 #define WDT_MODE_KEY            0x22000000
  55
  56 #define WDT_SWRST               0x14
  57 #define WDT_SWRST_KEY           0x1209
  58
  59 #define WDT_SWSYSRST            0x18U
  60 #define WDT_SWSYS_RST_KEY       0x88000000
  61
  62 #define WDT_SWSYSRST_EN         0xfc
  63
  64 #define DRV_NAME                "mtk-wdt"
  65 #define DRV_VERSION             "1.0"
  66
  67 #define MT7988_TOPRGU_SW_RST_NUM        24
  68
  69 static bool nowayout = WATCHDOG_NOWAYOUT;
  70 static unsigned int timeout;
  71
  72 struct mtk_wdt_dev {
  73         struct watchdog_device wdt_dev;
  74         void __iomem *wdt_base;
  75         spinlock_t lock; /* protects WDT_SWSYSRST reg */
  76         struct reset_controller_dev rcdev;
  77         bool disable_wdt_extrst;
  78         bool reset_by_toprgu;
  79         bool has_swsysrst_en;
  80 };
  81
  82 struct mtk_wdt_data {
  83         int toprgu_sw_rst_num;
  84         bool has_swsysrst_en;
  85 };
  86
  87 static const struct mtk_wdt_data mt2712_data = {
  88         .toprgu_sw_rst_num = MT2712_TOPRGU_SW_RST_NUM,
  89 };
  90
  91 static const struct mtk_wdt_data mt6735_data = {
  92         .toprgu_sw_rst_num = MT6735_TOPRGU_RST_NUM,
  93 };
  94
  95 static const struct mtk_wdt_data mt6795_data = {
  96         .toprgu_sw_rst_num = MT6795_TOPRGU_SW_RST_NUM,
  97 };
  98
  99 static const struct mtk_wdt_data mt7986_data = {
 100         .toprgu_sw_rst_num = MT7986_TOPRGU_SW_RST_NUM,
 101 };
 102
 103 static const struct mtk_wdt_data mt7988_data = {
 104         .toprgu_sw_rst_num = MT7988_TOPRGU_SW_RST_NUM,
 105         .has_swsysrst_en = true,
 106 };
 107
 108 static const struct mtk_wdt_data mt8183_data = {
 109         .toprgu_sw_rst_num = MT8183_TOPRGU_SW_RST_NUM,
 110 };
 111
 112 static const struct mtk_wdt_data mt8186_data = {
 113         .toprgu_sw_rst_num = MT8186_TOPRGU_SW_RST_NUM,
 114 };
 115
 116 static const struct mtk_wdt_data mt8188_data = {
 117         .toprgu_sw_rst_num = MT8188_TOPRGU_SW_RST_NUM,
 118 };
 119
 120 static const struct mtk_wdt_data mt8192_data = {
 121         .toprgu_sw_rst_num = MT8192_TOPRGU_SW_RST_NUM,
 122 };
 123
 124 static const struct mtk_wdt_data mt8195_data = {
 125         .toprgu_sw_rst_num = MT8195_TOPRGU_SW_RST_NUM,
 126 };
 127
 128 /**
 129  * toprgu_reset_sw_en_unlocked() - enable/disable software control for reset bit
 130  * @data: Pointer to instance of driver data.
 131  * @id: Bit number identifying the reset to be enabled or disabled.
 132  * @enable: If true, enable software control for that bit, disable otherwise.
 133  *
 134  * Context: The caller must hold lock of struct mtk_wdt_dev.
 135  */
 136 static void toprgu_reset_sw_en_unlocked(struct mtk_wdt_dev *data,
 137                                         unsigned long id, bool enable)
 138 {
 139         u32 tmp;
 140
 141         tmp = readl(data->wdt_base + WDT_SWSYSRST_EN);
 142         if (enable)
 143                 tmp |= BIT(id);
 144         else
 145                 tmp &= ~BIT(id);
 146
 147         writel(tmp, data->wdt_base + WDT_SWSYSRST_EN);
 148 }
 149
 150 static int toprgu_reset_update(struct reset_controller_dev *rcdev,
 151                                unsigned long id, bool assert)
 152 {
 153         unsigned int tmp;
 154         unsigned long flags;
 155         struct mtk_wdt_dev *data =
 156                  container_of(rcdev, struct mtk_wdt_dev, rcdev);
 157
 158         spin_lock_irqsave(&data->lock, flags);
 159
 160         if (assert && data->has_swsysrst_en)
 161                 toprgu_reset_sw_en_unlocked(data, id, true);
 162
 163         tmp = readl(data->wdt_base + WDT_SWSYSRST);
 164         if (assert)
 165                 tmp |= BIT(id);
 166         else
 167                 tmp &= ~BIT(id);
 168         tmp |= WDT_SWSYS_RST_KEY;
 169         writel(tmp, data->wdt_base + WDT_SWSYSRST);
 170
 171         if (!assert && data->has_swsysrst_en)
 172                 toprgu_reset_sw_en_unlocked(data, id, false);
 173
 174         spin_unlock_irqrestore(&data->lock, flags);
 175
 176         return 0;
 177 }
 178
 179 static int toprgu_reset_assert(struct reset_controller_dev *rcdev,
 180                                unsigned long id)
 181 {
 182         return toprgu_reset_update(rcdev, id, true);
 183 }
 184
 185 static int toprgu_reset_deassert(struct reset_controller_dev *rcdev,
 186                                  unsigned long id)
 187 {
 188         return toprgu_reset_update(rcdev, id, false);
 189 }
 190
 191 static int toprgu_reset(struct reset_controller_dev *rcdev,
 192                         unsigned long id)
 193 {
 194         int ret;
 195
 196         ret = toprgu_reset_assert(rcdev, id);
 197         if (ret)
 198                 return ret;
 199
 200         return toprgu_reset_deassert(rcdev, id);
 201 }
 202
 203 static const struct reset_control_ops toprgu_reset_ops = {
 204         .assert = toprgu_reset_assert,
 205         .deassert = toprgu_reset_deassert,
 206         .reset = toprgu_reset,
 207 };
 208
 209 static int toprgu_register_reset_controller(struct platform_device *pdev,
 210                                             int rst_num)
 211 {
 212         int ret;
 213         struct mtk_wdt_dev *mtk_wdt = platform_get_drvdata(pdev);
 214
 215         spin_lock_init(&mtk_wdt->lock);
 216
 217         mtk_wdt->rcdev.owner = THIS_MODULE;
 218         mtk_wdt->rcdev.nr_resets = rst_num;
 219         mtk_wdt->rcdev.ops = &toprgu_reset_ops;
 220         mtk_wdt->rcdev.of_node = pdev->dev.of_node;
 221         ret = devm_reset_controller_register(&pdev->dev, &mtk_wdt->rcdev);
 222         if (ret != 0)
 223                 dev_err(&pdev->dev,
 224                         "couldn't register wdt reset controller: %d\n", ret);
 225         return ret;
 226 }
 227
 228 static int mtk_wdt_restart(struct watchdog_device *wdt_dev,
 229                            unsigned long action, void *data)
 230 {
 231         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 232         void __iomem *wdt_base;
 233         u32 reg;
 234
 235         wdt_base = mtk_wdt->wdt_base;
 236
 237         /* Enable reset in order to issue a system reset instead of an IRQ */
 238         reg = readl(wdt_base + WDT_MODE);
 239         reg &= ~WDT_MODE_IRQ_EN;
 240         writel(reg | WDT_MODE_KEY, wdt_base + WDT_MODE);
 241
 242         while (1) {
 243                 writel(WDT_SWRST_KEY, wdt_base + WDT_SWRST);
 244                 mdelay(5);
 245         }
 246
 247         return 0;
 248 }
 249
 250 static int mtk_wdt_ping(struct watchdog_device *wdt_dev)
 251 {
 252         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 253         void __iomem *wdt_base = mtk_wdt->wdt_base;
 254
 255         iowrite32(WDT_RST_RELOAD, wdt_base + WDT_RST);
 256
 257         return 0;
 258 }
 259
 260 static int mtk_wdt_set_timeout(struct watchdog_device *wdt_dev,
 261                                 unsigned int timeout)
 262 {
 263         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 264         void __iomem *wdt_base = mtk_wdt->wdt_base;
 265         u32 reg;
 266
 267         wdt_dev->timeout = timeout;
 268         /*
 269          * In dual mode, irq will be triggered at timeout / 2
 270          * the real timeout occurs at timeout
 271          */
 272         if (wdt_dev->pretimeout)
 273                 wdt_dev->pretimeout = timeout / 2;
 274
 275         /*
 276          * One bit is the value of 512 ticks
 277          * The clock has 32 KHz
 278          */
 279         reg = WDT_LENGTH_TIMEOUT((timeout - wdt_dev->pretimeout) << 6)
 280                         | WDT_LENGTH_KEY;
 281         iowrite32(reg, wdt_base + WDT_LENGTH);
 282
 283         mtk_wdt_ping(wdt_dev);
 284
 285         return 0;
 286 }
 287
 288 static void mtk_wdt_init(struct watchdog_device *wdt_dev)
 289 {
 290         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 291         void __iomem *wdt_base;
 292
 293         wdt_base = mtk_wdt->wdt_base;
 294
 295         if (readl(wdt_base + WDT_MODE) & WDT_MODE_EN) {
 296                 set_bit(WDOG_HW_RUNNING, &wdt_dev->status);
 297                 mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
 298         }
 299 }
 300
 301 static int mtk_wdt_stop(struct watchdog_device *wdt_dev)
 302 {
 303         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 304         void __iomem *wdt_base = mtk_wdt->wdt_base;
 305         u32 reg;
 306
 307         reg = readl(wdt_base + WDT_MODE);
 308         reg &= ~WDT_MODE_EN;
 309         reg |= WDT_MODE_KEY;
 310         iowrite32(reg, wdt_base + WDT_MODE);
 311
 312         return 0;
 313 }
 314
 315 static int mtk_wdt_start(struct watchdog_device *wdt_dev)
 316 {
 317         u32 reg;
 318         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdt_dev);
 319         void __iomem *wdt_base = mtk_wdt->wdt_base;
 320         int ret;
 321
 322         ret = mtk_wdt_set_timeout(wdt_dev, wdt_dev->timeout);
 323         if (ret < 0)
 324                 return ret;
 325
 326         reg = ioread32(wdt_base + WDT_MODE);
 327         if (wdt_dev->pretimeout)
 328                 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
 329         else
 330                 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
 331         if (mtk_wdt->disable_wdt_extrst)
 332                 reg &= ~WDT_MODE_EXRST_EN;
 333         if (mtk_wdt->reset_by_toprgu)
 334                 reg |= WDT_MODE_CNT_SEL;
 335         reg |= (WDT_MODE_EN | WDT_MODE_KEY);
 336         iowrite32(reg, wdt_base + WDT_MODE);
 337
 338         return 0;
 339 }
 340
 341 static int mtk_wdt_set_pretimeout(struct watchdog_device *wdd,
 342                                   unsigned int timeout)
 343 {
 344         struct mtk_wdt_dev *mtk_wdt = watchdog_get_drvdata(wdd);
 345         void __iomem *wdt_base = mtk_wdt->wdt_base;
 346         u32 reg = ioread32(wdt_base + WDT_MODE);
 347
 348         if (timeout && !wdd->pretimeout) {
 349                 wdd->pretimeout = wdd->timeout / 2;
 350                 reg |= (WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
 351         } else if (!timeout && wdd->pretimeout) {
 352                 wdd->pretimeout = 0;
 353                 reg &= ~(WDT_MODE_IRQ_EN | WDT_MODE_DUAL_EN);
 354         } else {
 355                 return 0;
 356         }
 357
 358         reg |= WDT_MODE_KEY;
 359         iowrite32(reg, wdt_base + WDT_MODE);
 360
 361         return mtk_wdt_set_timeout(wdd, wdd->timeout);
 362 }
 363
 364 static irqreturn_t mtk_wdt_isr(int irq, void *arg)
 365 {
 366         struct watchdog_device *wdd = arg;
 367
 368         watchdog_notify_pretimeout(wdd);
 369
 370         return IRQ_HANDLED;
 371 }
 372
 373 static const struct watchdog_info mtk_wdt_info = {
 374         .identity       = DRV_NAME,
 375         .options        = WDIOF_SETTIMEOUT |
 376                           WDIOF_KEEPALIVEPING |
 377                           WDIOF_MAGICCLOSE,
 378 };
 379
 380 static const struct watchdog_info mtk_wdt_pt_info = {
 381         .identity       = DRV_NAME,
 382         .options        = WDIOF_SETTIMEOUT |
 383                           WDIOF_PRETIMEOUT |
 384                           WDIOF_KEEPALIVEPING |
 385                           WDIOF_MAGICCLOSE,
 386 };
 387
 388 static const struct watchdog_ops mtk_wdt_ops = {
 389         .owner          = THIS_MODULE,
 390         .start          = mtk_wdt_start,
 391         .stop           = mtk_wdt_stop,
 392         .ping           = mtk_wdt_ping,
 393         .set_timeout    = mtk_wdt_set_timeout,
 394         .set_pretimeout = mtk_wdt_set_pretimeout,
 395         .restart        = mtk_wdt_restart,
 396 };
 397
 398 static int mtk_wdt_probe(struct platform_device *pdev)
 399 {
 400         struct device *dev = &pdev->dev;
 401         struct mtk_wdt_dev *mtk_wdt;
 402         const struct mtk_wdt_data *wdt_data;
 403         int err, irq;
 404
 405         mtk_wdt = devm_kzalloc(dev, sizeof(*mtk_wdt), GFP_KERNEL);
 406         if (!mtk_wdt)
 407                 return -ENOMEM;
 408
 409         platform_set_drvdata(pdev, mtk_wdt);
 410
 411         mtk_wdt->wdt_base = devm_platform_ioremap_resource(pdev, 0);
 412         if (IS_ERR(mtk_wdt->wdt_base))
 413                 return PTR_ERR(mtk_wdt->wdt_base);
 414
 415         irq = platform_get_irq_optional(pdev, 0);
 416         if (irq > 0) {
 417                 err = devm_request_irq(&pdev->dev, irq, mtk_wdt_isr, 0, "wdt_bark",
 418                                        &mtk_wdt->wdt_dev);
 419                 if (err)
 420                         return err;
 421
 422                 mtk_wdt->wdt_dev.info = &mtk_wdt_pt_info;
 423                 mtk_wdt->wdt_dev.pretimeout = WDT_MAX_TIMEOUT / 2;
 424         } else {
 425                 if (irq == -EPROBE_DEFER)
 426                         return -EPROBE_DEFER;
 427
 428                 mtk_wdt->wdt_dev.info = &mtk_wdt_info;
 429         }
 430
 431         mtk_wdt->wdt_dev.ops = &mtk_wdt_ops;
 432         mtk_wdt->wdt_dev.timeout = WDT_MAX_TIMEOUT;
 433         mtk_wdt->wdt_dev.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT * 1000;
 434         mtk_wdt->wdt_dev.min_timeout = WDT_MIN_TIMEOUT;
 435         mtk_wdt->wdt_dev.parent = dev;
 436
 437         watchdog_init_timeout(&mtk_wdt->wdt_dev, timeout, dev);
 438         watchdog_set_nowayout(&mtk_wdt->wdt_dev, nowayout);
 439         watchdog_set_restart_priority(&mtk_wdt->wdt_dev, 128);
 440
 441         watchdog_set_drvdata(&mtk_wdt->wdt_dev, mtk_wdt);
 442
 443         mtk_wdt_init(&mtk_wdt->wdt_dev);
 444
 445         watchdog_stop_on_reboot(&mtk_wdt->wdt_dev);
 446         err = devm_watchdog_register_device(dev, &mtk_wdt->wdt_dev);
 447         if (unlikely(err))
 448                 return err;
 449
 450         dev_info(dev, "Watchdog enabled (timeout=%d sec, nowayout=%d)\n",
 451                  mtk_wdt->wdt_dev.timeout, nowayout);
 452
 453         wdt_data = of_device_get_match_data(dev);
 454         if (wdt_data) {
 455                 err = toprgu_register_reset_controller(pdev,
 456                                                        wdt_data->toprgu_sw_rst_num);
 457                 if (err)
 458                         return err;
 459
 460                 mtk_wdt->has_swsysrst_en = wdt_data->has_swsysrst_en;
 461         }
 462
 463         mtk_wdt->disable_wdt_extrst =
 464                 of_property_read_bool(dev->of_node, "mediatek,disable-extrst");
 465
 466         mtk_wdt->reset_by_toprgu =
 467                 of_property_read_bool(dev->of_node, "mediatek,reset-by-toprgu");
 468
 469         return 0;
 470 }
 471
 472 static int mtk_wdt_suspend(struct device *dev)
 473 {
 474         struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
 475
 476         if (watchdog_active(&mtk_wdt->wdt_dev))
 477                 mtk_wdt_stop(&mtk_wdt->wdt_dev);
 478
 479         return 0;
 480 }
 481
 482 static int mtk_wdt_resume(struct device *dev)
 483 {
 484         struct mtk_wdt_dev *mtk_wdt = dev_get_drvdata(dev);
 485
 486         if (watchdog_active(&mtk_wdt->wdt_dev)) {
 487                 mtk_wdt_start(&mtk_wdt->wdt_dev);
 488                 mtk_wdt_ping(&mtk_wdt->wdt_dev);
 489         }
 490
 491         return 0;
 492 }
 493
 494 static const struct of_device_id mtk_wdt_dt_ids[] = {
 495         { .compatible = "mediatek,mt2712-wdt", .data = &mt2712_data },
 496         { .compatible = "mediatek,mt6589-wdt" },
 497         { .compatible = "mediatek,mt6735-wdt", .data = &mt6735_data },
 498         { .compatible = "mediatek,mt6795-wdt", .data = &mt6795_data },
 499         { .compatible = "mediatek,mt7986-wdt", .data = &mt7986_data },
 500         { .compatible = "mediatek,mt7988-wdt", .data = &mt7988_data },
 501         { .compatible = "mediatek,mt8183-wdt", .data = &mt8183_data },
 502         { .compatible = "mediatek,mt8186-wdt", .data = &mt8186_data },
 503         { .compatible = "mediatek,mt8188-wdt", .data = &mt8188_data },
 504         { .compatible = "mediatek,mt8192-wdt", .data = &mt8192_data },
 505         { .compatible = "mediatek,mt8195-wdt", .data = &mt8195_data },
 506         { /* sentinel */ }
 507 };
 508 MODULE_DEVICE_TABLE(of, mtk_wdt_dt_ids);
 509
 510 static DEFINE_SIMPLE_DEV_PM_OPS(mtk_wdt_pm_ops,
 511                                 mtk_wdt_suspend, mtk_wdt_resume);
 512
 513 static struct platform_driver mtk_wdt_driver = {
 514         .probe          = mtk_wdt_probe,
 515         .driver         = {
 516                 .name           = DRV_NAME,
 517                 .pm             = pm_sleep_ptr(&mtk_wdt_pm_ops),
 518                 .of_match_table = mtk_wdt_dt_ids,
 519         },
 520 };
 521
 522 module_platform_driver(mtk_wdt_driver);
 523
 524 module_param(timeout, uint, 0);
 525 MODULE_PARM_DESC(timeout, "Watchdog heartbeat in seconds");
 526
 527 module_param(nowayout, bool, 0);
 528 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
 529                         __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
 530
 531 MODULE_LICENSE("GPL");
 532 MODULE_AUTHOR("Matthias Brugger <matthias.bgg@gmail.com>");
 533 MODULE_DESCRIPTION("Mediatek WatchDog Timer Driver");
 534 MODULE_VERSION(DRV_VERSION);