include/asm-generic/io.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2 /* Generic I/O port emulation.
   3  *
   4  * Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
   5  * Written by David Howells (dhowells@redhat.com)
   6  */
   7 #ifndef __ASM_GENERIC_IO_H
   8 #define __ASM_GENERIC_IO_H
   9
  10 #include <asm/page.h> /* I/O is all done through memory accesses */
  11 #include <linux/string.h> /* for memset() and memcpy() */
  12 #include <linux/sizes.h>
  13 #include <linux/types.h>
  14 #include <linux/instruction_pointer.h>
  15
  16 #ifdef CONFIG_GENERIC_IOMAP
  17 #include <asm-generic/iomap.h>
  18 #endif
  19
  20 #include <asm/mmiowb.h>
  21 #include <asm-generic/pci_iomap.h>
  22
  23 #ifndef __io_br
  24 #define __io_br()      barrier()
  25 #endif
  26
  27 /* prevent prefetching of coherent DMA data ahead of a dma-complete */
  28 #ifndef __io_ar
  29 #ifdef rmb
  30 #define __io_ar(v)      rmb()
  31 #else
  32 #define __io_ar(v)      barrier()
  33 #endif
  34 #endif
  35
  36 /* flush writes to coherent DMA data before possibly triggering a DMA read */
  37 #ifndef __io_bw
  38 #ifdef wmb
  39 #define __io_bw()      wmb()
  40 #else
  41 #define __io_bw()      barrier()
  42 #endif
  43 #endif
  44
  45 /* serialize device access against a spin_unlock, usually handled there. */
  46 #ifndef __io_aw
  47 #define __io_aw()      mmiowb_set_pending()
  48 #endif
  49
  50 #ifndef __io_pbw
  51 #define __io_pbw()     __io_bw()
  52 #endif
  53
  54 #ifndef __io_paw
  55 #define __io_paw()     __io_aw()
  56 #endif
  57
  58 #ifndef __io_pbr
  59 #define __io_pbr()     __io_br()
  60 #endif
  61
  62 #ifndef __io_par
  63 #define __io_par(v)     __io_ar(v)
  64 #endif
  65
  66 /*
  67  * "__DISABLE_TRACE_MMIO__" flag can be used to disable MMIO tracing for
  68  * specific kernel drivers in case of excessive/unwanted logging.
  69  *
  70  * Usage: Add a #define flag at the beginning of the driver file.
  71  * Ex: #define __DISABLE_TRACE_MMIO__
  72  *     #include <...>
  73  *     ...
  74  */
  75 #if IS_ENABLED(CONFIG_TRACE_MMIO_ACCESS) && !(defined(__DISABLE_TRACE_MMIO__))
  76 #include <linux/tracepoint-defs.h>
  77
  78 DECLARE_TRACEPOINT(rwmmio_write);
  79 DECLARE_TRACEPOINT(rwmmio_post_write);
  80 DECLARE_TRACEPOINT(rwmmio_read);
  81 DECLARE_TRACEPOINT(rwmmio_post_read);
  82
  83 void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
  84                     unsigned long caller_addr, unsigned long caller_addr0);
  85 void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
  86                          unsigned long caller_addr, unsigned long caller_addr0);
  87 void log_read_mmio(u8 width, const volatile void __iomem *addr,
  88                    unsigned long caller_addr, unsigned long caller_addr0);
  89 void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
  90                         unsigned long caller_addr, unsigned long caller_addr0);
  91
  92 #else
  93
  94 static inline void log_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
  95                                   unsigned long caller_addr, unsigned long caller_addr0) {}
  96 static inline void log_post_write_mmio(u64 val, u8 width, volatile void __iomem *addr,
  97                                        unsigned long caller_addr, unsigned long caller_addr0) {}
  98 static inline void log_read_mmio(u8 width, const volatile void __iomem *addr,
  99                                  unsigned long caller_addr, unsigned long caller_addr0) {}
 100 static inline void log_post_read_mmio(u64 val, u8 width, const volatile void __iomem *addr,
 101                                       unsigned long caller_addr, unsigned long caller_addr0) {}
 102
 103 #endif /* CONFIG_TRACE_MMIO_ACCESS */
 104
 105 /*
 106  * __raw_{read,write}{b,w,l,q}() access memory in native endianness.
 107  *
 108  * On some architectures memory mapped IO needs to be accessed differently.
 109  * On the simple architectures, we just read/write the memory location
 110  * directly.
 111  */
 112
 113 #ifndef __raw_readb
 114 #define __raw_readb __raw_readb
 115 static inline u8 __raw_readb(const volatile void __iomem *addr)
 116 {
 117         return *(const volatile u8 __force *)addr;
 118 }
 119 #endif
 120
 121 #ifndef __raw_readw
 122 #define __raw_readw __raw_readw
 123 static inline u16 __raw_readw(const volatile void __iomem *addr)
 124 {
 125         return *(const volatile u16 __force *)addr;
 126 }
 127 #endif
 128
 129 #ifndef __raw_readl
 130 #define __raw_readl __raw_readl
 131 static inline u32 __raw_readl(const volatile void __iomem *addr)
 132 {
 133         return *(const volatile u32 __force *)addr;
 134 }
 135 #endif
 136
 137 #ifdef CONFIG_64BIT
 138 #ifndef __raw_readq
 139 #define __raw_readq __raw_readq
 140 static inline u64 __raw_readq(const volatile void __iomem *addr)
 141 {
 142         return *(const volatile u64 __force *)addr;
 143 }
 144 #endif
 145 #endif /* CONFIG_64BIT */
 146
 147 #ifndef __raw_writeb
 148 #define __raw_writeb __raw_writeb
 149 static inline void __raw_writeb(u8 value, volatile void __iomem *addr)
 150 {
 151         *(volatile u8 __force *)addr = value;
 152 }
 153 #endif
 154
 155 #ifndef __raw_writew
 156 #define __raw_writew __raw_writew
 157 static inline void __raw_writew(u16 value, volatile void __iomem *addr)
 158 {
 159         *(volatile u16 __force *)addr = value;
 160 }
 161 #endif
 162
 163 #ifndef __raw_writel
 164 #define __raw_writel __raw_writel
 165 static inline void __raw_writel(u32 value, volatile void __iomem *addr)
 166 {
 167         *(volatile u32 __force *)addr = value;
 168 }
 169 #endif
 170
 171 #ifdef CONFIG_64BIT
 172 #ifndef __raw_writeq
 173 #define __raw_writeq __raw_writeq
 174 static inline void __raw_writeq(u64 value, volatile void __iomem *addr)
 175 {
 176         *(volatile u64 __force *)addr = value;
 177 }
 178 #endif
 179 #endif /* CONFIG_64BIT */
 180
 181 /*
 182  * {read,write}{b,w,l,q}() access little endian memory and return result in
 183  * native endianness.
 184  */
 185
 186 #ifndef readb
 187 #define readb readb
 188 static inline u8 readb(const volatile void __iomem *addr)
 189 {
 190         u8 val;
 191
 192         log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);
 193         __io_br();
 194         val = __raw_readb(addr);
 195         __io_ar(val);
 196         log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_);
 197         return val;
 198 }
 199 #endif
 200
 201 #ifndef readw
 202 #define readw readw
 203 static inline u16 readw(const volatile void __iomem *addr)
 204 {
 205         u16 val;
 206
 207         log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);
 208         __io_br();
 209         val = __le16_to_cpu((__le16 __force)__raw_readw(addr));
 210         __io_ar(val);
 211         log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_);
 212         return val;
 213 }
 214 #endif
 215
 216 #ifndef readl
 217 #define readl readl
 218 static inline u32 readl(const volatile void __iomem *addr)
 219 {
 220         u32 val;
 221
 222         log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);
 223         __io_br();
 224         val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
 225         __io_ar(val);
 226         log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_);
 227         return val;
 228 }
 229 #endif
 230
 231 #ifdef CONFIG_64BIT
 232 #ifndef readq
 233 #define readq readq
 234 static inline u64 readq(const volatile void __iomem *addr)
 235 {
 236         u64 val;
 237
 238         log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);
 239         __io_br();
 240         val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
 241         __io_ar(val);
 242         log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_);
 243         return val;
 244 }
 245 #endif
 246 #endif /* CONFIG_64BIT */
 247
 248 #ifndef writeb
 249 #define writeb writeb
 250 static inline void writeb(u8 value, volatile void __iomem *addr)
 251 {
 252         log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
 253         __io_bw();
 254         __raw_writeb(value, addr);
 255         __io_aw();
 256         log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
 257 }
 258 #endif
 259
 260 #ifndef writew
 261 #define writew writew
 262 static inline void writew(u16 value, volatile void __iomem *addr)
 263 {
 264         log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
 265         __io_bw();
 266         __raw_writew((u16 __force)cpu_to_le16(value), addr);
 267         __io_aw();
 268         log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
 269 }
 270 #endif
 271
 272 #ifndef writel
 273 #define writel writel
 274 static inline void writel(u32 value, volatile void __iomem *addr)
 275 {
 276         log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
 277         __io_bw();
 278         __raw_writel((u32 __force)__cpu_to_le32(value), addr);
 279         __io_aw();
 280         log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
 281 }
 282 #endif
 283
 284 #ifdef CONFIG_64BIT
 285 #ifndef writeq
 286 #define writeq writeq
 287 static inline void writeq(u64 value, volatile void __iomem *addr)
 288 {
 289         log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
 290         __io_bw();
 291         __raw_writeq((u64 __force)__cpu_to_le64(value), addr);
 292         __io_aw();
 293         log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
 294 }
 295 #endif
 296 #endif /* CONFIG_64BIT */
 297
 298 /*
 299  * {read,write}{b,w,l,q}_relaxed() are like the regular version, but
 300  * are not guaranteed to provide ordering against spinlocks or memory
 301  * accesses.
 302  */
 303 #ifndef readb_relaxed
 304 #define readb_relaxed readb_relaxed
 305 static inline u8 readb_relaxed(const volatile void __iomem *addr)
 306 {
 307         u8 val;
 308
 309         log_read_mmio(8, addr, _THIS_IP_, _RET_IP_);
 310         val = __raw_readb(addr);
 311         log_post_read_mmio(val, 8, addr, _THIS_IP_, _RET_IP_);
 312         return val;
 313 }
 314 #endif
 315
 316 #ifndef readw_relaxed
 317 #define readw_relaxed readw_relaxed
 318 static inline u16 readw_relaxed(const volatile void __iomem *addr)
 319 {
 320         u16 val;
 321
 322         log_read_mmio(16, addr, _THIS_IP_, _RET_IP_);
 323         val = __le16_to_cpu((__le16 __force)__raw_readw(addr));
 324         log_post_read_mmio(val, 16, addr, _THIS_IP_, _RET_IP_);
 325         return val;
 326 }
 327 #endif
 328
 329 #ifndef readl_relaxed
 330 #define readl_relaxed readl_relaxed
 331 static inline u32 readl_relaxed(const volatile void __iomem *addr)
 332 {
 333         u32 val;
 334
 335         log_read_mmio(32, addr, _THIS_IP_, _RET_IP_);
 336         val = __le32_to_cpu((__le32 __force)__raw_readl(addr));
 337         log_post_read_mmio(val, 32, addr, _THIS_IP_, _RET_IP_);
 338         return val;
 339 }
 340 #endif
 341
 342 #if defined(readq) && !defined(readq_relaxed)
 343 #define readq_relaxed readq_relaxed
 344 static inline u64 readq_relaxed(const volatile void __iomem *addr)
 345 {
 346         u64 val;
 347
 348         log_read_mmio(64, addr, _THIS_IP_, _RET_IP_);
 349         val = __le64_to_cpu((__le64 __force)__raw_readq(addr));
 350         log_post_read_mmio(val, 64, addr, _THIS_IP_, _RET_IP_);
 351         return val;
 352 }
 353 #endif
 354
 355 #ifndef writeb_relaxed
 356 #define writeb_relaxed writeb_relaxed
 357 static inline void writeb_relaxed(u8 value, volatile void __iomem *addr)
 358 {
 359         log_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
 360         __raw_writeb(value, addr);
 361         log_post_write_mmio(value, 8, addr, _THIS_IP_, _RET_IP_);
 362 }
 363 #endif
 364
 365 #ifndef writew_relaxed
 366 #define writew_relaxed writew_relaxed
 367 static inline void writew_relaxed(u16 value, volatile void __iomem *addr)
 368 {
 369         log_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
 370         __raw_writew((u16 __force)cpu_to_le16(value), addr);
 371         log_post_write_mmio(value, 16, addr, _THIS_IP_, _RET_IP_);
 372 }
 373 #endif
 374
 375 #ifndef writel_relaxed
 376 #define writel_relaxed writel_relaxed
 377 static inline void writel_relaxed(u32 value, volatile void __iomem *addr)
 378 {
 379         log_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
 380         __raw_writel((u32 __force)__cpu_to_le32(value), addr);
 381         log_post_write_mmio(value, 32, addr, _THIS_IP_, _RET_IP_);
 382 }
 383 #endif
 384
 385 #if defined(writeq) && !defined(writeq_relaxed)
 386 #define writeq_relaxed writeq_relaxed
 387 static inline void writeq_relaxed(u64 value, volatile void __iomem *addr)
 388 {
 389         log_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
 390         __raw_writeq((u64 __force)__cpu_to_le64(value), addr);
 391         log_post_write_mmio(value, 64, addr, _THIS_IP_, _RET_IP_);
 392 }
 393 #endif
 394
 395 /*
 396  * {read,write}s{b,w,l,q}() repeatedly access the same memory address in
 397  * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times).
 398  */
 399 #ifndef readsb
 400 #define readsb readsb
 401 static inline void readsb(const volatile void __iomem *addr, void *buffer,
 402                           unsigned int count)
 403 {
 404         if (count) {
 405                 u8 *buf = buffer;
 406
 407                 do {
 408                         u8 x = __raw_readb(addr);
 409                         *buf++ = x;
 410                 } while (--count);
 411         }
 412 }
 413 #endif
 414
 415 #ifndef readsw
 416 #define readsw readsw
 417 static inline void readsw(const volatile void __iomem *addr, void *buffer,
 418                           unsigned int count)
 419 {
 420         if (count) {
 421                 u16 *buf = buffer;
 422
 423                 do {
 424                         u16 x = __raw_readw(addr);
 425                         *buf++ = x;
 426                 } while (--count);
 427         }
 428 }
 429 #endif
 430
 431 #ifndef readsl
 432 #define readsl readsl
 433 static inline void readsl(const volatile void __iomem *addr, void *buffer,
 434                           unsigned int count)
 435 {
 436         if (count) {
 437                 u32 *buf = buffer;
 438
 439                 do {
 440                         u32 x = __raw_readl(addr);
 441                         *buf++ = x;
 442                 } while (--count);
 443         }
 444 }
 445 #endif
 446
 447 #ifdef CONFIG_64BIT
 448 #ifndef readsq
 449 #define readsq readsq
 450 static inline void readsq(const volatile void __iomem *addr, void *buffer,
 451                           unsigned int count)
 452 {
 453         if (count) {
 454                 u64 *buf = buffer;
 455
 456                 do {
 457                         u64 x = __raw_readq(addr);
 458                         *buf++ = x;
 459                 } while (--count);
 460         }
 461 }
 462 #endif
 463 #endif /* CONFIG_64BIT */
 464
 465 #ifndef writesb
 466 #define writesb writesb
 467 static inline void writesb(volatile void __iomem *addr, const void *buffer,
 468                            unsigned int count)
 469 {
 470         if (count) {
 471                 const u8 *buf = buffer;
 472
 473                 do {
 474                         __raw_writeb(*buf++, addr);
 475                 } while (--count);
 476         }
 477 }
 478 #endif
 479
 480 #ifndef writesw
 481 #define writesw writesw
 482 static inline void writesw(volatile void __iomem *addr, const void *buffer,
 483                            unsigned int count)
 484 {
 485         if (count) {
 486                 const u16 *buf = buffer;
 487
 488                 do {
 489                         __raw_writew(*buf++, addr);
 490                 } while (--count);
 491         }
 492 }
 493 #endif
 494
 495 #ifndef writesl
 496 #define writesl writesl
 497 static inline void writesl(volatile void __iomem *addr, const void *buffer,
 498                            unsigned int count)
 499 {
 500         if (count) {
 501                 const u32 *buf = buffer;
 502
 503                 do {
 504                         __raw_writel(*buf++, addr);
 505                 } while (--count);
 506         }
 507 }
 508 #endif
 509
 510 #ifdef CONFIG_64BIT
 511 #ifndef writesq
 512 #define writesq writesq
 513 static inline void writesq(volatile void __iomem *addr, const void *buffer,
 514                            unsigned int count)
 515 {
 516         if (count) {
 517                 const u64 *buf = buffer;
 518
 519                 do {
 520                         __raw_writeq(*buf++, addr);
 521                 } while (--count);
 522         }
 523 }
 524 #endif
 525 #endif /* CONFIG_64BIT */
 526
 527 #ifndef PCI_IOBASE
 528 #define PCI_IOBASE ((void __iomem *)0)
 529 #endif
 530
 531 #ifndef IO_SPACE_LIMIT
 532 #define IO_SPACE_LIMIT 0xffff
 533 #endif
 534
 535 /*
 536  * {in,out}{b,w,l}() access little endian I/O. {in,out}{b,w,l}_p() can be
 537  * implemented on hardware that needs an additional delay for I/O accesses to
 538  * take effect.
 539  */
 540
 541 #if !defined(inb) && !defined(_inb)
 542 #define _inb _inb
 543 #ifdef CONFIG_HAS_IOPORT
 544 static inline u8 _inb(unsigned long addr)
 545 {
 546         u8 val;
 547
 548         __io_pbr();
 549         val = __raw_readb(PCI_IOBASE + addr);
 550         __io_par(val);
 551         return val;
 552 }
 553 #else
 554 u8 _inb(unsigned long addr)
 555         __compiletime_error("inb()) requires CONFIG_HAS_IOPORT");
 556 #endif
 557 #endif
 558
 559 #if !defined(inw) && !defined(_inw)
 560 #define _inw _inw
 561 #ifdef CONFIG_HAS_IOPORT
 562 static inline u16 _inw(unsigned long addr)
 563 {
 564         u16 val;
 565
 566         __io_pbr();
 567         val = __le16_to_cpu((__le16 __force)__raw_readw(PCI_IOBASE + addr));
 568         __io_par(val);
 569         return val;
 570 }
 571 #else
 572 u16 _inw(unsigned long addr)
 573         __compiletime_error("inw() requires CONFIG_HAS_IOPORT");
 574 #endif
 575 #endif
 576
 577 #if !defined(inl) && !defined(_inl)
 578 #define _inl _inl
 579 #ifdef CONFIG_HAS_IOPORT
 580 static inline u32 _inl(unsigned long addr)
 581 {
 582         u32 val;
 583
 584         __io_pbr();
 585         val = __le32_to_cpu((__le32 __force)__raw_readl(PCI_IOBASE + addr));
 586         __io_par(val);
 587         return val;
 588 }
 589 #else
 590 u32 _inl(unsigned long addr)
 591         __compiletime_error("inl() requires CONFIG_HAS_IOPORT");
 592 #endif
 593 #endif
 594
 595 #if !defined(outb) && !defined(_outb)
 596 #define _outb _outb
 597 #ifdef CONFIG_HAS_IOPORT
 598 static inline void _outb(u8 value, unsigned long addr)
 599 {
 600         __io_pbw();
 601         __raw_writeb(value, PCI_IOBASE + addr);
 602         __io_paw();
 603 }
 604 #else
 605 void _outb(u8 value, unsigned long addr)
 606         __compiletime_error("outb() requires CONFIG_HAS_IOPORT");
 607 #endif
 608 #endif
 609
 610 #if !defined(outw) && !defined(_outw)
 611 #define _outw _outw
 612 #ifdef CONFIG_HAS_IOPORT
 613 static inline void _outw(u16 value, unsigned long addr)
 614 {
 615         __io_pbw();
 616         __raw_writew((u16 __force)cpu_to_le16(value), PCI_IOBASE + addr);
 617         __io_paw();
 618 }
 619 #else
 620 void _outw(u16 value, unsigned long addr)
 621         __compiletime_error("outw() requires CONFIG_HAS_IOPORT");
 622 #endif
 623 #endif
 624
 625 #if !defined(outl) && !defined(_outl)
 626 #define _outl _outl
 627 #ifdef CONFIG_HAS_IOPORT
 628 static inline void _outl(u32 value, unsigned long addr)
 629 {
 630         __io_pbw();
 631         __raw_writel((u32 __force)cpu_to_le32(value), PCI_IOBASE + addr);
 632         __io_paw();
 633 }
 634 #else
 635 void _outl(u32 value, unsigned long addr)
 636         __compiletime_error("outl() requires CONFIG_HAS_IOPORT");
 637 #endif
 638 #endif
 639
 640 #include <linux/logic_pio.h>
 641
 642 #ifndef inb
 643 #define inb _inb
 644 #endif
 645
 646 #ifndef inw
 647 #define inw _inw
 648 #endif
 649
 650 #ifndef inl
 651 #define inl _inl
 652 #endif
 653
 654 #ifndef outb
 655 #define outb _outb
 656 #endif
 657
 658 #ifndef outw
 659 #define outw _outw
 660 #endif
 661
 662 #ifndef outl
 663 #define outl _outl
 664 #endif
 665
 666 #ifndef inb_p
 667 #define inb_p inb_p
 668 static inline u8 inb_p(unsigned long addr)
 669 {
 670         return inb(addr);
 671 }
 672 #endif
 673
 674 #ifndef inw_p
 675 #define inw_p inw_p
 676 static inline u16 inw_p(unsigned long addr)
 677 {
 678         return inw(addr);
 679 }
 680 #endif
 681
 682 #ifndef inl_p
 683 #define inl_p inl_p
 684 static inline u32 inl_p(unsigned long addr)
 685 {
 686         return inl(addr);
 687 }
 688 #endif
 689
 690 #ifndef outb_p
 691 #define outb_p outb_p
 692 static inline void outb_p(u8 value, unsigned long addr)
 693 {
 694         outb(value, addr);
 695 }
 696 #endif
 697
 698 #ifndef outw_p
 699 #define outw_p outw_p
 700 static inline void outw_p(u16 value, unsigned long addr)
 701 {
 702         outw(value, addr);
 703 }
 704 #endif
 705
 706 #ifndef outl_p
 707 #define outl_p outl_p
 708 static inline void outl_p(u32 value, unsigned long addr)
 709 {
 710         outl(value, addr);
 711 }
 712 #endif
 713
 714 /*
 715  * {in,out}s{b,w,l}{,_p}() are variants of the above that repeatedly access a
 716  * single I/O port multiple times.
 717  */
 718
 719 #ifndef insb
 720 #define insb insb
 721 #ifdef CONFIG_HAS_IOPORT
 722 static inline void insb(unsigned long addr, void *buffer, unsigned int count)
 723 {
 724         readsb(PCI_IOBASE + addr, buffer, count);
 725 }
 726 #else
 727 void insb(unsigned long addr, void *buffer, unsigned int count)
 728         __compiletime_error("insb() requires HAS_IOPORT");
 729 #endif
 730 #endif
 731
 732 #ifndef insw
 733 #define insw insw
 734 #ifdef CONFIG_HAS_IOPORT
 735 static inline void insw(unsigned long addr, void *buffer, unsigned int count)
 736 {
 737         readsw(PCI_IOBASE + addr, buffer, count);
 738 }
 739 #else
 740 void insw(unsigned long addr, void *buffer, unsigned int count)
 741         __compiletime_error("insw() requires HAS_IOPORT");
 742 #endif
 743 #endif
 744
 745 #ifndef insl
 746 #define insl insl
 747 #ifdef CONFIG_HAS_IOPORT
 748 static inline void insl(unsigned long addr, void *buffer, unsigned int count)
 749 {
 750         readsl(PCI_IOBASE + addr, buffer, count);
 751 }
 752 #else
 753 void insl(unsigned long addr, void *buffer, unsigned int count)
 754         __compiletime_error("insl() requires HAS_IOPORT");
 755 #endif
 756 #endif
 757
 758 #ifndef outsb
 759 #define outsb outsb
 760 #ifdef CONFIG_HAS_IOPORT
 761 static inline void outsb(unsigned long addr, const void *buffer,
 762                          unsigned int count)
 763 {
 764         writesb(PCI_IOBASE + addr, buffer, count);
 765 }
 766 #else
 767 void outsb(unsigned long addr, const void *buffer, unsigned int count)
 768         __compiletime_error("outsb() requires HAS_IOPORT");
 769 #endif
 770 #endif
 771
 772 #ifndef outsw
 773 #define outsw outsw
 774 #ifdef CONFIG_HAS_IOPORT
 775 static inline void outsw(unsigned long addr, const void *buffer,
 776                          unsigned int count)
 777 {
 778         writesw(PCI_IOBASE + addr, buffer, count);
 779 }
 780 #else
 781 void outsw(unsigned long addr, const void *buffer, unsigned int count)
 782         __compiletime_error("outsw() requires HAS_IOPORT");
 783 #endif
 784 #endif
 785
 786 #ifndef outsl
 787 #define outsl outsl
 788 #ifdef CONFIG_HAS_IOPORT
 789 static inline void outsl(unsigned long addr, const void *buffer,
 790                          unsigned int count)
 791 {
 792         writesl(PCI_IOBASE + addr, buffer, count);
 793 }
 794 #else
 795 void outsl(unsigned long addr, const void *buffer, unsigned int count)
 796         __compiletime_error("outsl() requires HAS_IOPORT");
 797 #endif
 798 #endif
 799
 800 #ifndef insb_p
 801 #define insb_p insb_p
 802 static inline void insb_p(unsigned long addr, void *buffer, unsigned int count)
 803 {
 804         insb(addr, buffer, count);
 805 }
 806 #endif
 807
 808 #ifndef insw_p
 809 #define insw_p insw_p
 810 static inline void insw_p(unsigned long addr, void *buffer, unsigned int count)
 811 {
 812         insw(addr, buffer, count);
 813 }
 814 #endif
 815
 816 #ifndef insl_p
 817 #define insl_p insl_p
 818 static inline void insl_p(unsigned long addr, void *buffer, unsigned int count)
 819 {
 820         insl(addr, buffer, count);
 821 }
 822 #endif
 823
 824 #ifndef outsb_p
 825 #define outsb_p outsb_p
 826 static inline void outsb_p(unsigned long addr, const void *buffer,
 827                            unsigned int count)
 828 {
 829         outsb(addr, buffer, count);
 830 }
 831 #endif
 832
 833 #ifndef outsw_p
 834 #define outsw_p outsw_p
 835 static inline void outsw_p(unsigned long addr, const void *buffer,
 836                            unsigned int count)
 837 {
 838         outsw(addr, buffer, count);
 839 }
 840 #endif
 841
 842 #ifndef outsl_p
 843 #define outsl_p outsl_p
 844 static inline void outsl_p(unsigned long addr, const void *buffer,
 845                            unsigned int count)
 846 {
 847         outsl(addr, buffer, count);
 848 }
 849 #endif
 850
 851 #ifndef CONFIG_GENERIC_IOMAP
 852 #ifndef ioread8
 853 #define ioread8 ioread8
 854 static inline u8 ioread8(const volatile void __iomem *addr)
 855 {
 856         return readb(addr);
 857 }
 858 #endif
 859
 860 #ifndef ioread16
 861 #define ioread16 ioread16
 862 static inline u16 ioread16(const volatile void __iomem *addr)
 863 {
 864         return readw(addr);
 865 }
 866 #endif
 867
 868 #ifndef ioread32
 869 #define ioread32 ioread32
 870 static inline u32 ioread32(const volatile void __iomem *addr)
 871 {
 872         return readl(addr);
 873 }
 874 #endif
 875
 876 #ifdef CONFIG_64BIT
 877 #ifndef ioread64
 878 #define ioread64 ioread64
 879 static inline u64 ioread64(const volatile void __iomem *addr)
 880 {
 881         return readq(addr);
 882 }
 883 #endif
 884 #endif /* CONFIG_64BIT */
 885
 886 #ifndef iowrite8
 887 #define iowrite8 iowrite8
 888 static inline void iowrite8(u8 value, volatile void __iomem *addr)
 889 {
 890         writeb(value, addr);
 891 }
 892 #endif
 893
 894 #ifndef iowrite16
 895 #define iowrite16 iowrite16
 896 static inline void iowrite16(u16 value, volatile void __iomem *addr)
 897 {
 898         writew(value, addr);
 899 }
 900 #endif
 901
 902 #ifndef iowrite32
 903 #define iowrite32 iowrite32
 904 static inline void iowrite32(u32 value, volatile void __iomem *addr)
 905 {
 906         writel(value, addr);
 907 }
 908 #endif
 909
 910 #ifdef CONFIG_64BIT
 911 #ifndef iowrite64
 912 #define iowrite64 iowrite64
 913 static inline void iowrite64(u64 value, volatile void __iomem *addr)
 914 {
 915         writeq(value, addr);
 916 }
 917 #endif
 918 #endif /* CONFIG_64BIT */
 919
 920 #ifndef ioread16be
 921 #define ioread16be ioread16be
 922 static inline u16 ioread16be(const volatile void __iomem *addr)
 923 {
 924         return swab16(readw(addr));
 925 }
 926 #endif
 927
 928 #ifndef ioread32be
 929 #define ioread32be ioread32be
 930 static inline u32 ioread32be(const volatile void __iomem *addr)
 931 {
 932         return swab32(readl(addr));
 933 }
 934 #endif
 935
 936 #ifdef CONFIG_64BIT
 937 #ifndef ioread64be
 938 #define ioread64be ioread64be
 939 static inline u64 ioread64be(const volatile void __iomem *addr)
 940 {
 941         return swab64(readq(addr));
 942 }
 943 #endif
 944 #endif /* CONFIG_64BIT */
 945
 946 #ifndef iowrite16be
 947 #define iowrite16be iowrite16be
 948 static inline void iowrite16be(u16 value, void volatile __iomem *addr)
 949 {
 950         writew(swab16(value), addr);
 951 }
 952 #endif
 953
 954 #ifndef iowrite32be
 955 #define iowrite32be iowrite32be
 956 static inline void iowrite32be(u32 value, volatile void __iomem *addr)
 957 {
 958         writel(swab32(value), addr);
 959 }
 960 #endif
 961
 962 #ifdef CONFIG_64BIT
 963 #ifndef iowrite64be
 964 #define iowrite64be iowrite64be
 965 static inline void iowrite64be(u64 value, volatile void __iomem *addr)
 966 {
 967         writeq(swab64(value), addr);
 968 }
 969 #endif
 970 #endif /* CONFIG_64BIT */
 971
 972 #ifndef ioread8_rep
 973 #define ioread8_rep ioread8_rep
 974 static inline void ioread8_rep(const volatile void __iomem *addr, void *buffer,
 975                                unsigned int count)
 976 {
 977         readsb(addr, buffer, count);
 978 }
 979 #endif
 980
 981 #ifndef ioread16_rep
 982 #define ioread16_rep ioread16_rep
 983 static inline void ioread16_rep(const volatile void __iomem *addr,
 984                                 void *buffer, unsigned int count)
 985 {
 986         readsw(addr, buffer, count);
 987 }
 988 #endif
 989
 990 #ifndef ioread32_rep
 991 #define ioread32_rep ioread32_rep
 992 static inline void ioread32_rep(const volatile void __iomem *addr,
 993                                 void *buffer, unsigned int count)
 994 {
 995         readsl(addr, buffer, count);
 996 }
 997 #endif
 998
 999 #ifdef CONFIG_64BIT
1000 #ifndef ioread64_rep
1001 #define ioread64_rep ioread64_rep
1002 static inline void ioread64_rep(const volatile void __iomem *addr,
1003                                 void *buffer, unsigned int count)
1004 {
1005         readsq(addr, buffer, count);
1006 }
1007 #endif
1008 #endif /* CONFIG_64BIT */
1009
1010 #ifndef iowrite8_rep
1011 #define iowrite8_rep iowrite8_rep
1012 static inline void iowrite8_rep(volatile void __iomem *addr,
1013                                 const void *buffer,
1014                                 unsigned int count)
1015 {
1016         writesb(addr, buffer, count);
1017 }
1018 #endif
1019
1020 #ifndef iowrite16_rep
1021 #define iowrite16_rep iowrite16_rep
1022 static inline void iowrite16_rep(volatile void __iomem *addr,
1023                                  const void *buffer,
1024                                  unsigned int count)
1025 {
1026         writesw(addr, buffer, count);
1027 }
1028 #endif
1029
1030 #ifndef iowrite32_rep
1031 #define iowrite32_rep iowrite32_rep
1032 static inline void iowrite32_rep(volatile void __iomem *addr,
1033                                  const void *buffer,
1034                                  unsigned int count)
1035 {
1036         writesl(addr, buffer, count);
1037 }
1038 #endif
1039
1040 #ifdef CONFIG_64BIT
1041 #ifndef iowrite64_rep
1042 #define iowrite64_rep iowrite64_rep
1043 static inline void iowrite64_rep(volatile void __iomem *addr,
1044                                  const void *buffer,
1045                                  unsigned int count)
1046 {
1047         writesq(addr, buffer, count);
1048 }
1049 #endif
1050 #endif /* CONFIG_64BIT */
1051 #endif /* CONFIG_GENERIC_IOMAP */
1052
1053 #ifdef __KERNEL__
1054
1055 #define __io_virt(x) ((void __force *)(x))
1056
1057 /*
1058  * Change virtual addresses to physical addresses and vv.
1059  * These are pretty trivial
1060  */
1061 #ifndef virt_to_phys
1062 #define virt_to_phys virt_to_phys
1063 static inline unsigned long virt_to_phys(volatile void *address)
1064 {
1065         return __pa((unsigned long)address);
1066 }
1067 #endif
1068
1069 #ifndef phys_to_virt
1070 #define phys_to_virt phys_to_virt
1071 static inline void *phys_to_virt(unsigned long address)
1072 {
1073         return __va(address);
1074 }
1075 #endif
1076
1077 /**
1078  * DOC: ioremap() and ioremap_*() variants
1079  *
1080  * Architectures with an MMU are expected to provide ioremap() and iounmap()
1081  * themselves or rely on GENERIC_IOREMAP.  For NOMMU architectures we provide
1082  * a default nop-op implementation that expect that the physical address used
1083  * for MMIO are already marked as uncached, and can be used as kernel virtual
1084  * addresses.
1085  *
1086  * ioremap_wc() and ioremap_wt() can provide more relaxed caching attributes
1087  * for specific drivers if the architecture choses to implement them.  If they
1088  * are not implemented we fall back to plain ioremap. Conversely, ioremap_np()
1089  * can provide stricter non-posted write semantics if the architecture
1090  * implements them.
1091  */
1092 #ifndef CONFIG_MMU
1093 #ifndef ioremap
1094 #define ioremap ioremap
1095 static inline void __iomem *ioremap(phys_addr_t offset, size_t size)
1096 {
1097         return (void __iomem *)(unsigned long)offset;
1098 }
1099 #endif
1100
1101 #ifndef iounmap
1102 #define iounmap iounmap
1103 static inline void iounmap(volatile void __iomem *addr)
1104 {
1105 }
1106 #endif
1107 #elif defined(CONFIG_GENERIC_IOREMAP)
1108 #include <linux/pgtable.h>
1109
1110 void __iomem *generic_ioremap_prot(phys_addr_t phys_addr, size_t size,
1111                                    pgprot_t prot);
1112
1113 void __iomem *ioremap_prot(phys_addr_t phys_addr, size_t size,
1114                            unsigned long prot);
1115 void iounmap(volatile void __iomem *addr);
1116 void generic_iounmap(volatile void __iomem *addr);
1117
1118 #ifndef ioremap
1119 #define ioremap ioremap
1120 static inline void __iomem *ioremap(phys_addr_t addr, size_t size)
1121 {
1122         /* _PAGE_IOREMAP needs to be supplied by the architecture */
1123         return ioremap_prot(addr, size, _PAGE_IOREMAP);
1124 }
1125 #endif
1126 #endif /* !CONFIG_MMU || CONFIG_GENERIC_IOREMAP */
1127
1128 #ifndef ioremap_wc
1129 #define ioremap_wc ioremap
1130 #endif
1131
1132 #ifndef ioremap_wt
1133 #define ioremap_wt ioremap
1134 #endif
1135
1136 /*
1137  * ioremap_uc is special in that we do require an explicit architecture
1138  * implementation.  In general you do not want to use this function in a
1139  * driver and use plain ioremap, which is uncached by default.  Similarly
1140  * architectures should not implement it unless they have a very good
1141  * reason.
1142  */
1143 #ifndef ioremap_uc
1144 #define ioremap_uc ioremap_uc
1145 static inline void __iomem *ioremap_uc(phys_addr_t offset, size_t size)
1146 {
1147         return NULL;
1148 }
1149 #endif
1150
1151 /*
1152  * ioremap_np needs an explicit architecture implementation, as it
1153  * requests stronger semantics than regular ioremap(). Portable drivers
1154  * should instead use one of the higher-level abstractions, like
1155  * devm_ioremap_resource(), to choose the correct variant for any given
1156  * device and bus. Portable drivers with a good reason to want non-posted
1157  * write semantics should always provide an ioremap() fallback in case
1158  * ioremap_np() is not available.
1159  */
1160 #ifndef ioremap_np
1161 #define ioremap_np ioremap_np
1162 static inline void __iomem *ioremap_np(phys_addr_t offset, size_t size)
1163 {
1164         return NULL;
1165 }
1166 #endif
1167
1168 #ifdef CONFIG_HAS_IOPORT_MAP
1169 #ifndef CONFIG_GENERIC_IOMAP
1170 #ifndef ioport_map
1171 #define ioport_map ioport_map
1172 static inline void __iomem *ioport_map(unsigned long port, unsigned int nr)
1173 {
1174         port &= IO_SPACE_LIMIT;
1175         return (port > MMIO_UPPER_LIMIT) ? NULL : PCI_IOBASE + port;
1176 }
1177 #define ARCH_HAS_GENERIC_IOPORT_MAP
1178 #endif
1179
1180 #ifndef ioport_unmap
1181 #define ioport_unmap ioport_unmap
1182 static inline void ioport_unmap(void __iomem *p)
1183 {
1184 }
1185 #endif
1186 #else /* CONFIG_GENERIC_IOMAP */
1187 extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
1188 extern void ioport_unmap(void __iomem *p);
1189 #endif /* CONFIG_GENERIC_IOMAP */
1190 #endif /* CONFIG_HAS_IOPORT_MAP */
1191
1192 #ifndef CONFIG_GENERIC_IOMAP
1193 #ifndef pci_iounmap
1194 #define ARCH_WANTS_GENERIC_PCI_IOUNMAP
1195 #endif
1196 #endif
1197
1198 #ifndef xlate_dev_mem_ptr
1199 #define xlate_dev_mem_ptr xlate_dev_mem_ptr
1200 static inline void *xlate_dev_mem_ptr(phys_addr_t addr)
1201 {
1202         return __va(addr);
1203 }
1204 #endif
1205
1206 #ifndef unxlate_dev_mem_ptr
1207 #define unxlate_dev_mem_ptr unxlate_dev_mem_ptr
1208 static inline void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr)
1209 {
1210 }
1211 #endif
1212
1213 #ifndef memset_io
1214 /**
1215  * memset_io    Set a range of I/O memory to a constant value
1216  * @addr:       The beginning of the I/O-memory range to set
1217  * @val:        The value to set the memory to
1218  * @count:      The number of bytes to set
1219  *
1220  * Set a range of I/O memory to a given value.
1221  */
1222 void memset_io(volatile void __iomem *addr, int val, size_t count);
1223 #endif
1224
1225 #ifndef memcpy_fromio
1226 /**
1227  * memcpy_fromio        Copy a block of data from I/O memory
1228  * @dst:                The (RAM) destination for the copy
1229  * @src:                The (I/O memory) source for the data
1230  * @count:              The number of bytes to copy
1231  *
1232  * Copy a block of data from I/O memory.
1233  */
1234 void memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count);
1235 #endif
1236
1237 #ifndef memcpy_toio
1238 /**
1239  * memcpy_toio          Copy a block of data into I/O memory
1240  * @dst:                The (I/O memory) destination for the copy
1241  * @src:                The (RAM) source for the data
1242  * @count:              The number of bytes to copy
1243  *
1244  * Copy a block of data to I/O memory.
1245  */
1246 void memcpy_toio(volatile void __iomem *dst, const void *src, size_t count);
1247 #endif
1248
1249 extern int devmem_is_allowed(unsigned long pfn);
1250
1251 #endif /* __KERNEL__ */
1252
1253 #endif /* __ASM_GENERIC_IO_H */