include/dt-bindings/clock/qcom,sa8775p-dispcc.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2 /*
   3  * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
   7 #define _DT_BINDINGS_CLK_QCOM_SA8775P_DISP_CC_H
   8
   9 /* DISP_CC_0/1 clocks */
  10 #define MDSS_DISP_CC_MDSS_AHB1_CLK                              0
  11 #define MDSS_DISP_CC_MDSS_AHB_CLK                               1
  12 #define MDSS_DISP_CC_MDSS_AHB_CLK_SRC                           2
  13 #define MDSS_DISP_CC_MDSS_BYTE0_CLK                             3
  14 #define MDSS_DISP_CC_MDSS_BYTE0_CLK_SRC                         4
  15 #define MDSS_DISP_CC_MDSS_BYTE0_DIV_CLK_SRC                     5
  16 #define MDSS_DISP_CC_MDSS_BYTE0_INTF_CLK                        6
  17 #define MDSS_DISP_CC_MDSS_BYTE1_CLK                             7
  18 #define MDSS_DISP_CC_MDSS_BYTE1_CLK_SRC                         8
  19 #define MDSS_DISP_CC_MDSS_BYTE1_DIV_CLK_SRC                     9
  20 #define MDSS_DISP_CC_MDSS_BYTE1_INTF_CLK                        10
  21 #define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK                         11
  22 #define MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK_SRC                     12
  23 #define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK                      13
  24 #define MDSS_DISP_CC_MDSS_DPTX0_CRYPTO_CLK_SRC                  14
  25 #define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK                        15
  26 #define MDSS_DISP_CC_MDSS_DPTX0_LINK_CLK_SRC                    16
  27 #define MDSS_DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC                17
  28 #define MDSS_DISP_CC_MDSS_DPTX0_LINK_INTF_CLK                   18
  29 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK                      19
  30 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC                  20
  31 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK                      21
  32 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC                  22
  33 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK                      23
  34 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL2_CLK_SRC                  24
  35 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK                      25
  36 #define MDSS_DISP_CC_MDSS_DPTX0_PIXEL3_CLK_SRC                  26
  37 #define MDSS_DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK        27
  38 #define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK                         28
  39 #define MDSS_DISP_CC_MDSS_DPTX1_AUX_CLK_SRC                     29
  40 #define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK                      30
  41 #define MDSS_DISP_CC_MDSS_DPTX1_CRYPTO_CLK_SRC                  31
  42 #define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK                        32
  43 #define MDSS_DISP_CC_MDSS_DPTX1_LINK_CLK_SRC                    33
  44 #define MDSS_DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC                34
  45 #define MDSS_DISP_CC_MDSS_DPTX1_LINK_INTF_CLK                   35
  46 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK                      36
  47 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC                  37
  48 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK                      38
  49 #define MDSS_DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC                  39
  50 #define MDSS_DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK        40
  51 #define MDSS_DISP_CC_MDSS_ESC0_CLK                              41
  52 #define MDSS_DISP_CC_MDSS_ESC0_CLK_SRC                          42
  53 #define MDSS_DISP_CC_MDSS_ESC1_CLK                              43
  54 #define MDSS_DISP_CC_MDSS_ESC1_CLK_SRC                          44
  55 #define MDSS_DISP_CC_MDSS_MDP1_CLK                              45
  56 #define MDSS_DISP_CC_MDSS_MDP_CLK                               46
  57 #define MDSS_DISP_CC_MDSS_MDP_CLK_SRC                           47
  58 #define MDSS_DISP_CC_MDSS_MDP_LUT1_CLK                          48
  59 #define MDSS_DISP_CC_MDSS_MDP_LUT_CLK                           49
  60 #define MDSS_DISP_CC_MDSS_NON_GDSC_AHB_CLK                      50
  61 #define MDSS_DISP_CC_MDSS_PCLK0_CLK                             51
  62 #define MDSS_DISP_CC_MDSS_PCLK0_CLK_SRC                         52
  63 #define MDSS_DISP_CC_MDSS_PCLK1_CLK                             53
  64 #define MDSS_DISP_CC_MDSS_PCLK1_CLK_SRC                         54
  65 #define MDSS_DISP_CC_MDSS_PLL_LOCK_MONITOR_CLK                  55
  66 #define MDSS_DISP_CC_MDSS_RSCC_AHB_CLK                          56
  67 #define MDSS_DISP_CC_MDSS_RSCC_VSYNC_CLK                        57
  68 #define MDSS_DISP_CC_MDSS_VSYNC1_CLK                            58
  69 #define MDSS_DISP_CC_MDSS_VSYNC_CLK                             59
  70 #define MDSS_DISP_CC_MDSS_VSYNC_CLK_SRC                         60
  71 #define MDSS_DISP_CC_PLL0                                       61
  72 #define MDSS_DISP_CC_PLL1                                       62
  73 #define MDSS_DISP_CC_SLEEP_CLK                                  63
  74 #define MDSS_DISP_CC_SLEEP_CLK_SRC                              64
  75 #define MDSS_DISP_CC_SM_OBS_CLK                                 65
  76 #define MDSS_DISP_CC_XO_CLK                                     66
  77 #define MDSS_DISP_CC_XO_CLK_SRC                                 67
  78
  79 /* DISP_CC_0/1 power domains */
  80 #define MDSS_DISP_CC_MDSS_CORE_GDSC                             0
  81 #define MDSS_DISP_CC_MDSS_CORE_INT2_GDSC                        1
  82
  83 /* DISP_CC_0/1 resets */
  84 #define MDSS_DISP_CC_MDSS_CORE_BCR                              0
  85 #define MDSS_DISP_CC_MDSS_RSCC_BCR                              1
  86
  87 #endif