include/dt-bindings/clock/qcom,sm8550-gpucc.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
   2 /*
   3  * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
   4  */
   5
   6 #ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
   7 #define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8550_H
   8
   9 /* GPU_CC clocks */
  10 #define GPU_CC_AHB_CLK                                          0
  11 #define GPU_CC_CRC_AHB_CLK                                      1
  12 #define GPU_CC_CX_FF_CLK                                        2
  13 #define GPU_CC_CX_GMU_CLK                                       3
  14 #define GPU_CC_CXO_AON_CLK                                      4
  15 #define GPU_CC_CXO_CLK                                          5
  16 #define GPU_CC_DEMET_CLK                                        6
  17 #define GPU_CC_DEMET_DIV_CLK_SRC                                7
  18 #define GPU_CC_FF_CLK_SRC                                       8
  19 #define GPU_CC_FREQ_MEASURE_CLK                                 9
  20 #define GPU_CC_GMU_CLK_SRC                                      10
  21 #define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK                          11
  22 #define GPU_CC_HUB_AON_CLK                                      12
  23 #define GPU_CC_HUB_CLK_SRC                                      13
  24 #define GPU_CC_HUB_CX_INT_CLK                                   14
  25 #define GPU_CC_MEMNOC_GFX_CLK                                   15
  26 #define GPU_CC_MND1X_0_GFX3D_CLK                                16
  27 #define GPU_CC_MND1X_1_GFX3D_CLK                                17
  28 #define GPU_CC_PLL0                                             18
  29 #define GPU_CC_PLL1                                             19
  30 #define GPU_CC_SLEEP_CLK                                        20
  31 #define GPU_CC_XO_CLK_SRC                                       21
  32 #define GPU_CC_XO_DIV_CLK_SRC                                   22
  33
  34 /* GPU_CC power domains */
  35 #define GPU_CC_CX_GDSC                                          0
  36 #define GPU_CC_GX_GDSC                                          1
  37
  38 /* GPU_CC resets */
  39 #define GPUCC_GPU_CC_ACD_BCR                                    0
  40 #define GPUCC_GPU_CC_CX_BCR                                     1
  41 #define GPUCC_GPU_CC_FAST_HUB_BCR                               2
  42 #define GPUCC_GPU_CC_FF_BCR                                     3
  43 #define GPUCC_GPU_CC_GFX3D_AON_BCR                              4
  44 #define GPUCC_GPU_CC_GMU_BCR                                    5
  45 #define GPUCC_GPU_CC_GX_BCR                                     6
  46 #define GPUCC_GPU_CC_XO_BCR                                     7
  47
  48 #endif