| blob | fdbfb404f92a4ab27183905a2c60c89392547373 |
1 /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
2 /*
3 * Copyright (C) 2020 huangzhenwei@allwinnertech.com
4 * Copyright (C) 2021 Samuel Holland <samuel@sholland.org>
5 */
7 #ifndef _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
8 #define _DT_BINDINGS_CLK_SUN20I_D1_CCU_H_
10 #define CLK_PLL_CPUX 0
11 #define CLK_PLL_DDR0 1
12 #define CLK_PLL_PERIPH0_4X 2
13 #define CLK_PLL_PERIPH0_2X 3
14 #define CLK_PLL_PERIPH0_800M 4
15 #define CLK_PLL_PERIPH0 5
16 #define CLK_PLL_PERIPH0_DIV3 6
17 #define CLK_PLL_VIDEO0_4X 7
18 #define CLK_PLL_VIDEO0_2X 8
19 #define CLK_PLL_VIDEO0 9
20 #define CLK_PLL_VIDEO1_4X 10
21 #define CLK_PLL_VIDEO1_2X 11
22 #define CLK_PLL_VIDEO1 12
23 #define CLK_PLL_VE 13
24 #define CLK_PLL_AUDIO0_4X 14
25 #define CLK_PLL_AUDIO0_2X 15
26 #define CLK_PLL_AUDIO0 16
27 #define CLK_PLL_AUDIO1 17
28 #define CLK_PLL_AUDIO1_DIV2 18
29 #define CLK_PLL_AUDIO1_DIV5 19
30 #define CLK_CPUX 20
31 #define CLK_CPUX_AXI 21
32 #define CLK_CPUX_APB 22
33 #define CLK_PSI_AHB 23
34 #define CLK_APB0 24
35 #define CLK_APB1 25
36 #define CLK_MBUS 26
37 #define CLK_DE 27
38 #define CLK_BUS_DE 28
39 #define CLK_DI 29
40 #define CLK_BUS_DI 30
41 #define CLK_G2D 31
42 #define CLK_BUS_G2D 32
43 #define CLK_CE 33
44 #define CLK_BUS_CE 34
45 #define CLK_VE 35
46 #define CLK_BUS_VE 36
47 #define CLK_BUS_DMA 37
48 #define CLK_BUS_MSGBOX0 38
49 #define CLK_BUS_MSGBOX1 39
50 #define CLK_BUS_MSGBOX2 40
51 #define CLK_BUS_SPINLOCK 41
52 #define CLK_BUS_HSTIMER 42
53 #define CLK_AVS 43
54 #define CLK_BUS_DBG 44
55 #define CLK_BUS_PWM 45
56 #define CLK_BUS_IOMMU 46
57 #define CLK_DRAM 47
58 #define CLK_MBUS_DMA 48
59 #define CLK_MBUS_VE 49
60 #define CLK_MBUS_CE 50
61 #define CLK_MBUS_TVIN 51
62 #define CLK_MBUS_CSI 52
63 #define CLK_MBUS_G2D 53
64 #define CLK_MBUS_RISCV 54
65 #define CLK_BUS_DRAM 55
66 #define CLK_MMC0 56
67 #define CLK_MMC1 57
68 #define CLK_MMC2 58
69 #define CLK_BUS_MMC0 59
70 #define CLK_BUS_MMC1 60
71 #define CLK_BUS_MMC2 61
72 #define CLK_BUS_UART0 62
73 #define CLK_BUS_UART1 63
74 #define CLK_BUS_UART2 64
75 #define CLK_BUS_UART3 65
76 #define CLK_BUS_UART4 66
77 #define CLK_BUS_UART5 67
78 #define CLK_BUS_I2C0 68
79 #define CLK_BUS_I2C1 69
80 #define CLK_BUS_I2C2 70
81 #define CLK_BUS_I2C3 71
82 #define CLK_SPI0 72
83 #define CLK_SPI1 73
84 #define CLK_BUS_SPI0 74
85 #define CLK_BUS_SPI1 75
86 #define CLK_EMAC_25M 76
87 #define CLK_BUS_EMAC 77
88 #define CLK_IR_TX 78
89 #define CLK_BUS_IR_TX 79
90 #define CLK_BUS_GPADC 80
91 #define CLK_BUS_THS 81
92 #define CLK_I2S0 82
93 #define CLK_I2S1 83
94 #define CLK_I2S2 84
95 #define CLK_I2S2_ASRC 85
96 #define CLK_BUS_I2S0 86
97 #define CLK_BUS_I2S1 87
98 #define CLK_BUS_I2S2 88
99 #define CLK_SPDIF_TX 89
100 #define CLK_SPDIF_RX 90
101 #define CLK_BUS_SPDIF 91
102 #define CLK_DMIC 92
103 #define CLK_BUS_DMIC 93
104 #define CLK_AUDIO_DAC 94
105 #define CLK_AUDIO_ADC 95
106 #define CLK_BUS_AUDIO 96
107 #define CLK_USB_OHCI0 97
108 #define CLK_USB_OHCI1 98
109 #define CLK_BUS_OHCI0 99
110 #define CLK_BUS_OHCI1 100
111 #define CLK_BUS_EHCI0 101
112 #define CLK_BUS_EHCI1 102
113 #define CLK_BUS_OTG 103
114 #define CLK_BUS_LRADC 104
115 #define CLK_BUS_DPSS_TOP 105
116 #define CLK_HDMI_24M 106
117 #define CLK_HDMI_CEC_32K 107
118 #define CLK_HDMI_CEC 108
119 #define CLK_BUS_HDMI 109
120 #define CLK_MIPI_DSI 110
121 #define CLK_BUS_MIPI_DSI 111
122 #define CLK_TCON_LCD0 112
123 #define CLK_BUS_TCON_LCD0 113
124 #define CLK_TCON_TV 114
125 #define CLK_BUS_TCON_TV 115
126 #define CLK_TVE 116
127 #define CLK_BUS_TVE_TOP 117
128 #define CLK_BUS_TVE 118
129 #define CLK_TVD 119
130 #define CLK_BUS_TVD_TOP 120
131 #define CLK_BUS_TVD 121
132 #define CLK_LEDC 122
133 #define CLK_BUS_LEDC 123
134 #define CLK_CSI_TOP 124
135 #define CLK_CSI_MCLK 125
136 #define CLK_BUS_CSI 126
137 #define CLK_TPADC 127
138 #define CLK_BUS_TPADC 128
139 #define CLK_BUS_TZMA 129
140 #define CLK_DSP 130
141 #define CLK_BUS_DSP_CFG 131
142 #define CLK_RISCV 132
143 #define CLK_RISCV_AXI 133
144 #define CLK_BUS_RISCV_CFG 134
145 #define CLK_FANOUT_24M 135
146 #define CLK_FANOUT_12M 136
147 #define CLK_FANOUT_16M 137
148 #define CLK_FANOUT_25M 138
149 #define CLK_FANOUT_32K 139
150 #define CLK_FANOUT_27M 140
151 #define CLK_FANOUT_PCLK 141
152 #define CLK_FANOUT0 142
153 #define CLK_FANOUT1 143
154 #define CLK_FANOUT2 144
155 #define CLK_BUS_CAN0 145
156 #define CLK_BUS_CAN1 146