drm/panel-edp: Add STA 116QHD024002
[drm/drm-misc.git] / include / dt-bindings / interconnect / mediatek,mt8195.h
blob33e0e6cde732b1aaa714f4246676915ff72e812f
1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
2 /*
3 * Copyright (c) 2020 MediaTek Inc.
4 * Copyright (c) 2024 Collabora Ltd.
5 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
6 */
8 #ifndef __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
9 #define __DT_BINDINGS_INTERCONNECT_MEDIATEK_MT8195_H
11 #define SLAVE_DDR_EMI 0
12 #define MASTER_MCUSYS 1
13 #define MASTER_GPUSYS 2
14 #define MASTER_MMSYS 3
15 #define MASTER_MM_VPU 4
16 #define MASTER_MM_DISP 5
17 #define MASTER_MM_VDEC 6
18 #define MASTER_MM_VENC 7
19 #define MASTER_MM_CAM 8
20 #define MASTER_MM_IMG 9
21 #define MASTER_MM_MDP 10
22 #define MASTER_VPUSYS 11
23 #define MASTER_VPU_0 12
24 #define MASTER_VPU_1 13
25 #define MASTER_MDLASYS 14
26 #define MASTER_MDLA_0 15
27 #define MASTER_UFS 16
28 #define MASTER_PCIE_0 17
29 #define MASTER_PCIE_1 18
30 #define MASTER_USB 19
31 #define MASTER_DBGIF 20
32 #define SLAVE_HRT_DDR_EMI 21
33 #define MASTER_HRT_MMSYS 22
34 #define MASTER_HRT_MM_DISP 23
35 #define MASTER_HRT_MM_VDEC 24
36 #define MASTER_HRT_MM_VENC 25
37 #define MASTER_HRT_MM_CAM 26
38 #define MASTER_HRT_MM_IMG 27
39 #define MASTER_HRT_MM_MDP 28
40 #define MASTER_HRT_DBGIF 29
41 #define MASTER_WIFI 30
42 #define MASTER_BT 31
43 #define MASTER_NETSYS 32
44 #endif